diff --git a/libsrc/hdl/bsv/BRAM1.v b/libsrc/hdl/bsv/BRAM1.v index 21d8f1e6..af02f5ae 100644 --- a/libsrc/hdl/bsv/BRAM1.v +++ b/libsrc/hdl/bsv/BRAM1.v @@ -1,5 +1,4 @@ - -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2011 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,8 +18,8 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 24080 $ -// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $ +// $Revision: 28325 $ +// $Date: 2012-04-25 18:22:57 +0000 (Wed, 25 Apr 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else @@ -41,7 +40,6 @@ module BRAM1(CLK, parameter DATA_WIDTH = 1; parameter MEMSIZE = 1; - input CLK; input EN; input WE; @@ -50,8 +48,8 @@ module BRAM1(CLK, output [DATA_WIDTH-1:0] DO; reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1]; - reg [ADDR_WIDTH-1:0] ADDR_R; reg [DATA_WIDTH-1:0] DO_R; + reg [DATA_WIDTH-1:0] DO_R2; `ifdef BSV_NO_INITIAL_BLOCKS `else @@ -62,21 +60,26 @@ module BRAM1(CLK, for (i = 0; i < MEMSIZE; i = i + 1) begin RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end - ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } }; - DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end // synopsys translate_on `endif // !`ifdef BSV_NO_INITIAL_BLOCKS always @(posedge CLK) begin if (EN) begin - if (WE) - RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI; - ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR; + if (WE) begin + RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI; + DO_R <= `BSV_ASSIGNMENT_DELAY DI; + end + else begin + DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR]; + end end - DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R]; + DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R; end - assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R]; + // Output driver + assign DO = (PIPELINED) ? DO_R2 : DO_R; endmodule // BRAM1 diff --git a/libsrc/hdl/bsv/BRAM1BE.v b/libsrc/hdl/bsv/BRAM1BE.v index 5cb32c35..a45eb301 100644 --- a/libsrc/hdl/bsv/BRAM1BE.v +++ b/libsrc/hdl/bsv/BRAM1BE.v @@ -1,4 +1,4 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2011 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -18,8 +18,8 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 24080 $ -// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $ +// $Revision: 28325 $ +// $Date: 2012-04-25 18:22:57 +0000 (Wed, 25 Apr 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else @@ -50,8 +50,8 @@ module BRAM1BE(CLK, output [DATA_WIDTH-1:0] DO; reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1]; - reg [ADDR_WIDTH-1:0] ADDR_R; reg [DATA_WIDTH-1:0] DO_R; + reg [DATA_WIDTH-1:0] DO_R2; reg [DATA_WIDTH-1:0] DATA; wire [DATA_WIDTH-1:0] DATAwr; @@ -67,8 +67,8 @@ module BRAM1BE(CLK, for (i = 0; i < MEMSIZE; i = i + 1) begin RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end - ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } }; - DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end // synopsys translate_on `endif // !`ifdef BSV_NO_INITIAL_BLOCKS @@ -104,13 +104,18 @@ module BRAM1BE(CLK, always @(posedge CLK) begin if (EN) begin - if (|WE) - RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA; - ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR; + if (|WE) begin + RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA; + DO_R <= `BSV_ASSIGNMENT_DELAY DATA; + end + else begin + DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR]; + end end - DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R]; + DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R; end - assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R]; + // Output driver + assign DO = (PIPELINED) ? DO_R2 : DO_R; endmodule // BRAM1BE diff --git a/libsrc/hdl/bsv/BRAM1Load.v b/libsrc/hdl/bsv/BRAM1Load.v index c0e20484..d913d592 100644 --- a/libsrc/hdl/bsv/BRAM1Load.v +++ b/libsrc/hdl/bsv/BRAM1Load.v @@ -18,8 +18,8 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 25100 $ -// $Date: 2011-09-01 18:44:19 +0000 (Thu, 01 Sep 2011) $ +// $Revision: 28325 $ +// $Date: 2012-04-25 18:22:57 +0000 (Wed, 25 Apr 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else @@ -53,6 +53,7 @@ module BRAM1Load(CLK, reg [DATA_WIDTH-1:0] DO_R; reg [DATA_WIDTH-1:0] DO_R2; + // synopsys translate_off initial begin : init_block `ifdef BSV_NO_INITIAL_BLOCKS @@ -69,6 +70,7 @@ module BRAM1Load(CLK, else $readmemh(FILENAME, RAM, 0, MEMSIZE-1); end + // synopsys translate_on always @(posedge CLK) begin if (EN) begin diff --git a/libsrc/hdl/bsv/BRAM2.v b/libsrc/hdl/bsv/BRAM2.v index 9bee3f29..32318901 100644 --- a/libsrc/hdl/bsv/BRAM2.v +++ b/libsrc/hdl/bsv/BRAM2.v @@ -1,5 +1,4 @@ - -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2011 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,15 +18,15 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 24080 $ -// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $ +// $Revision: 28325 $ +// $Date: 2012-04-25 18:22:57 +0000 (Wed, 25 Apr 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif -// Dual-Ported BRAM (READ FIRST) +// Dual-Ported BRAM (WRITE FIRST) module BRAM2(CLKA, ENA, WEA, @@ -64,8 +63,8 @@ module BRAM2(CLKA, reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ; reg [DATA_WIDTH-1:0] DOA_R; reg [DATA_WIDTH-1:0] DOB_R; - reg [DATA_WIDTH-1:0] DOA_D1_R; - reg [DATA_WIDTH-1:0] DOB_D1_R; + reg [DATA_WIDTH-1:0] DOA_R2; + reg [DATA_WIDTH-1:0] DOB_R2; `ifdef BSV_NO_INITIAL_BLOCKS `else @@ -78,39 +77,40 @@ module BRAM2(CLKA, end DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; - DOA_D1_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; - DOB_D1_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; + DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; end // synopsys translate_on `endif // !`ifdef BSV_NO_INITIAL_BLOCKS always @(posedge CLKA) begin - DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA]; if (ENA) begin if (WEA) begin - RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA; - end + RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA; + DOA_R <= `BSV_ASSIGNMENT_DELAY DIA; + end + else begin + DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA]; + end end + DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R; end always @(posedge CLKB) begin - DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB]; if (ENB) begin if (WEB) begin - RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB; - end + RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB; + DOB_R <= `BSV_ASSIGNMENT_DELAY DIB; + end + else begin + DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB]; + end end + DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R; end - // Pipeline - always @(posedge CLKA) - DOA_D1_R <= DOA_R; - - always @(posedge CLKB) - DOB_D1_R <= DOB_R; - // Output drivers - assign DOA = (PIPELINED) ? DOA_D1_R : DOA_R; - assign DOB = (PIPELINED) ? DOB_D1_R : DOB_R; + assign DOA = (PIPELINED) ? DOA_R2 : DOA_R; + assign DOB = (PIPELINED) ? DOB_R2 : DOB_R; endmodule // BRAM2 diff --git a/libsrc/hdl/bsv/ClockDiv.v b/libsrc/hdl/bsv/ClockDiv.v index 01496cca..ff7da9b2 100644 --- a/libsrc/hdl/bsv/ClockDiv.v +++ b/libsrc/hdl/bsv/ClockDiv.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,20 +19,29 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 17872 $ -// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + // A clock divider circuit. // Division is based on the parameters, where // Division is upper - lower + 1 -// Duty cycle is : +// Duty cycle is : // let half = 1 << (width-1) -// (upper - half) / upper - lower + 1 +// (upper - half) / upper - lower + 1 // E.g., (2,1,3) is a divide by 3 duty cycle 2/3 // (2,0,3) is a divide by 4 duty cycle 2/4 // (1,0,1) is a divide by 2, duty cycle 1/2 @@ -41,17 +50,17 @@ // The offset allow edges for seperate modules to be determined // relative to each other. a clock divider with offset 1 occurs one // (fast) clock later than a clock with offset 0. -module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT); +module ClockDiv(CLK_IN, RST, PREEDGE, CLK_OUT); parameter width = 2 ; // must be sufficient to hold upper - parameter lower = 1 ; // + parameter lower = 1 ; // parameter upper = 3 ; parameter offset = 0; // offset for relative edges. // (0 <= offset <= (upper - lower) input CLK_IN; // input clock - input RST_N; - + input RST; + output PREEDGE; // output signal announcing an upcoming edge output CLK_OUT; // output clock @@ -61,16 +70,16 @@ module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT); // Wire constants for the parameters wire [width-1:0] upper_w ; wire [width-1:0] lower_w ; - + assign CLK_OUT = cntr[width-1] ; assign upper_w = upper ; assign lower_w = lower ; - + // The clock is about to tick when counter is about to set its msb // Note some simulators do not allow 0 width expressions wire [width-1:0] nexttick = ~ ( 'b01 << (width-1) ) ; - // Combinational block to generate next edge signal + // Combinational block to generate next edge signal always@( cntr or nexttick ) begin #0 @@ -78,8 +87,8 @@ module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT); // Since this read by other always blocks trigger by the output CLK of this module PREEDGE <= `BSV_ASSIGNMENT_DELAY (cntr == nexttick) ; end - - always@( posedge CLK_IN or negedge RST_N ) + + always@( posedge CLK_IN or `BSV_RESET_EDGE RST ) begin // The use of blocking assignment within this block insures // that the clock generated from cntr[MSB] occurs before any @@ -89,16 +98,16 @@ module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT); // updates occur. see // http://www.sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf - if ( RST_N == 0 ) - cntr = upper - offset ; + if ( RST == `BSV_RESET_VALUE ) + cntr = upper - offset ; else begin if ( cntr < upper_w ) cntr = cntr + 1 ; else cntr = lower_w ; - end // else: !if( RST_N == 0 ) - end // always@ ( posedge CLK_IN or negedge RST_N ) + end // else: !if( RST == `BSV_RESET_VALUE ) + end // always@ ( posedge CLK_IN or `BSV_RESET_EDGE RST ) `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS @@ -107,8 +116,8 @@ module ClockDiv(CLK_IN, RST_N, PREEDGE, CLK_OUT); begin #0 ; cntr = (upper - offset) ; - PREEDGE = 0 ; - end // initial begin + PREEDGE = 0 ; + end // initial begin // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS diff --git a/libsrc/hdl/bsv/Counter.v b/libsrc/hdl/bsv/Counter.v index 7735cfad..1e974369 100644 --- a/libsrc/hdl/bsv/Counter.v +++ b/libsrc/hdl/bsv/Counter.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,17 +19,26 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 24080 $ -// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + // N -bit counter with load, set and 2 increment module Counter(CLK, - RST_N, + RST, Q_OUT, DATA_A, ADDA, DATA_B, ADDB, @@ -40,7 +49,7 @@ module Counter(CLK, parameter init = 0; input CLK; - input RST_N; + input RST; input [width - 1 : 0] DATA_A; input ADDA; input [width - 1 : 0] DATA_B; @@ -58,8 +67,8 @@ module Counter(CLK, assign Q_OUT = q_state ; - always@(posedge CLK /*or negedge RST_N*/ ) begin - if (RST_N == 0) + always@(posedge CLK /*or `BSV_RESET_EDGE RST*/ ) begin + if (RST == `BSV_RESET_VALUE) q_state <= `BSV_ASSIGNMENT_DELAY init; else begin @@ -67,7 +76,7 @@ module Counter(CLK, q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ; else q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ; - end // else: !if(RST_N == 0) + end // else: !if(RST == `BSV_RESET_VALUE) end // always@ (posedge CLK) `ifdef BSV_NO_INITIAL_BLOCKS diff --git a/libsrc/hdl/bsv/FIFO1.v b/libsrc/hdl/bsv/FIFO1.v index dad98e84..899c34cb 100644 --- a/libsrc/hdl/bsv/FIFO1.v +++ b/libsrc/hdl/bsv/FIFO1.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,32 +19,41 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 24080 $ -// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + // Depth 1 FIFO -module FIFO1(CLK, - RST_N, - D_IN, - ENQ, - FULL_N, - D_OUT, - DEQ, - EMPTY_N, +module FIFO1(CLK, + RST, + D_IN, + ENQ, + FULL_N, + D_OUT, + DEQ, + EMPTY_N, CLR ); parameter width = 1; parameter guarded = 1; input CLK; - input RST_N; + input RST; input [width - 1 : 0] D_IN; input ENQ; input DEQ; @@ -59,12 +68,12 @@ module FIFO1(CLK, assign EMPTY_N = empty_reg ; - - + + `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS // synopsys translate_off - initial + initial begin D_OUT = {((width + 1)/2) {2'b10}} ; empty_reg = 1'b0 ; @@ -72,21 +81,21 @@ module FIFO1(CLK, // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS - + assign FULL_N = !empty_reg; - always@(posedge CLK /* or negedge RST_N */ ) + always@(posedge CLK /* or `BSV_RESET_EDGE RST */ ) begin - if (!RST_N) + if (RST == `BSV_RESET_VALUE) begin empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; - end // if (RST_N == 0) + end // if (RST == `BSV_RESET_VALUE) else begin if (CLR) begin empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; - end // if (CLR) + end // if (CLR) else if (ENQ) begin empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; @@ -95,16 +104,16 @@ module FIFO1(CLK, begin empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; end // if (DEQ) - end // else: !if(RST_N == 0) - end // always@ (posedge CLK or negedge RST_N) + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - always@(posedge CLK /* or negedge RST_N */) + always@(posedge CLK /* or `BSV_RESET_EDGE RST */) begin // Following section initializes the data registers which // may be desired only in some situations. - // Uncomment to initialize array + // Uncomment to initialize array /* - if (!RST_N) + if (RST == `BSV_RESET_VALUE) begin D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ; end @@ -113,29 +122,29 @@ module FIFO1(CLK, begin if (ENQ) D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; - end // else: !if(RST_N == 0) - end // always@ (posedge CLK or negedge RST_N) + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) // synopsys translate_off always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; - + deqerror = 0; enqerror = 0; - if ( RST_N ) + if (RST == ! `BSV_RESET_VALUE) begin if ( ! empty_reg && DEQ ) begin - deqerror = 1 ; + deqerror = 1 ; $display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ; end if ( ! FULL_N && ENQ && (!DEQ || guarded) ) begin - enqerror = 1 ; + enqerror = 1 ; $display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ; end - end // if ( RST_N ) + end // if (RST == ! `BSV_RESET_VALUE) end // synopsys translate_on diff --git a/libsrc/hdl/bsv/FIFO10.v b/libsrc/hdl/bsv/FIFO10.v index 509acf2a..e318f398 100644 --- a/libsrc/hdl/bsv/FIFO10.v +++ b/libsrc/hdl/bsv/FIFO10.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,29 +19,38 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 24080 $ -// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + // Depth 1 FIFO data size 0! -module FIFO10(CLK, - RST_N, - ENQ, - FULL_N, - DEQ, - EMPTY_N, +module FIFO10(CLK, + RST, + ENQ, + FULL_N, + DEQ, + EMPTY_N, CLR ); parameter guarded = 1; input CLK; - input RST_N; + input RST; input ENQ; input DEQ; input CLR ; @@ -52,26 +61,26 @@ module FIFO10(CLK, reg empty_reg ; assign EMPTY_N = empty_reg ; - + `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS // synopsys translate_off - initial + initial begin empty_reg = 1'b0; end // initial begin // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS - + assign FULL_N = !empty_reg; - always@(posedge CLK /* or negedge RST_N */) + always@(posedge CLK /* or `BSV_RESET_EDGE RST */) begin - if (!RST_N) + if (RST == `BSV_RESET_VALUE) begin empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; - end // if (RST_N == 0) + end // if (RST == `BSV_RESET_VALUE) else begin if (CLR) @@ -86,29 +95,29 @@ module FIFO10(CLK, begin empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; end // if (DEQ) - end // else: !if(RST_N == 0) - end // always@ (posedge CLK or negedge RST_N) - + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) + // synopsys translate_off always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; - + deqerror = 0; enqerror = 0; - if ( RST_N ) + if (RST == ! `BSV_RESET_VALUE) begin if ( ! empty_reg && DEQ ) begin - deqerror = 1 ; + deqerror = 1 ; $display( "Warning: FIFO10: %m -- Dequeuing from empty fifo" ) ; end if ( ! FULL_N && ENQ && (!DEQ || guarded) ) begin - enqerror = 1 ; + enqerror = 1 ; $display( "Warning: FIFO10: %m -- Enqueuing to a full fifo" ) ; end - end // if ( RST_N ) + end // if (RST == ! `BSV_RESET_VALUE) end // synopsys translate_on diff --git a/libsrc/hdl/bsv/FIFO2.v b/libsrc/hdl/bsv/FIFO2.v index 4985586e..6a1d608b 100644 --- a/libsrc/hdl/bsv/FIFO2.v +++ b/libsrc/hdl/bsv/FIFO2.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,18 +19,27 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 24080 $ -// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + // Depth 2 FIFO module FIFO2(CLK, - RST_N, + RST, D_IN, ENQ, FULL_N, @@ -43,7 +52,7 @@ module FIFO2(CLK, parameter guarded = 1; input CLK ; - input RST_N ; + input RST ; input [width - 1 : 0] D_IN; input ENQ; input DEQ; @@ -82,13 +91,13 @@ module FIFO2(CLK, // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS - always@(posedge CLK /* or negedge RST_N */) + always@(posedge CLK /* or `BSV_RESET_EDGE RST */) begin - if (!RST_N) + if (RST == `BSV_RESET_VALUE) begin empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - end // if (RST_N == 0) + end // if (RST == `BSV_RESET_VALUE) else begin if (CLR) @@ -106,18 +115,18 @@ module FIFO2(CLK, full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg; end // if ( DEQ && ! ENQ ) - end // else: !if(RST_N == 0) + end // else: !if(RST == `BSV_RESET_VALUE) - end // always@ (posedge CLK or negedge RST_N) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - always@(posedge CLK /* or negedge RST_N */ ) + always@(posedge CLK /* or `BSV_RESET_EDGE RST */ ) begin // Following section initializes the data registers which // may be desired only in some situations. // Uncomment to initialize array /* - if (!RST_N) + if (RST == `BSV_RESET_VALUE) begin data0_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ; data1_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ; @@ -129,8 +138,8 @@ module FIFO2(CLK, {width{d0di}} & D_IN | {width{d0d1}} & data1_reg | {width{d0h}} & data0_reg ; data1_reg <= `BSV_ASSIGNMENT_DELAY d1di ? D_IN : data1_reg ; - end // else: !if(RST_N == 0) - end // always@ (posedge CLK or negedge RST_N) + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) @@ -141,7 +150,7 @@ module FIFO2(CLK, deqerror = 0; enqerror = 0; - if ( RST_N ) + if (RST == ! `BSV_RESET_VALUE) begin if ( ! empty_reg && DEQ ) begin diff --git a/libsrc/hdl/bsv/FIFO20.v b/libsrc/hdl/bsv/FIFO20.v index 49d8ad94..0136ea21 100644 --- a/libsrc/hdl/bsv/FIFO20.v +++ b/libsrc/hdl/bsv/FIFO20.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,27 +19,36 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 17872 $ -// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif + // Depth 2 FIFO Data width 0 -module FIFO20(CLK, - RST_N, - ENQ, - FULL_N, - DEQ, - EMPTY_N, +module FIFO20(CLK, + RST, + ENQ, + FULL_N, + DEQ, + EMPTY_N, CLR ); parameter guarded = 1; - input RST_N; + input RST; input CLK; input ENQ; input CLR; @@ -53,66 +62,66 @@ module FIFO20(CLK, assign FULL_N = full_reg ; assign EMPTY_N = empty_reg ; - + `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS // synopsys translate_off - initial + initial begin empty_reg = 1'b0 ; full_reg = 1'b1 ; end // initial begin - // synopsys translate_on + // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS - always@(posedge CLK /* or negedge RST_N */) + always@(posedge CLK /* or `BSV_RESET_EDGE RST */) begin - if (!RST_N) + if (RST == `BSV_RESET_VALUE) begin empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - end // if (RST_N == 0) + end // if (RST == `BSV_RESET_VALUE) else begin - if (CLR) + if (CLR) begin empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - end - else if (ENQ && !DEQ) + end + else if (ENQ && !DEQ) begin empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg; - end // if (ENQ && !DEQ) - else if (!ENQ && DEQ) + end // if (ENQ && !DEQ) + else if (!ENQ && DEQ) begin full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg; end // if (!ENQ && DEQ) - end // else: !if(RST_N == 0) - end // always@ (posedge CLK or negedge RST_N) - + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) + // synopsys translate_off always@(posedge CLK) begin: error_checks reg deqerror, enqerror ; - + deqerror = 0; enqerror = 0; - if ( RST_N ) + if (RST == ! `BSV_RESET_VALUE) begin if ( ! empty_reg && DEQ ) begin - deqerror = 1 ; + deqerror = 1 ; $display( "Warning: FIFO20: %m -- Dequeuing from empty fifo" ) ; end if ( ! full_reg && ENQ && (!DEQ || guarded) ) begin - enqerror = 1 ; + enqerror = 1 ; $display( "Warning: FIFO20: %m -- Enqueuing to a full fifo" ) ; end - end // if ( RST_N ) + end // if (RST == ! `BSV_RESET_VALUE) end // synopsys translate_on - + endmodule diff --git a/libsrc/hdl/bsv/MakeReset0.v b/libsrc/hdl/bsv/MakeReset0.v index 8c7904d6..a7e74b5f 100644 --- a/libsrc/hdl/bsv/MakeReset0.v +++ b/libsrc/hdl/bsv/MakeReset0.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,58 +19,67 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 17872 $ -// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $ +// $Revision: 29452 $ +// $Date: 2012-08-27 22:01:48 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif + module MakeReset0 ( CLK, - RST_N, + RST, ASSERT_IN, ASSERT_OUT, - OUT_RST_N + OUT_RST ); - + parameter init = 1 ; input CLK ; - input RST_N ; + input RST ; input ASSERT_IN ; output ASSERT_OUT ; - output OUT_RST_N ; + output OUT_RST ; reg rst ; - assign ASSERT_OUT = !rst ; + assign ASSERT_OUT = rst == `BSV_RESET_VALUE ; - assign OUT_RST_N = rst ; + assign OUT_RST = rst ; - always@(posedge CLK or negedge RST_N) begin - if (RST_N == 0) - rst <= `BSV_ASSIGNMENT_DELAY init; - else + always@(posedge CLK or `BSV_RESET_EDGE RST) begin + if (RST == `BSV_RESET_VALUE) + rst <= `BSV_ASSIGNMENT_DELAY init ? ~ `BSV_RESET_VALUE : `BSV_RESET_VALUE; + else begin if (ASSERT_IN) - rst <= `BSV_ASSIGNMENT_DELAY 1'b0; + rst <= `BSV_ASSIGNMENT_DELAY `BSV_RESET_VALUE; else // if (rst == 1'b0) - rst <= `BSV_ASSIGNMENT_DELAY 1'b1; - end // else: !if(RST_N == 0) - end // always@ (posedge CLK or negedge RST_N) - + rst <= `BSV_ASSIGNMENT_DELAY ~ `BSV_RESET_VALUE; + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) + `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS // synopsys translate_off initial begin #0 ; - rst = 1'b1 ; + rst = ~ `BSV_RESET_VALUE ; end // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS diff --git a/libsrc/hdl/bsv/MakeResetA.v b/libsrc/hdl/bsv/MakeResetA.v index 6d8e4f5a..21b47ecd 100644 --- a/libsrc/hdl/bsv/MakeResetA.v +++ b/libsrc/hdl/bsv/MakeResetA.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,63 +19,72 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 20862 $ -// $Date: 2010-06-07 18:20:35 +0000 (Mon, 07 Jun 2010) $ +// $Revision: 29452 $ +// $Date: 2012-08-27 22:01:48 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + module MakeResetA ( CLK, - RST_N, + RST, ASSERT_IN, ASSERT_OUT, DST_CLK, - OUT_RST_N + OUT_RST ); parameter RSTDELAY = 2 ; // Width of reset shift reg parameter init = 1 ; input CLK ; - input RST_N ; + input RST ; input ASSERT_IN ; output ASSERT_OUT ; input DST_CLK ; - output OUT_RST_N ; + output OUT_RST ; reg rst ; - wire OUT_RST_N ; + wire OUT_RST ; - assign ASSERT_OUT = !rst ; + assign ASSERT_OUT = rst == `BSV_RESET_VALUE ; SyncResetA #(RSTDELAY) rstSync (.CLK(DST_CLK), - .IN_RST_N(rst), - .OUT_RST_N(OUT_RST_N)); + .IN_RST(rst), + .OUT_RST(OUT_RST)); - always@(posedge CLK or negedge RST_N) begin - if (RST_N == 0) - rst <= `BSV_ASSIGNMENT_DELAY init; + always@(posedge CLK or `BSV_RESET_EDGE RST) begin + if (RST == `BSV_RESET_VALUE) + rst <= `BSV_ASSIGNMENT_DELAY init ? ~ `BSV_RESET_VALUE : `BSV_RESET_VALUE ; else begin if (ASSERT_IN) - rst <= `BSV_ASSIGNMENT_DELAY 1'b0; + rst <= `BSV_ASSIGNMENT_DELAY `BSV_RESET_VALUE; else // if (rst == 1'b0) - rst <= `BSV_ASSIGNMENT_DELAY 1'b1; - end // else: !if(RST_N == 0) - end // always@ (posedge CLK or negedge RST_N) + rst <= `BSV_ASSIGNMENT_DELAY ~ `BSV_RESET_VALUE; + end // else: !if(RST == `BSV_RESET_VALUE) + end // always@ (posedge CLK or `BSV_RESET_EDGE RST) `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS // synopsys translate_off initial begin #0 ; - rst = 1'b1 ; + rst = ~ `BSV_RESET_VALUE ; end // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS diff --git a/libsrc/hdl/bsv/ResetEither.v b/libsrc/hdl/bsv/ResetEither.v index e782b867..0e0ead65 100644 --- a/libsrc/hdl/bsv/ResetEither.v +++ b/libsrc/hdl/bsv/ResetEither.v @@ -19,16 +19,26 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 17872 $ -// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $ +// $Revision: 29442 $ +// $Date: 2012-08-27 21:58:10 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + + // A separate module which instantiates a simple reset combining primitive. -// The primitive is simply an AND gate. +// The primitive is simply an AND gate for negative resets, an OR gate for positive resets. module ResetEither(A_RST, B_RST, RST_OUT @@ -39,6 +49,6 @@ module ResetEither(A_RST, output RST_OUT; - assign RST_OUT = A_RST & B_RST ; + assign RST_OUT = ((A_RST == `BSV_RESET_VALUE) || (B_RST == `BSV_RESET_VALUE)) ? `BSV_RESET_VALUE : ~ `BSV_RESET_VALUE; -endmodule +endmodule diff --git a/libsrc/hdl/bsv/ResetToBool.v b/libsrc/hdl/bsv/ResetToBool.v index 52bf0b4b..fc827cf8 100644 --- a/libsrc/hdl/bsv/ResetToBool.v +++ b/libsrc/hdl/bsv/ResetToBool.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,20 +19,28 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 24080 $ -// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $ +// $Revision: 29442 $ +// $Date: 2012-08-27 21:58:10 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + module ResetToBool( RST, VAL); - + input RST; output VAL; - - assign VAL = (RST == 1'b0); - + + assign VAL = (RST == `BSV_RESET_VALUE); + endmodule diff --git a/libsrc/hdl/bsv/SizedFIFO.v b/libsrc/hdl/bsv/SizedFIFO.v index f389335a..27733a6e 100644 --- a/libsrc/hdl/bsv/SizedFIFO.v +++ b/libsrc/hdl/bsv/SizedFIFO.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,26 +19,35 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 24080 $ -// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif + // Sized fifo. Model has output register which improves timing -module SizedFIFO(CLK, RST_N, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); +module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); parameter p1width = 1; // data width parameter p2depth = 3; parameter p3cntr_width = 1; // log(p2depth-1) // The -1 is allowed since this model has a fast output register parameter guarded = 1; - localparam p2depth2 = p2depth -2 ; + localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ; input CLK; - input RST_N; + input RST; input CLR; input [p1width - 1 : 0] D_IN; input ENQ; @@ -59,7 +68,7 @@ module SizedFIFO(CLK, RST_N, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); // if the depth is too small, don't create an ill-sized array; // instead, make a 1-sized array and let the initial block report an error - reg [p1width - 1 : 0] arr[0: ((p2depth >= 2) ? (p2depth2) : 0)]; + reg [p1width - 1 : 0] arr[0: p2depth2]; reg [p1width - 1 : 0] D_OUT; reg hasodata; @@ -92,7 +101,7 @@ module SizedFIFO(CLK, RST_N, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); head = {p3cntr_width {1'b0}} ; tail = {p3cntr_width {1'b0}} ; - for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1) + for (i = 0; i <= p2depth2; i = i + 1) begin arr[i] = D_OUT ; end @@ -100,9 +109,9 @@ module SizedFIFO(CLK, RST_N, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS - always @(posedge CLK /* or negedge RST_N */ ) + always @(posedge CLK /* or `BSV_RESET_EDGE RST */ ) begin - if (!RST_N) + if (RST == `BSV_RESET_VALUE) begin head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; @@ -120,7 +129,7 @@ module SizedFIFO(CLK, RST_N, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ; end */ - end // if (RST_N == 0) + end // if (RST == `BSV_RESET_VALUE) else begin @@ -190,8 +199,7 @@ module SizedFIFO(CLK, RST_N, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ; end end // if (ENQ) - end // else: !if(RST_N == 0) - + end // else: !if(RST == `BSV_RESET_VALUE) end // always @ (posedge CLK) // synopsys translate_off @@ -201,7 +209,7 @@ module SizedFIFO(CLK, RST_N, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); deqerror = 0; enqerror = 0; - if ( RST_N ) + if (RST == ! `BSV_RESET_VALUE) begin if ( ! EMPTY_N && DEQ ) begin @@ -224,16 +232,16 @@ module SizedFIFO(CLK, RST_N, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); integer ok ; ok = 1 ; - if ( p2depth <= 2 ) + if ( p2depth <= 1) begin ok = 0; - $display ( "ERROR SizedFIFO.v: depth parameter must be greater than 2" ) ; + $display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth); end if ( p3cntr_width <= 0 ) begin ok = 0; - $display ( "ERROR SizedFIFO.v: width parameter must be greater than 0" ) ; + $display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ; end if ( ok == 0 ) $finish ; diff --git a/libsrc/hdl/bsv/SyncBit.v b/libsrc/hdl/bsv/SyncBit.v index 04339007..acf02484 100644 --- a/libsrc/hdl/bsv/SyncBit.v +++ b/libsrc/hdl/bsv/SyncBit.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,75 +19,84 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 17872 $ -// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif + // A one bit data synchronization module, where data is synchronized // by passing through 2 registers of the destination clock module SyncBit ( sCLK, - sRST_N, + sRST, dCLK, sEN, sD_IN, dD_OUT ); parameter init = 1'b0; // initial value for all registers - + // Signals on source clock (sCLK) input sCLK; - input sRST_N; + input sRST; input sEN; input sD_IN; - + // Signals on destination clock (dCLK) input dCLK; output dD_OUT; - + reg sSyncReg; reg dSyncReg1, dSyncReg2; - + assign dD_OUT = dSyncReg2 ; - always @(posedge sCLK or negedge sRST_N) + always @(posedge sCLK or `BSV_RESET_EDGE sRST) begin - if (sRST_N ==0) + if (sRST == `BSV_RESET_VALUE) begin sSyncReg <= `BSV_ASSIGNMENT_DELAY init ; - end // if (sRST_N ==0) + end // if (sRST == `BSV_RESET_VALUE) else begin if ( sEN ) begin sSyncReg <= `BSV_ASSIGNMENT_DELAY (sD_IN == 1'b1) ? 1'b1 : 1'b0 ; end // if ( sEN ) - end // else: !if(sRST_N ==0) - end // always @ (posedge sCLK or negedge sRST_N) + end // else: !if(sRST == `BSV_RESET_VALUE) + end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST) - always @(posedge dCLK or negedge sRST_N) + always @(posedge dCLK or `BSV_RESET_EDGE sRST) begin - if (sRST_N ==0) + if (sRST == `BSV_RESET_VALUE) begin dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init ; dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init ; - end // if (sRST_N ==0) + end // if (sRST == `BSV_RESET_VALUE) else begin dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ; // clock domain crossing dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ; - end // else: !if(sRST_N ==0) - end // always @ (posedge dCLK or negedge sRST_N) + end // else: !if(sRST == `BSV_RESET_VALUE) + end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST) + - `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off + // synopsys translate_off initial begin sSyncReg = init ; diff --git a/libsrc/hdl/bsv/SyncFIFO.v b/libsrc/hdl/bsv/SyncFIFO.v index d17ebdd8..86a7d1dd 100644 --- a/libsrc/hdl/bsv/SyncFIFO.v +++ b/libsrc/hdl/bsv/SyncFIFO.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2010 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,14 +19,23 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 24080 $ -// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + // A clock synchronization FIFO where the enqueue and dequeue sides are in // different clock domains. // There are no restrictions w.r.t. clock frequencies @@ -37,7 +46,7 @@ // is delayed due to synchronization latency. module SyncFIFO( sCLK, - sRST_N, + sRST, dCLK, sENQ, sD_IN, @@ -54,7 +63,7 @@ module SyncFIFO( // input clock domain ports input sCLK ; - input sRST_N ; + input sRST ; input sENQ ; input [dataWidth -1 : 0] sD_IN ; output sFULL_N ; @@ -85,7 +94,7 @@ module SyncFIFO( wire dNextNotEmpty; // Reset generation - wire dRST_N ; + wire dRST ; // flops to sychronize enqueue and dequeue point across domains reg [indxWidth : 0] dSyncReg1, dEnqPtr ; @@ -94,7 +103,7 @@ module SyncFIFO( wire [indxWidth - 1 :0] sEnqPtrIndx, dDeqPtrIndx ; // Resets - assign dRST_N = sRST_N ; + assign dRST = sRST ; // Outputs assign dD_OUT = dDoutReg ; @@ -117,14 +126,14 @@ module SyncFIFO( assign sNextNotFull = (sGEnqPtr [indxWidth+1:1] ^ msb12set) != sDeqPtr ; assign sFutureNotFull = (sGEnqPtr1[indxWidth+1:1] ^ msb12set) != sDeqPtr ; - always @(posedge sCLK or negedge sRST_N) + always @(posedge sCLK or `BSV_RESET_EDGE sRST) begin - if (sRST_N == 0) + if (sRST == `BSV_RESET_VALUE) begin sGEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth +2 ) {1'b0}} ; sGEnqPtr1 <= `BSV_ASSIGNMENT_DELAY { {indxWidth {1'b0}}, 2'b11} ; sNotFullReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ; // Mark as full during reset to avoid spurious loads - end // if (sRST_N == 0) + end // if (sRST == `BSV_RESET_VALUE) else begin if ( sENQ ) @@ -137,24 +146,24 @@ module SyncFIFO( begin sNotFullReg <= `BSV_ASSIGNMENT_DELAY sNextNotFull ; end // else: !if( sENQ ) - end // else: !if(sRST_N == 0) - end // always @ (posedge sCLK or negedge sRST_N) + end // else: !if(sRST == `BSV_RESET_VALUE) + end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST) // Enqueue pointer synchronizer to dCLK - always @(posedge dCLK or negedge dRST_N) + always @(posedge dCLK or `BSV_RESET_EDGE dRST) begin - if (dRST_N == 0) + if (dRST == `BSV_RESET_VALUE) begin dSyncReg1 <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ; dEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ; - end // if (dRST_N == 0) + end // if (dRST == `BSV_RESET_VALUE) else begin dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sGEnqPtr[indxWidth+1:1] ; // Clock domain crossing dEnqPtr <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ; - end // else: !if(dRST_N == 0) - end // always @ (posedge dCLK or negedge dRST_N) + end // else: !if(dRST == `BSV_RESET_VALUE) + end // always @ (posedge dCLK or `BSV_RESET_EDGE dRST) //////////////////////////////////////////////////////////////////////// @@ -162,14 +171,14 @@ module SyncFIFO( // Enqueue Pointer and increment logic assign dNextNotEmpty = dGDeqPtr[indxWidth+1:1] != dEnqPtr ; - always @(posedge dCLK or negedge dRST_N) + always @(posedge dCLK or `BSV_RESET_EDGE dRST) begin - if (dRST_N == 0) + if (dRST == `BSV_RESET_VALUE) begin dGDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 2) {1'b0}} ; dGDeqPtr1 <= `BSV_ASSIGNMENT_DELAY {{indxWidth {1'b0}}, 2'b11 } ; dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ; - end // if (dRST_N == 0) + end // if (dRST == `BSV_RESET_VALUE) else begin if ((!dNotEmptyReg || dDEQ) && dNextNotEmpty) begin @@ -181,23 +190,23 @@ module SyncFIFO( else if (dDEQ && !dNextNotEmpty) begin dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0; end - end // else: !if(dRST_N == 0) - end // always @ (posedge dCLK or negedge dRST_N) + end // else: !if(dRST == `BSV_RESET_VALUE) + end // always @ (posedge dCLK or `BSV_RESET_EDGE dRST) // Dequeue pointer synchronized to sCLK - always @(posedge sCLK or negedge sRST_N) + always @(posedge sCLK or `BSV_RESET_EDGE sRST) begin - if (sRST_N == 0) + if (sRST == `BSV_RESET_VALUE) begin sSyncReg1 <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ; sDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ; // When reset mark as not empty - end // if (sRST_N == 0) + end // if (sRST == `BSV_RESET_VALUE) else begin sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dGDeqPtr[indxWidth+1:1] ; // clock domain crossing sDeqPtr <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ; - end // else: !if(sRST_N == 0) - end // always @ (posedge sCLK or negedge sRST_N) + end // else: !if(sRST == `BSV_RESET_VALUE) + end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST) //////////////////////////////////////////////////////////////////////// `ifdef BSV_NO_INITIAL_BLOCKS @@ -308,13 +317,13 @@ module testSyncFIFO() ; parameter fifodepth = 32; parameter fifoidx = 5; - wire sCLK, dCLK, dRST_N ; + wire sCLK, dCLK, dRST ; wire sENQ, dDEQ; wire sFULL_N, dEMPTY_N ; wire [dsize -1:0] sDIN, dDOUT ; reg [dsize -1:0] sCNT, dCNT ; - reg sRST_N, sCLR ; + reg sRST, sCLR ; ClockGen#(15,14,10) sc( sCLK ); ClockGen#(11,12,2600) dc( dCLK ); @@ -325,14 +334,14 @@ module testSyncFIFO() ; dCNT = 0; sCLR = 1'b0 ; - sRST_N = 0 ; + sRST = `BSV_RESET_VALUE ; $display( "running test" ) ; $dumpfile("SyncFIFO.vcd"); $dumpvars(5,testSyncFIFO) ; $dumpon ; #200 ; - sRST_N = 1 ; + sRST = !`BSV_RESET_VALUE ; #100000 $finish ; @@ -348,7 +357,7 @@ module testSyncFIFO() ; end SyncFIFO #(dsize,fifodepth,fifoidx) - dut( sCLK, sRST_N, dCLK, sENQ, sDIN, + dut( sCLK, sRST, dCLK, sENQ, sDIN, sFULL_N, // sCLR, dDEQ, dDOUT, dEMPTY_N ); diff --git a/libsrc/hdl/bsv/SyncHandshake.v b/libsrc/hdl/bsv/SyncHandshake.v index f2a85fb7..267b9e3c 100644 --- a/libsrc/hdl/bsv/SyncHandshake.v +++ b/libsrc/hdl/bsv/SyncHandshake.v @@ -1,4 +1,4 @@ -// Copyright (c) 2000-2011 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -18,20 +18,29 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 23129 $ -// $Date: 2011-02-04 14:48:46 +0000 (Fri, 04 Feb 2011) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + // // Transfer takes 2 dCLK to see data, // sRDY recovers takes 2 dCLK + 2 sCLK module SyncHandshake( sCLK, - sRST_N, + sRST, dCLK, sEN, sRDY, @@ -41,7 +50,7 @@ module SyncHandshake( // Source clock port signal input sCLK ; - input sRST_N ; + input sRST ; input sEN ; output sRDY ; @@ -59,9 +68,9 @@ module SyncHandshake( assign dPulse = dSyncReg2 != dLastState ; assign sRDY = sSyncReg2 == sToggleReg; - always @(posedge sCLK or negedge sRST_N) + always @(posedge sCLK or `BSV_RESET_EDGE sRST) begin - if (sRST_N == 0) + if (sRST == `BSV_RESET_VALUE) begin sSyncReg1 <= `BSV_ASSIGNMENT_DELAY ! init ; // Reset hi so sRDY is low during reset sSyncReg2 <= `BSV_ASSIGNMENT_DELAY ! init ; @@ -81,11 +90,11 @@ module SyncHandshake( end // if ( sEN ) end - end // always @ (posedge sCLK or negedge sRST_N) + end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST) - always @(posedge dCLK or negedge sRST_N) + always @(posedge dCLK or `BSV_RESET_EDGE sRST) begin - if (sRST_N == 0) + if (sRST == `BSV_RESET_VALUE) begin dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init; dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init; @@ -97,7 +106,7 @@ module SyncHandshake( dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ; dLastState <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ; end - end // always @ (posedge dCLK or negedge sRST_N) + end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST) `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS diff --git a/libsrc/hdl/bsv/SyncPulse.v b/libsrc/hdl/bsv/SyncPulse.v index 781037fd..f60407e2 100644 --- a/libsrc/hdl/bsv/SyncPulse.v +++ b/libsrc/hdl/bsv/SyncPulse.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,25 +19,34 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 17872 $ -// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + // A pulse based clock domain synchronization scheme. // When a sEN is asserted, a pulse is eventually sent to dPulse in the // destination clock domain. // Close and Multiple asserts of sEN may not be seen at the destination side. // Reset signal is not needed since it a pulse-based, rather than // level-based protocol -// Delay is 2 dCLK cycle. +// Delay is 2 dCLK cycle. // dPulse is not registered. module SyncPulse( sCLK, - sRST_N, + sRST, dCLK, sEN, dPulse @@ -45,23 +54,23 @@ module SyncPulse( // source clock ports input sCLK ; - input sRST_N ; + input sRST ; input sEN ; - + // destination clock ports input dCLK ; output dPulse ; - + // Flops to hold data reg sSyncReg; reg dSyncReg1, dSyncReg2; reg dSyncPulse; - + assign dPulse = dSyncReg2 != dSyncPulse ; - - always @(posedge sCLK or negedge sRST_N) + + always @(posedge sCLK or `BSV_RESET_EDGE sRST) begin - if (sRST_N == 0) + if (sRST == `BSV_RESET_VALUE) sSyncReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ; else begin @@ -69,26 +78,26 @@ module SyncPulse( begin sSyncReg <= `BSV_ASSIGNMENT_DELAY ! sSyncReg ; end - end // else: !if(sRST_N == 0) - end // always @ (posedge sCLK or negedge sRST_N) + end // else: !if(sRST == `BSV_RESET_VALUE) + end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST) - always @(posedge dCLK or negedge sRST_N ) + always @(posedge dCLK or `BSV_RESET_EDGE sRST ) begin - if (sRST_N == 0) + if (sRST == `BSV_RESET_VALUE) begin - dSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0 ; + dSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0 ; dSyncReg2 <= `BSV_ASSIGNMENT_DELAY 1'b0 ; dSyncPulse <= `BSV_ASSIGNMENT_DELAY 1'b0 ; - end // if (sRST_N == 0) + end // if (sRST == `BSV_RESET_VALUE) else begin dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ;// domain crossing dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ; dSyncPulse <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ; - end // else: !if(sRST_N == 0) - end // always @ (posedge dCLK or negedge sRST_N ) - + end // else: !if(sRST == `BSV_RESET_VALUE) + end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST ) + `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS // synopsys translate_off diff --git a/libsrc/hdl/bsv/SyncRegister.v b/libsrc/hdl/bsv/SyncRegister.v index 4a845ace..2e64221e 100644 --- a/libsrc/hdl/bsv/SyncRegister.v +++ b/libsrc/hdl/bsv/SyncRegister.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,14 +19,23 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 17872 $ -// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + // A register synchronization module across clock domains. // Uses a Handshake Pulse protocol to trigger the load on // destination side registers @@ -34,7 +43,7 @@ // sRDY recovers takes 3 dCLK + 3 sCLK module SyncRegister( sCLK, - sRST_N, + sRST, dCLK, sEN, sRDY, @@ -43,14 +52,14 @@ module SyncRegister( ); parameter width = 1 ; parameter init = { width {1'b0 }} ; - + // Source clock domain ports input sCLK ; - input sRST_N ; + input sRST ; input sEN ; input [width -1 : 0] sD_IN ; output sRDY ; - + // Destination clock domain ports input dCLK ; output [width -1 : 0] dD_OUT ; @@ -60,53 +69,53 @@ module SyncRegister( reg [width -1 : 0] dD_OUT ; // instantiate a Handshake Sync - SyncHandshake sync( .sCLK(sCLK), .sRST_N(sRST_N), + SyncHandshake sync( .sCLK(sCLK), .sRST(sRST), .dCLK(dCLK), .sEN(sEN), .sRDY(sRDY), .dPulse(dPulse) ) ; - always @(posedge sCLK or negedge sRST_N) + always @(posedge sCLK or `BSV_RESET_EDGE sRST) begin - if (sRST_N == 0) + if (sRST == `BSV_RESET_VALUE) begin sDataSyncIn <= `BSV_ASSIGNMENT_DELAY init ; - end // if (sRST_N == 0) + end // if (sRST == `BSV_RESET_VALUE) else begin if ( sEN ) begin sDataSyncIn <= `BSV_ASSIGNMENT_DELAY sD_IN ; end // if ( sEN ) - end // else: !if(sRST_N == 0) - end // always @ (posedge sCLK or negedge sRST_N) - + end // else: !if(sRST == `BSV_RESET_VALUE) + end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST) + // Transfer the data to destination domain when dPulsed is asserted. // Setup and hold time are assured since at least 2 dClks occured since // sDataSyncIn have been written. - always @(posedge dCLK or negedge sRST_N) + always @(posedge dCLK or `BSV_RESET_EDGE sRST) begin - if (sRST_N == 0) + if (sRST == `BSV_RESET_VALUE) begin dD_OUT <= `BSV_ASSIGNMENT_DELAY init ; - end // if (sRST_N == 0) + end // if (sRST == `BSV_RESET_VALUE) else begin if ( dPulse ) begin dD_OUT <= `BSV_ASSIGNMENT_DELAY sDataSyncIn ;// clock domain crossing end // if ( dPulse ) - end // else: !if(sRST_N == 0) - end // always @ (posedge dCLK or negedge sRST_N) + end // else: !if(sRST == `BSV_RESET_VALUE) + end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST) `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off + // synopsys translate_off initial begin sDataSyncIn = {((width + 1)/2){2'b10}} ; - dD_OUT = {((width + 1)/2){2'b10}} ; + dD_OUT = {((width + 1)/2){2'b10}} ; end // initial begin // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS @@ -114,41 +123,41 @@ module SyncRegister( endmodule // RegisterSync - - + + `ifdef testBluespec module testSyncRegister() ; parameter dsize = 8; - - wire sCLK, sRST_N, dCLK ; + + wire sCLK, sRST, dCLK ; wire sEN ; wire sRDY ; - + reg [dsize -1:0] sCNT ; wire [dsize -1:0] sDIN, dDOUT ; - + ClockGen#(20,9,10) sc( sCLK ); ClockGen#(11,12,26) dc( dCLK ); initial begin sCNT = 0; - + $dumpfile("SyncRegister.dump"); $dumpvars(5) ; $dumpon ; #100000 $finish ; end - + SyncRegister #(dsize) - dut( sCLK, sRST_N, dCLK, + dut( sCLK, sRST, dCLK, sEN, sRDY, sDIN, dDOUT ) ; - - + + assign sDIN = sCNT ; assign sEN = sRDY ; - + always @(posedge sCLK) begin if (sRDY ) @@ -157,9 +166,9 @@ module testSyncRegister() ; end end // always @ (posedge sCLK) - - + + endmodule // testSyncFIFO `endif - - + + diff --git a/libsrc/hdl/bsv/SyncReset0.v b/libsrc/hdl/bsv/SyncReset0.v index aaeee5a6..0b958f15 100644 --- a/libsrc/hdl/bsv/SyncReset0.v +++ b/libsrc/hdl/bsv/SyncReset0.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,23 +19,32 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 17872 $ -// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $ +// $Revision: 29441 $ +// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + module SyncReset0 ( - IN_RST_N, - OUT_RST_N + IN_RST, + OUT_RST ); - input IN_RST_N ; - output OUT_RST_N ; + input IN_RST ; + output OUT_RST ; - assign OUT_RST_N = IN_RST_N ; + assign OUT_RST = IN_RST ; endmodule diff --git a/libsrc/hdl/bsv/SyncResetA.v b/libsrc/hdl/bsv/SyncResetA.v index 7f2b535d..66da2015 100644 --- a/libsrc/hdl/bsv/SyncResetA.v +++ b/libsrc/hdl/bsv/SyncResetA.v @@ -1,5 +1,5 @@ -// Copyright (c) 2000-2009 Bluespec, Inc. +// Copyright (c) 2000-2012 Bluespec, Inc. // Permission is hereby granted, free of charge, to any person obtaining a copy // of this software and associated documentation files (the "Software"), to deal @@ -19,45 +19,55 @@ // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN // THE SOFTWARE. // -// $Revision: 20862 $ -// $Date: 2010-06-07 18:20:35 +0000 (Mon, 07 Jun 2010) $ +// $Revision: 29452 $ +// $Date: 2012-08-27 22:01:48 +0000 (Mon, 27 Aug 2012) $ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY `endif +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + + // A synchronization module for resets. Output resets are held for // RSTDELAY+1 cycles, RSTDELAY >= 0. Reset assertion is asynchronous, // while deassertion is synchronized to the clock. module SyncResetA ( - IN_RST_N, + IN_RST, CLK, - OUT_RST_N + OUT_RST ); parameter RSTDELAY = 1 ; // Width of reset shift reg input CLK ; - input IN_RST_N ; - output OUT_RST_N ; + input IN_RST ; + output OUT_RST ; reg [RSTDELAY:0] reset_hold ; + wire [RSTDELAY+1:0] next_reset = {reset_hold, ~ `BSV_RESET_VALUE} ; - assign OUT_RST_N = reset_hold[RSTDELAY] ; + assign OUT_RST = reset_hold[RSTDELAY] ; - always @( posedge CLK or negedge IN_RST_N ) + always @( posedge CLK or `BSV_RESET_EDGE IN_RST ) begin - if (!IN_RST_N) + if (IN_RST == `BSV_RESET_VALUE) begin - reset_hold <= `BSV_ASSIGNMENT_DELAY 'b0 ; + reset_hold <= `BSV_ASSIGNMENT_DELAY {RSTDELAY+1 {`BSV_RESET_VALUE}} ; end else begin - reset_hold <= `BSV_ASSIGNMENT_DELAY ( reset_hold << 1'b1 ) | 'b1 ; + reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:0]; end - end // always @ ( posedge CLK or negedge IN_RST_N ) + end // always @ ( posedge CLK or `BSV_RESET_EDGE IN_RST ) `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS @@ -66,7 +76,7 @@ module SyncResetA ( begin #0 ; // initialize out of reset forcing the designer to do one - reset_hold = {(RSTDELAY + 1) {1'b1}} ; + reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE}} ; end // synopsys translate_on `endif // BSV_NO_INITIAL_BLOCKS diff --git a/logs/n210-20120924_1532/fpgaTop-n210.srp b/logs/n210-20120924_1532/fpgaTop-n210.srp new file mode 100644 index 00000000..cbb5d4f5 --- /dev/null +++ b/logs/n210-20120924_1532/fpgaTop-n210.srp @@ -0,0 +1,409 @@ +Release 14.2 - xst P.28xd (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +--> + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) Partition Resource Summary + 9.3) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpgaTop-n210.prj" +Input Format : mixed + +---- Target Parameters +Output File Name : "fpgaTop" +Output Format : NGC +Target Device : xc3sd3400a-fg676-5 + +---- Source Options +Top Module Name : fpgaTop +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Use DSP Block : auto +Automatic Register Balancing : NO + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 32 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Library Search Order : work.lso +Keep Hierarchy : soft +Netlist Hierarchy : rebuilt +RTL Output : Yes +Read Cores : optimize +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "../../libsrc/hdl/bsv/BRAM1BE.v" in library work +Compiling verilog file "../../libsrc/hdl/bsv/BRAM1.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BRAM1Load.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BRAM2.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BypassCrossingWire.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BypassWire.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ClockDiv.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ClockInverter.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/Counter.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO10.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO1.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO20.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO2.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/MakeReset0.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/MakeResetA.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ResetEither.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ResetInverter.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ResetToBool.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/RevertReg.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SizedFIFO.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncBit.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncFIFO.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncHandshake.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncPulse.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncRegister.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncReset0.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncResetA.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/TriState.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkCRC32.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkGMAC.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkQBGMAC.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkGbeWrk.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkGbeQABS.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkQABSMF3.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkEDCPAdapter.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkEDDPAdapter.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkOCCP.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkOCEDP4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkLedN210.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkIQADCWorker.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkWSICaptureWorker4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkWSIPatternWorker4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkBiasWorker4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkSMAdapter4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkPWrk_n210.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkFTop_n210.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/n210_uuid.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/arSRLFIFOD.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/clock_n210.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/fpgaTop_n210.v" in library work +Module compiled +Module compiled +No errors in compilation +Analysis of file <"fpgaTop-n210.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +ERROR:HDLCompilers:91 - "../../rtl/mkBiasWorker4B.v" line 614 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkBiasWorker4B.v" line 628 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5087 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5098 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5109 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5120 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5131 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5142 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5153 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5187 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5200 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5210 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5220 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5230 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5240 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5249 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5259 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5269 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5280 Module 'SyncFIFO' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5290 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5294 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5298 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5302 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5306 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5310 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5314 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5318 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5322 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5326 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5330 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5334 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5338 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5342 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5346 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5350 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5354 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5358 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5362 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5366 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5370 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5374 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5378 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5382 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5386 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5390 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5394 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5398 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5402 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5406 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5409 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5420 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5431 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5442 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5453 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5464 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5475 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5486 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5497 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5508 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5519 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5530 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5541 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5552 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCCP.v" line 5563 Module 'FIFO1' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDCPAdapter.v" line 386 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDCPAdapter.v" line 397 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDCPAdapter.v" line 408 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDCPAdapter.v" line 419 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDCPAdapter.v" line 430 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDCPAdapter.v" line 441 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDCPAdapter.v" line 452 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDDPAdapter.v" line 380 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDDPAdapter.v" line 391 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDDPAdapter.v" line 402 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDDPAdapter.v" line 413 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDDPAdapter.v" line 380 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDDPAdapter.v" line 391 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDDPAdapter.v" line 402 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkEDDPAdapter.v" line 413 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2377 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2391 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2405 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2419 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2433 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2447 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2461 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2475 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2486 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2497 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2525 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2536 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2547 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2558 Module 'FIFO20' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2567 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2578 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2589 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2600 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2614 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2628 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2642 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2656 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2377 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2391 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2405 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2419 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2433 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2447 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2461 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2475 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2486 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2497 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2525 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2536 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2547 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2558 Module 'FIFO20' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2567 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2578 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2589 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2600 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2614 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2628 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2642 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkOCEDP4B.v" line 2656 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 611 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 622 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 633 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 644 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 655 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 666 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 677 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 688 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 699 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 710 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 721 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQABSMF3.v" line 732 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGbeQABS.v" line 526 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGbeQABS.v" line 537 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 603 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 611 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 619 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 626 Module 'SyncResetA' does not have a port named 'IN_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 627 Module 'SyncResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 646 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 656 Module 'SyncFIFO' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 667 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 674 Module 'SyncResetA' does not have a port named 'IN_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 675 Module 'SyncResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 865 Module 'SyncFIFO' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 876 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 883 Module 'SyncResetA' does not have a port named 'IN_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 884 Module 'SyncResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGMAC.v" line 889 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkQBGMAC.v" line 438 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkQBGMAC.v" line 448 Module 'SyncFIFO' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkQBGMAC.v" line 459 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkQBGMAC.v" line 465 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQBGMAC.v" line 476 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQBGMAC.v" line 491 Module 'SyncFIFO' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkQBGMAC.v" line 502 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkQBGMAC.v" line 508 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQBGMAC.v" line 519 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkQBGMAC.v" line 532 Module 'SyncBit' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkGbeQABS.v" line 585 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGbeQABS.v" line 596 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGbeQABS.v" line 608 Module 'Counter' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGbeQABS.v" line 621 Module 'Counter' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGbeQABS.v" line 646 Module 'MakeResetA' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGbeQABS.v" line 650 Module 'MakeResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkGbeWrk.v" line 301 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkFTop_n210.v" line 1420 Module 'SyncResetA' does not have a port named 'IN_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkFTop_n210.v" line 1421 Module 'SyncResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1315 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1325 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1347 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1357 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1364 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1378 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1403 Module 'SyncResetA' does not have a port named 'IN_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1404 Module 'SyncResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1411 Module 'ClockDiv' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1426 Module 'SyncReset0' does not have a port named 'IN_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1427 Module 'SyncReset0' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1439 Module 'SyncReset0' does not have a port named 'IN_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1440 Module 'SyncReset0' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1452 Module 'SyncReset0' does not have a port named 'IN_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1453 Module 'SyncReset0' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1465 Module 'SyncReset0' does not have a port named 'IN_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1466 Module 'SyncReset0' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1474 Module 'SyncResetA' does not have a port named 'IN_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1475 Module 'SyncResetA' does not have a port named 'OUT_RST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1481 Module 'SyncRegister' does not have a port named 'sRST' +ERROR:HDLCompilers:91 - "../../rtl/mkIQADCWorker.v" line 1491 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkPWrk_n210.v" line 535 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkPWrk_n210.v" line 546 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkPWrk_n210.v" line 560 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkPWrk_n210.v" line 574 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkPWrk_n210.v" line 586 Module 'Counter' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkPWrk_n210.v" line 599 Module 'Counter' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkPWrk_n210.v" line 626 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkSMAdapter4B.v" line 1132 Module 'FIFO10' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkSMAdapter4B.v" line 1161 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkSMAdapter4B.v" line 1172 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkSMAdapter4B.v" line 1186 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkSMAdapter4B.v" line 1132 Module 'FIFO10' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkSMAdapter4B.v" line 1161 Module 'SizedFIFO' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkSMAdapter4B.v" line 1172 Module 'FIFO2' does not have a port named 'RST' +ERROR:HDLCompilers:91 - "../../rtl/mkSMAdapter4B.v" line 1186 Module 'SizedFIFO' does not have a port named 'RST' +--> + + +Total memory usage is 578288 kilobytes + +Number of errors : 207 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/logs/n210-20120924_1532/fpgaTop.bld b/logs/n210-20120924_1532/fpgaTop.bld new file mode 100644 index 00000000..c59c16ce --- /dev/null +++ b/logs/n210-20120924_1532/fpgaTop.bld @@ -0,0 +1,18 @@ +Release 14.2 ngdbuild P.28xd (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +Command Line: /opt/Xilinx/14.2/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -sd +../../coregen/pcie_4243_axi_k6_gtx_x4_250 -sd ../../coregen/fft_v5_4k_strm_nat +-sd ../../coregen/ddc_4243_4ch_v5 -aul -aut -uc n210.ucf -p xc3sd3400a-fg676-5 +fpgaTop_csi.ngc fpgaTop.ngd + +WARNING:NgdBuild:257 - Launcher: Could not find the file + "/home/shep/projects/ocpi/build/tmp-n210/fpgaTop_csi" with extension "ngc" in + the search path. +ERROR:NgdBuild:1364 - Top-level input design file "fpgaTop_csi.ngc" cannot be + found or created. Please make sure the source file exists and is of a + recognized netlist format (e.g., ngo, ngc, edif, edn, or edf). +Total REAL time to NGDBUILD completion: 1 sec +Total CPU time to NGDBUILD completion: 1 sec + +Writing NGDBUILD log file "fpgaTop.bld"... diff --git a/logs/n210-20120924_1549/fpgaTop-n210.srp b/logs/n210-20120924_1549/fpgaTop-n210.srp new file mode 100644 index 00000000..0d16f33e --- /dev/null +++ b/logs/n210-20120924_1549/fpgaTop-n210.srp @@ -0,0 +1,7047 @@ +Release 14.2 - xst P.28xd (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +--> + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) Partition Resource Summary + 9.3) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpgaTop-n210.prj" +Input Format : mixed + +---- Target Parameters +Output File Name : "fpgaTop" +Output Format : NGC +Target Device : xc3sd3400a-fg676-5 + +---- Source Options +Top Module Name : fpgaTop +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Use DSP Block : auto +Automatic Register Balancing : NO + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 32 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Library Search Order : work.lso +Keep Hierarchy : soft +Netlist Hierarchy : rebuilt +RTL Output : Yes +Read Cores : optimize +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "../../libsrc/hdl/bsv/BRAM1BE.v" in library work +Compiling verilog file "../../libsrc/hdl/bsv/BRAM1.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BRAM1Load.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BRAM2.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BypassCrossingWire.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BypassWire.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ClockDiv.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ClockInverter.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/Counter.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO10.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO1.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO20.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO2.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/MakeReset0.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/MakeResetA.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ResetEither.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ResetInverter.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ResetToBool.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/RevertReg.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SizedFIFO.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncBit.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncFIFO.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncHandshake.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncPulse.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncRegister.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncReset0.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncResetA.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/TriState.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkCRC32.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkGMAC.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkQBGMAC.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkGbeWrk.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkGbeQABS.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkQABSMF3.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkEDCPAdapter.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkEDDPAdapter.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkOCCP.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkOCEDP4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkLedN210.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkIQADCWorker.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkWSICaptureWorker4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkWSIPatternWorker4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkBiasWorker4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkSMAdapter4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkPWrk_n210.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkFTop_n210.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/n210_uuid.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/arSRLFIFOD.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/clock_n210.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/fpgaTop_n210.v" in library work +Module compiled +Module compiled +No errors in compilation +Analysis of file <"fpgaTop-n210.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + + + +Analyzing hierarchy for module in library . + + + + + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Analyzing hierarchy for module in library . + + + + + + + + + + + + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + + + + + + + + + + + + + +Analyzing hierarchy for module in library . + + + + + + +Analyzing hierarchy for module in library . + + + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + + + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing top module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + + Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit . + Set user-defined property "DIFF_TERM = FALSE" for instance in unit . + Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit . + Set user-defined property "IBUF_LOW_PWR = TRUE" for instance in unit . + Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance in unit . + Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit . +Analyzing module in library . +"../../rtl/mkBiasWorker4B.v" line 784: Found Parallel Case directive in module . +"../../rtl/mkBiasWorker4B.v" line 1016: Found Parallel Case directive in module . +"../../rtl/mkBiasWorker4B.v" line 1040: Found Parallel Case directive in module . +"../../rtl/mkBiasWorker4B.v" line 1125: Found Parallel Case directive in module . +"../../rtl/mkBiasWorker4B.v" line 1148: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + + Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit . + Set user-defined property "CLKFX_DIVIDE = 4" for instance in unit . + Set user-defined property "CLKFX_MULTIPLY = 5" for instance in unit . + Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . + Set user-defined property "CLKIN_PERIOD = 10.000000" for instance in unit . + Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit . + Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . + Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit . + Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DSS_MODE = NONE" for instance in unit . + Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . + Set user-defined property "FACTORY_JF = C080" for instance in unit . + Set user-defined property "PHASE_SHIFT = 0" for instance in unit . + Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . +Analyzing module in library . +"../../rtl/mkOCCP.v" line 9803: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9836: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9867: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9898: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9929: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9964: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9995: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10026: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10057: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10088: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10119: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10150: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10181: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10212: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10243: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13250: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13282: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13314: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13346: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13378: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13409: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13440: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13471: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13502: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13533: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13564: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13595: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13626: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13657: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13687: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13709: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13730: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13751: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13775: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13799: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13823: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13847: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13871: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13892: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13914: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13937: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13961: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13985: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 14009: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 14033: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15062: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15372: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15581: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15635: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15689: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15744: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15799: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15854: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15909: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15964: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16019: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16074: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16129: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16184: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16239: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16294: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16349: Found Parallel Case directive in module . +Module is correct for synthesis. + + Set user-defined property "SIM_DNA_VALUE = 000000000000000" for instance in unit . +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + Calling function . + Calling function . + Calling function . + Calling function . +Module is correct for synthesis. + +Analyzing module in library . +WARNING:Xst:863 - "../../libsrc/hdl/bsv/MakeResetA.v" line 54: Name conflict ( and , renaming rst as rst_rnm0). +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkEDCPAdapter.v" line 734: Found Parallel Case directive in module . +"../../rtl/mkEDCPAdapter.v" line 918: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkEDDPAdapter.v" line 610: Found Parallel Case directive in module . +"../../rtl/mkEDDPAdapter.v" line 709: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkOCEDP4B.v" line 3737: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 4108: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 4483: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5018: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5185: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5546: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5566: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5813: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5836: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5904: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5922: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5939: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5955: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5995: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6013: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6030: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6047: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6088: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6106: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6123: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6140: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6181: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6199: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6216: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6233: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkOCEDP4B.v" line 3737: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 4108: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 4483: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5018: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5185: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5546: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5566: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5813: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5836: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5904: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5922: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5939: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5955: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5995: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6013: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6030: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6047: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6088: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6106: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6123: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6140: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6181: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6199: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6216: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6233: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkQABSMF3.v" line 970: Found Parallel Case directive in module . +"../../rtl/mkQABSMF3.v" line 1044: Found Parallel Case directive in module . +"../../rtl/mkQABSMF3.v" line 1112: Found Parallel Case directive in module . +"../../rtl/mkQABSMF3.v" line 1148: Found Parallel Case directive in module . +"../../rtl/mkQABSMF3.v" line 1277: Found Parallel Case directive in module . +"../../rtl/mkQABSMF3.v" line 1333: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkGMAC.v" line 1044: Found Parallel Case directive in module . +Module is correct for synthesis. + + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + Calling function . + Calling function . + Calling function . + Calling function . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + Calling function . + Calling function . + Calling function . + Calling function . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + Calling function . + Calling function . + Calling function . + Calling function . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkGbeWrk.v" line 413: Found Parallel Case directive in module . +"../../rtl/mkGbeWrk.v" line 577: Found Parallel Case directive in module . +"../../rtl/mkGbeWrk.v" line 601: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkIQADCWorker.v" line 1875: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2189: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2307: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2488: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2738: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2762: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2847: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2870: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2946: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +INFO:Xst:1432 - Contents of array may be accessed with a negative index, causing simulation mismatch. +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkPWrk_n210.v" line 802: Found Parallel Case directive in module . +"../../rtl/mkPWrk_n210.v" line 1120: Found Parallel Case directive in module . +"../../rtl/mkPWrk_n210.v" line 1144: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkSMAdapter4B.v" line 1530: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 1834: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 1933: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2040: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2064: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2108: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2128: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2166: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2185: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2221: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2241: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2347: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2370: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkSMAdapter4B.v" line 1530: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 1834: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 1933: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2040: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2064: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2108: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2128: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2166: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2185: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2221: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2241: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2347: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2370: Found Parallel Case directive in module . +Module is correct for synthesis. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... +INFO:Xst:2679 - Register in unit has a constant value of 0000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 01000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000101010111100110001110 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000001 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000010000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00010010001101000101011001111000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of X during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0001001000110100 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000001 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000010000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00010010001101000101011001111000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of X during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000000000001 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncResetA.v". +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkLedN210.v". + Found 5-bit 8-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 32-bit comparator greater for signal . + Found 32-bit up counter for signal . + Found 5-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 6 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 5 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 2x72-bit dual-port RAM for signal . + Found 72-bit register for signal . + Found 72-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit adder for signal >. + Found 1-bit adder for signal >. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 199. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 180. + Found 1-bit register for signal >. + Summary: + inferred 1 RAM(s). + inferred 77 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 72 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 2x61-bit dual-port RAM for signal . + Found 61-bit register for signal . + Found 61-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit adder for signal >. + Found 1-bit adder for signal >. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 199. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 180. + Found 1-bit register for signal >. + Summary: + inferred 1 RAM(s). + inferred 66 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 61 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO1.v". + Found 33-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 59-bit register for signal . + Found 59-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 120 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 40-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 82 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/BRAM1Load.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 1024x32-bit single-port RAM for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 32 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 2x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit adder for signal >. + Found 1-bit adder for signal >. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 199. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 180. + Found 1-bit register for signal >. + Summary: + inferred 1 RAM(s). + inferred 37 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 32 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncFIFO.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2x64-bit dual-port RAM for signal . + Found 64-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit xor2 for signal . + Found 2-bit xor2 for signal . + Found 2-bit register for signal . + Found 2-bit comparator not equal for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 80 D-type flip-flop(s). + inferred 3 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO1.v". + Found 34-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 35 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncHandshake.v". + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 69. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 6 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncResetA.v". +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 17-bit register for signal . + Summary: + inferred 17 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 79-bit register for signal . + Found 79-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 160 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 45-bit register for signal . + Found 45-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 92 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 48-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 98 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/BRAM2.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2048x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/BRAM2.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2048x40-bit dual-port RAM for signal . + Found 40-bit register for signal . + Found 40-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 80 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 258 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 66 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO20.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 262 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 139-bit register for signal . + Found 139-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 280 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 124 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 2x38-bit dual-port RAM for signal . + Found 38-bit register for signal . + Found 38-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit adder for signal >. + Found 1-bit adder for signal >. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 199. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 180. + Found 1-bit register for signal >. + Summary: + inferred 1 RAM(s). + inferred 43 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 38 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 36 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/Counter.v". + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 78. + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/Counter.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 78. + Summary: + inferred 4 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal >. + Summary: + inferred 1 Tristate(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncBit.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncFIFO.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 8x40-bit dual-port RAM for signal . + Found 40-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit xor2 for signal . + Found 4-bit xor2 for signal . + Found 4-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 68 D-type flip-flop(s). + inferred 3 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 22 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncResetA.v". +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 8-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkCRC32.v". + Found 32-bit register for signal . + Found 32-bit xor2 for signal . + Summary: + inferred 32 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncFIFO.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 8x10-bit dual-port RAM for signal . + Found 10-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit xor2 for signal . + Found 4-bit xor2 for signal . + Found 4-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 38 D-type flip-flop(s). + inferred 3 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/ClockInverter.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/ResetInverter.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncFIFO.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 16x10-bit dual-port RAM for signal . + Found 10-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 5-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit xor2 for signal . + Found 5-bit xor2 for signal . + Found 5-bit register for signal . + Found 5-bit comparator not equal for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 5-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 44 D-type flip-flop(s). + inferred 3 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 39-bit 16-to-1 multiplexer for signal <$varindex0000> created at line 51. + Found 624-bit register for signal . + Found 1-bit register for signal . + Found 39-bit register for signal . + Found 4-bit updown counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . +INFO:Xst:738 - HDL ADVISOR - 624 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. + Summary: + inferred 1 Counter(s). + inferred 666 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 39 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/BRAM2.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 1024x39-bit dual-port RAM for signal . + Found 39-bit register for signal . + Found 39-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 78 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/ClockDiv.v". + Found 3-bit up counter for signal . + Found 3-bit comparator less for signal created at line 105. + Summary: + inferred 1 Counter(s). + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/ResetEither.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncReset0.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/ResetToBool.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 53-bit register for signal . + Found 53-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 108 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 15x24-bit dual-port RAM for signal . + Found 24-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal . + Found 4-bit adder for signal . + Found 1-bit register for signal . + Found 4-bit comparator equal for signal created at line 199. + Found 1-bit register for signal . + Found 4-bit comparator equal for signal created at line 180. + Found 4-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 35 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 2 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 15x8-bit dual-port RAM for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal . + Found 4-bit adder for signal . + Found 1-bit register for signal . + Found 4-bit comparator equal for signal created at line 199. + Found 1-bit register for signal . + Found 4-bit comparator equal for signal created at line 180. + Found 4-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 19 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 2 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/Counter.v". + Found 10-bit register for signal . + Found 10-bit adder for signal created at line 78. + Summary: + inferred 10 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/Counter.v". + Found 32-bit register for signal . + Found 32-bit adder for signal created at line 78. + Summary: + inferred 32 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO10.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/BRAM2.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2048x61-bit dual-port RAM for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 122 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 70 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkBiasWorker4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiM_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiS_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Using one-hot encoding for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 1-bit register for signal . + Found 2-bit comparator greater for signal created at line 572. + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit comparator greater for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 12-bit adder for signal created at line 1275. + Found 32-bit adder for signal . + Summary: + inferred 2 Finite State Machine(s). + inferred 6 Counter(s). + inferred 314 D-type flip-flop(s). + inferred 8 Adder/Subtractor(s). + inferred 2 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/ocpi/clock_n210.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkEDCPAdapter.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Found 79-bit 4-to-1 multiplexer for signal . + Found 8-bit comparator equal for signal . + Found 8-bit comparator equal for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 48-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 48-bit comparator equal for signal created at line 616. + Found 48-bit comparator equal for signal created at line 616. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 48-bit register for signal . + Found 16-bit register for signal . + Found 48-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 9-bit register for signal . + Found 45-bit 4-to-1 multiplexer for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 820. + Found 48-bit register for signal . + Summary: + inferred 476 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 4 Comparator(s). + inferred 124 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkEDDPAdapter.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 6 | + | Transitions | 16 | + | Inputs | 3 | + | Outputs | 6 | + | Clock | CLK (rising_edge) | + | Clock enable | edpFsm_state_mkFSMstate$EN (positive) | + | Reset | RST_N (negative) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 16-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 637. + Found 4-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 48-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 140 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkOCEDP4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Found 16-bit register for signal . + Found 16-bit subtractor for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit subtractor for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit adder for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6732. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6738. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6754. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6760. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6772. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6786. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6792. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6798. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 12-bit subtractor for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 129-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 5073. + Found 4-bit comparator lessequal for signal . + Found 4-bit register for signal . + Found 16-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 53-bit register for signal . + Found 12-bit register for signal . + Found 12-bit comparator equal for signal . + Found 12-bit up counter for signal . + Found 12-bit comparator equal for signal created at line 4146. + Found 32-bit 4-to-1 multiplexer for signal . + Found 2-bit up counter for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 13-bit register for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 2-bit adder for signal . + Found 1-bit register for signal . + Found 13-bit register for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 10-bit comparator lessequal for signal . + Found 10-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 16-bit adder for signal created at line 3327. + Found 16-bit adder for signal created at line 3331. + Found 32-bit adder for signal created at line 3347. + Found 32-bit adder for signal created at line 3351. + Found 16-bit adder for signal created at line 3355. + Found 16-bit adder for signal created at line 3374. + Found 16-bit adder for signal created at line 3378. + Found 16-bit adder for signal created at line 3382. + Found 16-bit adder for signal created at line 3386. + Found 16-bit adder for signal created at line 3390. + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit adder for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 4-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 4-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 14-bit adder for signal . + Found 2-bit subtractor for signal . + Found 14-bit subtractor for signal . + Found 14-bit subtractor for signal . + Found 32-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 12-bit comparator not equal for signal . + Found 12-bit adder for signal created at line 6674. + Found 32-bit 4-to-1 multiplexer for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 2254. + Found 14-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal . + Found 32-bit register for signal . + Found 2-bit comparator greater for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 1-bit register for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 12-bit adder for signal . + Found 12-bit subtractor for signal . + Summary: + inferred 9 Counter(s). + inferred 1893 D-type flip-flop(s). + inferred 85 Adder/Subtractor(s). + inferred 24 Comparator(s). + inferred 327 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkOCEDP4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Found 16-bit register for signal . + Found 16-bit subtractor for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit subtractor for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit adder for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6732. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6738. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6754. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6760. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6772. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6786. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6792. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6798. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 12-bit subtractor for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 129-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 32-bit up counter for signal . + Found 16-bit up counter for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 5073. + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 17-bit register for signal . + Found 17-bit adder for signal . + Found 16-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 53-bit register for signal . + Found 12-bit register for signal . + Found 12-bit comparator equal for signal . + Found 12-bit up counter for signal . + Found 12-bit comparator equal for signal created at line 4146. + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 2-bit up counter for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 13-bit register for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 2-bit adder for signal . + Found 1-bit register for signal . + Found 13-bit register for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 10-bit comparator lessequal for signal . + Found 10-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 16-bit adder for signal created at line 3327. + Found 16-bit adder for signal created at line 3331. + Found 32-bit adder for signal created at line 3347. + Found 32-bit adder for signal created at line 3351. + Found 16-bit adder for signal created at line 3355. + Found 16-bit adder for signal created at line 3374. + Found 16-bit adder for signal created at line 3378. + Found 16-bit adder for signal created at line 3382. + Found 16-bit adder for signal created at line 3386. + Found 16-bit adder for signal created at line 3390. + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit adder for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 4-bit subtractor for signal . + Found 32-bit adder for signal . + Found 17-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 4-bit subtractor for signal . + Found 16-bit adder for signal . + Found 32-bit adder for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 14-bit adder for signal . + Found 2-bit subtractor for signal . + Found 14-bit subtractor for signal . + Found 14-bit subtractor for signal . + Found 32-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 12-bit comparator not equal for signal . + Found 12-bit adder for signal created at line 6674. + Found 32-bit 4-to-1 multiplexer for signal . + Found 17-bit comparator equal for signal created at line 6972. + Found 13-bit adder for signal . + Found 13-bit comparator lessequal for signal created at line 6980. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 2254. + Found 14-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal . + Found 32-bit register for signal . + Found 2-bit comparator greater for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 1-bit register for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 12-bit adder for signal . + Found 12-bit subtractor for signal . + Found 17-bit comparator lessequal for signal created at line 7017. + Summary: + inferred 10 Counter(s). + inferred 2136 D-type flip-flop(s). + inferred 92 Adder/Subtractor(s). + inferred 27 Comparator(s). + inferred 327 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkQABSMF3.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 120-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 120-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 260 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkGbeWrk.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Found 32-bit register for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 276. + Summary: + inferred 180 D-type flip-flop(s). + inferred 3 Adder/Subtractor(s). + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkPWrk_n210.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Found 87x2-bit ROM for signal . + Found 117x3-bit ROM for signal . + Found 32-bit register for signal . + Found 8-bit down counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 48-bit register for signal . + Found 1-bit 117-to-1 multiplexer for signal . + Found 1-bit 87-to-1 multiplexer for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 519. + Found 32-bit register for signal . + Found 8-bit adder for signal . + Summary: + inferred 2 ROM(s). + inferred 1 Counter(s). + inferred 299 D-type flip-flop(s). + inferred 4 Adder/Subtractor(s). + inferred 1 Comparator(s). + inferred 2 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkSMAdapter4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiM_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Using one-hot encoding for signal . + Found 12-bit adder for signal . + Found 24-bit adder for signal . + Found 12-bit comparator greater for signal created at line 1197. + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit comparator not equal for signal created at line 1786. + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 14-bit comparator lessequal for signal created at line 1800. + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 14-bit adder for signal . + Found 3-bit adder for signal created at line 2560. + Found 12-bit adder for signal created at line 1497. + Found 12-bit adder for signal . + Found 14-bit subtractor for signal . + Found 32-bit adder for signal . + Found 14-bit adder for signal . + Found 16-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 12-bit comparator equal for signal created at line 1601. + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 74-bit register for signal . + Found 12-bit register for signal . + Found 12-bit up counter for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 32-bit up counter for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 1057. + Found 12-bit comparator not equal for signal created at line 1369. + Found 2-bit register for signal . + Found 38-bit register for signal . + Found 38-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 12-bit adder for signal created at line 2594. + Found 12-bit comparator not equal for signal created at line 2594. + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit down counter for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit comparator greater for signal . + Found 12-bit adder for signal . + Found 14-bit comparator equal for signal . + Found 6-bit comparator lessequal for signal created at line 2606. + Found 6-bit comparator lessequal for signal created at line 2606. + Found 3-bit adder for signal . + Found 3-bit adder for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 10 Counter(s). + inferred 790 D-type flip-flop(s). + inferred 25 Adder/Subtractor(s). + inferred 11 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkSMAdapter4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiM_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiS_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Using one-hot encoding for signal . + Found 32-bit register for signal . + Found 32-bit adder for signal . + Found 12-bit adder for signal . + Found 24-bit adder for signal . + Found 12-bit comparator greater for signal created at line 1197. + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit comparator not equal for signal created at line 1786. + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 14-bit comparator lessequal for signal created at line 1800. + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 14-bit adder for signal . + Found 3-bit adder for signal created at line 2560. + Found 12-bit adder for signal created at line 1497. + Found 12-bit adder for signal . + Found 14-bit subtractor for signal . + Found 32-bit adder for signal . + Found 14-bit adder for signal . + Found 16-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 12-bit comparator equal for signal created at line 1601. + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 74-bit register for signal . + Found 12-bit register for signal . + Found 12-bit up counter for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 32-bit up counter for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 1057. + Found 12-bit comparator not equal for signal created at line 1369. + Found 2-bit register for signal . + Found 38-bit register for signal . + Found 38-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 12-bit adder for signal created at line 2594. + Found 12-bit comparator not equal for signal created at line 2594. + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 32-bit adder for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit comparator greater for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 12-bit adder for signal created at line 2496. + Found 12-bit adder for signal . + Found 14-bit comparator equal for signal . + Found 6-bit comparator lessequal for signal created at line 2606. + Found 6-bit comparator lessequal for signal created at line 2606. + Found 3-bit adder for signal . + Found 3-bit adder for signal . + Summary: + inferred 2 Finite State Machine(s). + inferred 11 Counter(s). + inferred 837 D-type flip-flop(s). + inferred 29 Adder/Subtractor(s). + inferred 11 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 64-bit register for signal . + Found 64-bit register for signal . + Summary: + inferred 128 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 28-bit register for signal . + Found 28-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkGMAC.v". +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 1-bit register for signal . + Found 12-bit adder for signal created at line 974. + Found 4-bit adder for signal created at line 978. + Found 32-bit comparator equal for signal created at line 984. + Found 12-bit adder for signal created at line 998. + Found 3-bit subtractor for signal . + Found 5-bit subtractor for signal created at line 1003. + Found 12-bit adder for signal created at line 1007. + Found 5-bit adder for signal created at line 1011. + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit comparator greater for signal created at line 1143. + Found 6-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 48-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 12-bit comparator less for signal . + Found 5-bit register for signal . + Found 5-bit comparator less for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 138 D-type flip-flop(s). + inferred 7 Adder/Subtractor(s). + inferred 4 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 16-bit register for signal . + Found 16-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 64 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 128-bit register for signal . + Found 128-bit register for signal . + Summary: + inferred 256 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkOCCP.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal <_281474976710656_MINUS_timeServ_delSecond__q1<27:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Found 3-bit comparator less for signal created at line 5701. + Found 32-bit register for signal . + Found 65-bit register for signal . + Found 8-bit comparator less for signal . + Found 8-bit comparator less for signal . + Found 24-bit comparator less for signal . + Found 24-bit comparator less for signal . + Found 64-bit register for signal . + Found 64-bit subtractor for signal . + Found 1-bit register for signal . + Found 7-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit comparator greatequal for signal created at line 10663. + Found 7-bit comparator lessequal for signal created at line 10663. + Found 57-bit register for signal . + Found 33-bit 4-to-1 multiplexer for signal . + Found 2-bit comparator not equal for signal created at line 16664. + Found 1-bit 16-to-1 multiplexer for signal . + Found 32-bit adder for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 17237. + Found 2-bit register for signal . + Found 32-bit 16-to-1 multiplexer for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 50-bit register for signal . + Found 1-bit register for signal . + Found 50-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 28-bit comparator less for signal . + Found 28-bit comparator greater for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit up counter for signal . + Found 28-bit up counter for signal . + Found 28-bit comparator lessequal for signal . + Found 28-bit comparator less for signal . + Found 28-bit register for signal . + Found 28-bit adder for signal created at line 12151. + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit subtractor for signal . + Found 4-bit subtractor for signal . + Found 4-bit register for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 50-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Summary: + inferred 3 Counter(s). + inferred 3806 D-type flip-flop(s). + inferred 54 Adder/Subtractor(s). + inferred 27 Comparator(s). + inferred 322 Multiplexer(s). + inferred 15 Combinational logic shifter(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkIQADCWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 21 | + | Inputs | 3 | + | Outputs | 11 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | adcCore_iseqFsm_state_mkFSMstate$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiM_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Using one-hot encoding for signal . + Found 1-bit 18-to-1 multiplexer for signal <$varindex0000> created at line 1852. + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 2-bit up counter for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 11-bit comparator not equal for signal created at line 3193. + Found 1-bit xor2 for signal created at line 3193. + Found 1-bit xor2 for signal created at line 3193. + Found 1-bit xor2 for signal created at line 3193. + Found 1-bit xor2 for signal created at line 3193. + Found 1-bit xor2 for signal created at line 3193. + Found 1-bit xor2 for signal created at line 3193. + Found 1-bit xor2 for signal created at line 3193. + Found 1-bit xor2 for signal created at line 3193. + Found 1-bit xor2 for signal created at line 3193. + Found 1-bit xor2 for signal created at line 3193. + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 16-bit subtractor for signal created at line 3217. + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit xor2 for signal created at line 3000. + Found 11-bit register for signal . + Found 11-bit adder for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 11-bit register for signal . + Found 11-bit register for signal . + Found 1-bit xor11 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 11-bit register for signal . + Found 11-bit register for signal . + Found 11-bit register for signal . + Found 1-bit xor11 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 1502. + Found 18-bit register for signal . + Found 1-bit xor2 for signal created at line 2568. + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 18-bit subtractor for signal . + Found 18-bit register for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 18-bit register for signal . + Found 1-bit xor18 for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 32-bit register for signal . + Found 32-bit comparator not equal for signal created at line 2625. + Found 32-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 4-bit subtractor for signal . + Found 32-bit adder for signal . + Found 2-bit subtractor for signal . + Found 3-bit subtractor for signal . + Found 16-bit adder for signal created at line 1813. + Found 3-bit subtractor for signal created at line 1834. + Found 4-bit subtractor for signal created at line 1838. + Found 18-bit adder for signal created at line 1856. + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 11-bit comparator not equal for signal . + Found 1-bit xor2 for signal . + Found 18-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 1259. + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 18-bit adder for signal . + Found 18-bit adder for signal . + Found 18-bit adder for signal . + Found 18-bit adder for signal . + Found 18-bit adder for signal . + Found 11-bit shifter logical left for signal . + Found 11-bit shifter logical left for signal . + Found 11-bit adder for signal . + Found 18-bit shifter logical left for signal . + Found 1-bit xor2 for signal created at line 3426. + Summary: + inferred 2 Finite State Machine(s). + inferred 5 Counter(s). + inferred 887 D-type flip-flop(s). + inferred 25 Adder/Subtractor(s). + inferred 5 Comparator(s). + inferred 5 Multiplexer(s). + inferred 3 Combinational logic shifter(s). + inferred 3 Xor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkQBGMAC.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 8-bit 4-to-1 multiplexer for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 554. + Found 30-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 570. + Found 1-bit register for signal . + Summary: + inferred 36 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 12 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkGbeQABS.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 195x2-bit ROM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 195-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit 195-to-1 multiplexer for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 25-bit register for signal . + Found 25-bit subtractor for signal created at line 836. + Found 25-bit comparator lessequal for signal created at line 836. + Found 25-bit comparator greater for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Summary: + inferred 1 ROM(s). + inferred 4 Counter(s). + inferred 107 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 2 Comparator(s). + inferred 2 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkFTop_n210.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 32-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 33 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/ocpi/fpgaTop_n210.v". +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +Unit synthesized. + +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. +WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . + This instance will be removed from the design along with all underlying logic +WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . + This instance will be removed from the design along with all underlying logic +WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . + This instance will be removed from the design along with all underlying logic +WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . + This instance will be removed from the design along with all underlying logic + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 55 + 1024x32-bit single-port RAM : 1 + 1024x39-bit dual-port RAM : 1 + 15x24-bit dual-port RAM : 1 + 15x8-bit dual-port RAM : 1 + 16x10-bit dual-port RAM : 1 + 2048x32-bit dual-port RAM : 8 + 2048x40-bit dual-port RAM : 2 + 2048x61-bit dual-port RAM : 2 + 2x32-bit dual-port RAM : 21 + 2x38-bit dual-port RAM : 2 + 2x61-bit dual-port RAM : 3 + 2x64-bit dual-port RAM : 1 + 2x72-bit dual-port RAM : 8 + 8x10-bit dual-port RAM : 1 + 8x40-bit dual-port RAM : 2 +# ROMs : 3 + 117x3-bit ROM : 1 + 195x2-bit ROM : 1 + 87x2-bit ROM : 1 +# Adders/Subtractors : 408 + 1-bit adder : 83 + 1-bit subtractor : 15 + 10-bit adder : 1 + 10-bit subtractor : 14 + 11-bit adder : 4 + 12-bit adder : 17 + 12-bit subtractor : 4 + 13-bit adder : 21 + 14-bit adder : 6 + 14-bit subtractor : 6 + 16-bit adder : 25 + 16-bit subtractor : 15 + 17-bit adder : 1 + 17-bit subtractor : 1 + 18-bit adder : 6 + 18-bit subtractor : 1 + 2-bit adder : 42 + 2-bit addsub : 14 + 2-bit subtractor : 23 + 24-bit adder : 2 + 25-bit subtractor : 1 + 28-bit adder : 1 + 3-bit adder : 42 + 3-bit subtractor : 3 + 32-bit adder : 34 + 4-bit adder : 11 + 4-bit subtractor : 8 + 5-bit adder : 1 + 5-bit subtractor : 2 + 50-bit adder : 1 + 64-bit subtractor : 1 + 8-bit adder : 2 +# Counters : 52 + 12-bit up counter : 4 + 16-bit up counter : 13 + 2-bit up counter : 3 + 28-bit up counter : 2 + 3-bit up counter : 1 + 32-bit up counter : 26 + 4-bit updown counter : 1 + 7-bit up counter : 1 + 8-bit down counter : 1 +# Registers : 1779 + 1-bit register : 862 + 10-bit register : 14 + 11-bit register : 6 + 12-bit register : 24 + 120-bit register : 2 + 128-bit register : 6 + 129-bit register : 3 + 13-bit register : 5 + 130-bit register : 4 + 139-bit register : 4 + 14-bit register : 16 + 15-bit register : 4 + 16-bit register : 62 + 17-bit register : 22 + 18-bit register : 8 + 2-bit register : 85 + 24-bit register : 1 + 25-bit register : 1 + 27-bit register : 2 + 28-bit register : 3 + 3-bit register : 57 + 30-bit register : 1 + 32-bit register : 181 + 33-bit register : 20 + 34-bit register : 39 + 38-bit register : 6 + 39-bit register : 19 + 4-bit register : 80 + 40-bit register : 74 + 45-bit register : 3 + 48-bit register : 12 + 5-bit register : 52 + 50-bit register : 2 + 53-bit register : 3 + 57-bit register : 1 + 59-bit register : 4 + 6-bit register : 5 + 61-bit register : 19 + 64-bit register : 5 + 65-bit register : 1 + 7-bit register : 1 + 72-bit register : 23 + 74-bit register : 2 + 79-bit register : 2 + 8-bit register : 29 + 9-bit register : 4 +# Comparators : 137 + 10-bit comparator lessequal : 11 + 11-bit comparator not equal : 2 + 12-bit comparator equal : 6 + 12-bit comparator greater : 2 + 12-bit comparator less : 1 + 12-bit comparator not equal : 6 + 13-bit comparator lessequal : 1 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 9 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 1 + 2-bit comparator greater : 14 + 2-bit comparator not equal : 4 + 24-bit comparator less : 2 + 25-bit comparator greater : 1 + 25-bit comparator lessequal : 1 + 28-bit comparator greater : 1 + 28-bit comparator less : 1 + 3-bit comparator less : 18 + 32-bit comparator equal : 1 + 32-bit comparator greater : 1 + 32-bit comparator less : 15 + 32-bit comparator not equal : 1 + 4-bit comparator equal : 4 + 4-bit comparator greater : 1 + 4-bit comparator lessequal : 3 + 4-bit comparator not equal : 9 + 48-bit comparator equal : 2 + 5-bit comparator less : 1 + 5-bit comparator not equal : 3 + 6-bit comparator lessequal : 4 + 7-bit comparator greatequal : 1 + 7-bit comparator lessequal : 1 + 8-bit comparator equal : 2 + 8-bit comparator less : 2 +# Multiplexers : 123 + 1-bit 11-to-1 multiplexer : 2 + 1-bit 117-to-1 multiplexer : 1 + 1-bit 16-to-1 multiplexer : 1 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 195-to-1 multiplexer : 2 + 1-bit 4-to-1 multiplexer : 34 + 1-bit 8-to-1 multiplexer : 2 + 1-bit 87-to-1 multiplexer : 1 + 11-bit 4-to-1 multiplexer : 16 + 32-bit 16-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 43 + 33-bit 4-to-1 multiplexer : 1 + 38-bit 4-to-1 multiplexer : 2 + 39-bit 16-to-1 multiplexer : 1 + 45-bit 4-to-1 multiplexer : 1 + 5-bit 8-to-1 multiplexer : 1 + 61-bit 4-to-1 multiplexer : 3 + 72-bit 4-to-1 multiplexer : 8 + 79-bit 4-to-1 multiplexer : 1 + 8-bit 4-to-1 multiplexer : 1 +# Logic shifters : 18 + 11-bit shifter logical left : 2 + 18-bit shifter logical left : 1 + 32-bit shifter logical left : 15 +# Tristates : 4 + 1-bit tristate buffer : 4 +# Xors : 186 + 1-bit xor11 : 2 + 1-bit xor18 : 1 + 1-bit xor2 : 171 + 2-bit xor2 : 2 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 2 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 0001 | 00000000010 + 0010 | 00000000100 + 0011 | 00000001000 + 0100 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 1000 | 00100000000 + 1001 | 01000000000 + 1010 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +------------------- + State | Encoding +------------------- + 000 | 000001 + 001 | 000010 + 010 | 000100 + 011 | 001000 + 100 | 010000 + 101 | 100000 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + +Synthesizing (advanced) Unit . +INFO:Xst:3038 - The RAM appears to be read-only. If that was not your intent please check the write enable description. +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 40-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 40-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 39-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 1024-word x 39-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 61-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 61-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 72-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 72-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 61-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 61-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 32-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 32-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 38-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 38-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 15-word x 24-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 15-word x 24-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 15-word x 8-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 15-word x 8-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 64-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 64-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 40-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 40-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 10-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 16-word x 10-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal <_varindex0000<0>>. + Found 16-bit dynamic shift register for signal <_varindex0000<1>>. + Found 16-bit dynamic shift register for signal <_varindex0000<2>>. + Found 16-bit dynamic shift register for signal <_varindex0000<3>>. + Found 16-bit dynamic shift register for signal <_varindex0000<4>>. + Found 16-bit dynamic shift register for signal <_varindex0000<5>>. + Found 16-bit dynamic shift register for signal <_varindex0000<6>>. + Found 16-bit dynamic shift register for signal <_varindex0000<7>>. + Found 16-bit dynamic shift register for signal <_varindex0000<8>>. + Found 16-bit dynamic shift register for signal <_varindex0000<9>>. + Found 16-bit dynamic shift register for signal <_varindex0000<10>>. + Found 16-bit dynamic shift register for signal <_varindex0000<11>>. + Found 16-bit dynamic shift register for signal <_varindex0000<12>>. + Found 16-bit dynamic shift register for signal <_varindex0000<13>>. + Found 16-bit dynamic shift register for signal <_varindex0000<14>>. + Found 16-bit dynamic shift register for signal <_varindex0000<15>>. + Found 16-bit dynamic shift register for signal <_varindex0000<16>>. + Found 16-bit dynamic shift register for signal <_varindex0000<17>>. + Found 16-bit dynamic shift register for signal <_varindex0000<18>>. + Found 16-bit dynamic shift register for signal <_varindex0000<19>>. + Found 16-bit dynamic shift register for signal <_varindex0000<20>>. + Found 16-bit dynamic shift register for signal <_varindex0000<21>>. + Found 16-bit dynamic shift register for signal <_varindex0000<22>>. + Found 16-bit dynamic shift register for signal <_varindex0000<23>>. + Found 16-bit dynamic shift register for signal <_varindex0000<24>>. + Found 16-bit dynamic shift register for signal <_varindex0000<25>>. + Found 16-bit dynamic shift register for signal <_varindex0000<26>>. + Found 16-bit dynamic shift register for signal <_varindex0000<27>>. + Found 16-bit dynamic shift register for signal <_varindex0000<28>>. + Found 16-bit dynamic shift register for signal <_varindex0000<29>>. + Found 16-bit dynamic shift register for signal <_varindex0000<30>>. + Found 16-bit dynamic shift register for signal <_varindex0000<31>>. + Found 16-bit dynamic shift register for signal <_varindex0000<32>>. + Found 16-bit dynamic shift register for signal <_varindex0000<33>>. + Found 16-bit dynamic shift register for signal <_varindex0000<34>>. + Found 16-bit dynamic shift register for signal <_varindex0000<35>>. + Found 16-bit dynamic shift register for signal <_varindex0000<36>>. + Found 16-bit dynamic shift register for signal <_varindex0000<37>>. + Found 16-bit dynamic shift register for signal <_varindex0000<38>>. +Unit synthesized (advanced). + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# FSMs : 8 +# RAMs : 55 + 1024x32-bit single-port block RAM : 1 + 1024x39-bit dual-port block RAM : 1 + 15x24-bit dual-port distributed RAM : 1 + 15x8-bit dual-port distributed RAM : 1 + 16x10-bit dual-port distributed RAM : 1 + 2048x32-bit dual-port block RAM : 8 + 2048x40-bit dual-port block RAM : 2 + 2048x61-bit dual-port block RAM : 2 + 2x32-bit dual-port distributed RAM : 21 + 2x38-bit dual-port distributed RAM : 2 + 2x61-bit dual-port distributed RAM : 3 + 2x64-bit dual-port distributed RAM : 1 + 2x72-bit dual-port distributed RAM : 8 + 8x10-bit dual-port distributed RAM : 1 + 8x40-bit dual-port distributed RAM : 2 +# ROMs : 3 + 117x3-bit ROM : 1 + 195x2-bit ROM : 1 + 87x2-bit ROM : 1 +# Adders/Subtractors : 397 + 1-bit adder : 83 + 1-bit subtractor : 15 + 10-bit adder : 1 + 10-bit subtractor : 14 + 11-bit adder : 3 + 12-bit adder : 15 + 12-bit subtractor : 4 + 13-bit adder : 21 + 14-bit adder : 6 + 14-bit subtractor : 4 + 16-bit adder : 25 + 16-bit subtractor : 15 + 17-bit adder : 1 + 17-bit subtractor : 1 + 18-bit adder : 6 + 18-bit subtractor : 1 + 2-bit adder : 42 + 2-bit addsub : 14 + 2-bit subtractor : 23 + 25-bit subtractor : 1 + 28-bit adder : 1 + 3-bit adder : 38 + 3-bit adder carry in : 2 + 3-bit subtractor : 3 + 32-bit adder : 33 + 4-bit adder : 11 + 4-bit subtractor : 9 + 5-bit adder : 1 + 5-bit subtractor : 1 + 50-bit adder : 1 + 64-bit subtractor : 1 + 8-bit adder : 1 +# Counters : 51 + 12-bit up counter : 4 + 16-bit up counter : 13 + 2-bit up counter : 3 + 28-bit up counter : 1 + 3-bit up counter : 1 + 32-bit up counter : 26 + 4-bit updown counter : 1 + 7-bit up counter : 1 + 8-bit down counter : 1 +# Accumulators : 6 + 10-bit up loadable accumulator : 1 + 14-bit down loadable accumulator : 2 + 16-bit up loadable accumulator : 1 + 32-bit up loadable accumulator : 1 + 8-bit up accumulator : 1 +# Registers : 21108 + Flip-Flops : 21108 +# Shift Registers : 39 + 16-bit dynamic shift register : 39 +# Comparators : 137 + 10-bit comparator lessequal : 11 + 11-bit comparator not equal : 2 + 12-bit comparator equal : 6 + 12-bit comparator greater : 2 + 12-bit comparator less : 1 + 12-bit comparator not equal : 6 + 13-bit comparator lessequal : 1 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 9 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 1 + 2-bit comparator greater : 14 + 2-bit comparator not equal : 4 + 24-bit comparator less : 2 + 25-bit comparator greater : 1 + 25-bit comparator lessequal : 1 + 28-bit comparator greater : 1 + 28-bit comparator less : 1 + 3-bit comparator less : 18 + 32-bit comparator equal : 1 + 32-bit comparator greater : 1 + 32-bit comparator less : 15 + 32-bit comparator not equal : 1 + 4-bit comparator equal : 4 + 4-bit comparator greater : 1 + 4-bit comparator lessequal : 3 + 4-bit comparator not equal : 9 + 48-bit comparator equal : 2 + 5-bit comparator less : 1 + 5-bit comparator not equal : 3 + 6-bit comparator lessequal : 4 + 7-bit comparator greatequal : 1 + 7-bit comparator lessequal : 1 + 8-bit comparator equal : 2 + 8-bit comparator less : 2 +# Multiplexers : 122 + 1-bit 11-to-1 multiplexer : 2 + 1-bit 117-to-1 multiplexer : 1 + 1-bit 16-to-1 multiplexer : 1 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 195-to-1 multiplexer : 2 + 1-bit 4-to-1 multiplexer : 34 + 1-bit 8-to-1 multiplexer : 2 + 1-bit 87-to-1 multiplexer : 1 + 11-bit 4-to-1 multiplexer : 16 + 32-bit 16-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 43 + 33-bit 4-to-1 multiplexer : 1 + 38-bit 4-to-1 multiplexer : 2 + 45-bit 4-to-1 multiplexer : 1 + 5-bit 8-to-1 multiplexer : 1 + 61-bit 4-to-1 multiplexer : 3 + 72-bit 4-to-1 multiplexer : 8 + 79-bit 4-to-1 multiplexer : 1 + 8-bit 4-to-1 multiplexer : 1 +# Logic shifters : 18 + 11-bit shifter logical left : 2 + 18-bit shifter logical left : 1 + 32-bit shifter logical left : 15 +# Xors : 186 + 1-bit xor11 : 2 + 1-bit xor18 : 1 + 1-bit xor2 : 171 + 2-bit xor2 : 2 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 2 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: _varindex0000, MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<0>, x__h8844<0>1, MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<17>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<1>, x__h8844<4>, Sh81, Sh90, MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<10>, fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1216. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: Sh65, MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<3>, Sh64, x__h8844<2>, Sh82, IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d1407_or0000, MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<2>, Sh83. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<5>, Sh67, Sh45, Sh66, Sh85, Sh84, Sh44, x__h8844<0>, MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<4>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<7>, Sh46, Sh86, Sh68, Sh47, Sh69, MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<6>, x__h8844<1>, Sh87. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: Sh88, Sh70, MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<8>, Sh89, MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<9>, Sh71, x__h8844<3>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<1>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<5>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<7>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<15>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<3>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<8>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<13>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<14>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<9>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<6>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<0>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<12>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<2>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<10>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<11>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<16>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<4>. +WARNING:Xst:2170 - Unit mkIQADCWorker : the following signal(s) form a combinatorial loop: MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<17>. + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. + +Mapping all equations... +Building and optimizing final netlist ... +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +Found area constraint ratio of 100 (+ 5) on block fpgaTop, actual ratio is 69. +FlipFlop ftop/gbe0/gmac/gmac/txRS_emitFCS_0 has been replicated 1 time(s) +FlipFlop ftop/gbe0/gmac/gmac/txRS_emitFCS_1 has been replicated 1 time(s) +FlipFlop ftop/gbe0/gmac/gmac/txRS_emitFCS_2 has been replicated 1 time(s) + +Final Macro Processing ... + +Processing Unit : + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 16441 + Flip-Flops : 16441 +# Shift Registers : 28 + 2-bit shift register : 28 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : fpgaTop.ngr +Top Level Output File Name : fpgaTop +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : soft + +Design Statistics +# IOs : 146 + +Cell Usage : +# BELS : 36156 +# AND2 : 1 +# GND : 91 +# INV : 1120 +# LUT1 : 2297 +# LUT2 : 4455 +# LUT2_D : 89 +# LUT2_L : 5 +# LUT3 : 6434 +# LUT3_D : 104 +# LUT3_L : 37 +# LUT4 : 12216 +# LUT4_D : 316 +# LUT4_L : 244 +# MULT_AND : 9 +# MUXCY : 4239 +# MUXF5 : 1078 +# MUXF6 : 95 +# MUXF7 : 36 +# OR2 : 1 +# OR3 : 1 +# VCC : 33 +# XORCY : 3255 +# FlipFlops/Latches : 16480 +# FD : 611 +# FDC : 362 +# FDCE : 592 +# FDE : 5083 +# FDP : 17 +# FDPE : 39 +# FDR : 380 +# FDRE : 5892 +# FDRS : 16 +# FDRSE : 73 +# FDS : 1892 +# FDSE : 1512 +# ODDR2 : 11 +# RAMS : 1253 +# RAM16X1D : 1206 +# RAMB16BWER : 47 +# Shift Registers : 31 +# SRL16 : 28 +# SRL16E : 3 +# Clock Buffers : 5 +# BUFG : 4 +# BUFGP : 1 +# IO Buffers : 102 +# IBUF : 40 +# IBUFDS : 1 +# IBUFG : 1 +# IOBUF : 1 +# OBUF : 58 +# OBUFT : 1 +# DCMs : 1 +# DCM_SP : 1 +# Others : 1 +# DNA_PORT : 1 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 3sd3400afg676-5 + + Number of Slices: 15970 out of 23872 66% + Number of Slice Flip Flops: 16480 out of 47744 34% + Number of 4 input LUTs: 29760 out of 47744 62% + Number used as logic: 27317 + Number used as Shift registers: 31 + Number used as RAMs: 2412 + Number of IOs: 146 + Number of bonded IOBs: 102 out of 469 21% + Number of BRAMs: 47 out of 126 37% + Number of GCLKs: 5 out of 24 20% + Number of DCMs: 1 out of 8 12% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +sys0_clkp | dcm:CLKDV | 17039 | +gmii_sysclk | IBUFG+BUFG | 563 | +sys0_clkp | dcm:CLK0 | 5 | +ftop/iqadc/adcCore_spiI_cd/cntr_2 | BUFG | 32 | +gmii_rx_clk | BUFGP | 136 | +-----------------------------------+------------------------+-------+ + +Asynchronous Control Signals Information: +---------------------------------------- +-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------+-------+ +ftop/iqadc/adcCore_statsCC/sRST_inv(ftop/iqadc/adcCore_statsCC/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_statsCC/dD_OUT_0) | 256 | +ftop/cp/timeServ_nowInCC/sRST_inv(ftop/cp/timeServ_nowInCC/sRST_inv1_INV_0:O) | NONE(ftop/cp/timeServ_nowInCC/dD_OUT_0) | 128 | +ftop/iqadc/adcCore_iseqFsm_state_mkFSMstate_FSM_Scst_FSM_inv(ftop/iqadc/adcCore_iseqFsm_state_mkFSMstate_FSM_Scst_FSM_inv1_INV_0:O)| NONE(ftop/iqadc/adcCore_sampF_rRdPtr_rsCounter_0) | 71 | +ftop/iqadc/adcCore_sampCC/sRST_inv(ftop/iqadc/adcCore_sampCC/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_sampCC/dD_OUT_0) | 56 | +ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1_Acst_inv(ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1_Acst_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/txRS_txF/dEnqPtr_0) | 46 | +ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr1_Acst_inv(ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr1_Acst_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_0) | 38 | +ftop/gbe0/gmac/rxF/dGDeqPtr1_Acst_inv(ftop/gbe0/gmac/rxF/dGDeqPtr1_Acst_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/rxF/dEnqPtr_0) | 38 | +ftop/gbe0/gmac/txF/dGDeqPtr1_Acst_inv(ftop/gbe0/gmac/txF/dGDeqPtr1_Acst_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/txF/dEnqPtr_0) | 38 | +ftop/iqadc/adcCore_sdrRst_OUT_RST_inv(ftop/iqadc/adcCore_sdrRst_OUT_RST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_sampF_rRdPtr_rdCounterPre_0) | 33 | +ftop/iqadc/adcCore_maxBurstLengthR/sRST_inv(ftop/iqadc/adcCore_maxBurstLengthR/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_maxBurstLengthR/dD_OUT_0) | 32 | +ftop/cp/timeServ_setRefF/dGDeqPtr1_Acst_inv(ftop/cp/timeServ_setRefF/dGDeqPtr1_Acst_inv1_INV_0:O) | NONE(ftop/cp/timeServ_setRefF/dEnqPtr_0) | 22 | +ftop/cp/wci_mReset_10/rstSync/IN_RST_inv(ftop/cp/wci_mReset_10/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_10/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_13/rstSync/IN_RST_inv(ftop/cp/wci_mReset_13/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_13/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_14/rstSync/IN_RST_inv(ftop/cp/wci_mReset_14/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_14/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_2/rstSync/IN_RST_inv(ftop/cp/wci_mReset_2/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_2/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_3/rstSync/IN_RST_inv(ftop/cp/wci_mReset_3/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_3/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_4/rstSync/IN_RST_inv(ftop/cp/wci_mReset_4/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_4/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_7/rstSync/IN_RST_inv(ftop/cp/wci_mReset_7/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_7/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_9/rstSync/IN_RST_inv(ftop/cp/wci_mReset_9/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_9/rstSync/reset_hold_0) | 17 | +ftop/gbe0/phyRst/rstSync/IN_RST_inv(ftop/gbe0/phyRst/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/gbe0/phyRst/rstSync/reset_hold_0) | 17 | +ftop/cp/timeServ_nowInCC/sync/sRST_inv(ftop/cp/timeServ_nowInCC/sync/sRST_inv1_INV_0:O) | NONE(ftop/cp/timeServ_nowInCC/sync/dLastState) | 6 | +ftop/iqadc/adcCore_acquireD/sync/sRST_inv(ftop/iqadc/adcCore_acquireD/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_acquireD/sync/dLastState) | 6 | +ftop/iqadc/adcCore_averageD/sync/sRST_inv(ftop/iqadc/adcCore_averageD/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_averageD/sync/dLastState) | 6 | +ftop/iqadc/adcCore_maxBurstLengthR/sync/sRST_inv(ftop/iqadc/adcCore_maxBurstLengthR/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_maxBurstLengthR/sync/dLastState)| 6 | +ftop/iqadc/adcCore_operateD/sync/sRST_inv(ftop/iqadc/adcCore_operateD/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_operateD/sync/dLastState) | 6 | +ftop/iqadc/adcCore_sampCC/sync/sRST_inv(ftop/iqadc/adcCore_sampCC/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_sampCC/sync/dLastState) | 6 | +ftop/iqadc/adcCore_statsCC/sync/sRST_inv(ftop/iqadc/adcCore_statsCC/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_statsCC/sync/dLastState) | 6 | +ftop/sma0/wciS0_MReset_n_inv(ftop/sma0/wciS0_MReset_n_inv571_INV_0:O) | NONE(ftop/sma0/wci_wslv_isReset_isInReset) | 4 | +ftop/sma1/wciS0_MReset_n_inv(ftop/sma1/wciS0_MReset_n_inv611_INV_0:O) | NONE(ftop/sma1/wci_wslv_isReset_isInReset) | 4 | +ftop/bias/wciS0_MReset_n_inv(ftop/bias/wciS0_MReset_n_inv321_INV_0:O) | NONE(ftop/bias/wci_wslv_isReset_isInReset) | 3 | +ftop/gbe0/gmac/gmac/rxRS_rxOperateS/sRST_inv(ftop/gbe0/gmac/gmac/rxRS_rxOperateS/sRST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg1) | 3 | +ftop/gbe0/gmac/gmac/txRS_txOperateS/sRST_inv(ftop/gbe0/gmac/gmac/txRS_txOperateS/sRST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg1) | 3 | +ftop/gbe0/gmac/rxOper/sRST_inv(ftop/gbe0/gmac/rxOper/sRST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/rxOper/dSyncReg1) | 3 | +ftop/gbe0/gmac/txOper/sRST_inv(ftop/gbe0/gmac/txOper/sRST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/txOper/dSyncReg1) | 3 | +ftop/iqadc/adcCore_spiI_cd/RST_inv(ftop/iqadc/adcCore_spiI_cd/RST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_spiI_cd/cntr_0) | 3 | +ftop/edp0/RST_N_inv(ftop/edp0/RST_N_inv1241_INV_0:O) | NONE(ftop/edp0/wci_isReset_isInReset) | 2 | +ftop/edp1/RST_N_inv(ftop/edp1/RST_N_inv1381_INV_0:O) | NONE(ftop/edp1/wci_isReset_isInReset) | 2 | +ftop/gbe0/gmac/gmac/rxRS_rxRst/IN_RST_inv(ftop/gbe0/gmac/gmac/rxRS_rxRst/IN_RST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold_0) | 2 | +ftop/gbe0/gmac/gmac/txRS_txRst/IN_RST_inv(ftop/gbe0/gmac/gmac/txRS_txRst/IN_RST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/txRS_txRst/reset_hold_0) | 2 | +ftop/gmiixo_rst/IN_RST_inv(ftop/gmiixo_rst/IN_RST_inv1_INV_0:O) | NONE(ftop/gmiixo_rst/reset_hold_0) | 2 | +ftop/iqadc/adcCore_acquireD/sRST_inv(ftop/iqadc/adcCore_acquireD/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_acquireD/dD_OUT_0) | 2 | +ftop/iqadc/adcCore_averageD/sRST_inv(ftop/iqadc/adcCore_averageD/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_averageD/dD_OUT_0) | 2 | +ftop/iqadc/adcCore_operateD/sRST_inv(ftop/iqadc/adcCore_operateD/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_operateD/dD_OUT_0) | 2 | +ftop/iqadc/adcCore_sdrRst/IN_RST_inv(ftop/iqadc/adcCore_sdrRst/IN_RST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_sdrRst/reset_hold_0) | 2 | +ftop/iqadc/adcCore_spiI_slowReset/IN_RST_inv(ftop/iqadc/adcCore_spiI_slowReset/IN_RST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_spiI_slowReset/reset_hold_0) | 2 | +ftop/cp/wci_mReset_10/RST_inv(ftop/cp/wci_mReset_10/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_10/rst_rnm0) | 1 | +ftop/cp/wci_mReset_13/RST_inv(ftop/cp/wci_mReset_13/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_13/rst_rnm0) | 1 | +ftop/cp/wci_mReset_14/RST_inv(ftop/cp/wci_mReset_14/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_14/rst_rnm0) | 1 | +ftop/cp/wci_mReset_2/RST_inv(ftop/cp/wci_mReset_2/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_2/rst_rnm0) | 1 | +ftop/cp/wci_mReset_3/RST_inv(ftop/cp/wci_mReset_3/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_3/rst_rnm0) | 1 | +ftop/cp/wci_mReset_4/RST_inv(ftop/cp/wci_mReset_4/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_4/rst_rnm0) | 1 | +ftop/cp/wci_mReset_7/RST_inv(ftop/cp/wci_mReset_7/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_7/rst_rnm0) | 1 | +ftop/cp/wci_mReset_9/RST_inv(ftop/cp/wci_mReset_9/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_9/rst_rnm0) | 1 | +ftop/gbe0/phyRst/RST_inv(ftop/gbe0/phyRst/RST_inv1_INV_0:O) | NONE(ftop/gbe0/phyRst/rst_rnm0) | 1 | +ftop/gbewrk/wciS0_MReset_n_inv(ftop/gbewrk/wciS0_MReset_n_inv1_INV_0:O) | NONE(ftop/gbewrk/wci_wslv_isReset_isInReset) | 1 | +ftop/pwrk/wciS0_MReset_n_inv(ftop/pwrk/wciS0_MReset_n_inv1_INV_0:O) | NONE(ftop/pwrk/wci_wslv_isReset_isInReset) | 1 | +-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: 8.680ns (Maximum Frequency: 115.206MHz) + Minimum input arrival time before clock: 1.378ns + Maximum output required time after clock: 7.658ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys0_clkp' + Clock period: 7.807ns (frequency: 128.096MHz) + Total number of paths / destination ports: 5270246 / 44078 +------------------------------------------------------------------------- +Delay: 15.613ns (Levels of Logic = 46) + Source: ftop/cp/cpReq_37 (FF) + Destination: ftop/cp/cpRespF/data0_reg_0 (FF) + Source Clock: sys0_clkp rising 0.5X + Destination Clock: sys0_clkp rising 0.5X + + Data Path: ftop/cp/cpReq_37 to ftop/cp/cpRespF/data0_reg_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDSE:C->Q 38 0.495 1.182 cpReq_37 (cpReq_37) + LUT2_D:I0->O 4 0.561 0.501 WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F_cmp_eq00011 (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F_cmp_eq0001) + LUT4:I3->O 17 0.561 0.895 _theResult_____1__h76813<1>1 (_theResult_____1__h76813<1>) + LUT4_D:I3->O 11 0.561 0.816 WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000) + LUT3:I2->O 19 0.561 0.988 WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T1 (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + LUT4:I1->O 1 0.562 0.000 WILL_FIRE_RL_completeWorkerRead_wg_lut<1> (WILL_FIRE_RL_completeWorkerRead_wg_lut<1>) + MUXCY:S->O 1 0.523 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<1> (WILL_FIRE_RL_completeWorkerRead_wg_cy<1>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<2> (WILL_FIRE_RL_completeWorkerRead_wg_cy<2>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<3> (WILL_FIRE_RL_completeWorkerRead_wg_cy<3>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<4> (WILL_FIRE_RL_completeWorkerRead_wg_cy<4>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<5> (WILL_FIRE_RL_completeWorkerRead_wg_cy<5>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<6> (WILL_FIRE_RL_completeWorkerRead_wg_cy<6>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<7> (WILL_FIRE_RL_completeWorkerRead_wg_cy<7>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<8> (WILL_FIRE_RL_completeWorkerRead_wg_cy<8>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<9> (WILL_FIRE_RL_completeWorkerRead_wg_cy<9>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<10> (WILL_FIRE_RL_completeWorkerRead_wg_cy<10>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<11> (WILL_FIRE_RL_completeWorkerRead_wg_cy<11>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<12> (WILL_FIRE_RL_completeWorkerRead_wg_cy<12>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<13> (WILL_FIRE_RL_completeWorkerRead_wg_cy<13>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<14> (WILL_FIRE_RL_completeWorkerRead_wg_cy<14>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<15> (WILL_FIRE_RL_completeWorkerRead_wg_cy<15>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<16> (WILL_FIRE_RL_completeWorkerRead_wg_cy<16>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<17> (WILL_FIRE_RL_completeWorkerRead_wg_cy<17>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<18> (WILL_FIRE_RL_completeWorkerRead_wg_cy<18>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<19> (WILL_FIRE_RL_completeWorkerRead_wg_cy<19>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<20> (WILL_FIRE_RL_completeWorkerRead_wg_cy<20>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<21> (WILL_FIRE_RL_completeWorkerRead_wg_cy<21>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<22> (WILL_FIRE_RL_completeWorkerRead_wg_cy<22>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<23> (WILL_FIRE_RL_completeWorkerRead_wg_cy<23>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<24> (WILL_FIRE_RL_completeWorkerRead_wg_cy<24>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<25> (WILL_FIRE_RL_completeWorkerRead_wg_cy<25>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<26> (WILL_FIRE_RL_completeWorkerRead_wg_cy<26>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<27> (WILL_FIRE_RL_completeWorkerRead_wg_cy<27>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<28> (WILL_FIRE_RL_completeWorkerRead_wg_cy<28>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<29> (WILL_FIRE_RL_completeWorkerRead_wg_cy<29>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<30> (WILL_FIRE_RL_completeWorkerRead_wg_cy<30>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<31> (WILL_FIRE_RL_completeWorkerRead_wg_cy<31>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<32> (WILL_FIRE_RL_completeWorkerRead_wg_cy<32>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<33> (WILL_FIRE_RL_completeWorkerRead_wg_cy<33>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<34> (WILL_FIRE_RL_completeWorkerRead_wg_cy<34>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<35> (WILL_FIRE_RL_completeWorkerRead_wg_cy<35>) + MUXCY:CI->O 10 0.179 0.773 WILL_FIRE_RL_completeWorkerRead_wg_cy<36> (WILL_FIRE_RL_completeWorkerRead) + LUT3:I2->O 7 0.561 0.604 cpRespF_ENQ1 (cpRespF_ENQ) + begin scope: 'cpRespF' + LUT4_D:I3->O 39 0.561 1.077 d0h1 (d0h) + LUT4_L:I3->LO 1 0.561 0.123 data0_reg_or0000<8>_SW0 (N2) + LUT3:I2->O 1 0.561 0.000 data0_reg_8_rstpot (data0_reg_8_rstpot) + FD:D 0.197 data0_reg_8 + ---------------------------------------- + Total 15.613ns (8.654ns logic, 6.959ns route) + (55.4% logic, 44.6% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'gmii_sysclk' + Clock period: 8.680ns (frequency: 115.206MHz) + Total number of paths / destination ports: 13746 / 1319 +------------------------------------------------------------------------- +Delay: 8.680ns (Levels of Logic = 7) + Source: ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_8 (FF) + Source Clock: gmii_sysclk rising + Destination Clock: gmii_sysclk rising + + Data Path: ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_8 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 24 0.495 1.172 dSyncReg2 (dSyncReg2) + end scope: 'txRS_txOperateS' + LUT2_D:I0->O 15 0.561 0.930 txRS_txData_D_IN<0>46 (N38) + LUT4_D:I1->O 10 0.562 0.752 MUX_txRS_crc_add_1__SEL_11 (MUX_txRS_crc_add_1__SEL_1) + LUT4:I3->O 11 0.561 0.859 txRS_crc_add_data<0>2 (txRS_crc_add_data<0>) + begin scope: 'txRS_crc' + LUT2_D:I1->O 3 0.562 0.453 rRemainder_D_IN<19>11 (N0) + LUT4:I3->O 3 0.561 0.453 rRemainder_D_IN<11>11 (N12) + LUT4:I3->O 1 0.561 0.000 rRemainder_D_IN<8> (rRemainder_D_IN<8>) + FDSE:D 0.197 rRemainder_8 + ---------------------------------------- + Total 8.680ns (4.060ns logic, 4.620ns route) + (46.8% logic, 53.2% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/iqadc/adcCore_spiI_cd/cntr_2' + Clock period: 6.274ns (frequency: 159.394MHz) + Total number of paths / destination ports: 223 / 63 +------------------------------------------------------------------------- +Delay: 6.274ns (Levels of Logic = 8) + Source: ftop/iqadc/adcCore_spiI_slowReset/reset_hold_1 (FF) + Destination: ftop/iqadc/adcCore_spiI_doResp (FF) + Source Clock: ftop/iqadc/adcCore_spiI_cd/cntr_2 rising + Destination Clock: ftop/iqadc/adcCore_spiI_cd/cntr_2 rising + + Data Path: ftop/iqadc/adcCore_spiI_slowReset/reset_hold_1 to ftop/iqadc/adcCore_spiI_doResp + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 3 0.495 0.559 reset_hold_1 (reset_hold_1) + end scope: 'adcCore_spiI_slowReset' + begin scope: 'adcCore_spiI_reqF_dCombinedReset' + LUT2:I0->O 2 0.561 0.380 RST_OUT1 (RST_OUT) + end scope: 'adcCore_spiI_reqF_dCombinedReset' + begin scope: 'adcCore_spiI_reqF_dInReset' + INV:I->O 12 0.562 0.819 VAL1_INV_0 (VAL) + end scope: 'adcCore_spiI_reqF_dInReset' + LUT4_D:I3->O 6 0.561 0.571 adcCore_spiI_doResp_D_IN21 (N224) + LUT4:I3->O 2 0.561 0.446 adcCore_spiI_doResp_D_IN31 (MUX_adcCore_spiI_xmt_d_write_1__SEL_2) + LUT2:I1->O 1 0.562 0.000 adcCore_spiI_doResp_D_IN1 (adcCore_spiI_doResp_D_IN) + FDR:D 0.197 adcCore_spiI_doResp + ---------------------------------------- + Total 6.274ns (3.499ns logic, 2.775ns route) + (55.8% logic, 44.2% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'gmii_rx_clk' + Clock period: 6.550ns (frequency: 152.681MHz) + Total number of paths / destination ports: 2319 / 310 +------------------------------------------------------------------------- +Delay: 6.550ns (Levels of Logic = 6) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_3 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_4 (FF) + Source Clock: gmii_rx_clk rising + Destination Clock: gmii_rx_clk rising + + Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_3 to ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 4 0.495 0.607 rxRS_rxAPipe_3 (rxRS_rxAPipe_3) + LUT2_L:I0->LO 1 0.561 0.102 MUX_rxRS_rxF_enq_1__SEL_1113 (MUX_rxRS_rxF_enq_1__SEL_1113) + LUT4:I3->O 2 0.561 0.488 MUX_rxRS_rxF_enq_1__SEL_1116 (MUX_rxRS_rxF_enq_1__SEL_1116) + LUT4:I0->O 14 0.561 0.916 WILL_FIRE_RL_rxRS_ingress_noadvance1 (WILL_FIRE_RL_rxRS_ingress_noadvance) + begin scope: 'rxRS_crc' + LUT2_D:I1->O 20 0.562 0.939 rRemainder_D_IN<16>21 (N14) + LUT4:I3->O 1 0.561 0.000 rRemainder_D_IN<22>1 (rRemainder_D_IN<22>) + FDSE:D 0.197 rRemainder_22 + ---------------------------------------- + Total 6.550ns (3.498ns logic, 3.052ns route) + (53.4% logic, 46.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'sys0_clkp' + Total number of paths / destination ports: 30 / 30 +------------------------------------------------------------------------- +Offset: 1.378ns (Levels of Logic = 2) + Source: fpga_rstn (PAD) + Destination: ftop/clkN210/rst_fd (FF) + Destination Clock: sys0_clkp rising + + Data Path: fpga_rstn to ftop/clkN210/rst_fd + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.824 0.357 fpga_rstn_IBUF (fpga_rstn_IBUF) + begin scope: 'ftop' + begin scope: 'clkN210' + FD:D 0.197 rst_fd + ---------------------------------------- + Total 1.378ns (1.021ns logic, 0.357ns route) + (74.1% logic, 25.9% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/iqadc/adcCore_spiI_cd/cntr_2' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 1.378ns (Levels of Logic = 2) + Source: adc_smiso (PAD) + Destination: ftop/iqadc/adcCore_spiI_sdiP (FF) + Destination Clock: ftop/iqadc/adcCore_spiI_cd/cntr_2 falling + + Data Path: adc_smiso to ftop/iqadc/adcCore_spiI_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.824 0.357 adc_smiso_IBUF (adc_smiso_IBUF) + begin scope: 'ftop' + begin scope: 'iqadc' + FD:D 0.197 adcCore_spiI_sdiP + ---------------------------------------- + Total 1.378ns (1.021ns logic, 0.357ns route) + (74.1% logic, 25.9% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'gmii_rx_clk' + Total number of paths / destination ports: 10 / 10 +------------------------------------------------------------------------- +Offset: 1.378ns (Levels of Logic = 3) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxData_0 (FF) + Destination Clock: gmii_rx_clk rising + + Data Path: gmii_rxd<0> to ftop/gbe0/gmac/gmac/rxRS_rxData_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.824 0.357 gmii_rxd_0_IBUF (gmii_rxd_0_IBUF) + begin scope: 'ftop' + begin scope: 'gbe0' + begin scope: 'gmac' + begin scope: 'gmac' + FD:D 0.197 rxRS_rxData_0 + ---------------------------------------- + Total 1.378ns (1.021ns logic, 0.357ns route) + (74.1% logic, 25.9% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys0_clkp' + Total number of paths / destination ports: 48 / 21 +------------------------------------------------------------------------- +Offset: 7.658ns (Levels of Logic = 5) + Source: ftop/ledLogic/freeCnt_23 (FF) + Destination: led<5> (PAD) + Source Clock: sys0_clkp rising 0.5X + + Data Path: ftop/ledLogic/freeCnt_23 to led<5> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 6 0.495 0.677 freeCnt_23 (freeCnt_23) + LUT4:I0->O 1 0.561 0.000 led<3>2 (led<3>2) + MUXF5:I0->O 2 0.229 0.382 led<3>_f5 (led<3>) + LUT4:I3->O 1 0.561 0.357 led<4>1 (led<4>) + end scope: 'ledLogic' + end scope: 'ftop' + OBUF:I->O 4.396 led_5_OBUF (led<5>) + ---------------------------------------- + Total 7.658ns (6.242ns logic, 1.416ns route) + (81.5% logic, 18.5% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'gmii_sysclk' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 5.248ns (Levels of Logic = 3) + Source: ftop/gbe0/gmac/gmac/gmacLED (FF) + Destination: gmii_led (PAD) + Source Clock: gmii_sysclk rising + + Data Path: ftop/gbe0/gmac/gmac/gmacLED to gmii_led + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.495 0.357 gmacLED (gmacLED) + end scope: 'gmac' + end scope: 'gmac' + end scope: 'gbe0' + end scope: 'ftop' + OBUF:I->O 4.396 gmii_led_OBUF (gmii_led) + ---------------------------------------- + Total 5.248ns (4.891ns logic, 0.357ns route) + (93.2% logic, 6.8% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/iqadc/adcCore_spiI_cd/cntr_2' + Total number of paths / destination ports: 4 / 3 +------------------------------------------------------------------------- +Offset: 6.233ns (Levels of Logic = 3) + Source: ftop/iqadc/adcCore_spiI_cGate (FF) + Destination: adc_sclk (PAD) + Source Clock: ftop/iqadc/adcCore_spiI_cd/cntr_2 rising + + Data Path: ftop/iqadc/adcCore_spiI_cGate to adc_sclk + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 1 0.495 0.423 adcCore_spiI_cGate (adcCore_spiI_cGate) + end scope: 'iqadc' + end scope: 'ftop' + LUT3:I1->O 1 0.562 0.357 adc_sclk1 (adc_sclk_OBUF) + OBUF:I->O 4.396 adc_sclk_OBUF (adc_sclk) + ---------------------------------------- + Total 6.233ns (5.453ns logic, 0.780ns route) + (87.5% logic, 12.5% route) + +========================================================================= + + +Total REAL time to Xst completion: 447.00 secs +Total CPU time to Xst completion: 446.50 secs + +--> + + +Total memory usage is 1436944 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 1676 ( 0 filtered) +Number of infos : 212 ( 0 filtered) + diff --git a/logs/n210-20120924_1549/fpgaTop.bld b/logs/n210-20120924_1549/fpgaTop.bld new file mode 100644 index 00000000..598d2a4d --- /dev/null +++ b/logs/n210-20120924_1549/fpgaTop.bld @@ -0,0 +1,668 @@ +Release 14.2 ngdbuild P.28xd (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +Command Line: /opt/Xilinx/14.2/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -sd +../../coregen/pcie_4243_axi_k6_gtx_x4_250 -sd ../../coregen/fft_v5_4k_strm_nat +-sd ../../coregen/ddc_4243_4ch_v5 -aul -aut -uc n210.ucf -p xc3sd3400a-fg676-5 +fpgaTop_csi.ngc fpgaTop.ngd + +Reading NGO file "/home/shep/projects/ocpi/build/tmp-n210/fpgaTop_csi.ngc" ... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "n210.ucf" ... +Resolving constraint associations... +Checking Constraint Associations... +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into DCM_SP instance dcm. The following new TNM + groups and period specifications were generated at the DCM_SP output(s): + CLK0: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into DCM_SP instance dcm. The following new TNM + groups and period specifications were generated at the DCM_SP output(s): + CLKDV: + +Done... + +INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance + dcm to 10.000000 ns based on the period specification ( [n210.ucf(470)]). +Checking expanded design ... +WARNING:NgdBuild:452 - logical net 'N4' has no driver +WARNING:NgdBuild:452 - logical net 'N5' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/adc_clkout' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<10>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<11>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<8>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<9>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<8>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<9>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<8>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<9>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<8>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<9>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<8>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MAddr<9>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_3_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<8>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MAddr<9>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_4_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<8>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MAddr<9>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_7_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<8>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MAddr<9>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_9_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<10>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<11>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<12>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<13>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<14>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<15>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<16>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<17>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<20>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<21>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<22>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<23>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<24>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<25>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<26>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<27>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<30>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<31>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<32>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<33>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<34>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<35>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<36>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<37>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0_client_request_get<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<10>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<11>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<12>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<13>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<14>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<15>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<16>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<17>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1_client_request_get<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<4>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<5>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<6>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<7>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<8>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp1_wmiS0_SData<9>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<10>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<11>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<12>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<13>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<14>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<15>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<16>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<17>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<20>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<21>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<22>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<23>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<24>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<25>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<26>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<27>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<30>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<31>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<32>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<33>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<34>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<35>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<36>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<37>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client1_request_get<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<10>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<11>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<12>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<13>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<14>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<15>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<16>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<17>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/flash_miso_i' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/gmii_col_i' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/gmii_crs_i' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/gmii_intr_i' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MAddr<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MAddr<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MDataByteEn<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MDataByteEn<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MDataByteEn<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MDataByteEn<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MDataLast' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<10>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<11>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<8>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<9>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MAddr<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MAddr<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MDataByteEn<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MDataByteEn<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MDataByteEn<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MDataByteEn<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MDataLast' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<4>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<5>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<6>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<7>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<32>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<33>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<34>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<35>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<36>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<37>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<4>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<5>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<6>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp0/edpReqF_D_OUT<7>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<32>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<33>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<34>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<35>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<36>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<37>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<4>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<5>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<6>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/edp0/edp_inF_D_OUT<7>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<4>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<5>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<6>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/emux/fork0_d1F_D_OUT<7>' has no driver + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 488 + +Total memory usage is 616744 kilobytes + +Writing NGD file "fpgaTop.ngd" ... +Total REAL time to NGDBUILD completion: 16 sec +Total CPU time to NGDBUILD completion: 16 sec + +Writing NGDBUILD log file "fpgaTop.bld"... diff --git a/logs/n210-20120924_1549/fpgaTop.par b/logs/n210-20120924_1549/fpgaTop.par new file mode 100644 index 00000000..617cc55e --- /dev/null +++ b/logs/n210-20120924_1549/fpgaTop.par @@ -0,0 +1,363 @@ +Release 14.2 par P.28xd (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +core980:: Mon Sep 24 15:42:41 2012 + +par -w -xe n fpgaTop_map.ncd fpgaTop.ncd fpgaTop.pcf + + +Constraints file: fpgaTop.pcf. +Loading device for application Rf_Device from file '3sd3400a.nph' in environment /opt/Xilinx/14.2/ISE_DS/ISE/. + "fpgaTop" is an NCD, version 3.2, device xc3sd3400a, package fg676, speed -5 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) + + +Device speed data version: "PRODUCTION 1.34 2012-07-09". + + +Design Summary Report: + + Number of External IOBs 109 out of 469 23% + + Number of External Input IOBs 47 + + Number of External Input IBUFs 47 + Number of LOCed External Input IBUFs 47 out of 47 100% + + + Number of External Output IOBs 59 + + Number of External Output IOBs 59 + Number of LOCed External Output IOBs 59 out of 59 100% + + + Number of External Bidir IOBs 1 + + Number of External Bidir IOBs 1 + Number of LOCed External Bidir IOBs 1 out of 1 100% + + + Number of BUFGMUXs 5 out of 24 20% + Number of LOCed BUFGMUXs 1 out of 5 20% + + Number of DCMs 1 out of 8 12% + Number of DNA_PORTs 1 out of 1 100% + Number of RAMB16BWERs 47 out of 126 37% + Number of Slices 18910 out of 23872 79% + Number of SLICEMs 1294 out of 11936 10% + + + +Overall effort level (-ol): Standard +Placer effort level (-pl): High +Placer cost table entry (-t): 1 +Router effort level (-rl): High +Extra effort level (-xe): Normal + + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN + bel_d_dcm_dll_lowf_minperiod_clkin + Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MINIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN + bel_d_dcm_dll_lowf_maxperiod_clkin + Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MAXIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" +Starting initial Timing Analysis. REAL time: 20 secs +Finished initial Timing Analysis. REAL time: 21 secs + +WARNING:Par:288 - The signal adc_clkout_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal flash_miso_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal gmii_col_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal gmii_crs_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal gmii_intr_IBUF has no load. PAR will not attempt to route this signal. + +Starting Placer +Total REAL time at the beginning of Placer: 21 secs +Total CPU time at the beginning of Placer: 21 secs + +Phase 1.1 Initial Placement Analysis +Phase 1.1 Initial Placement Analysis (Checksum:b7b97256) REAL time: 23 secs + +Phase 2.7 Design Feasibility Check +Phase 2.7 Design Feasibility Check (Checksum:b7b97256) REAL time: 23 secs + +Phase 3.31 Local Placement Optimization +Phase 3.31 Local Placement Optimization (Checksum:da692ce1) REAL time: 23 secs + +Phase 4.2 Initial Clock and IO Placement + +WARNING:Place:619 - This design is using a Side-BUFG site due to placement constraints on a BUFG, DCM, clock IOB or the + loads of these components. It is recommended that Top and Bottom BUFG sites be used instead of Side-BUFG sites + whenever possible because they can reach every clock region on the device. Side-BUFG sites can reach only clock + regions on the same side of the device and also preclude the use of certain Top and Bottom BUFGs in the same clock + region. +Phase 4.2 Initial Clock and IO Placement (Checksum:6e1b4409) REAL time: 30 secs + +............................ +..................................................................................................... +Phase 5.30 Global Clock Region Assignment +Phase 5.30 Global Clock Region Assignment (Checksum:6e1b4409) REAL time: 49 secs + +Phase 6.36 Local Placement Optimization +Phase 6.36 Local Placement Optimization (Checksum:6e1b4409) REAL time: 49 secs + +Phase 7.8 Global Placement +.......................... +............................................................................................................................................................................... +............................................ +...................................................................................................................................................................... +........................................ +...................................... +.................... +.............................. +Phase 7.8 Global Placement (Checksum:dc58af34) REAL time: 2 mins 15 secs + +Phase 8.5 Local Placement Optimization +Phase 8.5 Local Placement Optimization (Checksum:dc58af34) REAL time: 2 mins 16 secs + +Phase 9.18 Placement Optimization +Phase 9.18 Placement Optimization (Checksum:1b351ce3) REAL time: 2 mins 44 secs + +Phase 10.5 Local Placement Optimization +Phase 10.5 Local Placement Optimization (Checksum:1b351ce3) REAL time: 2 mins 45 secs + +Total REAL time to Placer completion: 2 mins 46 secs +Total CPU time to Placer completion: 2 mins 46 secs +Writing design to file fpgaTop.ncd + + + + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN + bel_d_dcm_dll_lowf_minperiod_clkin + Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MINIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN + bel_d_dcm_dll_lowf_maxperiod_clkin + Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MAXIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN + bel_d_dcm_dll_lowf_minperiod_clkin + Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MINIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN + bel_d_dcm_dll_lowf_maxperiod_clkin + Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MAXIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" +Starting Router + + +Phase 1 : 133686 unrouted; REAL time: 3 mins 8 secs + +Phase 2 : 114342 unrouted; REAL time: 3 mins 11 secs + +Phase 3 : 31654 unrouted; REAL time: 3 mins 28 secs + +Phase 4 : 31658 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 32 secs + +Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 56 secs + +Updating file: fpgaTop.ncd with current fully routed design. + +Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins 13 secs + +Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins 16 secs + +Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins 25 secs +WARNING:Route:455 - CLK Net:ftop/clkIn_O may have excessive skew because + 2 CLK pins and 0 NON_CLK pins failed to route using a CLK template. +WARNING:Route:455 - CLK Net:adc_sclkdrv may have excessive skew because + 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. + +Total REAL time to Router completion: 4 mins 27 secs +Total CPU time to Router completion: 4 mins 27 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| ftop/sys1Clk | BUFGMUX_X1Y0| No |11145 | 0.467 | 1.826 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/gmiixo_clk_O | BUFGMUX_X3Y8| No | 411 | 0.291 | 1.055 | ++---------------------+--------------+------+------+------------+-------------+ +| gmii_rx_clk_BUFGP | BUFGMUX_X3Y6|Yes | 80 | 0.204 | 1.007 | ++---------------------+--------------+------+------+------------+-------------+ +| adc_sclkdrv | BUFGMUX_X1Y10| No | 27 | 0.132 | 1.554 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/sys0Clk | BUFGMUX_X2Y1| No | 2 | 0.000 | 1.437 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/clkIn_O | Local| | 4 | 1.965 | 3.595 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/cp/dna_cnt<0> | Local| | 11 | 0.000 | 4.660 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + +* The fanout is the number of component pins not the individual BEL loads, +for example SLICE loads not FF loads. + +Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +---------------------------------------------------------------------------------------------------------- + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +---------------------------------------------------------------------------------------------------------- + TS_GMIISYSCLK = PERIOD TIMEGRP "GMIISYSCL | SETUP | 0.111ns| 7.889ns| 0| 0 + K" 8 ns HIGH 50% | HOLD | 0.601ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_ftop_clkN210_clkdv_unbuf = PERIOD TIME | SETUP | 0.503ns| 19.497ns| 0| 0 + GRP "ftop_clkN210_clkdv_unbuf" TS | HOLD | 0.440ns| | 0| 0 + _SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_GMIIRXCLK = PERIOD TIMEGRP "GMIIRXCLK" | SETUP | 1.083ns| 6.917ns| 0| 0 + 8 ns HIGH 50% | HOLD | 0.736ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_ftop_clkN210_clk0_unbuf = PERIOD TIMEG | SETUP | 3.467ns| 6.533ns| 0| 0 + RP "ftop_clkN210_clk0_unbuf" TS_S | HOLD | 4.695ns| | 0| 0 + YS0CLK HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 10 | SETUP | 8.414ns| 1.586ns| 0| 0 + ns HIGH 50% | HOLD | 0.915ns| | 0| 0 + | MINLOWPULSE | 5.200ns| 4.800ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + + +Derived Constraint Report +Review Timing Report for more details on the following derived constraints. +To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" +or "Run Timing Analysis" from Timing Analyzer (timingan). +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 10.000ns| 4.800ns| 9.748ns| 0| 0| 2| 5249683| +| TS_ftop_clkN210_clk0_unbuf | 10.000ns| 6.533ns| N/A| 0| 0| 1| 0| +| TS_ftop_clkN210_clkdv_unbuf | 20.000ns| 19.497ns| N/A| 0| 0| 5249682| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +All constraints were met. + + +Generating Pad Report. + +All signals are completely routed. + +WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + +Total REAL time to PAR completion: 4 mins 36 secs +Total CPU time to PAR completion: 4 mins 35 secs + +Peak Memory Usage: 1250 MB + +Placement: Completed - No errors found. +Routing: Completed - No errors found. +Timing: Completed - No errors found. + +Number of error messages: 0 +Number of warning messages: 10 +Number of info messages: 0 + +Writing design to file fpgaTop.ncd + + + +PAR done! diff --git a/logs/n210-20120924_1549/fpgaTop.twr b/logs/n210-20120924_1549/fpgaTop.twr new file mode 100644 index 00000000..0e75387f --- /dev/null +++ b/logs/n210-20120924_1549/fpgaTop.twr @@ -0,0 +1,5946 @@ +-------------------------------------------------------------------------------- +Release 14.2 Trace (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +/opt/Xilinx/14.2/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 20 -fastpaths -xml +fpgaTop.twx fpgaTop.ncd -o fpgaTop.twr fpgaTop.pcf + +Design file: fpgaTop.ncd +Physical constraint file: fpgaTop.pcf +Device,package,speed: xc3sd3400a,fg676,-5 (PRODUCTION 1.34 2012-07-09) +Report level: verbose report, limited to 20 items per constraint + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. +INFO:Timing:3390 - This architecture does not support a default System Jitter + value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock + Uncertainty calculation. +INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and + 'Phase Error' calculations, these terms will be zero in the Clock + Uncertainty calculation. Please make appropriate modification to + SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase + Error. +184 logic loops found and disabled. + + ---------------------------------------------------------------------- + ! Warning: The following connections close logic loops, and some paths ! + ! through these connections may not be analyzed. To better ! + ! understand the logic associated with these loops, run a ! + ! Analyze Against User-Defined End-Point Analysis inside ! + ! Timing Analyzer (timingan) with the listed signal as a ! + ! source NET (*signal_name). The Timing Report will display ! + ! all the paths associated with this signal and the logic ! + ! loop will be reported. ! + ! ! + ! Signal Driver Load ! + ! -------------------------------- ---------------- ---------------- ! + ! nter_rsCounter_write_1__VAL_1<1> SLICE_X0Y21.X SLICE_X0Y20.F2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X0Y20.G3 ! + ! nter_rsCounter_write_1__VAL_1<1> SLICE_X0Y21.X SLICE_X0Y20.G2 ! + ! nter_rsCounter_write_1__VAL_1<1> SLICE_X0Y21.X SLICE_X1Y23.F1 ! + ! nter_rsCounter_write_1__VAL_1<2> SLICE_X1Y18.X SLICE_X0Y19.F3 ! + ! nter_rsCounter_write_1__VAL_1<0> SLICE_X3Y18.X SLICE_X3Y19.F2 ! + ! nter_rsCounter_write_1__VAL_1<0> SLICE_X3Y18.X SLICE_X3Y19.G2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X3Y19.G3 ! + ! ftop/iqadc/N369 SLICE_X3Y22.X SLICE_X3Y19.G1 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X3Y19.G4 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X3Y19.BX ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X7Y25.F2 ! + ! nter_rsCounter_write_1__VAL_1<4> SLICE_X0Y27.X SLICE_X3Y26.F2 ! + ! nter_rsCounter_write_1__VAL_1<4> SLICE_X0Y27.X SLICE_X3Y26.G2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X3Y26.G4 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X3Y24.F1 ! + ! nter_rsCounter_write_1__VAL_1<5> SLICE_X1Y27.X SLICE_X1Y25.F1 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X1Y25.G4 ! + ! nter_rsCounter_write_1__VAL_1<5> SLICE_X1Y27.X SLICE_X1Y25.G1 ! + ! ftop/iqadc/N370 SLICE_X3Y24.X SLICE_X1Y25.G3 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X1Y25.G2 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X1Y25.BX ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X1Y27.G4 ! + ! ftop/iqadc/N223 SLICE_X3Y25.X SLICE_X1Y27.G1 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X1Y27.G3 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X1Y27.BX ! + ! nter_rsCounter_write_1__VAL_1<4> SLICE_X0Y27.X SLICE_X2Y20.F2 ! + ! nter_rsCounter_write_1__VAL_1<3> SLICE_X1Y21.X SLICE_X1Y20.F1 ! + ! nter_rsCounter_write_1__VAL_1<3> SLICE_X1Y21.X SLICE_X1Y20.G1 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X1Y20.G3 ! + ! ftop/iqadc/N369 SLICE_X3Y22.X SLICE_X1Y20.G4 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X1Y20.G2 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X1Y20.BX ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X3Y25.G3 ! + ! ftop/iqadc/Mmux__varindex0000_5_f7SLICE_X6Y25.Y SLICE_X3Y25.G4 ! + ! ftop/iqadc/x__h8844<4> SLICE_X3Y22.Y SLICE_X3Y25.G2 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X1Y21.G3 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X1Y21.G2 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X1Y21.BX ! + ! ftop/iqadc/N223 SLICE_X3Y25.X SLICE_X0Y26.F4 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X0Y26.F1 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X0Y26.F2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X1Y26.F3 ! + ! nter_rsCounter_write_1__VAL_1<9> SLICE_X0Y26.X SLICE_X1Y26.F1 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X1Y26.F2 ! + ! ftop/iqadc/N369 SLICE_X3Y22.X SLICE_X1Y26.F4 ! + ! nter_rsCounter_write_1__VAL_1<9> SLICE_X0Y26.X SLICE_X1Y26.G4 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X1Y26.BX ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X0Y26.BX ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X3Y27.F2 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X3Y27.F3 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X6Y26.F3 ! + ! ter_rsCounter_write_1__VAL_1<10> SLICE_X3Y27.X SLICE_X6Y26.F4 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X6Y26.F2 ! + ! ftop/iqadc/N369 SLICE_X3Y22.X SLICE_X6Y26.F1 ! + ! ter_rsCounter_write_1__VAL_1<10> SLICE_X3Y27.X SLICE_X6Y26.G2 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X6Y26.BX ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X3Y27.BX ! + ! nter_rsCounter_write_1__VAL_1<7> SLICE_X1Y29.X SLICE_X1Y28.F1 ! + ! nter_rsCounter_write_1__VAL_1<7> SLICE_X1Y29.X SLICE_X1Y28.G3 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X1Y28.G4 ! + ! ftop/iqadc/N370 SLICE_X3Y24.X SLICE_X1Y28.G2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X1Y28.G1 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X1Y28.BX ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X1Y29.G4 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X1Y29.G3 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X1Y29.BX ! + ! ftop/iqadc/N223 SLICE_X3Y25.X SLICE_X2Y27.F3 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X2Y27.F4 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X2Y27.F2 ! + ! nter_rsCounter_write_1__VAL_1<8> SLICE_X2Y27.X SLICE_X2Y26.F2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X2Y26.F1 ! + ! ftop/iqadc/N369 SLICE_X3Y22.X SLICE_X2Y26.F3 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X2Y26.F4 ! + ! nter_rsCounter_write_1__VAL_1<8> SLICE_X2Y27.X SLICE_X2Y26.G2 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X2Y26.BX ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X2Y27.BX ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X2Y30.F4 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X2Y30.F3 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X3Y28.F2 ! + ! ter_rsCounter_write_1__VAL_1<14> SLICE_X2Y30.X SLICE_X3Y28.F1 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X3Y28.F3 ! + ! ftop/iqadc/N370 SLICE_X3Y24.X SLICE_X3Y28.F4 ! + ! ter_rsCounter_write_1__VAL_1<14> SLICE_X2Y30.X SLICE_X3Y28.G1 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X3Y28.BX ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X2Y30.BX ! + ! ter_rsCounter_write_1__VAL_1<13> SLICE_X2Y29.X SLICE_X2Y24.F3 ! + ! ftop/iqadc/N223 SLICE_X3Y25.X SLICE_X2Y19.F3 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X2Y19.F4 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X2Y19.F2 ! + ! ter_rsCounter_write_1__VAL_1<12> SLICE_X2Y19.X SLICE_X2Y18.F4 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X2Y18.F1 ! + ! ftop/iqadc/N370 SLICE_X3Y24.X SLICE_X2Y18.F2 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X2Y18.F3 ! + ! ter_rsCounter_write_1__VAL_1<12> SLICE_X2Y19.X SLICE_X2Y18.G2 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X2Y18.BX ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X2Y19.BX ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X2Y16.F2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X2Y16.F4 ! + ! ter_rsCounter_write_1__VAL_1<11> SLICE_X2Y16.X SLICE_X3Y16.F4 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X3Y16.F3 ! + ! ftop/iqadc/N369 SLICE_X3Y22.X SLICE_X3Y16.F1 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X3Y16.F2 ! + ! ter_rsCounter_write_1__VAL_1<11> SLICE_X2Y16.X SLICE_X3Y16.G4 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X3Y16.BX ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X2Y16.BX ! + ! ftop/iqadc/N405 SLICE_X1Y23.X SLICE_X3Y22.G1 ! + ! nter_rsCounter_write_1__VAL_1<6> SLICE_X0Y31.X SLICE_X1Y31.F3 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X1Y31.G1 ! + ! nter_rsCounter_write_1__VAL_1<6> SLICE_X0Y31.X SLICE_X1Y31.G3 ! + ! ftop/iqadc/N370 SLICE_X3Y24.X SLICE_X1Y31.G2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X1Y31.G4 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X1Y31.BX ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X0Y31.G2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X0Y31.G3 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X0Y31.BX ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X3Y26.G1 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X3Y26.BX ! + ! ftop/iqadc/N223 SLICE_X3Y25.X SLICE_X0Y27.G4 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X0Y27.G1 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X0Y27.G2 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X0Y27.BX ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X7Y25.G3 ! + ! nter_rsCounter_write_1__VAL_1<0> SLICE_X3Y18.X SLICE_X7Y25.G2 ! + ! nter_rsCounter_write_1__VAL_1<2> SLICE_X1Y18.X SLICE_X7Y25.G4 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X7Y25.BX ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X7Y24.F3 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X7Y24.G2 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X7Y24.BX ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X7Y24.BY ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X6Y25.F2 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X6Y25.G3 ! + ! nter_rsCounter_write_1__VAL_1<1> SLICE_X0Y21.X SLICE_X6Y25.G2 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X6Y25.BX ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X6Y24.F3 ! + ! ter_rsCounter_write_1__VAL_1<13> SLICE_X2Y29.X SLICE_X6Y24.F2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X2Y31.F4 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X2Y31.F2 ! + ! ter_rsCounter_write_1__VAL_1<15> SLICE_X2Y31.X SLICE_X3Y30.F3 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X3Y30.F2 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X3Y30.F1 ! + ! ter_rsCounter_write_1__VAL_1<15> SLICE_X2Y31.X SLICE_X3Y30.G3 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X3Y30.BX ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X2Y31.BX ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X6Y24.G1 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X6Y24.BX ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X6Y24.BY ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X6Y25.BY ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X3Y25.F3 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X3Y18.G3 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X3Y18.G4 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X3Y18.BX ! + ! nter_rsCounter_write_1__VAL_1<2> SLICE_X1Y18.X SLICE_X0Y25.F1 ! + ! nter_rsCounter_write_1__VAL_1<1> SLICE_X0Y21.X SLICE_X0Y25.F4 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X0Y25.G4 ! + ! ter_rsCounter_write_1__VAL_1<17> SLICE_X0Y25.Y SLICE_X0Y25.G2 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X0Y28.F3 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X0Y28.F2 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X0Y28.F1 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X2Y28.G4 ! + ! ter_rsCounter_write_1__VAL_1<16> SLICE_X2Y28.Y SLICE_X2Y28.G2 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X0Y28.G2 ! + ! ftop/iqadc/x__h8844<1> SLICE_X1Y22.X SLICE_X0Y28.G1 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X0Y28.G3 ! + ! ter_rsCounter_write_1__VAL_1<13> SLICE_X2Y29.X SLICE_X2Y28.F2 ! + ! ter_rsCounter_write_1__VAL_1<13> SLICE_X2Y29.X SLICE_X2Y21.G4 ! + ! nter_rsCounter_write_1__VAL_1<2> SLICE_X1Y18.X SLICE_X0Y22.F1 ! + ! nter_rsCounter_write_1__VAL_1<1> SLICE_X0Y21.X SLICE_X0Y22.F4 ! + ! nter_rsCounter_write_1__VAL_1<2> SLICE_X1Y18.X SLICE_X0Y19.G3 ! + ! ftop/iqadc/N369 SLICE_X3Y22.X SLICE_X0Y19.G1 ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X0Y19.G2 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X0Y19.BX ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X1Y18.G1 ! + ! ftop/iqadc/x__h8844<2> SLICE_X3Y21.X SLICE_X1Y18.G2 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X1Y18.BX ! + ! ter_rsCounter_write_1__VAL_1<13> SLICE_X2Y29.X SLICE_X2Y21.F4 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X0Y20.BX ! + ! ftop/iqadc/x__h8844<0> SLICE_X0Y24.F5 SLICE_X0Y21.G3 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X0Y21.BX ! + ! ter_rsCounter_write_1__VAL_1<13> SLICE_X2Y29.X SLICE_X2Y25.G3 ! + ! ter_rsCounter_write_1__VAL_1<13> SLICE_X2Y29.X SLICE_X3Y29.F3 ! + ! ter_rsCounter_write_1__VAL_1<13> SLICE_X2Y29.X SLICE_X3Y29.G3 ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X3Y29.BX ! + ! ftop/iqadc/x__h8844<3> SLICE_X2Y23.X SLICE_X2Y29.BX ! + ---------------------------------------------------------------------- + + +================================================================================ +Timing constraint: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 10 ns HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.800ns. +-------------------------------------------------------------------------------- +Slack (setup path): 8.414ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/clkN210/lock_flop (FF) + Destination: ftop/clkN210/lock_flop2 (FF) + Requirement: 10.000ns + Data Path Delay: 1.577ns (Levels of Logic = 1) + Clock Path Skew: -0.009ns (0.054 - 0.063) + Source Clock: ftop/clkIn_O rising at 0.000ns + Destination Clock: ftop/clkIn_O rising at 10.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/clkN210/lock_flop to ftop/clkN210/lock_flop2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X51Y11.YQ Tcko 0.524 ftop/clkN210/locked_d + ftop/clkN210/lock_flop + SLICE_X50Y13.G1 net (fanout=1) 0.382 ftop/clkN210/locked_d + SLICE_X50Y13.CLK Tgck 0.671 ftop/clkN210/unlock3 + ftop/clkN210/edge_cap + ftop/clkN210/lock_flop2 + ------------------------------------------------- --------------------------- + Total 1.577ns (1.195ns logic, 0.382ns route) + (75.8% logic, 24.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 8.747ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/clkN210/lock_flop2 (FF) + Destination: ftop/clkN210/lock_flop3 (FF) + Requirement: 10.000ns + Data Path Delay: 1.253ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: ftop/clkIn_O rising at 0.000ns + Destination Clock: ftop/clkIn_O rising at 10.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/clkN210/lock_flop2 to ftop/clkN210/lock_flop3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X50Y13.YQ Tcko 0.596 ftop/clkN210/unlock3 + ftop/clkN210/lock_flop2 + SLICE_X50Y13.BX net (fanout=2) 0.420 ftop/clkN210/unlock2 + SLICE_X50Y13.CLK Tdick 0.237 ftop/clkN210/unlock3 + ftop/clkN210/lock_flop3 + ------------------------------------------------- --------------------------- + Total 1.253ns (0.833ns logic, 0.420ns route) + (66.5% logic, 33.5% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 10 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.915ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/clkN210/lock_flop2 (FF) + Destination: ftop/clkN210/lock_flop3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.915ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: ftop/clkIn_O rising at 10.000ns + Destination Clock: ftop/clkIn_O rising at 10.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/clkN210/lock_flop2 to ftop/clkN210/lock_flop3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X50Y13.YQ Tcko 0.477 ftop/clkN210/unlock3 + ftop/clkN210/lock_flop2 + SLICE_X50Y13.BX net (fanout=2) 0.336 ftop/clkN210/unlock2 + SLICE_X50Y13.CLK Tckdi (-Th) -0.102 ftop/clkN210/unlock3 + ftop/clkN210/lock_flop3 + ------------------------------------------------- --------------------------- + Total 0.915ns (0.579ns logic, 0.336ns route) + (63.3% logic, 36.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 1.159ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/clkN210/lock_flop (FF) + Destination: ftop/clkN210/lock_flop2 (FF) + Requirement: 0.000ns + Data Path Delay: 1.175ns (Levels of Logic = 1) + Clock Path Skew: 0.016ns (0.067 - 0.051) + Source Clock: ftop/clkIn_O rising at 10.000ns + Destination Clock: ftop/clkIn_O rising at 10.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/clkN210/lock_flop to ftop/clkN210/lock_flop2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X51Y11.YQ Tcko 0.419 ftop/clkN210/locked_d + ftop/clkN210/lock_flop + SLICE_X50Y13.G1 net (fanout=1) 0.306 ftop/clkN210/locked_d + SLICE_X50Y13.CLK Tckg (-Th) -0.450 ftop/clkN210/unlock3 + ftop/clkN210/edge_cap + ftop/clkN210/lock_flop2 + ------------------------------------------------- --------------------------- + Total 1.175ns (0.869ns logic, 0.306ns route) + (74.0% logic, 26.0% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 10 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 5.200ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 2.400ns (Tdcmpw_CLKIN_100_150) + Physical resource: ftop/clkN210/dcm/CLKIN + Logical resource: ftop/clkN210/dcm/CLKIN + Location pin: DCM_X1Y0.CLKIN + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 5.200ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 2.400ns (Tdcmpw_CLKIN_100_150) + Physical resource: ftop/clkN210/dcm/CLKIN + Logical resource: ftop/clkN210/dcm/CLKIN + Location pin: DCM_X1Y0.CLKIN + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 6.430ns (period - min period limit) + Period: 10.000ns + Min period limit: 3.570ns (280.112MHz) (Tdcmpc) + Physical resource: ftop/clkN210/dcm/CLKIN + Logical resource: ftop/clkN210/dcm/CLKIN + Location pin: DCM_X1Y0.CLKIN + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 6.430ns (period - min period limit) + Period: 10.000ns + Min period limit: 3.570ns (280.112MHz) (Tdcmpco) + Physical resource: ftop/clkN210/dcm/CLK0 + Logical resource: ftop/clkN210/dcm/CLK0 + Location pin: DCM_X1Y0.CLK0 + Clock network: ftop/clkN210/clk0_unbuf +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 0.664ns (Tcl) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop3/CK + Location pin: SLICE_X50Y13.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 0.664ns (Tch) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop3/CK + Location pin: SLICE_X50Y13.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - min period limit) + Period: 10.000ns + Min period limit: 1.328ns (753.012MHz) (Tcp) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop3/CK + Location pin: SLICE_X50Y13.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 0.664ns (Tcl) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop2/CK + Location pin: SLICE_X50Y13.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 0.664ns (Tch) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop2/CK + Location pin: SLICE_X50Y13.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - min period limit) + Period: 10.000ns + Min period limit: 1.328ns (753.012MHz) (Tcp) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop2/CK + Location pin: SLICE_X50Y13.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 0.624ns (Tcl) + Physical resource: ftop/clkN210/locked_d/CLK + Logical resource: ftop/clkN210/lock_flop/CK + Location pin: SLICE_X51Y11.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 0.624ns (Tch) + Physical resource: ftop/clkN210/locked_d/CLK + Logical resource: ftop/clkN210/lock_flop/CK + Location pin: SLICE_X51Y11.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - min period limit) + Period: 10.000ns + Min period limit: 1.248ns (801.282MHz) (Tcp) + Physical resource: ftop/clkN210/locked_d/CLK + Logical resource: ftop/clkN210/lock_flop/CK + Location pin: SLICE_X51Y11.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 0.624ns (Tcl) + Physical resource: ftop/clkN210/rstInD/CLK + Logical resource: ftop/clkN210/rst_fd/CK + Location pin: SLICE_X79Y49.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 0.624ns (Tch) + Physical resource: ftop/clkN210/rstInD/CLK + Logical resource: ftop/clkN210/rst_fd/CK + Location pin: SLICE_X79Y49.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - min period limit) + Period: 10.000ns + Min period limit: 1.248ns (801.282MHz) (Tcp) + Physical resource: ftop/clkN210/rstInD/CLK + Logical resource: ftop/clkN210/rst_fd/CK + Location pin: SLICE_X79Y49.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 14.653ns (period - min period limit) + Period: 20.000ns + Min period limit: 5.347ns (187.021MHz) (Tdcmpdv) + Physical resource: ftop/clkN210/dcm/CLKDV + Logical resource: ftop/clkN210/dcm/CLKDV + Location pin: DCM_X1Y0.CLKDV + Clock network: ftop/clkN210/clkdv_unbuf +-------------------------------------------------------------------------------- +Slack: 190.000ns (max period limit - period) + Period: 10.000ns + Max period limit: 200.000ns (5.000MHz) (Tdcmpc) + Physical resource: ftop/clkN210/dcm/CLKIN + Logical resource: ftop/clkN210/dcm/CLKIN + Location pin: DCM_X1Y0.CLKIN + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 190.000ns (max period limit - period) + Period: 10.000ns + Max period limit: 200.000ns (5.000MHz) (Tdcmpco) + Physical resource: ftop/clkN210/dcm/CLK0 + Logical resource: ftop/clkN210/dcm/CLK0 + Location pin: DCM_X1Y0.CLK0 + Clock network: ftop/clkN210/clk0_unbuf +-------------------------------------------------------------------------------- +Slack: 3205.800ns (max period limit - period) + Period: 20.000ns + Max period limit: 3225.800ns (0.310MHz) (Tdcmpdv) + Physical resource: ftop/clkN210/dcm/CLKDV + Logical resource: ftop/clkN210/dcm/CLKDV + Location pin: DCM_X1Y0.CLKDV + Clock network: ftop/clkN210/clkdv_unbuf +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMIISYSCLK = PERIOD TIMEGRP "GMIISYSCLK" 8 ns HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 13743 paths analyzed, 1977 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 7.889ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.111ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_11 (FF) + Requirement: 8.000ns + Data Path Delay: 7.821ns (Levels of Logic = 6) + Clock Path Skew: -0.068ns (0.592 - 0.660) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X94Y190.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_9 + SLICE_X97Y192.G2 net (fanout=5) 0.723 ftop/gbe0/gmac/gmac/txRS_txF_dD_OUT<9> + SLICE_X97Y192.Y Tilo 0.561 ftop/gbe0/gmac/gmac/N50 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>212 + SLICE_X100Y192.G2 net (fanout=17) 1.072 ftop/gbe0/gmac/gmac/N29 + SLICE_X100Y192.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>1_SW2 + SLICE_X100Y192.F1 net (fanout=1) 0.610 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>1_SW2/O + SLICE_X100Y192.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<7>1 + SLICE_X101Y196.G1 net (fanout=3) 0.618 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + SLICE_X101Y196.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CONCAT_ETC___d363<26>1 + SLICE_X101Y196.F3 net (fanout=10) 0.121 ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_IF_IF_IF_IF_rRemainder_XOR_rwAddIn_wg_ETC___d368<31> + SLICE_X101Y196.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<11>11 + SLICE_X100Y196.F2 net (fanout=3) 0.599 ftop/gbe0/gmac/gmac/txRS_crc/N12 + SLICE_X100Y196.CLK Tfck 0.656 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<11> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<11> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_11 + ------------------------------------------------- --------------------------- + Total 7.821ns (4.078ns logic, 3.743ns route) + (52.1% logic, 47.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.119ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_ptr_0 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_37 (FF) + Requirement: 8.000ns + Data Path Delay: 7.820ns (Levels of Logic = 5) + Clock Path Skew: -0.061ns (0.390 - 0.451) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_ptr_0 to ftop/gbe0/gmac/txfun_inF/data0_reg_37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y188.YQ Tcko 0.524 ftop/gbe0/gmac/txfun_ptr<1> + ftop/gbe0/gmac/txfun_ptr_0 + SLICE_X109Y188.BX net (fanout=27) 0.929 ftop/gbe0/gmac/txfun_ptr<0> + SLICE_X109Y188.F5 Tbxf5 0.524 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_3 + SLICE_X109Y188.FXINA net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_3 + SLICE_X109Y188.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y185.F1 net (fanout=3) 0.585 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y185.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.G1 net (fanout=7) 0.407 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N01 + ftop/gbe0/gmac/txfun_inF/d0d11 + SLICE_X104Y176.F2 net (fanout=40) 1.475 ftop/gbe0/gmac/txfun_inF/d0d1 + SLICE_X104Y176.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF/N18 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<37>_SW0 + SLICE_X104Y177.SR net (fanout=1) 0.941 ftop/gbe0/gmac/txfun_inF/N18 + SLICE_X104Y177.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<37> + ftop/gbe0/gmac/txfun_inF/data0_reg_37 + ------------------------------------------------- --------------------------- + Total 7.820ns (3.483ns logic, 4.337ns route) + (44.5% logic, 55.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.119ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_ptr_0 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_37 (FF) + Requirement: 8.000ns + Data Path Delay: 7.820ns (Levels of Logic = 5) + Clock Path Skew: -0.061ns (0.390 - 0.451) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_ptr_0 to ftop/gbe0/gmac/txfun_inF/data0_reg_37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y188.YQ Tcko 0.524 ftop/gbe0/gmac/txfun_ptr<1> + ftop/gbe0/gmac/txfun_ptr_0 + SLICE_X109Y189.BX net (fanout=27) 0.929 ftop/gbe0/gmac/txfun_ptr<0> + SLICE_X109Y189.F5 Tbxf5 0.524 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y188.FXINB net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y188.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y185.F1 net (fanout=3) 0.585 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y185.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.G1 net (fanout=7) 0.407 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N01 + ftop/gbe0/gmac/txfun_inF/d0d11 + SLICE_X104Y176.F2 net (fanout=40) 1.475 ftop/gbe0/gmac/txfun_inF/d0d1 + SLICE_X104Y176.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF/N18 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<37>_SW0 + SLICE_X104Y177.SR net (fanout=1) 0.941 ftop/gbe0/gmac/txfun_inF/N18 + SLICE_X104Y177.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<37> + ftop/gbe0/gmac/txfun_inF/data0_reg_37 + ------------------------------------------------- --------------------------- + Total 7.820ns (3.483ns logic, 4.337ns route) + (44.5% logic, 55.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.166ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_11 (FF) + Requirement: 8.000ns + Data Path Delay: 7.786ns (Levels of Logic = 6) + Clock Path Skew: -0.048ns (0.592 - 0.640) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X94Y186.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg + SLICE_X97Y192.G1 net (fanout=8) 0.688 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + SLICE_X97Y192.Y Tilo 0.561 ftop/gbe0/gmac/gmac/N50 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>212 + SLICE_X100Y192.G2 net (fanout=17) 1.072 ftop/gbe0/gmac/gmac/N29 + SLICE_X100Y192.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>1_SW2 + SLICE_X100Y192.F1 net (fanout=1) 0.610 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>1_SW2/O + SLICE_X100Y192.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<7>1 + SLICE_X101Y196.G1 net (fanout=3) 0.618 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + SLICE_X101Y196.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CONCAT_ETC___d363<26>1 + SLICE_X101Y196.F3 net (fanout=10) 0.121 ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_IF_IF_IF_IF_rRemainder_XOR_rwAddIn_wg_ETC___d368<31> + SLICE_X101Y196.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<11>11 + SLICE_X100Y196.F2 net (fanout=3) 0.599 ftop/gbe0/gmac/gmac/txRS_crc/N12 + SLICE_X100Y196.CLK Tfck 0.656 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<11> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<11> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_11 + ------------------------------------------------- --------------------------- + Total 7.786ns (4.078ns logic, 3.708ns route) + (52.4% logic, 47.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.188ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txDV (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_iobTxEna/FF1 (FF) + Requirement: 4.000ns + Data Path Delay: 3.847ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.730 - 0.695) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O falling at 4.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txDV to ftop/gbe0/gmac/gmac/txRS_iobTxEna/FF1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y184.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/txRS_txDV + ftop/gbe0/gmac/gmac/txRS_txDV + D26.O2 net (fanout=2) 2.618 ftop/gbe0/gmac/gmac/txRS_txDV + D26.OTCLK2 Tioock 0.708 gmii_tx_en + ftop/gbe0/gmac/gmac/txRS_iobTxEna/FF1 + ------------------------------------------------- --------------------------- + Total 3.847ns (1.229ns logic, 2.618ns route) + (31.9% logic, 68.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.193ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_19 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_37 (FF) + Requirement: 8.000ns + Data Path Delay: 7.771ns (Levels of Logic = 5) + Clock Path Skew: -0.036ns (0.390 - 0.426) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_19 to ftop/gbe0/gmac/txfun_inF/data0_reg_37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y182.YQ Tcko 0.524 ftop/gbe0/gmac/txfun_inF_D_OUT<19> + ftop/gbe0/gmac/txfun_inF/data0_reg_19 + SLICE_X109Y189.F2 net (fanout=5) 0.716 ftop/gbe0/gmac/txfun_inF_D_OUT<19> + SLICE_X109Y189.F5 Tif5 0.688 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00021 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y188.FXINB net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y188.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y185.F1 net (fanout=3) 0.585 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y185.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.G1 net (fanout=7) 0.407 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N01 + ftop/gbe0/gmac/txfun_inF/d0d11 + SLICE_X104Y176.F2 net (fanout=40) 1.475 ftop/gbe0/gmac/txfun_inF/d0d1 + SLICE_X104Y176.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF/N18 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<37>_SW0 + SLICE_X104Y177.SR net (fanout=1) 0.941 ftop/gbe0/gmac/txfun_inF/N18 + SLICE_X104Y177.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<37> + ftop/gbe0/gmac/txfun_inF/data0_reg_37 + ------------------------------------------------- --------------------------- + Total 7.771ns (3.647ns logic, 4.124ns route) + (46.9% logic, 53.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.199ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_11 (FF) + Requirement: 8.000ns + Data Path Delay: 7.716ns (Levels of Logic = 6) + Clock Path Skew: -0.085ns (0.592 - 0.677) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y188.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X96Y195.G3 net (fanout=24) 0.664 ftop/gbe0/gmac/gmac/txRS_txOperateS_dD_OUT + SLICE_X96Y195.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N46 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<0>46 + SLICE_X97Y194.G1 net (fanout=16) 0.989 ftop/gbe0/gmac/gmac/N38 + SLICE_X97Y194.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<1> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X100Y192.F2 net (fanout=11) 0.644 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X100Y192.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<7>1 + SLICE_X101Y196.G1 net (fanout=3) 0.618 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + SLICE_X101Y196.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CONCAT_ETC___d363<26>1 + SLICE_X101Y196.F3 net (fanout=10) 0.121 ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_IF_IF_IF_IF_rRemainder_XOR_rwAddIn_wg_ETC___d368<31> + SLICE_X101Y196.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<11>11 + SLICE_X100Y196.F2 net (fanout=3) 0.599 ftop/gbe0/gmac/gmac/txRS_crc/N12 + SLICE_X100Y196.CLK Tfck 0.656 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<11> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<11> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_11 + ------------------------------------------------- --------------------------- + Total 7.716ns (4.081ns logic, 3.635ns route) + (52.9% logic, 47.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.271ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_18 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_37 (FF) + Requirement: 8.000ns + Data Path Delay: 7.687ns (Levels of Logic = 5) + Clock Path Skew: -0.042ns (0.390 - 0.432) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_18 to ftop/gbe0/gmac/txfun_inF/data0_reg_37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X110Y184.YQ Tcko 0.596 ftop/gbe0/gmac/txfun_inF_D_OUT<18> + ftop/gbe0/gmac/txfun_inF/data0_reg_18 + SLICE_X109Y189.F3 net (fanout=5) 0.560 ftop/gbe0/gmac/txfun_inF_D_OUT<18> + SLICE_X109Y189.F5 Tif5 0.688 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00021 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y188.FXINB net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y188.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y185.F1 net (fanout=3) 0.585 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y185.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.G1 net (fanout=7) 0.407 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N01 + ftop/gbe0/gmac/txfun_inF/d0d11 + SLICE_X104Y176.F2 net (fanout=40) 1.475 ftop/gbe0/gmac/txfun_inF/d0d1 + SLICE_X104Y176.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF/N18 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<37>_SW0 + SLICE_X104Y177.SR net (fanout=1) 0.941 ftop/gbe0/gmac/txfun_inF/N18 + SLICE_X104Y177.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<37> + ftop/gbe0/gmac/txfun_inF/data0_reg_37 + ------------------------------------------------- --------------------------- + Total 7.687ns (3.719ns logic, 3.968ns route) + (48.4% logic, 51.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.274ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxfun_inF/data0_reg_9 (FF) + Destination: ftop/gbe0/gmac/rxfun_inF/data0_reg_6 (FF) + Requirement: 8.000ns + Data Path Delay: 7.572ns (Levels of Logic = 4) + Clock Path Skew: -0.154ns (0.413 - 0.567) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/rxfun_inF/data0_reg_9 to ftop/gbe0/gmac/rxfun_inF/data0_reg_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y45.YQ Tcko 0.524 ftop/gbe0/gmac/rxfun_inF_D_OUT<9> + ftop/gbe0/gmac/rxfun_inF/data0_reg_9 + SLICE_X110Y43.G2 net (fanout=8) 0.515 ftop/gbe0/gmac/rxfun_inF_D_OUT<9> + SLICE_X110Y43.Y Tilo 0.616 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel_SW2 + SLICE_X110Y43.F3 net (fanout=1) 0.021 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel_SW2/O + SLICE_X110Y43.X Tilo 0.601 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y47.G1 net (fanout=23) 1.747 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y47.Y Tilo 0.561 ftop/gbe0/gmac/rxfun_inF/N2 + ftop/gbe0/gmac/rxfun_inF/d0d11 + SLICE_X110Y47.F4 net (fanout=10) 1.259 ftop/gbe0/gmac/rxfun_inF/d0d1 + SLICE_X110Y47.X Tilo 0.601 ftop/gbe0/gmac/rxfun_outF_D_OUT<36> + ftop/gbe0/gmac/rxfun_inF/data0_reg_or0000<6>_SW0 + SLICE_X108Y49.SR net (fanout=1) 0.694 ftop/gbe0/gmac/rxfun_inF/N8 + SLICE_X108Y49.CLK Tsrck 0.433 ftop/gbe0/gmac/rxfun_inF_D_OUT<6> + ftop/gbe0/gmac/rxfun_inF/data0_reg_6 + ------------------------------------------------- --------------------------- + Total 7.572ns (3.336ns logic, 4.236ns route) + (44.1% logic, 55.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.278ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxfun_ptr_0 (FF) + Destination: ftop/gbe0/gmac/rxfun_inF/data0_reg_6 (FF) + Requirement: 8.000ns + Data Path Delay: 7.557ns (Levels of Logic = 4) + Clock Path Skew: -0.165ns (0.413 - 0.578) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/rxfun_ptr_0 to ftop/gbe0/gmac/rxfun_inF/data0_reg_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y42.YQ Tcko 0.524 ftop/gbe0/gmac/rxfun_ptr<1> + ftop/gbe0/gmac/rxfun_ptr_0 + SLICE_X110Y43.G1 net (fanout=4) 0.500 ftop/gbe0/gmac/rxfun_ptr<0> + SLICE_X110Y43.Y Tilo 0.616 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel_SW2 + SLICE_X110Y43.F3 net (fanout=1) 0.021 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel_SW2/O + SLICE_X110Y43.X Tilo 0.601 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y47.G1 net (fanout=23) 1.747 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y47.Y Tilo 0.561 ftop/gbe0/gmac/rxfun_inF/N2 + ftop/gbe0/gmac/rxfun_inF/d0d11 + SLICE_X110Y47.F4 net (fanout=10) 1.259 ftop/gbe0/gmac/rxfun_inF/d0d1 + SLICE_X110Y47.X Tilo 0.601 ftop/gbe0/gmac/rxfun_outF_D_OUT<36> + ftop/gbe0/gmac/rxfun_inF/data0_reg_or0000<6>_SW0 + SLICE_X108Y49.SR net (fanout=1) 0.694 ftop/gbe0/gmac/rxfun_inF/N8 + SLICE_X108Y49.CLK Tsrck 0.433 ftop/gbe0/gmac/rxfun_inF_D_OUT<6> + ftop/gbe0/gmac/rxfun_inF/data0_reg_6 + ------------------------------------------------- --------------------------- + Total 7.557ns (3.336ns logic, 4.221ns route) + (44.1% logic, 55.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.292ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxfun_inF/empty_reg (FF) + Destination: ftop/gbe0/gmac/rxfun_inF/data0_reg_6 (FF) + Requirement: 8.000ns + Data Path Delay: 7.643ns (Levels of Logic = 3) + Clock Path Skew: -0.065ns (0.413 - 0.478) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/rxfun_inF/empty_reg to ftop/gbe0/gmac/rxfun_inF/data0_reg_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X114Y49.XQ Tcko 0.521 ftop/gbe0/gmac/rxfun_inF_EMPTY_N + ftop/gbe0/gmac/rxfun_inF/empty_reg + SLICE_X110Y43.F2 net (fanout=6) 1.226 ftop/gbe0/gmac/rxfun_inF_EMPTY_N + SLICE_X110Y43.X Tilo 0.601 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y47.G1 net (fanout=23) 1.747 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y47.Y Tilo 0.561 ftop/gbe0/gmac/rxfun_inF/N2 + ftop/gbe0/gmac/rxfun_inF/d0d11 + SLICE_X110Y47.F4 net (fanout=10) 1.259 ftop/gbe0/gmac/rxfun_inF/d0d1 + SLICE_X110Y47.X Tilo 0.601 ftop/gbe0/gmac/rxfun_outF_D_OUT<36> + ftop/gbe0/gmac/rxfun_inF/data0_reg_or0000<6>_SW0 + SLICE_X108Y49.SR net (fanout=1) 0.694 ftop/gbe0/gmac/rxfun_inF/N8 + SLICE_X108Y49.CLK Tsrck 0.433 ftop/gbe0/gmac/rxfun_inF_D_OUT<6> + ftop/gbe0/gmac/rxfun_inF/data0_reg_6 + ------------------------------------------------- --------------------------- + Total 7.643ns (2.717ns logic, 4.926ns route) + (35.5% logic, 64.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.309ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxfun_inF/empty_reg (FF) + Destination: ftop/gbe0/gmac/rxfun_inF/data0_reg_7 (FF) + Requirement: 8.000ns + Data Path Delay: 7.661ns (Levels of Logic = 3) + Clock Path Skew: -0.030ns (0.448 - 0.478) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/rxfun_inF/empty_reg to ftop/gbe0/gmac/rxfun_inF/data0_reg_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X114Y49.XQ Tcko 0.521 ftop/gbe0/gmac/rxfun_inF_EMPTY_N + ftop/gbe0/gmac/rxfun_inF/empty_reg + SLICE_X110Y43.F2 net (fanout=6) 1.226 ftop/gbe0/gmac/rxfun_inF_EMPTY_N + SLICE_X110Y43.X Tilo 0.601 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y48.G1 net (fanout=23) 1.521 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y48.Y Tilo 0.561 ftop/gbe0/gmac/rxfun_inF/N4 + ftop/gbe0/gmac/rxfun_inF/d0h1 + SLICE_X111Y48.F4 net (fanout=10) 1.220 ftop/gbe0/gmac/rxfun_inF/d0h + SLICE_X111Y48.X Tilo 0.562 ftop/gbe0/gmac/rxfun_outF_D_OUT<37> + ftop/gbe0/gmac/rxfun_inF/data0_reg_or0000<7>_SW0 + SLICE_X111Y49.SR net (fanout=1) 1.016 ftop/gbe0/gmac/rxfun_inF/N6 + SLICE_X111Y49.CLK Tsrck 0.433 ftop/gbe0/gmac/rxfun_inF_D_OUT<7> + ftop/gbe0/gmac/rxfun_inF/data0_reg_7 + ------------------------------------------------- --------------------------- + Total 7.661ns (2.678ns logic, 4.983ns route) + (35.0% logic, 65.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.328ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_8 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_37 (FF) + Requirement: 8.000ns + Data Path Delay: 7.644ns (Levels of Logic = 5) + Clock Path Skew: -0.028ns (0.390 - 0.418) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_8 to ftop/gbe0/gmac/txfun_inF/data0_reg_37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y185.YQ Tcko 0.524 ftop/gbe0/gmac/txfun_inF_D_OUT<8> + ftop/gbe0/gmac/txfun_inF/data0_reg_8 + SLICE_X109Y189.G2 net (fanout=5) 0.589 ftop/gbe0/gmac/txfun_inF_D_OUT<8> + SLICE_X109Y189.F5 Tif5 0.688 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00031 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y188.FXINB net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y188.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y185.F1 net (fanout=3) 0.585 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y185.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.G1 net (fanout=7) 0.407 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N01 + ftop/gbe0/gmac/txfun_inF/d0d11 + SLICE_X104Y176.F2 net (fanout=40) 1.475 ftop/gbe0/gmac/txfun_inF/d0d1 + SLICE_X104Y176.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF/N18 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<37>_SW0 + SLICE_X104Y177.SR net (fanout=1) 0.941 ftop/gbe0/gmac/txfun_inF/N18 + SLICE_X104Y177.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<37> + ftop/gbe0/gmac/txfun_inF/data0_reg_37 + ------------------------------------------------- --------------------------- + Total 7.644ns (3.647ns logic, 3.997ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.335ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxfun_inF/data0_reg_8 (FF) + Destination: ftop/gbe0/gmac/rxfun_inF/data0_reg_6 (FF) + Requirement: 8.000ns + Data Path Delay: 7.583ns (Levels of Logic = 3) + Clock Path Skew: -0.082ns (0.413 - 0.495) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/rxfun_inF/data0_reg_8 to ftop/gbe0/gmac/rxfun_inF/data0_reg_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y49.YQ Tcko 0.596 ftop/gbe0/gmac/rxfun_inF_D_OUT<8> + ftop/gbe0/gmac/rxfun_inF/data0_reg_8 + SLICE_X110Y43.F1 net (fanout=8) 1.091 ftop/gbe0/gmac/rxfun_inF_D_OUT<8> + SLICE_X110Y43.X Tilo 0.601 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y47.G1 net (fanout=23) 1.747 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y47.Y Tilo 0.561 ftop/gbe0/gmac/rxfun_inF/N2 + ftop/gbe0/gmac/rxfun_inF/d0d11 + SLICE_X110Y47.F4 net (fanout=10) 1.259 ftop/gbe0/gmac/rxfun_inF/d0d1 + SLICE_X110Y47.X Tilo 0.601 ftop/gbe0/gmac/rxfun_outF_D_OUT<36> + ftop/gbe0/gmac/rxfun_inF/data0_reg_or0000<6>_SW0 + SLICE_X108Y49.SR net (fanout=1) 0.694 ftop/gbe0/gmac/rxfun_inF/N8 + SLICE_X108Y49.CLK Tsrck 0.433 ftop/gbe0/gmac/rxfun_inF_D_OUT<6> + ftop/gbe0/gmac/rxfun_inF/data0_reg_6 + ------------------------------------------------- --------------------------- + Total 7.583ns (2.792ns logic, 4.791ns route) + (36.8% logic, 63.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.347ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_3 (FF) + Requirement: 8.000ns + Data Path Delay: 7.612ns (Levels of Logic = 4) + Clock Path Skew: -0.041ns (0.315 - 0.356) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y188.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X96Y195.G3 net (fanout=24) 0.664 ftop/gbe0/gmac/gmac/txRS_txOperateS_dD_OUT + SLICE_X96Y195.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N46 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<0>46 + SLICE_X97Y194.G1 net (fanout=16) 0.989 ftop/gbe0/gmac/gmac/N38 + SLICE_X97Y194.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<1> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X90Y186.F3 net (fanout=11) 0.859 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X90Y186.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_txF_dDEQ + ftop/gbe0/gmac/gmac/txRS_txF_dDEQ + SLICE_X94Y186.G3 net (fanout=3) 0.536 ftop/gbe0/gmac/gmac/txRS_txF_dDEQ + SLICE_X94Y186.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_and00001 + SLICE_X100Y189.CE net (fanout=10) 1.491 ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_and0000 + SLICE_X100Y189.CLK Tceck 0.155 ftop/gbe0/gmac/gmac/txRS_txF_dD_OUT<3> + ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_3 + ------------------------------------------------- --------------------------- + Total 7.612ns (3.073ns logic, 4.539ns route) + (40.4% logic, 59.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.347ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_7 (FF) + Requirement: 8.000ns + Data Path Delay: 7.612ns (Levels of Logic = 4) + Clock Path Skew: -0.041ns (0.315 - 0.356) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y188.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X96Y195.G3 net (fanout=24) 0.664 ftop/gbe0/gmac/gmac/txRS_txOperateS_dD_OUT + SLICE_X96Y195.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N46 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<0>46 + SLICE_X97Y194.G1 net (fanout=16) 0.989 ftop/gbe0/gmac/gmac/N38 + SLICE_X97Y194.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<1> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X90Y186.F3 net (fanout=11) 0.859 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X90Y186.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_txF_dDEQ + ftop/gbe0/gmac/gmac/txRS_txF_dDEQ + SLICE_X94Y186.G3 net (fanout=3) 0.536 ftop/gbe0/gmac/gmac/txRS_txF_dDEQ + SLICE_X94Y186.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_and00001 + SLICE_X100Y188.CE net (fanout=10) 1.491 ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_and0000 + SLICE_X100Y188.CLK Tceck 0.155 ftop/gbe0/gmac/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_7 + ------------------------------------------------- --------------------------- + Total 7.612ns (3.073ns logic, 4.539ns route) + (40.4% logic, 59.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.352ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxfun_inF/data0_reg_8 (FF) + Destination: ftop/gbe0/gmac/rxfun_inF/data0_reg_7 (FF) + Requirement: 8.000ns + Data Path Delay: 7.601ns (Levels of Logic = 3) + Clock Path Skew: -0.047ns (0.448 - 0.495) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/rxfun_inF/data0_reg_8 to ftop/gbe0/gmac/rxfun_inF/data0_reg_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y49.YQ Tcko 0.596 ftop/gbe0/gmac/rxfun_inF_D_OUT<8> + ftop/gbe0/gmac/rxfun_inF/data0_reg_8 + SLICE_X110Y43.F1 net (fanout=8) 1.091 ftop/gbe0/gmac/rxfun_inF_D_OUT<8> + SLICE_X110Y43.X Tilo 0.601 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y48.G1 net (fanout=23) 1.521 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y48.Y Tilo 0.561 ftop/gbe0/gmac/rxfun_inF/N4 + ftop/gbe0/gmac/rxfun_inF/d0h1 + SLICE_X111Y48.F4 net (fanout=10) 1.220 ftop/gbe0/gmac/rxfun_inF/d0h + SLICE_X111Y48.X Tilo 0.562 ftop/gbe0/gmac/rxfun_outF_D_OUT<37> + ftop/gbe0/gmac/rxfun_inF/data0_reg_or0000<7>_SW0 + SLICE_X111Y49.SR net (fanout=1) 1.016 ftop/gbe0/gmac/rxfun_inF/N6 + SLICE_X111Y49.CLK Tsrck 0.433 ftop/gbe0/gmac/rxfun_inF_D_OUT<7> + ftop/gbe0/gmac/rxfun_inF/data0_reg_7 + ------------------------------------------------- --------------------------- + Total 7.601ns (2.753ns logic, 4.848ns route) + (36.2% logic, 63.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.352ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_29 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_37 (FF) + Requirement: 8.000ns + Data Path Delay: 7.592ns (Levels of Logic = 5) + Clock Path Skew: -0.056ns (0.390 - 0.446) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_29 to ftop/gbe0/gmac/txfun_inF/data0_reg_37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X110Y187.YQ Tcko 0.596 ftop/gbe0/gmac/txfun_inF_D_OUT<29> + ftop/gbe0/gmac/txfun_inF/data0_reg_29 + SLICE_X109Y188.G1 net (fanout=5) 0.465 ftop/gbe0/gmac/txfun_inF_D_OUT<29> + SLICE_X109Y188.F5 Tif5 0.688 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00011 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_3 + SLICE_X109Y188.FXINA net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_3 + SLICE_X109Y188.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y185.F1 net (fanout=3) 0.585 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y185.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.G1 net (fanout=7) 0.407 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N01 + ftop/gbe0/gmac/txfun_inF/d0d11 + SLICE_X104Y176.F2 net (fanout=40) 1.475 ftop/gbe0/gmac/txfun_inF/d0d1 + SLICE_X104Y176.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF/N18 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<37>_SW0 + SLICE_X104Y177.SR net (fanout=1) 0.941 ftop/gbe0/gmac/txfun_inF/N18 + SLICE_X104Y177.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<37> + ftop/gbe0/gmac/txfun_inF/data0_reg_37 + ------------------------------------------------- --------------------------- + Total 7.592ns (3.719ns logic, 3.873ns route) + (49.0% logic, 51.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.356ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_38 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_37 (FF) + Requirement: 8.000ns + Data Path Delay: 7.583ns (Levels of Logic = 5) + Clock Path Skew: -0.061ns (0.390 - 0.451) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_38 to ftop/gbe0/gmac/txfun_inF/data0_reg_37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X110Y188.YQ Tcko 0.596 ftop/gbe0/gmac/txfun_inF_D_OUT<38> + ftop/gbe0/gmac/txfun_inF/data0_reg_38 + SLICE_X109Y188.F2 net (fanout=5) 0.456 ftop/gbe0/gmac/txfun_inF_D_OUT<38> + SLICE_X109Y188.F5 Tif5 0.688 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00001 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_3 + SLICE_X109Y188.FXINA net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_3 + SLICE_X109Y188.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y185.F1 net (fanout=3) 0.585 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y185.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.G1 net (fanout=7) 0.407 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y183.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N01 + ftop/gbe0/gmac/txfun_inF/d0d11 + SLICE_X104Y176.F2 net (fanout=40) 1.475 ftop/gbe0/gmac/txfun_inF/d0d1 + SLICE_X104Y176.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF/N18 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<37>_SW0 + SLICE_X104Y177.SR net (fanout=1) 0.941 ftop/gbe0/gmac/txfun_inF/N18 + SLICE_X104Y177.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<37> + ftop/gbe0/gmac/txfun_inF/data0_reg_37 + ------------------------------------------------- --------------------------- + Total 7.583ns (3.719ns logic, 3.864ns route) + (49.0% logic, 51.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.356ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxfun_inF/data0_reg_9 (FF) + Destination: ftop/gbe0/gmac/rxfun_inF/data0_reg_7 (FF) + Requirement: 8.000ns + Data Path Delay: 7.590ns (Levels of Logic = 4) + Clock Path Skew: -0.054ns (0.080 - 0.134) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/rxfun_inF/data0_reg_9 to ftop/gbe0/gmac/rxfun_inF/data0_reg_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y45.YQ Tcko 0.524 ftop/gbe0/gmac/rxfun_inF_D_OUT<9> + ftop/gbe0/gmac/rxfun_inF/data0_reg_9 + SLICE_X110Y43.G2 net (fanout=8) 0.515 ftop/gbe0/gmac/rxfun_inF_D_OUT<9> + SLICE_X110Y43.Y Tilo 0.616 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel_SW2 + SLICE_X110Y43.F3 net (fanout=1) 0.021 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel_SW2/O + SLICE_X110Y43.X Tilo 0.601 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y48.G1 net (fanout=23) 1.521 ftop/gbe0/gmac/WILL_FIRE_RL_rxfun_unfunnel + SLICE_X113Y48.Y Tilo 0.561 ftop/gbe0/gmac/rxfun_inF/N4 + ftop/gbe0/gmac/rxfun_inF/d0h1 + SLICE_X111Y48.F4 net (fanout=10) 1.220 ftop/gbe0/gmac/rxfun_inF/d0h + SLICE_X111Y48.X Tilo 0.562 ftop/gbe0/gmac/rxfun_outF_D_OUT<37> + ftop/gbe0/gmac/rxfun_inF/data0_reg_or0000<7>_SW0 + SLICE_X111Y49.SR net (fanout=1) 1.016 ftop/gbe0/gmac/rxfun_inF/N6 + SLICE_X111Y49.CLK Tsrck 0.433 ftop/gbe0/gmac/rxfun_inF_D_OUT<7> + ftop/gbe0/gmac/rxfun_inF/data0_reg_7 + ------------------------------------------------- --------------------------- + Total 7.590ns (3.297ns logic, 4.293ns route) + (43.4% logic, 56.6% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMIISYSCLK = PERIOD TIMEGRP "GMIISYSCLK" 8 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.601ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_30 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem31.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.745ns (Levels of Logic = 1) + Clock Path Skew: 0.144ns (0.886 - 0.742) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_30 to ftop/gbe0/gmac/rxF/Mram_fifoMem31.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y43.YQ Tcko 0.419 ftop/gbe0/gmac/rxfun_outF_D_OUT<30> + ftop/gbe0/gmac/rxfun_outF/data0_reg_30 + SLICE_X110Y39.BY net (fanout=2) 0.456 ftop/gbe0/gmac/rxfun_outF_D_OUT<30> + SLICE_X110Y39.CLK Tdh (-Th) 0.130 ftop/gbe0/gmac/rxF/_varindex0000<30> + ftop/gbe0/gmac/rxF/Mram_fifoMem31.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.745ns (0.289ns logic, 0.456ns route) + (38.8% logic, 61.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.602ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_30 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem31.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.746ns (Levels of Logic = 1) + Clock Path Skew: 0.144ns (0.886 - 0.742) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_30 to ftop/gbe0/gmac/rxF/Mram_fifoMem31.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y43.YQ Tcko 0.419 ftop/gbe0/gmac/rxfun_outF_D_OUT<30> + ftop/gbe0/gmac/rxfun_outF/data0_reg_30 + SLICE_X110Y39.BY net (fanout=2) 0.456 ftop/gbe0/gmac/rxfun_outF_D_OUT<30> + SLICE_X110Y39.CLK Tdh (-Th) 0.129 ftop/gbe0/gmac/rxF/_varindex0000<30> + ftop/gbe0/gmac/rxF/Mram_fifoMem31.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.746ns (0.290ns logic, 0.456ns route) + (38.9% logic, 61.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.615ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_39 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem40.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.630ns (Levels of Logic = 1) + Clock Path Skew: 0.015ns (0.097 - 0.082) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_39 to ftop/gbe0/gmac/rxF/Mram_fifoMem40.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X107Y40.YQ Tcko 0.419 ftop/gbe0/gmac/rxfun_outF_D_OUT<39> + ftop/gbe0/gmac/rxfun_outF/data0_reg_39 + SLICE_X106Y40.BY net (fanout=2) 0.341 ftop/gbe0/gmac/rxfun_outF_D_OUT<39> + SLICE_X106Y40.CLK Tdh (-Th) 0.130 ftop/gbe0/gmac/rxF/_varindex0000<39> + ftop/gbe0/gmac/rxF/Mram_fifoMem40.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.630ns (0.289ns logic, 0.341ns route) + (45.9% logic, 54.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.616ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_39 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem40.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.631ns (Levels of Logic = 1) + Clock Path Skew: 0.015ns (0.097 - 0.082) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_39 to ftop/gbe0/gmac/rxF/Mram_fifoMem40.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X107Y40.YQ Tcko 0.419 ftop/gbe0/gmac/rxfun_outF_D_OUT<39> + ftop/gbe0/gmac/rxfun_outF/data0_reg_39 + SLICE_X106Y40.BY net (fanout=2) 0.341 ftop/gbe0/gmac/rxfun_outF_D_OUT<39> + SLICE_X106Y40.CLK Tdh (-Th) 0.129 ftop/gbe0/gmac/rxF/_varindex0000<39> + ftop/gbe0/gmac/rxF/Mram_fifoMem40.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.631ns (0.290ns logic, 0.341ns route) + (46.0% logic, 54.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.626ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_17 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem18.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.631ns (Levels of Logic = 1) + Clock Path Skew: 0.005ns (0.031 - 0.026) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_17 to ftop/gbe0/gmac/rxF/Mram_fifoMem18.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y27.YQ Tcko 0.419 ftop/gbe0/gmac/rxfun_outF_D_OUT<17> + ftop/gbe0/gmac/rxfun_outF/data0_reg_17 + SLICE_X110Y27.BY net (fanout=2) 0.342 ftop/gbe0/gmac/rxfun_outF_D_OUT<17> + SLICE_X110Y27.CLK Tdh (-Th) 0.130 ftop/gbe0/gmac/rxF/_varindex0000<17> + ftop/gbe0/gmac/rxF/Mram_fifoMem18.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.631ns (0.289ns logic, 0.342ns route) + (45.8% logic, 54.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.627ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_17 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem18.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.632ns (Levels of Logic = 1) + Clock Path Skew: 0.005ns (0.031 - 0.026) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_17 to ftop/gbe0/gmac/rxF/Mram_fifoMem18.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y27.YQ Tcko 0.419 ftop/gbe0/gmac/rxfun_outF_D_OUT<17> + ftop/gbe0/gmac/rxfun_outF/data0_reg_17 + SLICE_X110Y27.BY net (fanout=2) 0.342 ftop/gbe0/gmac/rxfun_outF_D_OUT<17> + SLICE_X110Y27.CLK Tdh (-Th) 0.129 ftop/gbe0/gmac/rxF/_varindex0000<17> + ftop/gbe0/gmac/rxF/Mram_fifoMem18.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.632ns (0.290ns logic, 0.342ns route) + (45.9% logic, 54.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.639ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem36.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.765ns (Levels of Logic = 1) + Clock Path Skew: 0.126ns (0.578 - 0.452) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxF/Mram_fifoMem36.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y43.YQ Tcko 0.419 ftop/gbe0/gmac/rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxF/sGEnqPtr_2 + SLICE_X110Y42.G3 net (fanout=43) 0.347 ftop/gbe0/gmac/rxF/sGEnqPtr<2> + SLICE_X110Y42.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/rxF/_varindex0000<35> + ftop/gbe0/gmac/rxF/Mram_fifoMem36.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.765ns (0.418ns logic, 0.347ns route) + (54.6% logic, 45.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.639ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem36.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.765ns (Levels of Logic = 1) + Clock Path Skew: 0.126ns (0.578 - 0.452) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxF/Mram_fifoMem36.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y43.YQ Tcko 0.419 ftop/gbe0/gmac/rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxF/sGEnqPtr_2 + SLICE_X110Y42.G3 net (fanout=43) 0.347 ftop/gbe0/gmac/rxF/sGEnqPtr<2> + SLICE_X110Y42.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/rxF/_varindex0000<35> + ftop/gbe0/gmac/rxF/Mram_fifoMem36.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.765ns (0.418ns logic, 0.347ns route) + (54.6% logic, 45.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.654ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.787ns (Levels of Logic = 1) + Clock Path Skew: 0.133ns (0.585 - 0.452) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y43.YQ Tcko 0.419 ftop/gbe0/gmac/rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxF/sGEnqPtr_2 + SLICE_X110Y41.G3 net (fanout=43) 0.369 ftop/gbe0/gmac/rxF/sGEnqPtr<2> + SLICE_X110Y41.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/rxF/_varindex0000<38> + ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.787ns (0.418ns logic, 0.369ns route) + (53.1% logic, 46.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.654ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.787ns (Levels of Logic = 1) + Clock Path Skew: 0.133ns (0.585 - 0.452) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y43.YQ Tcko 0.419 ftop/gbe0/gmac/rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxF/sGEnqPtr_2 + SLICE_X110Y41.G3 net (fanout=43) 0.369 ftop/gbe0/gmac/rxF/sGEnqPtr<2> + SLICE_X110Y41.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/rxF/_varindex0000<38> + ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.787ns (0.418ns logic, 0.369ns route) + (53.1% logic, 46.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.661ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_sr_5 (FF) + Destination: ftop/gbe0/gmac/rxfun_outF/data1_reg_25 (FF) + Requirement: 0.000ns + Data Path Delay: 0.799ns (Levels of Logic = 0) + Clock Path Skew: 0.138ns (0.886 - 0.748) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_sr_5 to ftop/gbe0/gmac/rxfun_outF/data1_reg_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y41.XQ Tcko 0.396 ftop/gbe0/gmac/rxfun_sr<5> + ftop/gbe0/gmac/rxfun_sr_5 + SLICE_X110Y38.BX net (fanout=3) 0.301 ftop/gbe0/gmac/rxfun_sr<5> + SLICE_X110Y38.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/rxfun_outF/data1_reg<25> + ftop/gbe0/gmac/rxfun_outF/data1_reg_25 + ------------------------------------------------- --------------------------- + Total 0.799ns (0.498ns logic, 0.301ns route) + (62.3% logic, 37.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.671ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_sr_9 (FF) + Destination: ftop/gbe0/gmac/rxfun_sr_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.839ns (Levels of Logic = 0) + Clock Path Skew: 0.168ns (0.855 - 0.687) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_sr_9 to ftop/gbe0/gmac/rxfun_sr_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X113Y40.XQ Tcko 0.396 ftop/gbe0/gmac/rxfun_sr<9> + ftop/gbe0/gmac/rxfun_sr_9 + SLICE_X112Y38.BX net (fanout=3) 0.341 ftop/gbe0/gmac/rxfun_sr<9> + SLICE_X112Y38.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/rxfun_sr<19> + ftop/gbe0/gmac/rxfun_sr_19 + ------------------------------------------------- --------------------------- + Total 0.839ns (0.498ns logic, 0.341ns route) + (59.4% logic, 40.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.679ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_16 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem17.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.691ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.080 - 0.068) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_16 to ftop/gbe0/gmac/rxF/Mram_fifoMem17.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X110Y31.YQ Tcko 0.477 ftop/gbe0/gmac/rxfun_outF_D_OUT<16> + ftop/gbe0/gmac/rxfun_outF/data0_reg_16 + SLICE_X110Y30.BY net (fanout=2) 0.344 ftop/gbe0/gmac/rxfun_outF_D_OUT<16> + SLICE_X110Y30.CLK Tdh (-Th) 0.130 ftop/gbe0/gmac/rxF/_varindex0000<16> + ftop/gbe0/gmac/rxF/Mram_fifoMem17.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.691ns (0.347ns logic, 0.344ns route) + (50.2% logic, 49.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.680ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_16 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem17.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.692ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.080 - 0.068) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_16 to ftop/gbe0/gmac/rxF/Mram_fifoMem17.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X110Y31.YQ Tcko 0.477 ftop/gbe0/gmac/rxfun_outF_D_OUT<16> + ftop/gbe0/gmac/rxfun_outF/data0_reg_16 + SLICE_X110Y30.BY net (fanout=2) 0.344 ftop/gbe0/gmac/rxfun_outF_D_OUT<16> + SLICE_X110Y30.CLK Tdh (-Th) 0.129 ftop/gbe0/gmac/rxF/_varindex0000<16> + ftop/gbe0/gmac/rxF/Mram_fifoMem17.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.692ns (0.348ns logic, 0.344ns route) + (50.3% logic, 49.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.688ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_38 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.817ns (Levels of Logic = 1) + Clock Path Skew: 0.129ns (0.585 - 0.456) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_38 to ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y41.YQ Tcko 0.419 ftop/gbe0/gmac/rxfun_outF_D_OUT<38> + ftop/gbe0/gmac/rxfun_outF/data0_reg_38 + SLICE_X110Y41.BY net (fanout=2) 0.528 ftop/gbe0/gmac/rxfun_outF_D_OUT<38> + SLICE_X110Y41.CLK Tdh (-Th) 0.130 ftop/gbe0/gmac/rxF/_varindex0000<38> + ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.817ns (0.289ns logic, 0.528ns route) + (35.4% logic, 64.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.689ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_38 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.818ns (Levels of Logic = 1) + Clock Path Skew: 0.129ns (0.585 - 0.456) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_38 to ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y41.YQ Tcko 0.419 ftop/gbe0/gmac/rxfun_outF_D_OUT<38> + ftop/gbe0/gmac/rxfun_outF/data0_reg_38 + SLICE_X110Y41.BY net (fanout=2) 0.528 ftop/gbe0/gmac/rxfun_outF_D_OUT<38> + SLICE_X110Y41.CLK Tdh (-Th) 0.129 ftop/gbe0/gmac/rxF/_varindex0000<38> + ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.818ns (0.290ns logic, 0.528ns route) + (35.5% logic, 64.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.689ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/sSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_txF/sDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.766ns (Levels of Logic = 0) + Clock Path Skew: 0.077ns (0.428 - 0.351) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/sSyncReg1_1 to ftop/gbe0/gmac/gmac/txRS_txF/sDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y200.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/txRS_txF/sSyncReg1<1> + ftop/gbe0/gmac/gmac/txRS_txF/sSyncReg1_1 + SLICE_X111Y200.BX net (fanout=1) 0.287 ftop/gbe0/gmac/gmac/txRS_txF/sSyncReg1<1> + SLICE_X111Y200.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/txRS_txF/sDeqPtr<1> + ftop/gbe0/gmac/gmac/txRS_txF/sDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.766ns (0.479ns logic, 0.287ns route) + (62.5% logic, 37.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.698ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_sr_8 (FF) + Destination: ftop/gbe0/gmac/rxfun_sr_18 (FF) + Requirement: 0.000ns + Data Path Delay: 0.866ns (Levels of Logic = 0) + Clock Path Skew: 0.168ns (0.855 - 0.687) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_sr_8 to ftop/gbe0/gmac/rxfun_sr_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X113Y40.YQ Tcko 0.419 ftop/gbe0/gmac/rxfun_sr<9> + ftop/gbe0/gmac/rxfun_sr_8 + SLICE_X112Y38.BY net (fanout=3) 0.310 ftop/gbe0/gmac/rxfun_sr<8> + SLICE_X112Y38.CLK Tckdi (-Th) -0.137 ftop/gbe0/gmac/rxfun_sr<19> + ftop/gbe0/gmac/rxfun_sr_18 + ------------------------------------------------- --------------------------- + Total 0.866ns (0.556ns logic, 0.310ns route) + (64.2% logic, 35.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.732ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxF/sSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/rxF/sDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.745ns (Levels of Logic = 0) + Clock Path Skew: 0.013ns (0.082 - 0.069) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxF/sSyncReg1_1 to ftop/gbe0/gmac/rxF/sDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X107Y44.XQ Tcko 0.396 ftop/gbe0/gmac/rxF/sSyncReg1<1> + ftop/gbe0/gmac/rxF/sSyncReg1_1 + SLICE_X107Y45.BX net (fanout=1) 0.287 ftop/gbe0/gmac/rxF/sSyncReg1<1> + SLICE_X107Y45.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/rxF/sDeqPtr<1> + ftop/gbe0/gmac/rxF/sDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.745ns (0.458ns logic, 0.287ns route) + (61.5% logic, 38.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.740ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_3 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_txF/dEnqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.745ns (Levels of Logic = 0) + Clock Path Skew: 0.005ns (0.035 - 0.030) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_3 to ftop/gbe0/gmac/gmac/txRS_txF/dEnqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X95Y191.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1<3> + ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_3 + SLICE_X95Y190.BX net (fanout=1) 0.287 ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1<3> + SLICE_X95Y190.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/txRS_txF/dEnqPtr<3> + ftop/gbe0/gmac/gmac/txRS_txF/dEnqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.745ns (0.458ns logic, 0.287ns route) + (61.5% logic, 38.5% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMIISYSCLK = PERIOD TIMEGRP "GMIISYSCLK" 8 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_1/SR + Location pin: SLICE_X112Y74.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_1/SR + Location pin: SLICE_X112Y74.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_0/SR + Location pin: SLICE_X112Y74.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_0/SR + Location pin: SLICE_X112Y74.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_3/SR + Location pin: SLICE_X108Y77.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_3/SR + Location pin: SLICE_X108Y77.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_2/SR + Location pin: SLICE_X108Y77.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_2/SR + Location pin: SLICE_X108Y77.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr_3/SR + Location pin: SLICE_X110Y72.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr_3/SR + Location pin: SLICE_X110Y72.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr_2/SR + Location pin: SLICE_X110Y72.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr_2/SR + Location pin: SLICE_X110Y72.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr<4>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr_4/SR + Location pin: SLICE_X104Y74.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr<4>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr_4/SR + Location pin: SLICE_X104Y74.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/rxOper_dD_OUT/SR + Logical resource: ftop/gbe0/gmac/rxOper/dSyncReg2/SR + Location pin: SLICE_X106Y172.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/rxOper_dD_OUT/SR + Logical resource: ftop/gbe0/gmac/rxOper/dSyncReg2/SR + Location pin: SLICE_X106Y172.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_1/SR + Location pin: SLICE_X112Y72.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_1/SR + Location pin: SLICE_X112Y72.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_0/SR + Location pin: SLICE_X112Y72.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_0/SR + Location pin: SLICE_X112Y72.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMIIRXCLK = PERIOD TIMEGRP "GMIIRXCLK" 8 ns HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 2541 paths analyzed, 474 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 6.917ns. +-------------------------------------------------------------------------------- +Slack (setup path): 1.083ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_F (RAM) + Requirement: 8.000ns + Data Path Delay: 6.681ns (Levels of Logic = 5) + Clock Path Skew: -0.236ns (0.348 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X105Y82.G1 net (fanout=11) 1.154 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X105Y82.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4>1 + SLICE_X104Y78.BY net (fanout=1) 0.744 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4> + SLICE_X104Y78.CLK Tds -0.075 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_F + ------------------------------------------------- --------------------------- + Total 6.681ns (2.766ns logic, 3.915ns route) + (41.4% logic, 58.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.084ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_G (RAM) + Requirement: 8.000ns + Data Path Delay: 6.680ns (Levels of Logic = 5) + Clock Path Skew: -0.236ns (0.348 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X105Y82.G1 net (fanout=11) 1.154 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X105Y82.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4>1 + SLICE_X104Y78.BY net (fanout=1) 0.744 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4> + SLICE_X104Y78.CLK Tds -0.076 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_G + ------------------------------------------------- --------------------------- + Total 6.680ns (2.765ns logic, 3.915ns route) + (41.4% logic, 58.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.086ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_F (RAM) + Requirement: 8.000ns + Data Path Delay: 6.678ns (Levels of Logic = 5) + Clock Path Skew: -0.236ns (0.348 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X105Y82.F1 net (fanout=11) 1.150 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X105Y82.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5>1 + SLICE_X104Y79.BY net (fanout=1) 0.744 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + SLICE_X104Y79.CLK Tds -0.075 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<5> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_F + ------------------------------------------------- --------------------------- + Total 6.678ns (2.767ns logic, 3.911ns route) + (41.4% logic, 58.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.087ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_G (RAM) + Requirement: 8.000ns + Data Path Delay: 6.677ns (Levels of Logic = 5) + Clock Path Skew: -0.236ns (0.348 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X105Y82.F1 net (fanout=11) 1.150 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X105Y82.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5>1 + SLICE_X104Y79.BY net (fanout=1) 0.744 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + SLICE_X104Y79.CLK Tds -0.076 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<5> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_G + ------------------------------------------------- --------------------------- + Total 6.677ns (2.766ns logic, 3.911ns route) + (41.4% logic, 58.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.088ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_F (RAM) + Requirement: 8.000ns + Data Path Delay: 6.698ns (Levels of Logic = 4) + Clock Path Skew: -0.214ns (0.348 - 0.562) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y96.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 + SLICE_X113Y97.F1 net (fanout=3) 1.515 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X105Y82.G1 net (fanout=11) 1.154 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X105Y82.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4>1 + SLICE_X104Y78.BY net (fanout=1) 0.744 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4> + SLICE_X104Y78.CLK Tds -0.075 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_F + ------------------------------------------------- --------------------------- + Total 6.698ns (2.130ns logic, 4.568ns route) + (31.8% logic, 68.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.089ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_G (RAM) + Requirement: 8.000ns + Data Path Delay: 6.697ns (Levels of Logic = 4) + Clock Path Skew: -0.214ns (0.348 - 0.562) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y96.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 + SLICE_X113Y97.F1 net (fanout=3) 1.515 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X105Y82.G1 net (fanout=11) 1.154 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X105Y82.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4>1 + SLICE_X104Y78.BY net (fanout=1) 0.744 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4> + SLICE_X104Y78.CLK Tds -0.076 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_G + ------------------------------------------------- --------------------------- + Total 6.697ns (2.129ns logic, 4.568ns route) + (31.8% logic, 68.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.091ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_F (RAM) + Requirement: 8.000ns + Data Path Delay: 6.695ns (Levels of Logic = 4) + Clock Path Skew: -0.214ns (0.348 - 0.562) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y96.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 + SLICE_X113Y97.F1 net (fanout=3) 1.515 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X105Y82.F1 net (fanout=11) 1.150 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X105Y82.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5>1 + SLICE_X104Y79.BY net (fanout=1) 0.744 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + SLICE_X104Y79.CLK Tds -0.075 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<5> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_F + ------------------------------------------------- --------------------------- + Total 6.695ns (2.131ns logic, 4.564ns route) + (31.8% logic, 68.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.092ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_G (RAM) + Requirement: 8.000ns + Data Path Delay: 6.694ns (Levels of Logic = 4) + Clock Path Skew: -0.214ns (0.348 - 0.562) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y96.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 + SLICE_X113Y97.F1 net (fanout=3) 1.515 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X105Y82.F1 net (fanout=11) 1.150 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X105Y82.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5>1 + SLICE_X104Y79.BY net (fanout=1) 0.744 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + SLICE_X104Y79.CLK Tds -0.076 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<5> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_G + ------------------------------------------------- --------------------------- + Total 6.694ns (2.130ns logic, 4.564ns route) + (31.8% logic, 68.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.183ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg (FF) + Requirement: 8.000ns + Data Path Delay: 6.650ns (Levels of Logic = 5) + Clock Path Skew: -0.167ns (0.417 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X110Y77.BX net (fanout=17) 1.006 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X110Y77.CLK Tdick 0.760 ftop/gbe0/gmac/gmac/rxRS_rxF_sFULL_N + ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg_mux0000175 + ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg + ------------------------------------------------- --------------------------- + Total 6.650ns (3.602ns logic, 3.048ns route) + (54.2% logic, 45.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.188ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg (FF) + Requirement: 8.000ns + Data Path Delay: 6.667ns (Levels of Logic = 4) + Clock Path Skew: -0.145ns (0.417 - 0.562) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y96.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 + SLICE_X113Y97.F1 net (fanout=3) 1.515 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X110Y77.BX net (fanout=17) 1.006 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X110Y77.CLK Tdick 0.760 ftop/gbe0/gmac/gmac/rxRS_rxF_sFULL_N + ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg_mux0000175 + ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg + ------------------------------------------------- --------------------------- + Total 6.667ns (2.966ns logic, 3.701ns route) + (44.5% logic, 55.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.193ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.571ns (Levels of Logic = 4) + Clock Path Skew: -0.236ns (0.348 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y79.SR net (fanout=17) 1.395 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y79.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<5> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.WE + ------------------------------------------------- --------------------------- + Total 6.571ns (3.134ns logic, 3.437ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.193ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.571ns (Levels of Logic = 4) + Clock Path Skew: -0.236ns (0.348 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y78.SR net (fanout=17) 1.395 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y78.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE + ------------------------------------------------- --------------------------- + Total 6.571ns (3.134ns logic, 3.437ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.198ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.588ns (Levels of Logic = 3) + Clock Path Skew: -0.214ns (0.348 - 0.562) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y96.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 + SLICE_X113Y97.F1 net (fanout=3) 1.515 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y78.SR net (fanout=17) 1.395 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y78.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE + ------------------------------------------------- --------------------------- + Total 6.588ns (2.498ns logic, 4.090ns route) + (37.9% logic, 62.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.198ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.588ns (Levels of Logic = 3) + Clock Path Skew: -0.214ns (0.348 - 0.562) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y96.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 + SLICE_X113Y97.F1 net (fanout=3) 1.515 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y79.SR net (fanout=17) 1.395 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y79.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<5> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.WE + ------------------------------------------------- --------------------------- + Total 6.588ns (2.498ns logic, 4.090ns route) + (37.9% logic, 62.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.218ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4 (FF) + Requirement: 8.000ns + Data Path Delay: 6.608ns (Levels of Logic = 4) + Clock Path Skew: -0.174ns (0.410 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X110Y79.CE net (fanout=17) 1.569 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X110Y79.CLK Tceck 0.155 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4 + ------------------------------------------------- --------------------------- + Total 6.608ns (2.997ns logic, 3.611ns route) + (45.4% logic, 54.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.223ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4 (FF) + Requirement: 8.000ns + Data Path Delay: 6.625ns (Levels of Logic = 3) + Clock Path Skew: -0.152ns (0.410 - 0.562) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y96.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 + SLICE_X113Y97.F1 net (fanout=3) 1.515 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X110Y79.CE net (fanout=17) 1.569 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X110Y79.CLK Tceck 0.155 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4 + ------------------------------------------------- --------------------------- + Total 6.625ns (2.361ns logic, 4.264ns route) + (35.6% logic, 64.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.244ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.564ns (Levels of Logic = 4) + Clock Path Skew: -0.192ns (0.392 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y79.SR net (fanout=17) 1.388 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y79.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.WE + ------------------------------------------------- --------------------------- + Total 6.564ns (3.134ns logic, 3.430ns route) + (47.7% logic, 52.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.249ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.581ns (Levels of Logic = 3) + Clock Path Skew: -0.170ns (0.392 - 0.562) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y96.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_1 + SLICE_X113Y97.F1 net (fanout=3) 1.515 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<1> + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y79.SR net (fanout=17) 1.388 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y79.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.WE + ------------------------------------------------- --------------------------- + Total 6.581ns (2.498ns logic, 4.083ns route) + (38.0% logic, 62.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.260ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.557ns (Levels of Logic = 4) + Clock Path Skew: -0.183ns (0.401 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y74.SR net (fanout=17) 1.381 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y74.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<6> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.WE + ------------------------------------------------- --------------------------- + Total 6.557ns (3.134ns logic, 3.423ns route) + (47.8% logic, 52.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.260ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.557ns (Levels of Logic = 4) + Clock Path Skew: -0.183ns (0.401 - 0.584) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y101.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.G3 net (fanout=2) 0.548 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X113Y97.Y Tilo 0.561 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X113Y97.F2 net (fanout=1) 0.314 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X113Y97.X Tilo 0.562 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.G4 net (fanout=2) 1.155 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X111Y95.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X111Y95.F4 net (fanout=11) 0.025 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X111Y95.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y75.SR net (fanout=17) 1.381 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y75.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<7> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.WE + ------------------------------------------------- --------------------------- + Total 6.557ns (3.134ns logic, 3.423ns route) + (47.8% logic, 52.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMIIRXCLK = PERIOD TIMEGRP "GMIIRXCLK" 8 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.736ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem2.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.811ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (0.458 - 0.383) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem2.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y80.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X110Y83.G2 net (fanout=13) 0.416 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X110Y83.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem2.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.811ns (0.395ns logic, 0.416ns route) + (48.7% logic, 51.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.736ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem2.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.811ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (0.458 - 0.383) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem2.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y80.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X110Y83.G2 net (fanout=13) 0.416 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X110Y83.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem2.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.811ns (0.395ns logic, 0.416ns route) + (48.7% logic, 51.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.736ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem1.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.811ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (0.458 - 0.383) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem1.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y80.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X110Y82.G2 net (fanout=13) 0.416 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X110Y82.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<0> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem1.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.811ns (0.395ns logic, 0.416ns route) + (48.7% logic, 51.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.736ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem1.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.811ns (Levels of Logic = 1) + Clock Path Skew: 0.075ns (0.458 - 0.383) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem1.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y80.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X110Y82.G2 net (fanout=13) 0.416 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X110Y82.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<0> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem1.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.811ns (0.395ns logic, 0.416ns route) + (48.7% logic, 51.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.749ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.803ns (Levels of Logic = 1) + Clock Path Skew: 0.054ns (0.471 - 0.417) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y76.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X108Y75.G3 net (fanout=13) 0.385 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X108Y75.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<7> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.803ns (0.418ns logic, 0.385ns route) + (52.1% logic, 47.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.749ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.803ns (Levels of Logic = 1) + Clock Path Skew: 0.054ns (0.471 - 0.417) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y76.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X108Y75.G3 net (fanout=13) 0.385 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X108Y75.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<7> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.803ns (0.418ns logic, 0.385ns route) + (52.1% logic, 47.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.749ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.803ns (Levels of Logic = 1) + Clock Path Skew: 0.054ns (0.471 - 0.417) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y76.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X108Y74.G3 net (fanout=13) 0.385 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X108Y74.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<6> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.803ns (0.418ns logic, 0.385ns route) + (52.1% logic, 47.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.749ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.803ns (Levels of Logic = 1) + Clock Path Skew: 0.054ns (0.471 - 0.417) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y76.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X108Y74.G3 net (fanout=13) 0.385 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X108Y74.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<6> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.803ns (0.418ns logic, 0.385ns route) + (52.1% logic, 47.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.775ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_3 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.785ns (Levels of Logic = 0) + Clock Path Skew: 0.010ns (0.067 - 0.057) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_3 to ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y74.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_3 + SLICE_X110Y75.BX net (fanout=1) 0.287 ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<3> + SLICE_X110Y75.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.785ns (0.498ns logic, 0.287ns route) + (63.4% logic, 36.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.783ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_15 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_23 (FF) + Requirement: 0.000ns + Data Path Delay: 0.783ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_15 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X107Y94.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxPipe<15> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_15 + SLICE_X107Y92.BX net (fanout=2) 0.325 ftop/gbe0/gmac/gmac/rxRS_rxPipe<15> + SLICE_X107Y92.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_23 + ------------------------------------------------- --------------------------- + Total 0.783ns (0.458ns logic, 0.325ns route) + (58.5% logic, 41.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.801ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.817ns (Levels of Logic = 1) + Clock Path Skew: 0.016ns (0.047 - 0.031) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y80.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X108Y79.G2 net (fanout=13) 0.422 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X108Y79.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.817ns (0.395ns logic, 0.422ns route) + (48.3% logic, 51.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.801ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.817ns (Levels of Logic = 1) + Clock Path Skew: 0.016ns (0.047 - 0.031) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y80.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X108Y79.G2 net (fanout=13) 0.422 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X108Y79.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.817ns (0.395ns logic, 0.422ns route) + (48.3% logic, 51.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.804ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.806ns (Levels of Logic = 0) + Clock Path Skew: 0.002ns (0.014 - 0.012) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y78.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_1 + SLICE_X102Y79.BX net (fanout=1) 0.287 ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1> + SLICE_X102Y79.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.806ns (0.519ns logic, 0.287ns route) + (64.4% logic, 35.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.807ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_11 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.808ns (Levels of Logic = 0) + Clock Path Skew: 0.001ns (0.027 - 0.026) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_11 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y97.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxPipe<11> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_11 + SLICE_X108Y94.BX net (fanout=2) 0.310 ftop/gbe0/gmac/gmac/rxRS_rxPipe<11> + SLICE_X108Y94.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxPipe<19> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_19 + ------------------------------------------------- --------------------------- + Total 0.808ns (0.498ns logic, 0.310ns route) + (61.6% logic, 38.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.809ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_9 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_17 (FF) + Requirement: 0.000ns + Data Path Delay: 0.807ns (Levels of Logic = 0) + Clock Path Skew: -0.002ns (0.035 - 0.037) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_9 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X110Y94.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/rxRS_rxPipe<9> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_9 + SLICE_X111Y92.BX net (fanout=2) 0.328 ftop/gbe0/gmac/gmac/rxRS_rxPipe<9> + SLICE_X111Y92.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/rxRS_rxPipe<17> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_17 + ------------------------------------------------- --------------------------- + Total 0.807ns (0.479ns logic, 0.328ns route) + (59.4% logic, 40.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.817ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_19 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_27 (FF) + Requirement: 0.000ns + Data Path Delay: 0.816ns (Levels of Logic = 0) + Clock Path Skew: -0.001ns (0.022 - 0.023) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_19 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y94.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/rxRS_rxPipe<19> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_19 + SLICE_X108Y93.BX net (fanout=2) 0.297 ftop/gbe0/gmac/gmac/rxRS_rxPipe<19> + SLICE_X108Y93.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxPipe<27> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_27 + ------------------------------------------------- --------------------------- + Total 0.816ns (0.519ns logic, 0.297ns route) + (63.6% logic, 36.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.819ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.815ns (Levels of Logic = 0) + Clock Path Skew: -0.004ns (0.036 - 0.040) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_0 to ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y79.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<0> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_0 + SLICE_X109Y80.BY net (fanout=6) 0.297 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<0> + SLICE_X109Y80.CLK Tckdi (-Th) -0.122 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_0 + ------------------------------------------------- --------------------------- + Total 0.815ns (0.518ns logic, 0.297ns route) + (63.6% logic, 36.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.838ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_21 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_29 (FF) + Requirement: 0.000ns + Data Path Delay: 0.832ns (Levels of Logic = 0) + Clock Path Skew: -0.006ns (0.013 - 0.019) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_21 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y92.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/rxRS_rxPipe<21> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_21 + SLICE_X108Y91.BX net (fanout=2) 0.313 ftop/gbe0/gmac/gmac/rxRS_rxPipe<21> + SLICE_X108Y91.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxPipe<29> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_29 + ------------------------------------------------- --------------------------- + Total 0.832ns (0.519ns logic, 0.313ns route) + (62.4% logic, 37.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.852ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.868ns (Levels of Logic = 1) + Clock Path Skew: 0.016ns (0.047 - 0.031) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_0 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y80.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_0 + SLICE_X108Y79.G1 net (fanout=10) 0.450 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<0> + SLICE_X108Y79.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.868ns (0.418ns logic, 0.450ns route) + (48.2% logic, 51.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.852ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_0 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.868ns (Levels of Logic = 1) + Clock Path Skew: 0.016ns (0.047 - 0.031) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_0 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y80.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_0 + SLICE_X108Y79.G1 net (fanout=10) 0.450 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<0> + SLICE_X108Y79.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.868ns (0.418ns logic, 0.450ns route) + (48.2% logic, 51.8% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMIIRXCLK = PERIOD TIMEGRP "GMIIRXCLK" 8 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_1/SR + Location pin: SLICE_X102Y78.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_1/SR + Location pin: SLICE_X102Y78.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_0/SR + Location pin: SLICE_X102Y78.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_0/SR + Location pin: SLICE_X102Y78.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_1/SR + Location pin: SLICE_X102Y79.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_1/SR + Location pin: SLICE_X102Y79.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_0/SR + Location pin: SLICE_X102Y79.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_0/SR + Location pin: SLICE_X102Y79.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_3/SR + Location pin: SLICE_X110Y75.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_3/SR + Location pin: SLICE_X110Y75.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_2/SR + Location pin: SLICE_X110Y75.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_2/SR + Location pin: SLICE_X110Y75.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<4>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4/SR + Location pin: SLICE_X110Y79.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<4>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4/SR + Location pin: SLICE_X110Y79.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF_sFULL_N/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg/SR + Location pin: SLICE_X110Y77.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF_sFULL_N/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg/SR + Location pin: SLICE_X110Y77.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold<0>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold_0/SR + Location pin: SLICE_X106Y87.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold<0>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold_0/SR + Location pin: SLICE_X106Y87.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.504ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.248ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_3/SR + Location pin: SLICE_X111Y74.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.504ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.248ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_3/SR + Location pin: SLICE_X111Y74.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_clkN210_clk0_unbuf = PERIOD TIMEGRP +"ftop_clkN210_clk0_unbuf" TS_SYS0CLK HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 6.533ns. +-------------------------------------------------------------------------------- +Slack (setup path): 3.467ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/clkN210/rst_fd (FF) + Destination: ftop/clkN210/clk0_rst (FF) + Requirement: 10.000ns + Data Path Delay: 1.518ns (Levels of Logic = 0) + Clock Path Skew: -5.015ns (-1.420 - 3.595) + Source Clock: ftop/clkIn_O rising at 0.000ns + Destination Clock: ftop/sys0Clk rising at 10.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/clkN210/rst_fd to ftop/clkN210/clk0_rst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y49.YQ Tcko 0.524 ftop/clkN210/rstInD + ftop/clkN210/rst_fd + SLICE_X79Y48.SR net (fanout=3) 0.561 ftop/clkN210/rstInD + SLICE_X79Y48.CLK Tsrck 0.433 ftop/sys0Rst + ftop/clkN210/clk0_rst + ------------------------------------------------- --------------------------- + Total 1.518ns (0.957ns logic, 0.561ns route) + (63.0% logic, 37.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_ftop_clkN210_clk0_unbuf = PERIOD TIMEGRP "ftop_clkN210_clk0_unbuf" + TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 4.695ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/clkN210/rst_fd (FF) + Destination: ftop/clkN210/clk0_rst (FF) + Requirement: 0.000ns + Data Path Delay: 1.158ns (Levels of Logic = 0) + Clock Path Skew: -3.537ns (-0.661 - 2.876) + Source Clock: ftop/clkIn_O rising at 10.000ns + Destination Clock: ftop/sys0Clk rising at 10.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/clkN210/rst_fd to ftop/clkN210/clk0_rst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y49.YQ Tcko 0.419 ftop/clkN210/rstInD + ftop/clkN210/rst_fd + SLICE_X79Y48.SR net (fanout=3) 0.449 ftop/clkN210/rstInD + SLICE_X79Y48.CLK Tcksr (-Th) -0.290 ftop/sys0Rst + ftop/clkN210/clk0_rst + ------------------------------------------------- --------------------------- + Total 1.158ns (0.709ns logic, 0.449ns route) + (61.2% logic, 38.8% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_clkN210_clk0_unbuf = PERIOD TIMEGRP "ftop_clkN210_clk0_unbuf" + TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 0.624ns (Tcl) + Physical resource: ftop/sys0Rst/CLK + Logical resource: ftop/clkN210/clk0_rst/CK + Location pin: SLICE_X79Y48.CLK + Clock network: ftop/sys0Clk +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 0.624ns (Tch) + Physical resource: ftop/sys0Rst/CLK + Logical resource: ftop/clkN210/clk0_rst/CK + Location pin: SLICE_X79Y48.CLK + Clock network: ftop/sys0Clk +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - min period limit) + Period: 10.000ns + Min period limit: 1.248ns (801.282MHz) (Tcp) + Physical resource: ftop/sys0Rst/CLK + Logical resource: ftop/clkN210/clk0_rst/CK + Location pin: SLICE_X79Y48.CLK + Clock network: ftop/sys0Clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_clkN210_clkdv_unbuf = PERIOD TIMEGRP +"ftop_clkN210_clkdv_unbuf" TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 5249682 paths analyzed, 66581 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 19.497ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.503ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_24 (FF) + Destination: ftop/cp/cpRespF/data0_reg_38 (FF) + Requirement: 20.000ns + Data Path Delay: 19.473ns (Levels of Logic = 19) + Clock Path Skew: -0.024ns (0.757 - 0.781) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_24 to ftop/cp/cpRespF/data0_reg_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X55Y78.YQ Tcko 0.524 ftop/cp/cpReq<16> + ftop/cp/cpReq_24 + SLICE_X52Y79.G2 net (fanout=8) 0.532 ftop/cp/cpReq<24> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X64Y67.G4 net (fanout=40) 0.535 ftop/cp/cpRespF/d0h + SLICE_X64Y67.Y Tilo 0.616 ftop/cp_server_response_get<38> + ftop/cp/cpRespF/data0_reg_or0000<38>_SW0 + SLICE_X64Y67.F2 net (fanout=1) 0.735 ftop/cp/cpRespF/data0_reg_or0000<38>_SW0/O + SLICE_X64Y67.CLK Tfck 0.656 ftop/cp_server_response_get<38> + ftop/cp/cpRespF/data0_reg_38_rstpot + ftop/cp/cpRespF/data0_reg_38 + ------------------------------------------------- --------------------------- + Total 19.473ns (7.724ns logic, 11.749ns route) + (39.7% logic, 60.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.562ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_24 (FF) + Destination: ftop/cp/cpRespF/data0_reg_12 (FF) + Requirement: 20.000ns + Data Path Delay: 19.407ns (Levels of Logic = 19) + Clock Path Skew: -0.031ns (0.750 - 0.781) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_24 to ftop/cp/cpRespF/data0_reg_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X55Y78.YQ Tcko 0.524 ftop/cp/cpReq<16> + ftop/cp/cpReq_24 + SLICE_X52Y79.G2 net (fanout=8) 0.532 ftop/cp/cpReq<24> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X60Y70.G1 net (fanout=40) 1.169 ftop/cp/cpRespF/d0h + SLICE_X60Y70.Y Tilo 0.616 ftop/cp_server_response_get<12> + ftop/cp/cpRespF/data0_reg_or0000<12>_SW0 + SLICE_X60Y70.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<12>_SW0/O + SLICE_X60Y70.CLK Tfck 0.656 ftop/cp_server_response_get<12> + ftop/cp/cpRespF/data0_reg_12_rstpot + ftop/cp/cpRespF/data0_reg_12 + ------------------------------------------------- --------------------------- + Total 19.407ns (7.724ns logic, 11.683ns route) + (39.8% logic, 60.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.564ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_25 (FF) + Destination: ftop/cp/cpRespF/data0_reg_38 (FF) + Requirement: 20.000ns + Data Path Delay: 19.408ns (Levels of Logic = 19) + Clock Path Skew: -0.028ns (0.757 - 0.785) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_25 to ftop/cp/cpRespF/data0_reg_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X53Y78.XQ Tcko 0.495 ftop/cp/cpReq<25> + ftop/cp/cpReq_25 + SLICE_X52Y79.G1 net (fanout=6) 0.496 ftop/cp/cpReq<25> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X64Y67.G4 net (fanout=40) 0.535 ftop/cp/cpRespF/d0h + SLICE_X64Y67.Y Tilo 0.616 ftop/cp_server_response_get<38> + ftop/cp/cpRespF/data0_reg_or0000<38>_SW0 + SLICE_X64Y67.F2 net (fanout=1) 0.735 ftop/cp/cpRespF/data0_reg_or0000<38>_SW0/O + SLICE_X64Y67.CLK Tfck 0.656 ftop/cp_server_response_get<38> + ftop/cp/cpRespF/data0_reg_38_rstpot + ftop/cp/cpRespF/data0_reg_38 + ------------------------------------------------- --------------------------- + Total 19.408ns (7.695ns logic, 11.713ns route) + (39.6% logic, 60.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.573ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_23 (FF) + Destination: ftop/cp/cpRespF/data0_reg_38 (FF) + Requirement: 20.000ns + Data Path Delay: 19.399ns (Levels of Logic = 19) + Clock Path Skew: -0.028ns (0.757 - 0.785) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_23 to ftop/cp/cpRespF/data0_reg_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X52Y78.XQ Tcko 0.521 ftop/cp/cpReq<23> + ftop/cp/cpReq_23 + SLICE_X49Y82.G4 net (fanout=19) 1.314 ftop/cp/cpReq<23> + SLICE_X49Y82.Y Tilo 0.561 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/Msub_wn__h76794_xor<3>11 + SLICE_X49Y82.F4 net (fanout=2) 0.290 ftop/cp/wn__h76794<3> + SLICE_X49Y82.X Tilo 0.562 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/_theResult_____1__h76813<3>1 + SLICE_X45Y90.G1 net (fanout=17) 0.880 ftop/cp/_theResult_____1__h76813<3> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X64Y67.G4 net (fanout=40) 0.535 ftop/cp/cpRespF/d0h + SLICE_X64Y67.Y Tilo 0.616 ftop/cp_server_response_get<38> + ftop/cp/cpRespF/data0_reg_or0000<38>_SW0 + SLICE_X64Y67.F2 net (fanout=1) 0.735 ftop/cp/cpRespF/data0_reg_or0000<38>_SW0/O + SLICE_X64Y67.CLK Tfck 0.656 ftop/cp_server_response_get<38> + ftop/cp/cpRespF/data0_reg_38_rstpot + ftop/cp/cpRespF/data0_reg_38 + ------------------------------------------------- --------------------------- + Total 19.399ns (7.627ns logic, 11.772ns route) + (39.3% logic, 60.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.623ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_25 (FF) + Destination: ftop/cp/cpRespF/data0_reg_12 (FF) + Requirement: 20.000ns + Data Path Delay: 19.342ns (Levels of Logic = 19) + Clock Path Skew: -0.035ns (0.750 - 0.785) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_25 to ftop/cp/cpRespF/data0_reg_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X53Y78.XQ Tcko 0.495 ftop/cp/cpReq<25> + ftop/cp/cpReq_25 + SLICE_X52Y79.G1 net (fanout=6) 0.496 ftop/cp/cpReq<25> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X60Y70.G1 net (fanout=40) 1.169 ftop/cp/cpRespF/d0h + SLICE_X60Y70.Y Tilo 0.616 ftop/cp_server_response_get<12> + ftop/cp/cpRespF/data0_reg_or0000<12>_SW0 + SLICE_X60Y70.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<12>_SW0/O + SLICE_X60Y70.CLK Tfck 0.656 ftop/cp_server_response_get<12> + ftop/cp/cpRespF/data0_reg_12_rstpot + ftop/cp/cpRespF/data0_reg_12 + ------------------------------------------------- --------------------------- + Total 19.342ns (7.695ns logic, 11.647ns route) + (39.8% logic, 60.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.632ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_23 (FF) + Destination: ftop/cp/cpRespF/data0_reg_12 (FF) + Requirement: 20.000ns + Data Path Delay: 19.333ns (Levels of Logic = 19) + Clock Path Skew: -0.035ns (0.750 - 0.785) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_23 to ftop/cp/cpRespF/data0_reg_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X52Y78.XQ Tcko 0.521 ftop/cp/cpReq<23> + ftop/cp/cpReq_23 + SLICE_X49Y82.G4 net (fanout=19) 1.314 ftop/cp/cpReq<23> + SLICE_X49Y82.Y Tilo 0.561 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/Msub_wn__h76794_xor<3>11 + SLICE_X49Y82.F4 net (fanout=2) 0.290 ftop/cp/wn__h76794<3> + SLICE_X49Y82.X Tilo 0.562 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/_theResult_____1__h76813<3>1 + SLICE_X45Y90.G1 net (fanout=17) 0.880 ftop/cp/_theResult_____1__h76813<3> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X60Y70.G1 net (fanout=40) 1.169 ftop/cp/cpRespF/d0h + SLICE_X60Y70.Y Tilo 0.616 ftop/cp_server_response_get<12> + ftop/cp/cpRespF/data0_reg_or0000<12>_SW0 + SLICE_X60Y70.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<12>_SW0/O + SLICE_X60Y70.CLK Tfck 0.656 ftop/cp_server_response_get<12> + ftop/cp/cpRespF/data0_reg_12_rstpot + ftop/cp/cpRespF/data0_reg_12 + ------------------------------------------------- --------------------------- + Total 19.333ns (7.627ns logic, 11.706ns route) + (39.5% logic, 60.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.646ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_24 (FF) + Destination: ftop/cp/cpRespF/data0_reg_27 (FF) + Requirement: 20.000ns + Data Path Delay: 19.311ns (Levels of Logic = 19) + Clock Path Skew: -0.043ns (0.489 - 0.532) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_24 to ftop/cp/cpRespF/data0_reg_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X55Y78.YQ Tcko 0.524 ftop/cp/cpReq<16> + ftop/cp/cpReq_24 + SLICE_X52Y79.G2 net (fanout=8) 0.532 ftop/cp/cpReq<24> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X60Y74.G3 net (fanout=40) 1.073 ftop/cp/cpRespF/d0h + SLICE_X60Y74.Y Tilo 0.616 ftop/cp_server_response_get<27> + ftop/cp/cpRespF/data0_reg_or0000<27>_SW0 + SLICE_X60Y74.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<27>_SW0/O + SLICE_X60Y74.CLK Tfck 0.656 ftop/cp_server_response_get<27> + ftop/cp/cpRespF/data0_reg_27_rstpot + ftop/cp/cpRespF/data0_reg_27 + ------------------------------------------------- --------------------------- + Total 19.311ns (7.724ns logic, 11.587ns route) + (40.0% logic, 60.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.649ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_24 (FF) + Destination: ftop/cp/cpRespF/data0_reg_3 (FF) + Requirement: 20.000ns + Data Path Delay: 19.266ns (Levels of Logic = 19) + Clock Path Skew: -0.085ns (0.696 - 0.781) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_24 to ftop/cp/cpRespF/data0_reg_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X55Y78.YQ Tcko 0.524 ftop/cp/cpReq<16> + ftop/cp/cpReq_24 + SLICE_X52Y79.G2 net (fanout=8) 0.532 ftop/cp/cpReq<24> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X66Y65.G2 net (fanout=40) 1.042 ftop/cp/cpRespF/d0h + SLICE_X66Y65.Y Tilo 0.616 ftop/cp_server_response_get<3> + ftop/cp/cpRespF/data0_reg_or0000<3>_SW0 + SLICE_X66Y65.F3 net (fanout=1) 0.021 ftop/cp/cpRespF/data0_reg_or0000<3>_SW0/O + SLICE_X66Y65.CLK Tfck 0.656 ftop/cp_server_response_get<3> + ftop/cp/cpRespF/data0_reg_3_rstpot + ftop/cp/cpRespF/data0_reg_3 + ------------------------------------------------- --------------------------- + Total 19.266ns (7.724ns logic, 11.542ns route) + (40.1% logic, 59.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.706ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_21 (FF) + Destination: ftop/cp/cpRespF/data0_reg_38 (FF) + Requirement: 20.000ns + Data Path Delay: 19.282ns (Levels of Logic = 19) + Clock Path Skew: -0.012ns (0.757 - 0.769) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_21 to ftop/cp/cpRespF/data0_reg_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X52Y80.XQ Tcko 0.521 ftop/cp/cpReq<21> + ftop/cp/cpReq_21 + SLICE_X49Y82.G2 net (fanout=20) 1.197 ftop/cp/cpReq<21> + SLICE_X49Y82.Y Tilo 0.561 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/Msub_wn__h76794_xor<3>11 + SLICE_X49Y82.F4 net (fanout=2) 0.290 ftop/cp/wn__h76794<3> + SLICE_X49Y82.X Tilo 0.562 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/_theResult_____1__h76813<3>1 + SLICE_X45Y90.G1 net (fanout=17) 0.880 ftop/cp/_theResult_____1__h76813<3> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X64Y67.G4 net (fanout=40) 0.535 ftop/cp/cpRespF/d0h + SLICE_X64Y67.Y Tilo 0.616 ftop/cp_server_response_get<38> + ftop/cp/cpRespF/data0_reg_or0000<38>_SW0 + SLICE_X64Y67.F2 net (fanout=1) 0.735 ftop/cp/cpRespF/data0_reg_or0000<38>_SW0/O + SLICE_X64Y67.CLK Tfck 0.656 ftop/cp_server_response_get<38> + ftop/cp/cpRespF/data0_reg_38_rstpot + ftop/cp/cpRespF/data0_reg_38 + ------------------------------------------------- --------------------------- + Total 19.282ns (7.627ns logic, 11.655ns route) + (39.6% logic, 60.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.707ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_25 (FF) + Destination: ftop/cp/cpRespF/data0_reg_27 (FF) + Requirement: 20.000ns + Data Path Delay: 19.246ns (Levels of Logic = 19) + Clock Path Skew: -0.047ns (0.489 - 0.536) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_25 to ftop/cp/cpRespF/data0_reg_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X53Y78.XQ Tcko 0.495 ftop/cp/cpReq<25> + ftop/cp/cpReq_25 + SLICE_X52Y79.G1 net (fanout=6) 0.496 ftop/cp/cpReq<25> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X60Y74.G3 net (fanout=40) 1.073 ftop/cp/cpRespF/d0h + SLICE_X60Y74.Y Tilo 0.616 ftop/cp_server_response_get<27> + ftop/cp/cpRespF/data0_reg_or0000<27>_SW0 + SLICE_X60Y74.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<27>_SW0/O + SLICE_X60Y74.CLK Tfck 0.656 ftop/cp_server_response_get<27> + ftop/cp/cpRespF/data0_reg_27_rstpot + ftop/cp/cpRespF/data0_reg_27 + ------------------------------------------------- --------------------------- + Total 19.246ns (7.695ns logic, 11.551ns route) + (40.0% logic, 60.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.710ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_25 (FF) + Destination: ftop/cp/cpRespF/data0_reg_3 (FF) + Requirement: 20.000ns + Data Path Delay: 19.201ns (Levels of Logic = 19) + Clock Path Skew: -0.089ns (0.696 - 0.785) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_25 to ftop/cp/cpRespF/data0_reg_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X53Y78.XQ Tcko 0.495 ftop/cp/cpReq<25> + ftop/cp/cpReq_25 + SLICE_X52Y79.G1 net (fanout=6) 0.496 ftop/cp/cpReq<25> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X66Y65.G2 net (fanout=40) 1.042 ftop/cp/cpRespF/d0h + SLICE_X66Y65.Y Tilo 0.616 ftop/cp_server_response_get<3> + ftop/cp/cpRespF/data0_reg_or0000<3>_SW0 + SLICE_X66Y65.F3 net (fanout=1) 0.021 ftop/cp/cpRespF/data0_reg_or0000<3>_SW0/O + SLICE_X66Y65.CLK Tfck 0.656 ftop/cp_server_response_get<3> + ftop/cp/cpRespF/data0_reg_3_rstpot + ftop/cp/cpRespF/data0_reg_3 + ------------------------------------------------- --------------------------- + Total 19.201ns (7.695ns logic, 11.506ns route) + (40.1% logic, 59.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.716ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_23 (FF) + Destination: ftop/cp/cpRespF/data0_reg_27 (FF) + Requirement: 20.000ns + Data Path Delay: 19.237ns (Levels of Logic = 19) + Clock Path Skew: -0.047ns (0.489 - 0.536) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_23 to ftop/cp/cpRespF/data0_reg_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X52Y78.XQ Tcko 0.521 ftop/cp/cpReq<23> + ftop/cp/cpReq_23 + SLICE_X49Y82.G4 net (fanout=19) 1.314 ftop/cp/cpReq<23> + SLICE_X49Y82.Y Tilo 0.561 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/Msub_wn__h76794_xor<3>11 + SLICE_X49Y82.F4 net (fanout=2) 0.290 ftop/cp/wn__h76794<3> + SLICE_X49Y82.X Tilo 0.562 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/_theResult_____1__h76813<3>1 + SLICE_X45Y90.G1 net (fanout=17) 0.880 ftop/cp/_theResult_____1__h76813<3> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X60Y74.G3 net (fanout=40) 1.073 ftop/cp/cpRespF/d0h + SLICE_X60Y74.Y Tilo 0.616 ftop/cp_server_response_get<27> + ftop/cp/cpRespF/data0_reg_or0000<27>_SW0 + SLICE_X60Y74.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<27>_SW0/O + SLICE_X60Y74.CLK Tfck 0.656 ftop/cp_server_response_get<27> + ftop/cp/cpRespF/data0_reg_27_rstpot + ftop/cp/cpRespF/data0_reg_27 + ------------------------------------------------- --------------------------- + Total 19.237ns (7.627ns logic, 11.610ns route) + (39.6% logic, 60.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.719ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_23 (FF) + Destination: ftop/cp/cpRespF/data0_reg_3 (FF) + Requirement: 20.000ns + Data Path Delay: 19.192ns (Levels of Logic = 19) + Clock Path Skew: -0.089ns (0.696 - 0.785) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_23 to ftop/cp/cpRespF/data0_reg_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X52Y78.XQ Tcko 0.521 ftop/cp/cpReq<23> + ftop/cp/cpReq_23 + SLICE_X49Y82.G4 net (fanout=19) 1.314 ftop/cp/cpReq<23> + SLICE_X49Y82.Y Tilo 0.561 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/Msub_wn__h76794_xor<3>11 + SLICE_X49Y82.F4 net (fanout=2) 0.290 ftop/cp/wn__h76794<3> + SLICE_X49Y82.X Tilo 0.562 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/_theResult_____1__h76813<3>1 + SLICE_X45Y90.G1 net (fanout=17) 0.880 ftop/cp/_theResult_____1__h76813<3> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X66Y65.G2 net (fanout=40) 1.042 ftop/cp/cpRespF/d0h + SLICE_X66Y65.Y Tilo 0.616 ftop/cp_server_response_get<3> + ftop/cp/cpRespF/data0_reg_or0000<3>_SW0 + SLICE_X66Y65.F3 net (fanout=1) 0.021 ftop/cp/cpRespF/data0_reg_or0000<3>_SW0/O + SLICE_X66Y65.CLK Tfck 0.656 ftop/cp_server_response_get<3> + ftop/cp/cpRespF/data0_reg_3_rstpot + ftop/cp/cpRespF/data0_reg_3 + ------------------------------------------------- --------------------------- + Total 19.192ns (7.627ns logic, 11.565ns route) + (39.7% logic, 60.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.719ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_24 (FF) + Destination: ftop/cp/cpRespF/data0_reg_24 (FF) + Requirement: 20.000ns + Data Path Delay: 19.195ns (Levels of Logic = 19) + Clock Path Skew: -0.086ns (0.446 - 0.532) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_24 to ftop/cp/cpRespF/data0_reg_24 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X55Y78.YQ Tcko 0.524 ftop/cp/cpReq<16> + ftop/cp/cpReq_24 + SLICE_X52Y79.G2 net (fanout=8) 0.532 ftop/cp/cpReq<24> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X65Y72.G3 net (fanout=40) 0.526 ftop/cp/cpRespF/d0h + SLICE_X65Y72.Y Tilo 0.561 ftop/cp_server_response_get<24> + ftop/cp/cpRespF/data0_reg_or0000<24>_SW0 + SLICE_X65Y72.F1 net (fanout=1) 0.575 ftop/cp/cpRespF/data0_reg_or0000<24>_SW0/O + SLICE_X65Y72.CLK Tfck 0.602 ftop/cp_server_response_get<24> + ftop/cp/cpRespF/data0_reg_24_rstpot + ftop/cp/cpRespF/data0_reg_24 + ------------------------------------------------- --------------------------- + Total 19.195ns (7.615ns logic, 11.580ns route) + (39.7% logic, 60.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.765ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_21 (FF) + Destination: ftop/cp/cpRespF/data0_reg_12 (FF) + Requirement: 20.000ns + Data Path Delay: 19.216ns (Levels of Logic = 19) + Clock Path Skew: -0.019ns (0.750 - 0.769) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_21 to ftop/cp/cpRespF/data0_reg_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X52Y80.XQ Tcko 0.521 ftop/cp/cpReq<21> + ftop/cp/cpReq_21 + SLICE_X49Y82.G2 net (fanout=20) 1.197 ftop/cp/cpReq<21> + SLICE_X49Y82.Y Tilo 0.561 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/Msub_wn__h76794_xor<3>11 + SLICE_X49Y82.F4 net (fanout=2) 0.290 ftop/cp/wn__h76794<3> + SLICE_X49Y82.X Tilo 0.562 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/_theResult_____1__h76813<3>1 + SLICE_X45Y90.G1 net (fanout=17) 0.880 ftop/cp/_theResult_____1__h76813<3> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X60Y70.G1 net (fanout=40) 1.169 ftop/cp/cpRespF/d0h + SLICE_X60Y70.Y Tilo 0.616 ftop/cp_server_response_get<12> + ftop/cp/cpRespF/data0_reg_or0000<12>_SW0 + SLICE_X60Y70.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<12>_SW0/O + SLICE_X60Y70.CLK Tfck 0.656 ftop/cp_server_response_get<12> + ftop/cp/cpRespF/data0_reg_12_rstpot + ftop/cp/cpRespF/data0_reg_12 + ------------------------------------------------- --------------------------- + Total 19.216ns (7.627ns logic, 11.589ns route) + (39.7% logic, 60.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.766ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_24 (FF) + Destination: ftop/cp/cpRespF/data0_reg_35 (FF) + Requirement: 20.000ns + Data Path Delay: 19.192ns (Levels of Logic = 19) + Clock Path Skew: -0.042ns (0.739 - 0.781) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_24 to ftop/cp/cpRespF/data0_reg_35 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X55Y78.YQ Tcko 0.524 ftop/cp/cpReq<16> + ftop/cp/cpReq_24 + SLICE_X52Y79.G2 net (fanout=8) 0.532 ftop/cp/cpReq<24> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X64Y64.G2 net (fanout=40) 0.954 ftop/cp/cpRespF/d0h + SLICE_X64Y64.Y Tilo 0.616 ftop/cp_server_response_get<35> + ftop/cp/cpRespF/data0_reg_or0000<35>_SW0 + SLICE_X64Y64.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<35>_SW0/O + SLICE_X64Y64.CLK Tfck 0.656 ftop/cp_server_response_get<35> + ftop/cp/cpRespF/data0_reg_35_rstpot + ftop/cp/cpRespF/data0_reg_35 + ------------------------------------------------- --------------------------- + Total 19.192ns (7.724ns logic, 11.468ns route) + (40.2% logic, 59.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.780ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_24 (FF) + Destination: ftop/cp/cpRespF/data0_reg_5 (FF) + Requirement: 20.000ns + Data Path Delay: 19.211ns (Levels of Logic = 19) + Clock Path Skew: -0.009ns (0.772 - 0.781) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_24 to ftop/cp/cpRespF/data0_reg_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X55Y78.YQ Tcko 0.524 ftop/cp/cpReq<16> + ftop/cp/cpReq_24 + SLICE_X52Y79.G2 net (fanout=8) 0.532 ftop/cp/cpReq<24> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X63Y69.G3 net (fanout=40) 0.497 ftop/cp/cpRespF/d0h + SLICE_X63Y69.Y Tilo 0.561 ftop/cp_server_response_get<5> + ftop/cp/cpRespF/data0_reg_or0000<5>_SW0 + SLICE_X63Y69.F1 net (fanout=1) 0.620 ftop/cp/cpRespF/data0_reg_or0000<5>_SW0/O + SLICE_X63Y69.CLK Tfck 0.602 ftop/cp_server_response_get<5> + ftop/cp/cpRespF/data0_reg_5_rstpot + ftop/cp/cpRespF/data0_reg_5 + ------------------------------------------------- --------------------------- + Total 19.211ns (7.615ns logic, 11.596ns route) + (39.6% logic, 60.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.780ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_25 (FF) + Destination: ftop/cp/cpRespF/data0_reg_24 (FF) + Requirement: 20.000ns + Data Path Delay: 19.130ns (Levels of Logic = 19) + Clock Path Skew: -0.090ns (0.446 - 0.536) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_25 to ftop/cp/cpRespF/data0_reg_24 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X53Y78.XQ Tcko 0.495 ftop/cp/cpReq<25> + ftop/cp/cpReq_25 + SLICE_X52Y79.G1 net (fanout=6) 0.496 ftop/cp/cpReq<25> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X65Y72.G3 net (fanout=40) 0.526 ftop/cp/cpRespF/d0h + SLICE_X65Y72.Y Tilo 0.561 ftop/cp_server_response_get<24> + ftop/cp/cpRespF/data0_reg_or0000<24>_SW0 + SLICE_X65Y72.F1 net (fanout=1) 0.575 ftop/cp/cpRespF/data0_reg_or0000<24>_SW0/O + SLICE_X65Y72.CLK Tfck 0.602 ftop/cp_server_response_get<24> + ftop/cp/cpRespF/data0_reg_24_rstpot + ftop/cp/cpRespF/data0_reg_24 + ------------------------------------------------- --------------------------- + Total 19.130ns (7.586ns logic, 11.544ns route) + (39.7% logic, 60.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.789ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_23 (FF) + Destination: ftop/cp/cpRespF/data0_reg_24 (FF) + Requirement: 20.000ns + Data Path Delay: 19.121ns (Levels of Logic = 19) + Clock Path Skew: -0.090ns (0.446 - 0.536) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_23 to ftop/cp/cpRespF/data0_reg_24 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X52Y78.XQ Tcko 0.521 ftop/cp/cpReq<23> + ftop/cp/cpReq_23 + SLICE_X49Y82.G4 net (fanout=19) 1.314 ftop/cp/cpReq<23> + SLICE_X49Y82.Y Tilo 0.561 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/Msub_wn__h76794_xor<3>11 + SLICE_X49Y82.F4 net (fanout=2) 0.290 ftop/cp/wn__h76794<3> + SLICE_X49Y82.X Tilo 0.562 ftop/cp/_theResult_____1__h76813<3> + ftop/cp/_theResult_____1__h76813<3>1 + SLICE_X45Y90.G1 net (fanout=17) 0.880 ftop/cp/_theResult_____1__h76813<3> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X65Y72.G3 net (fanout=40) 0.526 ftop/cp/cpRespF/d0h + SLICE_X65Y72.Y Tilo 0.561 ftop/cp_server_response_get<24> + ftop/cp/cpRespF/data0_reg_or0000<24>_SW0 + SLICE_X65Y72.F1 net (fanout=1) 0.575 ftop/cp/cpRespF/data0_reg_or0000<24>_SW0/O + SLICE_X65Y72.CLK Tfck 0.602 ftop/cp_server_response_get<24> + ftop/cp/cpRespF/data0_reg_24_rstpot + ftop/cp/cpRespF/data0_reg_24 + ------------------------------------------------- --------------------------- + Total 19.121ns (7.518ns logic, 11.603ns route) + (39.3% logic, 60.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.815ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_24 (FF) + Destination: ftop/cp/cpRespF/data0_reg_23 (FF) + Requirement: 20.000ns + Data Path Delay: 19.094ns (Levels of Logic = 19) + Clock Path Skew: -0.091ns (0.441 - 0.532) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_24 to ftop/cp/cpRespF/data0_reg_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X55Y78.YQ Tcko 0.524 ftop/cp/cpReq<16> + ftop/cp/cpReq_24 + SLICE_X52Y79.G2 net (fanout=8) 0.532 ftop/cp/cpReq<24> + SLICE_X52Y79.Y Tilo 0.616 ftop/cp/wn___1__h77584<3> + ftop/cp/Msub_wn___1__h77584_cy<1>11 + SLICE_X50Y80.F1 net (fanout=2) 0.888 ftop/cp/Msub_wn___1__h77584_cy<1> + SLICE_X50Y80.X Tilo 0.601 ftop/cp/_theResult_____1__h76813<2> + ftop/cp/_theResult_____1__h76813<2>1 + SLICE_X45Y90.G3 net (fanout=17) 1.041 ftop/cp/_theResult_____1__h76813<2> + SLICE_X45Y90.Y Tilo 0.561 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X37Y110.G1 net (fanout=11) 2.377 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X37Y110.Y Tilo 0.561 ftop/cp/wci_respF_4_D_IN<0>7 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X51Y90.F3 net (fanout=8) 2.989 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X51Y90.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X51Y91.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X51Y92.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X51Y93.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X51Y94.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X51Y95.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X51Y96.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X51Y97.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X51Y98.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X51Y99.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X51Y100.XB Tcinxb 0.216 ftop/cp/dispatched_D_IN115 + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X59Y77.G2 net (fanout=10) 1.830 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X59Y77.Y Tilo 0.561 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X64Y68.G3 net (fanout=7) 0.822 ftop/cp/cpRespF_ENQ + SLICE_X64Y68.Y Tilo 0.616 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X65Y74.G4 net (fanout=40) 0.979 ftop/cp/cpRespF/d0h + SLICE_X65Y74.Y Tilo 0.561 ftop/cp_server_response_get<23> + ftop/cp/cpRespF/data0_reg_or0000<23>_SW0 + SLICE_X65Y74.F3 net (fanout=1) 0.021 ftop/cp/cpRespF/data0_reg_or0000<23>_SW0/O + SLICE_X65Y74.CLK Tfck 0.602 ftop/cp_server_response_get<23> + ftop/cp/cpRespF/data0_reg_23_rstpot + ftop/cp/cpRespF/data0_reg_23 + ------------------------------------------------- --------------------------- + Total 19.094ns (7.615ns logic, 11.479ns route) + (39.9% logic, 60.1% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_ftop_clkN210_clkdv_unbuf = PERIOD TIMEGRP "ftop_clkN210_clkdv_unbuf" + TS_SYS0CLK * 2 HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.440ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/sma0/wsiM_reqFifo_q_0_33 (FF) + Destination: ftop/bias/wsiS_reqFifo/Mram_arr34.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.620ns (Levels of Logic = 1) + Clock Path Skew: 0.180ns (1.003 - 0.823) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/sma0/wsiM_reqFifo_q_0_33 to ftop/bias/wsiS_reqFifo/Mram_arr34.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X71Y102.XQ Tcko 0.396 ftop/sma0_wsiM0_MData<21> + ftop/sma0/wsiM_reqFifo_q_0_33 + SLICE_X70Y104.BY net (fanout=2) 0.354 ftop/sma0_wsiM0_MData<21> + SLICE_X70Y104.CLK Tdh (-Th) 0.130 ftop/bias/wsiS_reqFifo/_varindex0000<33> + ftop/bias/wsiS_reqFifo/Mram_arr34.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.620ns (0.266ns logic, 0.354ns route) + (42.9% logic, 57.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.441ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/sma0/wsiM_reqFifo_q_0_33 (FF) + Destination: ftop/bias/wsiS_reqFifo/Mram_arr34.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.621ns (Levels of Logic = 1) + Clock Path Skew: 0.180ns (1.003 - 0.823) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/sma0/wsiM_reqFifo_q_0_33 to ftop/bias/wsiS_reqFifo/Mram_arr34.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X71Y102.XQ Tcko 0.396 ftop/sma0_wsiM0_MData<21> + ftop/sma0/wsiM_reqFifo_q_0_33 + SLICE_X70Y104.BY net (fanout=2) 0.354 ftop/sma0_wsiM0_MData<21> + SLICE_X70Y104.CLK Tdh (-Th) 0.129 ftop/bias/wsiS_reqFifo/_varindex0000<33> + ftop/bias/wsiS_reqFifo/Mram_arr34.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.621ns (0.267ns logic, 0.354ns route) + (43.0% logic, 57.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.514ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_9_q_0_25 (FF) + Destination: ftop/gbewrk/wci_wslv_reqF/Mram_arr26.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.605ns (Levels of Logic = 1) + Clock Path Skew: 0.091ns (0.385 - 0.294) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_9_q_0_25 to ftop/gbewrk/wci_wslv_reqF/Mram_arr26.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y98.XQ Tcko 0.417 ftop/cp_wci_Vm_9_MData<25> + ftop/cp/wci_reqF_9_q_0_25 + SLICE_X86Y100.BY net (fanout=2) 0.318 ftop/cp_wci_Vm_9_MData<25> + SLICE_X86Y100.CLK Tdh (-Th) 0.130 ftop/gbewrk/wci_wslv_reqF/_varindex0000<25> + ftop/gbewrk/wci_wslv_reqF/Mram_arr26.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.605ns (0.287ns logic, 0.318ns route) + (47.4% logic, 52.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.515ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_9_q_0_25 (FF) + Destination: ftop/gbewrk/wci_wslv_reqF/Mram_arr26.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.606ns (Levels of Logic = 1) + Clock Path Skew: 0.091ns (0.385 - 0.294) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_9_q_0_25 to ftop/gbewrk/wci_wslv_reqF/Mram_arr26.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y98.XQ Tcko 0.417 ftop/cp_wci_Vm_9_MData<25> + ftop/cp/wci_reqF_9_q_0_25 + SLICE_X86Y100.BY net (fanout=2) 0.318 ftop/cp_wci_Vm_9_MData<25> + SLICE_X86Y100.CLK Tdh (-Th) 0.129 ftop/gbewrk/wci_wslv_reqF/_varindex0000<25> + ftop/gbewrk/wci_wslv_reqF/Mram_arr26.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.606ns (0.288ns logic, 0.318ns route) + (47.5% logic, 52.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.524ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_4_q_0_10 (FF) + Destination: ftop/sma1/wci_wslv_reqF/Mram_arr11.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.623ns (Levels of Logic = 1) + Clock Path Skew: 0.099ns (0.442 - 0.343) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_4_q_0_10 to ftop/sma1/wci_wslv_reqF/Mram_arr11.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X15Y133.YQ Tcko 0.419 ftop/cp_wci_Vm_4_MData<11> + ftop/cp/wci_reqF_4_q_0_10 + SLICE_X12Y134.BY net (fanout=2) 0.334 ftop/cp_wci_Vm_4_MData<10> + SLICE_X12Y134.CLK Tdh (-Th) 0.130 ftop/sma1/wci_wslv_reqF/_varindex0000<10> + ftop/sma1/wci_wslv_reqF/Mram_arr11.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.623ns (0.289ns logic, 0.334ns route) + (46.4% logic, 53.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.525ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_4_q_0_10 (FF) + Destination: ftop/sma1/wci_wslv_reqF/Mram_arr11.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.624ns (Levels of Logic = 1) + Clock Path Skew: 0.099ns (0.442 - 0.343) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_4_q_0_10 to ftop/sma1/wci_wslv_reqF/Mram_arr11.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X15Y133.YQ Tcko 0.419 ftop/cp_wci_Vm_4_MData<11> + ftop/cp/wci_reqF_4_q_0_10 + SLICE_X12Y134.BY net (fanout=2) 0.334 ftop/cp_wci_Vm_4_MData<10> + SLICE_X12Y134.CLK Tdh (-Th) 0.129 ftop/sma1/wci_wslv_reqF/_varindex0000<10> + ftop/sma1/wci_wslv_reqF/Mram_arr11.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.624ns (0.290ns logic, 0.334ns route) + (46.5% logic, 53.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.528ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_10_q_0_23 (FF) + Destination: ftop/iqadc/wci_wslv_reqF/Mram_arr24.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.598ns (Levels of Logic = 1) + Clock Path Skew: 0.070ns (0.398 - 0.328) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_10_q_0_23 to ftop/iqadc/wci_wslv_reqF/Mram_arr24.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y99.XQ Tcko 0.417 ftop/cp_wci_Vm_10_MData<23> + ftop/cp/wci_reqF_10_q_0_23 + SLICE_X22Y98.BY net (fanout=2) 0.311 ftop/cp_wci_Vm_10_MData<23> + SLICE_X22Y98.CLK Tdh (-Th) 0.130 ftop/iqadc/wci_wslv_reqF/_varindex0000<23> + ftop/iqadc/wci_wslv_reqF/Mram_arr24.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.598ns (0.287ns logic, 0.311ns route) + (48.0% logic, 52.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.529ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_10_q_0_23 (FF) + Destination: ftop/iqadc/wci_wslv_reqF/Mram_arr24.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.599ns (Levels of Logic = 1) + Clock Path Skew: 0.070ns (0.398 - 0.328) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_10_q_0_23 to ftop/iqadc/wci_wslv_reqF/Mram_arr24.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y99.XQ Tcko 0.417 ftop/cp_wci_Vm_10_MData<23> + ftop/cp/wci_reqF_10_q_0_23 + SLICE_X22Y98.BY net (fanout=2) 0.311 ftop/cp_wci_Vm_10_MData<23> + SLICE_X22Y98.CLK Tdh (-Th) 0.129 ftop/iqadc/wci_wslv_reqF/_varindex0000<23> + ftop/iqadc/wci_wslv_reqF/Mram_arr24.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.599ns (0.288ns logic, 0.311ns route) + (48.1% logic, 51.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.533ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_14_q_0_3 (FF) + Destination: ftop/edp1/wci_reqF/Mram_arr4.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.592ns (Levels of Logic = 1) + Clock Path Skew: 0.059ns (0.303 - 0.244) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_14_q_0_3 to ftop/edp1/wci_reqF/Mram_arr4.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y149.XQ Tcko 0.396 ftop/cp_wci_Vm_14_MData<3> + ftop/cp/wci_reqF_14_q_0_3 + SLICE_X76Y148.BY net (fanout=2) 0.326 ftop/cp_wci_Vm_14_MData<3> + SLICE_X76Y148.CLK Tdh (-Th) 0.130 ftop/edp1/wci_reqF/_varindex0000<3> + ftop/edp1/wci_reqF/Mram_arr4.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.592ns (0.266ns logic, 0.326ns route) + (44.9% logic, 55.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.534ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_14_q_0_3 (FF) + Destination: ftop/edp1/wci_reqF/Mram_arr4.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.593ns (Levels of Logic = 1) + Clock Path Skew: 0.059ns (0.303 - 0.244) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_14_q_0_3 to ftop/edp1/wci_reqF/Mram_arr4.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y149.XQ Tcko 0.396 ftop/cp_wci_Vm_14_MData<3> + ftop/cp/wci_reqF_14_q_0_3 + SLICE_X76Y148.BY net (fanout=2) 0.326 ftop/cp_wci_Vm_14_MData<3> + SLICE_X76Y148.CLK Tdh (-Th) 0.129 ftop/edp1/wci_reqF/_varindex0000<3> + ftop/edp1/wci_reqF/Mram_arr4.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.593ns (0.267ns logic, 0.326ns route) + (45.0% logic, 55.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.537ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/td_7 (FF) + Destination: ftop/cp/timeServ_setRefF/Mram_fifoMem40.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.598ns (Levels of Logic = 1) + Clock Path Skew: 0.061ns (0.578 - 0.517) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/td_7 to ftop/cp/timeServ_setRefF/Mram_fifoMem40.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X62Y34.XQ Tcko 0.417 ftop/cp/td<7> + ftop/cp/td_7 + SLICE_X64Y34.BY net (fanout=2) 0.311 ftop/cp/td<7> + SLICE_X64Y34.CLK Tdh (-Th) 0.130 ftop/cp/timeServ_setRefF_dD_OUT<39> + ftop/cp/timeServ_setRefF/Mram_fifoMem40.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.598ns (0.287ns logic, 0.311ns route) + (48.0% logic, 52.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.538ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/td_7 (FF) + Destination: ftop/cp/timeServ_setRefF/Mram_fifoMem40.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.599ns (Levels of Logic = 1) + Clock Path Skew: 0.061ns (0.578 - 0.517) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/td_7 to ftop/cp/timeServ_setRefF/Mram_fifoMem40.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X62Y34.XQ Tcko 0.417 ftop/cp/td<7> + ftop/cp/td_7 + SLICE_X64Y34.BY net (fanout=2) 0.311 ftop/cp/td<7> + SLICE_X64Y34.CLK Tdh (-Th) 0.129 ftop/cp/timeServ_setRefF_dD_OUT<39> + ftop/cp/timeServ_setRefF/Mram_fifoMem40.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.599ns (0.288ns logic, 0.311ns route) + (48.1% logic, 51.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.539ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pwrk/i2cC_vrReadData_2 (FF) + Destination: ftop/pwrk/i2cC_fResponse/Mram_arr3.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.563ns (Levels of Logic = 1) + Clock Path Skew: 0.024ns (0.104 - 0.080) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/pwrk/i2cC_vrReadData_2 to ftop/pwrk/i2cC_fResponse/Mram_arr3.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X95Y47.XQ Tcko 0.396 ftop/pwrk/i2cC_vrReadData_2 + ftop/pwrk/i2cC_vrReadData_2 + SLICE_X94Y44.BY net (fanout=3) 0.297 ftop/pwrk/i2cC_vrReadData_2 + SLICE_X94Y44.CLK Tdh (-Th) 0.130 ftop/pwrk/i2cC_fResponse/_varindex0000<2> + ftop/pwrk/i2cC_fResponse/Mram_arr3.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.563ns (0.266ns logic, 0.297ns route) + (47.2% logic, 52.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.540ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pwrk/i2cC_vrReadData_2 (FF) + Destination: ftop/pwrk/i2cC_fResponse/Mram_arr3.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.564ns (Levels of Logic = 1) + Clock Path Skew: 0.024ns (0.104 - 0.080) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/pwrk/i2cC_vrReadData_2 to ftop/pwrk/i2cC_fResponse/Mram_arr3.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X95Y47.XQ Tcko 0.396 ftop/pwrk/i2cC_vrReadData_2 + ftop/pwrk/i2cC_vrReadData_2 + SLICE_X94Y44.BY net (fanout=3) 0.297 ftop/pwrk/i2cC_vrReadData_2 + SLICE_X94Y44.CLK Tdh (-Th) 0.129 ftop/pwrk/i2cC_fResponse/_varindex0000<2> + ftop/pwrk/i2cC_fResponse/Mram_arr3.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.564ns (0.267ns logic, 0.297ns route) + (47.3% logic, 52.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.542ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_3_q_0_17 (FF) + Destination: ftop/bias/wci_wslv_reqF/Mram_arr18.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.615ns (Levels of Logic = 1) + Clock Path Skew: 0.073ns (0.405 - 0.332) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_3_q_0_17 to ftop/bias/wci_wslv_reqF/Mram_arr18.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X92Y127.XQ Tcko 0.417 ftop/cp_wci_Vm_3_MData<17> + ftop/cp/wci_reqF_3_q_0_17 + SLICE_X94Y127.BY net (fanout=2) 0.328 ftop/cp_wci_Vm_3_MData<17> + SLICE_X94Y127.CLK Tdh (-Th) 0.130 ftop/bias/wci_wslv_reqF/_varindex0000<17> + ftop/bias/wci_wslv_reqF/Mram_arr18.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.615ns (0.287ns logic, 0.328ns route) + (46.7% logic, 53.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.543ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_3_q_0_17 (FF) + Destination: ftop/bias/wci_wslv_reqF/Mram_arr18.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.616ns (Levels of Logic = 1) + Clock Path Skew: 0.073ns (0.405 - 0.332) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_3_q_0_17 to ftop/bias/wci_wslv_reqF/Mram_arr18.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X92Y127.XQ Tcko 0.417 ftop/cp_wci_Vm_3_MData<17> + ftop/cp/wci_reqF_3_q_0_17 + SLICE_X94Y127.BY net (fanout=2) 0.328 ftop/cp_wci_Vm_3_MData<17> + SLICE_X94Y127.CLK Tdh (-Th) 0.129 ftop/bias/wci_wslv_reqF/_varindex0000<17> + ftop/bias/wci_wslv_reqF/Mram_arr18.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.616ns (0.288ns logic, 0.328ns route) + (46.8% logic, 53.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.545ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_10_q_0_15 (FF) + Destination: ftop/iqadc/wci_wslv_reqF/Mram_arr16.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.607ns (Levels of Logic = 1) + Clock Path Skew: 0.062ns (0.371 - 0.309) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_10_q_0_15 to ftop/iqadc/wci_wslv_reqF/Mram_arr16.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X19Y110.XQ Tcko 0.396 ftop/cp_wci_Vm_10_MData<15> + ftop/cp/wci_reqF_10_q_0_15 + SLICE_X16Y111.BY net (fanout=2) 0.341 ftop/cp_wci_Vm_10_MData<15> + SLICE_X16Y111.CLK Tdh (-Th) 0.130 ftop/iqadc/wci_wslv_reqF/_varindex0000<15> + ftop/iqadc/wci_wslv_reqF/Mram_arr16.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.607ns (0.266ns logic, 0.341ns route) + (43.8% logic, 56.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.546ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_10_q_0_15 (FF) + Destination: ftop/iqadc/wci_wslv_reqF/Mram_arr16.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.608ns (Levels of Logic = 1) + Clock Path Skew: 0.062ns (0.371 - 0.309) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_10_q_0_15 to ftop/iqadc/wci_wslv_reqF/Mram_arr16.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X19Y110.XQ Tcko 0.396 ftop/cp_wci_Vm_10_MData<15> + ftop/cp/wci_reqF_10_q_0_15 + SLICE_X16Y111.BY net (fanout=2) 0.341 ftop/cp_wci_Vm_10_MData<15> + SLICE_X16Y111.CLK Tdh (-Th) 0.129 ftop/iqadc/wci_wslv_reqF/_varindex0000<15> + ftop/iqadc/wci_wslv_reqF/Mram_arr16.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.608ns (0.267ns logic, 0.341ns route) + (43.9% logic, 56.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.552ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_3_q_0_10 (FF) + Destination: ftop/bias/wci_wslv_reqF/Mram_arr11.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.619ns (Levels of Logic = 1) + Clock Path Skew: 0.067ns (0.375 - 0.308) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_3_q_0_10 to ftop/bias/wci_wslv_reqF/Mram_arr11.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y140.YQ Tcko 0.419 ftop/cp_wci_Vm_3_MData<11> + ftop/cp/wci_reqF_3_q_0_10 + SLICE_X90Y140.BY net (fanout=2) 0.330 ftop/cp_wci_Vm_3_MData<10> + SLICE_X90Y140.CLK Tdh (-Th) 0.130 ftop/bias/wci_wslv_reqF/_varindex0000<10> + ftop/bias/wci_wslv_reqF/Mram_arr11.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.619ns (0.289ns logic, 0.330ns route) + (46.7% logic, 53.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.553ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_9_q_0_14 (FF) + Destination: ftop/gbewrk/wci_wslv_reqF/Mram_arr15.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.615ns (Levels of Logic = 1) + Clock Path Skew: 0.062ns (0.362 - 0.300) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_9_q_0_14 to ftop/gbewrk/wci_wslv_reqF/Mram_arr15.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X89Y92.YQ Tcko 0.419 ftop/cp_wci_Vm_9_MData<15> + ftop/cp/wci_reqF_9_q_0_14 + SLICE_X90Y93.BY net (fanout=2) 0.326 ftop/cp_wci_Vm_9_MData<14> + SLICE_X90Y93.CLK Tdh (-Th) 0.130 ftop/gbewrk/wci_wslv_reqF/_varindex0000<14> + ftop/gbewrk/wci_wslv_reqF/Mram_arr15.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.615ns (0.289ns logic, 0.326ns route) + (47.0% logic, 53.0% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_clkN210_clkdv_unbuf = PERIOD TIMEGRP "ftop_clkN210_clkdv_unbuf" + TS_SYS0CLK * 2 HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/pwrk/wci_wslv_isReset_isInReset/SR + Logical resource: ftop/pwrk/wci_wslv_isReset_isInReset/SR + Location pin: SLICE_X24Y96.SR + Clock network: ftop/cp_RST_N_wci_Vm_7 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/pwrk/wci_wslv_isReset_isInReset/SR + Logical resource: ftop/pwrk/wci_wslv_isReset_isInReset/SR + Location pin: SLICE_X24Y96.SR + Clock network: ftop/cp_RST_N_wci_Vm_7 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/edp1/wmi_wmi_isReset_isInReset/SR + Logical resource: ftop/edp1/wmi_wmi_isReset_isInReset/SR + Location pin: SLICE_X24Y147.SR + Clock network: ftop/cp_RST_N_wci_Vm_14 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/edp1/wmi_wmi_isReset_isInReset/SR + Logical resource: ftop/edp1/wmi_wmi_isReset_isInReset/SR + Location pin: SLICE_X24Y147.SR + Clock network: ftop/cp_RST_N_wci_Vm_14 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<31>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_31/SR + Location pin: SLICE_X62Y28.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<31>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_31/SR + Location pin: SLICE_X62Y28.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<31>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_30/SR + Location pin: SLICE_X62Y28.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<31>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_30/SR + Location pin: SLICE_X62Y28.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<23>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_23/SR + Location pin: SLICE_X60Y26.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<23>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_23/SR + Location pin: SLICE_X60Y26.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<23>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_22/SR + Location pin: SLICE_X60Y26.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<23>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_22/SR + Location pin: SLICE_X60Y26.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<15>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_15/SR + Location pin: SLICE_X62Y21.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<15>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_15/SR + Location pin: SLICE_X62Y21.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<15>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_14/SR + Location pin: SLICE_X62Y21.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<15>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_14/SR + Location pin: SLICE_X62Y21.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<41>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_41/SR + Location pin: SLICE_X62Y30.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<41>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_41/SR + Location pin: SLICE_X62Y30.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<41>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_40/SR + Location pin: SLICE_X62Y30.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/timeServ_nowInCC_dD_OUT<41>/SR + Logical resource: ftop/cp/timeServ_nowInCC/dD_OUT_40/SR + Location pin: SLICE_X62Y30.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- + + +Derived Constraint Report +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 10.000ns| 4.800ns| 9.748ns| 0| 0| 2| 5249683| +| TS_ftop_clkN210_clk0_unbuf | 10.000ns| 6.533ns| N/A| 0| 0| 1| 0| +| TS_ftop_clkN210_clkdv_unbuf | 20.000ns| 19.497ns| N/A| 0| 0| 5249682| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +All constraints were met. + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Clock to Setup on destination clock gmii_rx_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +gmii_rx_clk | 6.917| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock gmii_sysclk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +gmii_sysclk | 7.889| | 3.812| | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 19.497| | | | +sys0_clkp | 19.497| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 19.497| | | | +sys0_clkp | 19.497| | | | +---------------+---------+---------+---------+---------+ + + +Timing summary: +--------------- + +Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) + +Constraints cover 5265969 paths, 0 nets, and 124430 connections + +Design statistics: + Minimum period: 19.497ns{1} (Maximum frequency: 51.290MHz) + + +------------------------------------Footnotes----------------------------------- +1) The minimum period statistic assumes all single cycle delays. + +Analysis completed Mon Sep 24 15:48:01 2012 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 923 MB + + + diff --git a/logs/n210-20120924_1549/fpgaTop_map.mrp b/logs/n210-20120924_1549/fpgaTop_map.mrp new file mode 100644 index 00000000..e9fbfb6a --- /dev/null +++ b/logs/n210-20120924_1549/fpgaTop_map.mrp @@ -0,0 +1,1370 @@ +Release 14.2 Map P.28xd (lin64) +Xilinx Mapping Report File for Design 'fpgaTop' + +Design Information +------------------ +Command Line : map -p xc3sd3400a-fg676-5 -w -ir off -pr off -o fpgaTop_map.ncd +fpgaTop.ngd fpgaTop.pcf +Target Device : xc3sd3400a +Target Package : fg676 +Target Speed : -5 +Mapper Version : spartan3adsp -- $Revision: 1.55 $ +Mapped Date : Mon Sep 24 15:42:00 2012 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 16 +Logic Utilization: + Number of Slice Flip Flops: 16,331 out of 47,744 34% + Number of 4 input LUTs: 26,699 out of 47,744 55% +Logic Distribution: + Number of occupied Slices: 18,910 out of 23,872 79% + Number of Slices containing only related logic: 18,910 out of 18,910 100% + Number of Slices containing unrelated logic: 0 out of 18,910 0% + *See NOTES below for an explanation of the effects of unrelated logic. + Total Number of 4 input LUTs: 29,036 out of 47,744 60% + Number used as logic: 24,256 + Number used as a route-thru: 2,337 + Number used for Dual Port RAMs: 2,412 + (Two LUTs used per Dual Port RAM) + Number used as Shift registers: 31 + + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + + Number of bonded IOBs: 109 out of 469 23% + IOB Master Pads: 1 + IOB Slave Pads: 1 + Number of ODDR2s used: 11 + Number of DDR_ALIGNMENT = NONE 11 + Number of DDR_ALIGNMENT = C0 0 + Number of DDR_ALIGNMENT = C1 0 + Number of BUFGMUXs: 5 out of 24 20% + Number of DCMs: 1 out of 8 12% + Number of RAMB16BWERs: 47 out of 126 37% + Number of DNA_PORTs: 1 out of 1 100% + +Average Fanout of Non-Clock Nets: 3.46 + +Peak Memory Usage: 1071 MB +Total REAL time to MAP completion: 39 secs +Total CPU time to MAP completion: 39 secs + +NOTES: + + Related logic is defined as being logic that shares connectivity - e.g. two + LUTs are "related" if they share common inputs. When assembling slices, + Map gives priority to combine logic that is related. Doing so results in + the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin packing + unrelated logic into a slice once 99% of the slices are occupied through + related logic packing. + + Note that once logic distribution reaches the 99% level through related + logic packing, this does not mean the device is completely utilized. + Unrelated logic packing will then begin, continuing until all usable LUTs + and FFs are occupied. Depending on your timing budget, increased levels of + unrelated logic packing may adversely affect the overall timing performance + of your design. + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX + symbol "physical_group_adc_sclkdrv/ftop/iqadc/adcCore_spiI_cd/cntr_2_BUFG" + (output signal=adc_sclkdrv) has a mix of clock and non-clock loads. The + non-clock loads are: + Pin I0 of adc_sclk1 +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. + +Section 3 - Informational +------------------------- +INFO:LIT:243 - Logical network N4 has no load. +INFO:LIT:395 - The above info message is repeated 2068 more times for the + following (max. 5 shown): + N5, + dac_sen, + dac_smiso, + dac_lock, + dac_sclk + To see the details of these info messages, please use the -detail switch. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs. + +Section 4 - Removed Logic Summary +--------------------------------- + 152 block(s) removed + 215 block(s) optimized away + 496 signal(s) removed + +Section 5 - Removed Logic +------------------------- + +The trimmed logic report below shows the logic removed from your design due to +sourceless or loadless signals, and VCC or ground connections. If the removal +of a signal or symbol results in the subsequent removal of an additional signal +or symbol, the message explaining that second removal will be indented. This +indentation will be repeated as a chain of related logic is removed. + +To quickly locate the original cause for the removal of a chain of logic, look +above the place where that logic is listed in the trimming report, then locate +the lines that are least indented (begin at the leftmost edge). + +The signal "ftop/CLK_GATE_rxclkBnd" is sourceless and has been removed. +The signal "ftop/eddp1/edpReqF/d1di" is sourceless and has been removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_8" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<8>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_9" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<9>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_18" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<18>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_19" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<19>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_20" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<20>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_21" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<21>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_22" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<22>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_23" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<23>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_24" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<24>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_25" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<25>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_26" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<26>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_27" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<27>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_28" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<28>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_29" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<29>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_30" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<30>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_31" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<31>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_32" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<32>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_33" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<33>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_34" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<34>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_35" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<35>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_36" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<36>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_37" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<37>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_38" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<38>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_39" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<39>" is sourceless and has been +removed. +The signal "ftop/eddp1/edpReqF/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/eddp1/edpReqF/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/eddp1/dpReqF/d1di" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_8" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<8>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_9" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<9>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_18" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<18>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_19" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<19>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_20" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<20>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_21" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<21>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_22" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<22>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_23" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<23>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_24" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<24>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_25" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<25>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_26" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<26>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_27" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<27>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_28" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<28>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_29" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<29>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_30" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<30>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_31" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<31>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_32" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<32>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_33" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<33>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_34" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<34>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_35" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<35>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_36" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<36>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_37" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<37>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_38" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<38>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_39" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<39>" is sourceless and has been removed. +The signal "ftop/eddp1/dpReqF/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/eddp1/dpReqF/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/eddp0/edpReqF/d1di" is sourceless and has been removed. + Sourceless block "ftop/eddp0/edpReqF/data1_reg_8" (FF) removed. + The signal "ftop/eddp0/edpReqF/data1_reg<8>" is sourceless and has been removed. + Sourceless block "ftop/eddp0/edpReqF/data1_reg_9" (FF) removed. + The signal "ftop/eddp0/edpReqF/data1_reg<9>" is sourceless and has been removed. + Sourceless block "ftop/eddp0/edpReqF/data1_reg_18" (FF) removed. + The signal "ftop/eddp0/edpReqF/data1_reg<18>" is sourceless and has been +removed. + Sourceless block "ftop/eddp0/edpReqF/data1_reg_19" (FF) removed. + The signal "ftop/eddp0/edpReqF/data1_reg<19>" is sourceless and has been +removed. + Sourceless block "ftop/eddp0/edpReqF/data1_reg_28" (FF) removed. + The signal "ftop/eddp0/edpReqF/data1_reg<28>" is sourceless and has been +removed. + Sourceless block "ftop/eddp0/edpReqF/data1_reg_29" (FF) removed. + The signal "ftop/eddp0/edpReqF/data1_reg<29>" is sourceless and has been +removed. + Sourceless block "ftop/eddp0/edpReqF/data1_reg_38" (FF) removed. + The signal "ftop/eddp0/edpReqF/data1_reg<38>" is sourceless and has been +removed. + Sourceless block "ftop/eddp0/edpReqF/data1_reg_39" (FF) removed. + The signal "ftop/eddp0/edpReqF/data1_reg<39>" is sourceless and has been +removed. +The signal "ftop/eddp0/edpReqF/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/eddp0/edpReqF/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/eddp0/dpReqF/d1di" is sourceless and has been removed. + Sourceless block "ftop/eddp0/dpReqF/data1_reg_8" (FF) removed. + The signal "ftop/eddp0/dpReqF/data1_reg<8>" is sourceless and has been removed. + Sourceless block "ftop/eddp0/dpReqF/data1_reg_9" (FF) removed. + The signal "ftop/eddp0/dpReqF/data1_reg<9>" is sourceless and has been removed. + Sourceless block "ftop/eddp0/dpReqF/data1_reg_18" (FF) removed. + The signal "ftop/eddp0/dpReqF/data1_reg<18>" is sourceless and has been removed. + Sourceless block "ftop/eddp0/dpReqF/data1_reg_19" (FF) removed. + The signal "ftop/eddp0/dpReqF/data1_reg<19>" is sourceless and has been removed. + Sourceless block "ftop/eddp0/dpReqF/data1_reg_28" (FF) removed. + The signal "ftop/eddp0/dpReqF/data1_reg<28>" is sourceless and has been removed. + Sourceless block "ftop/eddp0/dpReqF/data1_reg_29" (FF) removed. + The signal "ftop/eddp0/dpReqF/data1_reg<29>" is sourceless and has been removed. + Sourceless block "ftop/eddp0/dpReqF/data1_reg_38" (FF) removed. + The signal "ftop/eddp0/dpReqF/data1_reg<38>" is sourceless and has been removed. + Sourceless block "ftop/eddp0/dpReqF/data1_reg_39" (FF) removed. + The signal "ftop/eddp0/dpReqF/data1_reg<39>" is sourceless and has been removed. +The signal "ftop/eddp0/dpReqF/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/eddp0/dpReqF/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/edp0/N233" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inProcF_ENQ2" (ROM) removed. + The signal "ftop/edp0/edp_inProcF_ENQ" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inProcF/empty_reg_and00011" (ROM) removed. + The signal "ftop/edp0/edp_inProcF/empty_reg_and0001" is sourceless and has been +removed. + Sourceless block "ftop/edp0/edp_inProcF/empty_reg" (SFF) removed. + The signal "ftop/edp0/edp_inProcF_EMPTY_N" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inProcF/full_reg_not00011" (ROM) removed. + The signal "ftop/edp0/edp_inProcF/full_reg_not0001" is sourceless and has been +removed. + Sourceless block "ftop/edp0/edp_inProcF/empty_reg_and00001" (ROM) removed. + The signal "ftop/edp0/edp_inProcF/empty_reg_and0000" is sourceless and has been +removed. +The signal "ftop/edp0/edp_inProcF/empty_reg_not0001" is sourceless and has been +removed. +The signal "ftop/edp0/edp_inProcF/empty_reg_or0000" is sourceless and has been +removed. +The signal "ftop/edp0/edp_inProcF/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/edp0/edp_inF/d1di" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inF/data1_reg_8" (FF) removed. + The signal "ftop/edp0/edp_inF/data1_reg<8>" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inF/data1_reg_9" (FF) removed. + The signal "ftop/edp0/edp_inF/data1_reg<9>" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inF/data1_reg_18" (FF) removed. + The signal "ftop/edp0/edp_inF/data1_reg<18>" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inF/data1_reg_19" (FF) removed. + The signal "ftop/edp0/edp_inF/data1_reg<19>" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inF/data1_reg_28" (FF) removed. + The signal "ftop/edp0/edp_inF/data1_reg<28>" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inF/data1_reg_29" (FF) removed. + The signal "ftop/edp0/edp_inF/data1_reg<29>" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inF/data1_reg_38" (FF) removed. + The signal "ftop/edp0/edp_inF/data1_reg<38>" is sourceless and has been removed. + Sourceless block "ftop/edp0/edp_inF/data1_reg_39" (FF) removed. + The signal "ftop/edp0/edp_inF/data1_reg<39>" is sourceless and has been removed. +The signal "ftop/edp0/edp_inF/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/edp0/edp_inF/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/edp0/bram_memory_3/DOA<0>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<10>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<11>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<12>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<13>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<14>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<15>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<16>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<17>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<18>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<19>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<1>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<20>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<21>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<22>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<23>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<24>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<25>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<26>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<27>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<28>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<29>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<2>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<30>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<31>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<3>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<4>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<5>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<6>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<7>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<8>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_3/DOA<9>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<0>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<10>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<11>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<12>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<13>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<14>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<15>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<16>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<17>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<18>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<19>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<1>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<20>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<21>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<22>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<23>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<24>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<25>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<26>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<27>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<28>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<29>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<2>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<30>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<31>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<3>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<4>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<5>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<6>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<7>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<8>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2/DOA<9>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<0>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<10>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<11>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<12>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<13>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<14>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<15>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<16>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<17>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<18>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<19>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<1>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<20>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<21>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<22>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<23>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<24>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<25>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<26>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<27>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<28>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<29>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<2>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<30>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<31>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<3>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<4>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<5>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<6>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<7>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<8>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1/DOA<9>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<0>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<10>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<11>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<12>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<13>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<14>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<15>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<16>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<17>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<18>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<19>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<1>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<20>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<21>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<22>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<23>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<24>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<25>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<26>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<27>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<28>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<29>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<2>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<30>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<31>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<3>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<4>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<5>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<6>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<7>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<8>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory/DOA<9>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<10>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<11>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<12>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<13>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<14>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<15>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<16>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<17>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<18>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<19>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<20>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<21>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<22>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<23>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<24>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<25>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<26>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<27>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<28>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<29>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<30>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<31>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<8>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<9>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<0>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<10>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<11>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<12>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<13>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<14>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<15>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<16>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<17>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<18>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<19>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<1>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<20>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<21>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<22>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<23>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<24>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<25>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<26>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<27>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<28>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<29>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<2>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<30>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<31>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<3>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<4>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<5>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<6>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<7>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<8>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<9>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<0>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<10>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<11>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<12>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<13>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<14>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<15>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<16>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<17>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<18>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<19>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<1>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<20>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<21>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<22>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<23>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<24>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<25>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<26>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<27>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<28>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<29>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<2>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<30>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<31>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<3>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<4>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<5>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<6>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<7>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<8>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<9>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_DOB<24>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_DOB<25>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_DOB<26>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_DOB<27>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_DOB<28>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_DOB<29>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_DOB<30>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_DOB<31>" is sourceless and has been removed. +The signal "ftop/edp1/edp_inF/d1di" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_8" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<8>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_9" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<9>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_18" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<18>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_19" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<19>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_20" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<20>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_21" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<21>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_22" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<22>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_23" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<23>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_24" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<24>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_25" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<25>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_26" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<26>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_27" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<27>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_28" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<28>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_29" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<29>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_30" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<30>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_31" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<31>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_32" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<32>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_33" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<33>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_34" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<34>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_35" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<35>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_36" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<36>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_37" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<37>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_38" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<38>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_39" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<39>" is sourceless and has been removed. +The signal "ftop/edp1/edp_inF/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/edp1/edp_inF/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<0>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<10>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<11>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<12>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<13>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<14>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<15>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<16>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<17>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<18>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<19>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<1>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<20>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<21>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<22>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<23>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<24>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<25>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<26>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<27>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<28>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<29>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<2>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<30>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<31>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<32>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<33>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<34>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<35>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<36>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<37>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<38>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<39>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<3>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<4>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<5>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<6>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<7>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<8>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<9>" is sourceless and has been +removed. +The signal "ftop/emux/fork1_d1F/d1di" is sourceless and has been removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_8" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<8>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_9" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<9>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_18" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<18>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_19" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<19>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_20" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<20>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_21" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<21>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_22" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<22>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_23" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<23>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_24" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<24>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_25" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<25>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_26" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<26>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_27" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<27>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_28" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<28>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_29" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<29>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_30" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<30>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_31" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<31>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_32" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<32>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_33" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<33>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_34" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<34>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_35" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<35>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_36" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<36>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_37" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<37>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_38" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<38>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_39" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<39>" is sourceless and has been +removed. +The signal "ftop/emux/fork1_d1F/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/emux/fork1_d1F/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/emux/fork1_d0F/d1di" is sourceless and has been removed. + Sourceless block "ftop/emux/fork1_d0F/data1_reg_8" (FF) removed. + The signal "ftop/emux/fork1_d0F/data1_reg<8>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d0F/data1_reg_9" (FF) removed. + The signal "ftop/emux/fork1_d0F/data1_reg<9>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d0F/data1_reg_18" (FF) removed. + The signal "ftop/emux/fork1_d0F/data1_reg<18>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d0F/data1_reg_19" (FF) removed. + The signal "ftop/emux/fork1_d0F/data1_reg<19>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d0F/data1_reg_28" (FF) removed. + The signal "ftop/emux/fork1_d0F/data1_reg<28>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d0F/data1_reg_29" (FF) removed. + The signal "ftop/emux/fork1_d0F/data1_reg<29>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d0F/data1_reg_38" (FF) removed. + The signal "ftop/emux/fork1_d0F/data1_reg<38>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d0F/data1_reg_39" (FF) removed. + The signal "ftop/emux/fork1_d0F/data1_reg<39>" is sourceless and has been +removed. +The signal "ftop/emux/fork1_d0F/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/emux/fork1_d0F/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/sma0/respF_memory/DOA<0>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<10>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<11>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<12>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<13>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<14>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<15>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<16>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<17>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<18>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<19>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<1>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<20>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<21>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<22>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<23>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<24>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<25>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<26>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<27>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<28>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<29>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<2>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<30>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<31>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<32>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<33>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<34>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<35>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<36>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<37>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<38>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<39>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<3>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<40>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<41>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<42>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<43>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<44>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<4>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<54>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<55>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<56>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<57>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<58>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<59>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<5>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<60>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<6>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<7>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<8>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<9>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOB<44>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOB<54>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOB<55>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<54>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<55>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<56>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<57>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<58>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<59>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<60>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOB<54>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOB<55>" is sourceless and has been removed. +The signal "ftop/iqadc/adcCore_sampF_memory/DOA<36>" is sourceless and has been +removed. +The signal "ftop/iqadc/adcCore_sampF_memory/DOA<37>" is sourceless and has been +removed. +The signal "ftop/iqadc/adcCore_sampF_memory/DOA<38>" is sourceless and has been +removed. +The signal "ftop/iqadc/adcCore_sampF_memory/DOB<37>" is sourceless and has been +removed. +The signal "ftop/iqadc/adcCore_sampF_memory/DOB<38>" is sourceless and has been +removed. +The signal "ftop/gbe0/gmac/RDY_phyInterrupt" is sourceless and has been removed. +Unused block "ftop/edp0/edp_inProcF/empty_reg_not00011_INV_0" (BUF) removed. +Unused block "ftop/edp0/edp_inProcF/empty_reg_or00001_INV_0" (BUF) removed. +Unused block "ftop/edp0/edp_inProcF_ENQ11" (ROM) removed. +Unused block "ftop/edp1/edp_inF/d1di1" (ROM) removed. +Unused block "ftop/edp1/edp_inF/full_reg_not00011" (ROM) removed. +Unused block "ftop/eddp0/dpReqF/d1di1" (ROM) removed. +Unused block "ftop/eddp0/dpReqF/full_reg_not00011" (ROM) removed. +Unused block "ftop/eddp0/edpReqF/d1di1" (ROM) removed. +Unused block "ftop/eddp0/edpReqF/full_reg_not00011" (ROM) removed. +Unused block "ftop/eddp1/dpReqF/d1di1" (ROM) removed. +Unused block "ftop/eddp1/dpReqF/full_reg_not00011" (ROM) removed. +Unused block "ftop/eddp1/edpReqF/d1di1" (ROM) removed. +Unused block "ftop/eddp1/edpReqF/full_reg_not00011" (ROM) removed. +Unused block "ftop/edp0/edp_inF/d1di1" (ROM) removed. +Unused block "ftop/edp0/edp_inF/full_reg_not00011" (ROM) removed. +Unused block "ftop/emux/fork1_d0F/d1di1" (ROM) removed. +Unused block "ftop/emux/fork1_d0F/full_reg_not00011" (ROM) removed. +Unused block "ftop/emux/fork1_d1F/d1di1" (ROM) removed. +Unused block "ftop/emux/fork1_d1F/full_reg_not00011" (ROM) removed. + +Optimized Block(s): +TYPE BLOCK +GND ftop/XST_GND +VCC ftop/XST_VCC +GND ftop/bias/XST_GND +VCC ftop/bias/XST_VCC +GND ftop/bias/wci_wslv_reqF/XST_GND +GND ftop/bias/wsiS_reqFifo/XST_GND +GND ftop/clkN210/XST_GND +GND ftop/cp/XST_GND +VCC ftop/cp/XST_VCC +GND ftop/cp/adminResp1F/XST_GND +GND ftop/cp/adminResp2F/XST_GND +GND ftop/cp/adminResp3F/XST_GND +GND ftop/cp/adminResp4F/XST_GND +GND ftop/cp/adminRespF/XST_GND +GND ftop/cp/rom_memory/XST_GND +GND ftop/cp/rom_serverAdapter_outDataCore/XST_GND +GND ftop/cp/timeServ_setRefF/XST_GND +VCC ftop/cp/wci_mReset_10/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_13/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_14/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_2/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_3/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_4/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_7/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_9/rstSync/XST_VCC +GND ftop/cp/wci_respF/XST_GND +GND ftop/cp/wci_respF_1/XST_GND +GND ftop/cp/wci_respF_10/XST_GND +GND ftop/cp/wci_respF_11/XST_GND +GND ftop/cp/wci_respF_12/XST_GND +GND ftop/cp/wci_respF_13/XST_GND +GND ftop/cp/wci_respF_14/XST_GND +GND ftop/cp/wci_respF_2/XST_GND +GND ftop/cp/wci_respF_3/XST_GND +GND ftop/cp/wci_respF_4/XST_GND +GND ftop/cp/wci_respF_5/XST_GND +GND ftop/cp/wci_respF_6/XST_GND +GND ftop/cp/wci_respF_7/XST_GND +GND ftop/cp/wci_respF_8/XST_GND +GND ftop/cp/wci_respF_9/XST_GND +GND ftop/edcp/XST_GND +VCC ftop/edcp/XST_VCC +GND ftop/eddp0/XST_GND +GND ftop/eddp1/XST_GND +GND ftop/edp0/XST_GND +VCC ftop/edp0/XST_VCC +GND ftop/edp0/bram_memory/XST_GND +GND ftop/edp0/bram_memory_1/XST_GND +GND ftop/edp0/bram_memory_2/XST_GND +GND ftop/edp0/bram_memory_3/XST_GND +GND ftop/edp0/bram_serverAdapterB_1_outDataCore/XST_GND +GND ftop/edp0/bram_serverAdapterB_2_outDataCore/XST_GND +GND ftop/edp0/bram_serverAdapterB_3_outDataCore/XST_GND +GND ftop/edp0/bram_serverAdapterB_outDataCore/XST_GND +FDSE ftop/edp0/edp_inProcF/full_reg + optimized to 1 +LUT3 ftop/edp0/edp_inProcF/full_reg_mux00001 + optimized to 1 +GND ftop/edp0/wci_reqF/XST_GND +GND ftop/edp0/wmi_wmi_dhF/XST_GND +GND ftop/edp0/wmi_wmi_mFlagF/XST_GND +GND ftop/edp0/wmi_wmi_reqF/XST_GND +LUT1 ftop/edp1/Madd_MUX_edp_tlpBRAM_writeDWAddr_write_1__VAL_1_xor<11>_rt + optimized to 0 +GND ftop/edp1/XST_GND +VCC ftop/edp1/XST_VCC +GND ftop/edp1/bram_memory/XST_GND +GND ftop/edp1/bram_memory_1/XST_GND +GND ftop/edp1/bram_memory_2/XST_GND +GND ftop/edp1/bram_memory_3/XST_GND +GND ftop/edp1/bram_serverAdapterA_1_outDataCore/XST_GND +GND ftop/edp1/bram_serverAdapterA_2_outDataCore/XST_GND +GND ftop/edp1/bram_serverAdapterA_3_outDataCore/XST_GND +GND ftop/edp1/bram_serverAdapterA_outDataCore/XST_GND +GND ftop/edp1/bram_serverAdapterB_1_outDataCore/XST_GND +GND ftop/edp1/bram_serverAdapterB_outDataCore/XST_GND +LUT2 ftop/edp1/edp_inF/d0d11 + optimized to 0 +INV ftop/edp1/edp_inF/empty_reg_not00011_INV_0 +FDSE ftop/edp1/edp_inF/full_reg + optimized to 1 +LUT3 ftop/edp1/edp_inF/full_reg_mux00001 + optimized to 1 +GND ftop/edp1/edp_outBF_memory/XST_GND +GND ftop/edp1/edp_tlpBRAM_mReqF/XST_GND +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<0>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<101>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<103>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<105>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<107>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<109>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<10>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<111>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<113>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<115>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<117>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<119>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<121>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<123>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<125>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<127>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<128>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<2>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<42>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<43>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<44>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mRespF/data0_reg_or0000<129>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mRespF/data0_reg_or0000<131>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mRespF/data0_reg_or0000<133>1 + optimized to 0 +GND ftop/edp1/wci_reqF/XST_GND +GND ftop/edp1/wmi_wmi_dhF/XST_GND +GND ftop/edp1/wmi_wmi_mFlagF/XST_GND +GND ftop/edp1/wmi_wmi_reqF/XST_GND +VCC ftop/emux/XST_VCC +GND ftop/gbe0/XST_GND +VCC ftop/gbe0/XST_VCC +GND ftop/gbe0/gmac/XST_GND +VCC ftop/gbe0/gmac/XST_VCC +GND ftop/gbe0/gmac/gmac/XST_GND +VCC ftop/gbe0/gmac/gmac/XST_VCC +GND ftop/gbe0/gmac/gmac/rxRS_rxF/XST_GND +VCC ftop/gbe0/gmac/gmac/rxRS_rxRst/XST_VCC +VCC ftop/gbe0/gmac/gmac/txRS_txRst/XST_VCC +GND ftop/gbe0/gmac/rxF/XST_GND +GND ftop/gbe0/gmac/txF/XST_GND +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<0>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<11>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<13>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<16>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<17>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<1>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<22>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<23>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<24>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<25>1 + optimized to 0 +GND ftop/gbe0/mdi_fResponse/XST_GND +GND ftop/gbe0/mdi_rPlayIndex/XST_GND +VCC ftop/gbe0/mdi_rPrescaler/XST_VCC +VCC ftop/gbe0/phyRst/rstSync/XST_VCC +GND ftop/gbewrk/XST_GND +VCC ftop/gbewrk/XST_VCC +GND ftop/gbewrk/wci_wslv_reqF/XST_GND +VCC ftop/gmiixo_rst/XST_VCC +GND ftop/iqadc/XST_GND +VCC ftop/iqadc/XST_VCC +GND ftop/iqadc/adcCore_colGate_sampF/XST_GND +GND ftop/iqadc/adcCore_sampF_memory/XST_GND +VCC ftop/iqadc/adcCore_sampF_memory/XST_VCC +VCC ftop/iqadc/adcCore_sdrRst/XST_VCC +VCC ftop/iqadc/adcCore_spiI_slowReset/XST_VCC +GND ftop/iqadc/wci_wslv_reqF/XST_GND +GND ftop/ledLogic/XST_GND +VCC ftop/ledLogic/XST_VCC +GND ftop/pwrk/XST_GND +VCC ftop/pwrk/XST_VCC +VCC ftop/pwrk/flashC_reqF/XST_VCC +LUT3 ftop/pwrk/i2cC_fResponse/ring_empty_not000111 + optimized to 0 +GND ftop/pwrk/i2cC_rPlayIndex/XST_GND +GND ftop/pwrk/i2cC_rPrescaler/XST_GND +GND ftop/pwrk/wci_wslv_reqF/XST_GND +GND ftop/sma0/XST_GND +VCC ftop/sma0/XST_VCC +GND ftop/sma0/mesgTokenF/XST_GND +GND ftop/sma0/respF_memory/XST_GND +GND ftop/sma0/wci_wslv_reqF/XST_GND +GND ftop/sma0/wsiS_reqFifo/XST_GND +GND ftop/sma1/XST_GND +VCC ftop/sma1/XST_VCC +GND ftop/sma1/mesgTokenF/XST_GND +GND ftop/sma1/respF_memory/XST_GND +GND ftop/sma1/wci_wslv_reqF/XST_GND +GND ftop/sma1/wsiS_reqFifo/XST_GND +LUT2 ftop/eddp0/dpReqF/d0d11 + optimized to 0 +FDSE ftop/eddp0/dpReqF/full_reg + optimized to 1 +LUT3 ftop/eddp0/dpReqF/full_reg_mux00001 + optimized to 1 +LUT2 ftop/eddp0/edpReqF/d0d11 + optimized to 0 +FDSE ftop/eddp0/edpReqF/full_reg + optimized to 1 +LUT3 ftop/eddp0/edpReqF/full_reg_mux00001 + optimized to 1 +LUT2 ftop/eddp1/dpReqF/d0d11 + optimized to 0 +FDSE ftop/eddp1/dpReqF/full_reg + optimized to 1 +LUT3 ftop/eddp1/dpReqF/full_reg_mux00001 + optimized to 1 +LUT2 ftop/eddp1/edpReqF/d0d11 + optimized to 0 +FDSE ftop/eddp1/edpReqF/full_reg + optimized to 1 +LUT3 ftop/eddp1/edpReqF/full_reg_mux00001 + optimized to 1 +LUT2 ftop/edp0/edp_inF/d0d11 + optimized to 0 +FDSE ftop/edp0/edp_inF/full_reg + optimized to 1 +LUT3 ftop/edp0/edp_inF/full_reg_mux00001 + optimized to 1 +LUT2 ftop/emux/fork1_d0F/d0d11 + optimized to 0 +FDSE ftop/emux/fork1_d0F/full_reg + optimized to 1 +LUT3 ftop/emux/fork1_d0F/full_reg_mux00001 + optimized to 1 +LUT2 ftop/emux/fork1_d1F/d0d11 + optimized to 0 +FDSE ftop/emux/fork1_d1F/full_reg + optimized to 1 +LUT3 ftop/emux/fork1_d1F/full_reg_mux00001 + optimized to 1 + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IBUF/IFD | SUSPEND | +| | | | | Strength | Rate | | | Delay | | ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| adc_clkout | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<0> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<1> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<2> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<3> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<4> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<5> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<6> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<7> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<8> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<9> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<10> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<11> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<12> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<13> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<0> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<1> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<2> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<3> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<4> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<5> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<6> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<7> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<8> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<9> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<10> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<11> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<12> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<13> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_sclk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| adc_sen | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| adc_smiso | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_smosi | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<16> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<17> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<18> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<19> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<20> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<21> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<22> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<23> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<24> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<25> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<26> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<27> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<28> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<29> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<30> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<31> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| flash_clk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| flash_csn | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| flash_miso | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| flash_mosi | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| fpga_rstn | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_col | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_crs | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_gtx_clk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_intr | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_led | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| gmii_rstn | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| gmii_rx_clk | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rx_dv | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rx_er | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<0> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<1> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<2> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<3> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<4> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<5> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<6> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<7> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_sysclk | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_tx_en | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_tx_er | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| i2c_scl | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| i2c_sda | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| led<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| led<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| led<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| led<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| led<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| mdio_mdc | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| mdio_mdd | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| sys0_clkn | DIFFSI_NDT | INPUT | LVDS_25 | | | | | 0 / 0 | | +| sys0_clkp | DIFFMI_NDT | INPUT | LVDS_25 | | | | | 0 / 0 | | ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + + No area groups were found in this design. + +---------------------- + +Section 10 - Timing Report +-------------------------- +This design was not run using timing mode. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +No control set information for this architecture. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. diff --git a/rtl/mkBiasWorker16B.v b/rtl/mkBiasWorker16B.v index 9dd62482..44b289cc 100644 --- a/rtl/mkBiasWorker16B.v +++ b/rtl/mkBiasWorker16B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:19 EDT 2012 +// On Mon Sep 24 15:03:32 EDT 2012 // // // Ports: @@ -45,7 +45,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkBiasWorker16B(wciS0_Clk, @@ -543,17 +551,17 @@ module mkBiasWorker16B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h11265, v__h11418, v__h3628, v__h3802, v__h3946; - reg [31 : 0] _theResult____h11402; - wire [127 : 0] x_data__h10151; - wire [31 : 0] rdat__h11492, - rdat__h11592, - rdat__h11606, - rdat__h11614, - rdat__h11620, - rdat__h11634, - rdat__h11642; - wire [15 : 0] x__h11496; + reg [63 : 0] v__h11501, v__h11656, v__h3706, v__h3881, v__h4025; + reg [31 : 0] _theResult____h11640; + wire [127 : 0] x_data__h10386; + wire [31 : 0] rdat__h11730, + rdat__h11830, + rdat__h11844, + rdat__h11852, + rdat__h11858, + rdat__h11872, + rdat__h11880; + wire [15 : 0] x__h11734; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -604,7 +612,7 @@ module mkBiasWorker16B(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -618,7 +626,7 @@ module mkBiasWorker16B(wciS0_Clk, SizedFIFO #(.p1width(32'd169), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wsiS_reqFifo$D_IN), .ENQ(wsiS_reqFifo$ENQ), @@ -628,13 +636,6 @@ module mkBiasWorker16B(wciS0_Clk, .FULL_N(wsiS_reqFifo$FULL_N), .EMPTY_N(wsiS_reqFifo$EMPTY_N)); - // rule RL_wci_cfwr - assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && - wci_wslv_wci_cfwr_pw$whas && - !WILL_FIRE_RL_wci_wslv_ctl_op_start && - !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - // rule RL_wci_wslv_ctl_op_start assign WILL_FIRE_RL_wci_wslv_ctl_op_start = wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && @@ -654,6 +655,13 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_cState == 3'd2 && wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_start && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && @@ -794,7 +802,7 @@ module mkBiasWorker16B(wciS0_Clk, assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h11402 } ; + { 2'd1, _theResult____h11640 } ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = @@ -803,7 +811,7 @@ module mkBiasWorker16B(wciS0_Clk, wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { wsiS_reqFifo$D_OUT[168:152], - x_data__h10151, + x_data__h10386, wsiS_reqFifo$D_OUT[23:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = (wsiM_reqFifo_c_r == 2'd2) ? @@ -1283,15 +1291,15 @@ module mkBiasWorker16B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign rdat__h11492 = hasDebugLogic ? { 16'd0, x__h11496 } : 32'd0 ; - assign rdat__h11592 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11606 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11614 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h11620 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11634 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11642 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign x__h11496 = { wsiS_statusR, wsiM_statusR } ; - assign x_data__h10151 = + assign rdat__h11730 = hasDebugLogic ? { 16'd0, x__h11734 } : 32'd0 ; + assign rdat__h11830 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11844 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11852 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11858 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11872 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11880 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign x__h11734 = { wsiS_statusR, wsiM_statusR } ; + assign x_data__h10386 = { wsiS_reqFifo$D_OUT[151:120] + biasValue, wsiS_reqFifo$D_OUT[119:88] + biasValue, wsiS_reqFifo$D_OUT[87:56] + biasValue, @@ -1299,22 +1307,22 @@ module mkBiasWorker16B(wciS0_Clk, always@(wci_wslv_reqF$D_OUT or biasValue or controlReg or - rdat__h11492 or - rdat__h11592 or - rdat__h11606 or - rdat__h11614 or rdat__h11620 or rdat__h11634 or rdat__h11642) + rdat__h11730 or + rdat__h11830 or + rdat__h11844 or + rdat__h11852 or rdat__h11858 or rdat__h11872 or rdat__h11880) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: _theResult____h11402 = biasValue; - 8'h04: _theResult____h11402 = controlReg; - 8'h20: _theResult____h11402 = rdat__h11492; - 8'h24: _theResult____h11402 = rdat__h11592; - 8'h28: _theResult____h11402 = rdat__h11606; - 8'h2C: _theResult____h11402 = rdat__h11614; - 8'h30: _theResult____h11402 = rdat__h11620; - 8'h34: _theResult____h11402 = rdat__h11634; - 8'h38: _theResult____h11402 = rdat__h11642; - default: _theResult____h11402 = 32'd0; + 8'h0: _theResult____h11640 = biasValue; + 8'h04: _theResult____h11640 = controlReg; + 8'h20: _theResult____h11640 = rdat__h11730; + 8'h24: _theResult____h11640 = rdat__h11830; + 8'h28: _theResult____h11640 = rdat__h11844; + 8'h2C: _theResult____h11640 = rdat__h11852; + 8'h30: _theResult____h11640 = rdat__h11858; + 8'h34: _theResult____h11640 = rdat__h11872; + 8'h38: _theResult____h11640 = rdat__h11880; + default: _theResult____h11640 = 32'd0; endcase end @@ -1322,7 +1330,7 @@ module mkBiasWorker16B(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; @@ -1451,8 +1459,8 @@ module mkBiasWorker16B(wciS0_Clk, wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -1529,97 +1537,97 @@ module mkBiasWorker16B(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_cfwr) - begin - v__h11265 = $time; - #0; - end - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_cfwr) - $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h11265, - wci_wslv_reqF$D_OUT[63:32], - wci_wslv_reqF$D_OUT[67:64], - wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3628 = $time; + v__h3706 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3628, + v__h3706, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_biasValue$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_biasValue$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + begin + v__h11501 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", + v__h11501, + wci_wslv_reqF$D_OUT[63:32], + wci_wslv_reqF$D_OUT[67:64], + wci_wslv_reqF$D_OUT[31:0]); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3946 = $time; + v__h4025 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3946, + v__h4025, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3802 = $time; + v__h3881 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3802, + v__h3881, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h11418 = $time; + v__h11656 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h11418, + v__h11656, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - _theResult____h11402); - if (wciS0_MReset_n) + _theResult____h11640); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue$write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue$write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end diff --git a/rtl/mkBiasWorker32B.v b/rtl/mkBiasWorker32B.v index 940ebf84..44604cf5 100644 --- a/rtl/mkBiasWorker32B.v +++ b/rtl/mkBiasWorker32B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:20 EDT 2012 +// On Mon Sep 24 15:03:34 EDT 2012 // // // Ports: @@ -45,7 +45,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkBiasWorker32B(wciS0_Clk, @@ -543,17 +551,17 @@ module mkBiasWorker32B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h12045, v__h12198, v__h3628, v__h3802, v__h3946; - reg [31 : 0] _theResult____h12182; - wire [255 : 0] x_data__h10151; - wire [31 : 0] rdat__h12272, - rdat__h12372, - rdat__h12386, - rdat__h12394, - rdat__h12400, - rdat__h12414, - rdat__h12422; - wire [15 : 0] x__h12276; + reg [63 : 0] v__h12281, v__h12436, v__h3706, v__h3881, v__h4025; + reg [31 : 0] _theResult____h12420; + wire [255 : 0] x_data__h10386; + wire [31 : 0] rdat__h12510, + rdat__h12610, + rdat__h12624, + rdat__h12632, + rdat__h12638, + rdat__h12652, + rdat__h12660; + wire [15 : 0] x__h12514; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -604,7 +612,7 @@ module mkBiasWorker32B(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -618,7 +626,7 @@ module mkBiasWorker32B(wciS0_Clk, SizedFIFO #(.p1width(32'd313), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wsiS_reqFifo$D_IN), .ENQ(wsiS_reqFifo$ENQ), @@ -628,13 +636,6 @@ module mkBiasWorker32B(wciS0_Clk, .FULL_N(wsiS_reqFifo$FULL_N), .EMPTY_N(wsiS_reqFifo$EMPTY_N)); - // rule RL_wci_cfwr - assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && - wci_wslv_wci_cfwr_pw$whas && - !WILL_FIRE_RL_wci_wslv_ctl_op_start && - !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - // rule RL_wci_wslv_ctl_op_start assign WILL_FIRE_RL_wci_wslv_ctl_op_start = wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && @@ -654,6 +655,13 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_cState == 3'd2 && wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_start && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && @@ -794,7 +802,7 @@ module mkBiasWorker32B(wciS0_Clk, assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h12182 } ; + { 2'd1, _theResult____h12420 } ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = @@ -803,7 +811,7 @@ module mkBiasWorker32B(wciS0_Clk, wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { wsiS_reqFifo$D_OUT[312:296], - x_data__h10151, + x_data__h10386, wsiS_reqFifo$D_OUT[39:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = (wsiM_reqFifo_c_r == 2'd2) ? @@ -1283,15 +1291,15 @@ module mkBiasWorker32B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign rdat__h12272 = hasDebugLogic ? { 16'd0, x__h12276 } : 32'd0 ; - assign rdat__h12372 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h12386 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h12394 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h12400 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h12414 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h12422 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign x__h12276 = { wsiS_statusR, wsiM_statusR } ; - assign x_data__h10151 = + assign rdat__h12510 = hasDebugLogic ? { 16'd0, x__h12514 } : 32'd0 ; + assign rdat__h12610 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h12624 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h12632 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h12638 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h12652 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h12660 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign x__h12514 = { wsiS_statusR, wsiM_statusR } ; + assign x_data__h10386 = { wsiS_reqFifo$D_OUT[295:264] + biasValue, wsiS_reqFifo$D_OUT[263:232] + biasValue, wsiS_reqFifo$D_OUT[231:200] + biasValue, @@ -1303,22 +1311,22 @@ module mkBiasWorker32B(wciS0_Clk, always@(wci_wslv_reqF$D_OUT or biasValue or controlReg or - rdat__h12272 or - rdat__h12372 or - rdat__h12386 or - rdat__h12394 or rdat__h12400 or rdat__h12414 or rdat__h12422) + rdat__h12510 or + rdat__h12610 or + rdat__h12624 or + rdat__h12632 or rdat__h12638 or rdat__h12652 or rdat__h12660) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: _theResult____h12182 = biasValue; - 8'h04: _theResult____h12182 = controlReg; - 8'h20: _theResult____h12182 = rdat__h12272; - 8'h24: _theResult____h12182 = rdat__h12372; - 8'h28: _theResult____h12182 = rdat__h12386; - 8'h2C: _theResult____h12182 = rdat__h12394; - 8'h30: _theResult____h12182 = rdat__h12400; - 8'h34: _theResult____h12182 = rdat__h12414; - 8'h38: _theResult____h12182 = rdat__h12422; - default: _theResult____h12182 = 32'd0; + 8'h0: _theResult____h12420 = biasValue; + 8'h04: _theResult____h12420 = controlReg; + 8'h20: _theResult____h12420 = rdat__h12510; + 8'h24: _theResult____h12420 = rdat__h12610; + 8'h28: _theResult____h12420 = rdat__h12624; + 8'h2C: _theResult____h12420 = rdat__h12632; + 8'h30: _theResult____h12420 = rdat__h12638; + 8'h34: _theResult____h12420 = rdat__h12652; + 8'h38: _theResult____h12420 = rdat__h12660; + default: _theResult____h12420 = 32'd0; endcase end @@ -1326,7 +1334,7 @@ module mkBiasWorker32B(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; @@ -1455,8 +1463,8 @@ module mkBiasWorker32B(wciS0_Clk, wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -1535,97 +1543,97 @@ module mkBiasWorker32B(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_cfwr) - begin - v__h12045 = $time; - #0; - end - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_cfwr) - $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h12045, - wci_wslv_reqF$D_OUT[63:32], - wci_wslv_reqF$D_OUT[67:64], - wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3628 = $time; + v__h3706 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3628, + v__h3706, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_biasValue$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_biasValue$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + begin + v__h12281 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", + v__h12281, + wci_wslv_reqF$D_OUT[63:32], + wci_wslv_reqF$D_OUT[67:64], + wci_wslv_reqF$D_OUT[31:0]); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3946 = $time; + v__h4025 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3946, + v__h4025, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3802 = $time; + v__h3881 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3802, + v__h3881, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h12198 = $time; + v__h12436 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h12198, + v__h12436, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - _theResult____h12182); - if (wciS0_MReset_n) + _theResult____h12420); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue$write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue$write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end diff --git a/rtl/mkBiasWorker4B.v b/rtl/mkBiasWorker4B.v index 5704cc2b..778fb6a2 100644 --- a/rtl/mkBiasWorker4B.v +++ b/rtl/mkBiasWorker4B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:17 EDT 2012 +// On Mon Sep 24 15:03:30 EDT 2012 // // // Ports: @@ -45,7 +45,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkBiasWorker4B(wciS0_Clk, @@ -542,17 +550,17 @@ module mkBiasWorker4B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h10679, v__h10832, v__h3628, v__h3802, v__h3946; - reg [31 : 0] _theResult____h10816; - wire [31 : 0] rdat__h10906, - rdat__h11006, - rdat__h11020, - rdat__h11028, - rdat__h11034, - rdat__h11048, - rdat__h11056, - x_data__h10151; - wire [15 : 0] x__h10910; + reg [63 : 0] v__h10915, v__h11070, v__h3706, v__h3881, v__h4025; + reg [31 : 0] _theResult____h11054; + wire [31 : 0] rdat__h11144, + rdat__h11244, + rdat__h11258, + rdat__h11266, + rdat__h11272, + rdat__h11286, + rdat__h11294, + x_data__h10386; + wire [15 : 0] x__h11148; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -603,7 +611,7 @@ module mkBiasWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -617,7 +625,7 @@ module mkBiasWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd61), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wsiS_reqFifo$D_IN), .ENQ(wsiS_reqFifo$ENQ), @@ -627,13 +635,6 @@ module mkBiasWorker4B(wciS0_Clk, .FULL_N(wsiS_reqFifo$FULL_N), .EMPTY_N(wsiS_reqFifo$EMPTY_N)); - // rule RL_wci_cfwr - assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && - wci_wslv_wci_cfwr_pw$whas && - !WILL_FIRE_RL_wci_wslv_ctl_op_start && - !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - // rule RL_wci_wslv_ctl_op_start assign WILL_FIRE_RL_wci_wslv_ctl_op_start = wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && @@ -653,6 +654,13 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_cState == 3'd2 && wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_start && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && @@ -793,12 +801,12 @@ module mkBiasWorker4B(wciS0_Clk, assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h10816 } ; + { 2'd1, _theResult____h11054 } ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = { wsiS_reqFifo$D_OUT[60:44], - x_data__h10151, + x_data__h10386, wsiS_reqFifo$D_OUT[11:0] } ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = (wsiM_reqFifo_c_r == 2'd1) ? @@ -1281,34 +1289,34 @@ module mkBiasWorker4B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign rdat__h10906 = hasDebugLogic ? { 16'd0, x__h10910 } : 32'd0 ; - assign rdat__h11006 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11020 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11028 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h11034 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11048 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11056 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign x__h10910 = { wsiS_statusR, wsiM_statusR } ; - assign x_data__h10151 = wsiS_reqFifo$D_OUT[43:12] + biasValue ; + assign rdat__h11144 = hasDebugLogic ? { 16'd0, x__h11148 } : 32'd0 ; + assign rdat__h11244 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11258 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11266 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11272 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11286 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11294 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign x__h11148 = { wsiS_statusR, wsiM_statusR } ; + assign x_data__h10386 = wsiS_reqFifo$D_OUT[43:12] + biasValue ; always@(wci_wslv_reqF$D_OUT or biasValue or controlReg or - rdat__h10906 or - rdat__h11006 or - rdat__h11020 or - rdat__h11028 or rdat__h11034 or rdat__h11048 or rdat__h11056) + rdat__h11144 or + rdat__h11244 or + rdat__h11258 or + rdat__h11266 or rdat__h11272 or rdat__h11286 or rdat__h11294) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: _theResult____h10816 = biasValue; - 8'h04: _theResult____h10816 = controlReg; - 8'h20: _theResult____h10816 = rdat__h10906; - 8'h24: _theResult____h10816 = rdat__h11006; - 8'h28: _theResult____h10816 = rdat__h11020; - 8'h2C: _theResult____h10816 = rdat__h11028; - 8'h30: _theResult____h10816 = rdat__h11034; - 8'h34: _theResult____h10816 = rdat__h11048; - 8'h38: _theResult____h10816 = rdat__h11056; - default: _theResult____h10816 = 32'd0; + 8'h0: _theResult____h11054 = biasValue; + 8'h04: _theResult____h11054 = controlReg; + 8'h20: _theResult____h11054 = rdat__h11144; + 8'h24: _theResult____h11054 = rdat__h11244; + 8'h28: _theResult____h11054 = rdat__h11258; + 8'h2C: _theResult____h11054 = rdat__h11266; + 8'h30: _theResult____h11054 = rdat__h11272; + 8'h34: _theResult____h11054 = rdat__h11286; + 8'h38: _theResult____h11054 = rdat__h11294; + default: _theResult____h11054 = 32'd0; endcase end @@ -1316,7 +1324,7 @@ module mkBiasWorker4B(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; @@ -1443,8 +1451,8 @@ module mkBiasWorker4B(wciS0_Clk, wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -1521,97 +1529,97 @@ module mkBiasWorker4B(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_cfwr) - begin - v__h10679 = $time; - #0; - end - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_cfwr) - $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h10679, - wci_wslv_reqF$D_OUT[63:32], - wci_wslv_reqF$D_OUT[67:64], - wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3628 = $time; + v__h3706 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3628, + v__h3706, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_biasValue$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_biasValue$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + begin + v__h10915 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", + v__h10915, + wci_wslv_reqF$D_OUT[63:32], + wci_wslv_reqF$D_OUT[67:64], + wci_wslv_reqF$D_OUT[31:0]); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3946 = $time; + v__h4025 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3946, + v__h4025, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3802 = $time; + v__h3881 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3802, + v__h3881, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h10832 = $time; + v__h11070 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h10832, + v__h11070, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - _theResult____h10816); - if (wciS0_MReset_n) + _theResult____h11054); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue$write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue$write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end diff --git a/rtl/mkBiasWorker8B.v b/rtl/mkBiasWorker8B.v index e0617042..01aba010 100644 --- a/rtl/mkBiasWorker8B.v +++ b/rtl/mkBiasWorker8B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:18 EDT 2012 +// On Mon Sep 24 15:03:31 EDT 2012 // // // Ports: @@ -45,7 +45,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkBiasWorker8B(wciS0_Clk, @@ -541,17 +549,17 @@ module mkBiasWorker8B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h10875, v__h11028, v__h3628, v__h3802, v__h3946; - reg [31 : 0] _theResult____h11012; - wire [63 : 0] x_data__h10151; - wire [31 : 0] rdat__h11102, - rdat__h11202, - rdat__h11216, - rdat__h11224, - rdat__h11230, - rdat__h11244, - rdat__h11252; - wire [15 : 0] x__h11106; + reg [63 : 0] v__h11111, v__h11266, v__h3706, v__h3881, v__h4025; + reg [31 : 0] _theResult____h11250; + wire [63 : 0] x_data__h10386; + wire [31 : 0] rdat__h11340, + rdat__h11440, + rdat__h11454, + rdat__h11462, + rdat__h11468, + rdat__h11482, + rdat__h11490; + wire [15 : 0] x__h11344; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -602,7 +610,7 @@ module mkBiasWorker8B(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -616,7 +624,7 @@ module mkBiasWorker8B(wciS0_Clk, SizedFIFO #(.p1width(32'd97), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wsiS_reqFifo$D_IN), .ENQ(wsiS_reqFifo$ENQ), @@ -626,13 +634,6 @@ module mkBiasWorker8B(wciS0_Clk, .FULL_N(wsiS_reqFifo$FULL_N), .EMPTY_N(wsiS_reqFifo$EMPTY_N)); - // rule RL_wci_cfwr - assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && - wci_wslv_wci_cfwr_pw$whas && - !WILL_FIRE_RL_wci_wslv_ctl_op_start && - !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - // rule RL_wci_wslv_ctl_op_start assign WILL_FIRE_RL_wci_wslv_ctl_op_start = wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && @@ -652,6 +653,13 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_cState == 3'd2 && wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_start && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && @@ -792,7 +800,7 @@ module mkBiasWorker8B(wciS0_Clk, assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h11012 } ; + { 2'd1, _theResult____h11250 } ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = @@ -801,7 +809,7 @@ module mkBiasWorker8B(wciS0_Clk, wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { wsiS_reqFifo$D_OUT[96:80], - x_data__h10151, + x_data__h10386, wsiS_reqFifo$D_OUT[15:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = (wsiM_reqFifo_c_r == 2'd2) ? @@ -1280,36 +1288,36 @@ module mkBiasWorker8B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign rdat__h11102 = hasDebugLogic ? { 16'd0, x__h11106 } : 32'd0 ; - assign rdat__h11202 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11216 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11224 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h11230 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11244 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11252 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign x__h11106 = { wsiS_statusR, wsiM_statusR } ; - assign x_data__h10151 = + assign rdat__h11340 = hasDebugLogic ? { 16'd0, x__h11344 } : 32'd0 ; + assign rdat__h11440 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11454 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11462 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11468 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11482 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11490 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign x__h11344 = { wsiS_statusR, wsiM_statusR } ; + assign x_data__h10386 = { wsiS_reqFifo$D_OUT[79:48] + biasValue, wsiS_reqFifo$D_OUT[47:16] + biasValue } ; always@(wci_wslv_reqF$D_OUT or biasValue or controlReg or - rdat__h11102 or - rdat__h11202 or - rdat__h11216 or - rdat__h11224 or rdat__h11230 or rdat__h11244 or rdat__h11252) + rdat__h11340 or + rdat__h11440 or + rdat__h11454 or + rdat__h11462 or rdat__h11468 or rdat__h11482 or rdat__h11490) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: _theResult____h11012 = biasValue; - 8'h04: _theResult____h11012 = controlReg; - 8'h20: _theResult____h11012 = rdat__h11102; - 8'h24: _theResult____h11012 = rdat__h11202; - 8'h28: _theResult____h11012 = rdat__h11216; - 8'h2C: _theResult____h11012 = rdat__h11224; - 8'h30: _theResult____h11012 = rdat__h11230; - 8'h34: _theResult____h11012 = rdat__h11244; - 8'h38: _theResult____h11012 = rdat__h11252; - default: _theResult____h11012 = 32'd0; + 8'h0: _theResult____h11250 = biasValue; + 8'h04: _theResult____h11250 = controlReg; + 8'h20: _theResult____h11250 = rdat__h11340; + 8'h24: _theResult____h11250 = rdat__h11440; + 8'h28: _theResult____h11250 = rdat__h11454; + 8'h2C: _theResult____h11250 = rdat__h11462; + 8'h30: _theResult____h11250 = rdat__h11468; + 8'h34: _theResult____h11250 = rdat__h11482; + 8'h38: _theResult____h11250 = rdat__h11490; + default: _theResult____h11250 = 32'd0; endcase end @@ -1317,7 +1325,7 @@ module mkBiasWorker8B(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; @@ -1446,8 +1454,8 @@ module mkBiasWorker8B(wciS0_Clk, wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -1524,97 +1532,97 @@ module mkBiasWorker8B(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_cfwr) - begin - v__h10875 = $time; - #0; - end - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_cfwr) - $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h10875, - wci_wslv_reqF$D_OUT[63:32], - wci_wslv_reqF$D_OUT[67:64], - wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3628 = $time; + v__h3706 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3628, + v__h3706, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_biasValue$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_biasValue$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + begin + v__h11111 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", + v__h11111, + wci_wslv_reqF$D_OUT[63:32], + wci_wslv_reqF$D_OUT[67:64], + wci_wslv_reqF$D_OUT[31:0]); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3946 = $time; + v__h4025 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3946, + v__h4025, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3802 = $time; + v__h3881 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3802, + v__h3881, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h11028 = $time; + v__h11266 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h11028, + v__h11266, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - _theResult____h11012); - if (wciS0_MReset_n) + _theResult____h11250); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue$write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue$write_1__SEL_2) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); end diff --git a/rtl/mkEDCPAdapter.v b/rtl/mkEDCPAdapter.v index 4f57766d..b005189b 100644 --- a/rtl/mkEDCPAdapter.v +++ b/rtl/mkEDCPAdapter.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:00 EDT 2012 +// On Mon Sep 24 15:03:09 EDT 2012 // // // Ports: @@ -34,7 +34,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkEDCPAdapter(CLK, @@ -327,15 +335,15 @@ module mkEDCPAdapter(CLK, CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q6, CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q9; reg CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q5; - wire [47 : 0] x__h3792, x__h5523, x__h5564, x__h5619, y__h5585, y__h5630; - wire [31 : 0] bedw__h2286; - wire [15 : 0] x__h5652, x__h5720; - wire [7 : 0] IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d466; - wire [3 : 0] x__h2311; + wire [47 : 0] x__h3828, x__h5559, x__h5600, x__h5655, y__h5621, y__h5666; + wire [31 : 0] bedw__h2322; + wire [15 : 0] x__h5688, x__h5756; + wire [7 : 0] IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465; + wire [3 : 0] x__h2347; wire IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21__ETC___d152, IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23__ETC___d150, - dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454, - dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d455, + dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463, + dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464, dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155, dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23_AND_ETC___d196, eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100, @@ -375,7 +383,7 @@ module mkEDCPAdapter(CLK, assign RDY_ecpTx = 1'd1 ; // submodule cpReqF - FIFO2 #(.width(32'd59), .guarded(32'd1)) cpReqF(.RST_N(RST_N), + FIFO2 #(.width(32'd59), .guarded(32'd1)) cpReqF(.RST(RST_N), .CLK(CLK), .D_IN(cpReqF$D_IN), .ENQ(cpReqF$ENQ), @@ -386,7 +394,7 @@ module mkEDCPAdapter(CLK, .EMPTY_N(cpReqF$EMPTY_N)); // submodule cpRespF - FIFO2 #(.width(32'd40), .guarded(32'd1)) cpRespF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) cpRespF(.RST(RST_N), .CLK(CLK), .D_IN(cpRespF$D_IN), .ENQ(cpRespF$ENQ), @@ -397,7 +405,7 @@ module mkEDCPAdapter(CLK, .EMPTY_N(cpRespF$EMPTY_N)); // submodule dcpReqF - FIFO2 #(.width(32'd79), .guarded(32'd1)) dcpReqF(.RST_N(RST_N), + FIFO2 #(.width(32'd79), .guarded(32'd1)) dcpReqF(.RST(RST_N), .CLK(CLK), .D_IN(dcpReqF$D_IN), .ENQ(dcpReqF$ENQ), @@ -408,7 +416,7 @@ module mkEDCPAdapter(CLK, .EMPTY_N(dcpReqF$EMPTY_N)); // submodule dcpRespF - FIFO2 #(.width(32'd45), .guarded(32'd1)) dcpRespF(.RST_N(RST_N), + FIFO2 #(.width(32'd45), .guarded(32'd1)) dcpRespF(.RST(RST_N), .CLK(CLK), .D_IN(dcpRespF$D_IN), .ENQ(dcpRespF$ENQ), @@ -419,7 +427,7 @@ module mkEDCPAdapter(CLK, .EMPTY_N(dcpRespF$EMPTY_N)); // submodule eMAddrF - FIFO2 #(.width(32'd48), .guarded(32'd1)) eMAddrF(.RST_N(RST_N), + FIFO2 #(.width(32'd48), .guarded(32'd1)) eMAddrF(.RST(RST_N), .CLK(CLK), .D_IN(eMAddrF$D_IN), .ENQ(eMAddrF$ENQ), @@ -430,7 +438,7 @@ module mkEDCPAdapter(CLK, .EMPTY_N(eMAddrF$EMPTY_N)); // submodule ecpReqF - FIFO2 #(.width(32'd40), .guarded(32'd1)) ecpReqF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) ecpReqF(.RST(RST_N), .CLK(CLK), .D_IN(ecpReqF$D_IN), .ENQ(ecpReqF$ENQ), @@ -441,7 +449,7 @@ module mkEDCPAdapter(CLK, .EMPTY_N(ecpReqF$EMPTY_N)); // submodule ecpRespF - FIFO2 #(.width(32'd40), .guarded(32'd1)) ecpRespF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) ecpRespF(.RST(RST_N), .CLK(CLK), .D_IN(ecpRespF$D_IN), .ENQ(ecpRespF$ENQ), @@ -457,12 +465,12 @@ module mkEDCPAdapter(CLK, // rule RL_dcp_to_cp_request assign WILL_FIRE_RL_dcp_to_cp_request = dcpReqF$EMPTY_N && - IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21__ETC___d152 && - !WILL_FIRE_RL_cp_to_dcp_response ; + IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21__ETC___d152 ; // rule RL_cp_to_dcp_response assign WILL_FIRE_RL_cp_to_dcp_response = - dcpRespF$FULL_N && cpRespF$EMPTY_N ; + dcpRespF$FULL_N && cpRespF$EMPTY_N && + !WILL_FIRE_RL_dcp_to_cp_request ; // rule RL_edpFsm_action_l243c16 assign WILL_FIRE_RL_edpFsm_action_l243c16 = @@ -653,20 +661,20 @@ module mkEDCPAdapter(CLK, WILL_FIRE_RL_cp_to_dcp_response ; // register eAddr - assign eAddr$D_IN = bedw__h2286 ; + assign eAddr$D_IN = bedw__h2322 ; assign eAddr$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd5 ; // register eDAddr - assign eDAddr$D_IN = (ptr == 4'd0) ? x__h3792 : x__h5564 ; + assign eDAddr$D_IN = (ptr == 4'd0) ? x__h3828 : x__h5600 ; assign eDAddr$EN = WILL_FIRE_RL_ecp_ingress && (ptr == 4'd0 || ptr == 4'd1) ; // register eDMH - assign eDMH$D_IN = bedw__h2286 ; + assign eDMH$D_IN = bedw__h2322 ; assign eDMH$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd4 ; // register eData - assign eData$D_IN = bedw__h2286 ; + assign eData$D_IN = bedw__h2322 ; assign eData$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd6 ; // register eDoReq @@ -674,16 +682,16 @@ module mkEDCPAdapter(CLK, assign eDoReq$EN = 1'd1 ; // register eMAddr - assign eMAddr$D_IN = (ptr == 4'd1) ? x__h5523 : x__h5619 ; + assign eMAddr$D_IN = (ptr == 4'd1) ? x__h5559 : x__h5655 ; assign eMAddr$EN = WILL_FIRE_RL_ecp_ingress && (ptr == 4'd1 || ptr == 4'd2) ; // register ePli - assign ePli$D_IN = x__h5720 ; + assign ePli$D_IN = x__h5756 ; assign ePli$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd3 ; // register eTyp - assign eTyp$D_IN = x__h5652 ; + assign eTyp$D_IN = x__h5688 ; assign eTyp$EN = WILL_FIRE_RL_ecp_ingress && ptr == 4'd3 ; // register ecpEgress @@ -800,17 +808,17 @@ module mkEDCPAdapter(CLK, (dcpReqF$D_OUT[78:77] == 2'd0 && !dcpReqF$D_OUT[40] || dcpReqF$D_OUT[78:77] != 2'd0 && (dcpReqF$D_OUT[78:77] == 2'd1 && - (!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d455 || + (!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 || !lastTag[8]) && !dcpReqF$D_OUT[76] || dcpReqF$D_OUT[78:77] != 2'd1 && - (!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 || + (!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 || !lastTag[8]) && !dcpReqF$D_OUT[44])) ; // register ptr assign ptr$D_IN = - (x__h2311 == 4'd0) ? ((ptr == 4'd15) ? ptr : ptr + 4'd1) : 4'd0 ; + (x__h2347 == 4'd0) ? ((ptr == 4'd15) ? ptr : ptr + 4'd1) : 4'd0 ; assign ptr$EN = WILL_FIRE_RL_ecp_ingress ; // register uMAddr @@ -941,7 +949,7 @@ module mkEDCPAdapter(CLK, (dcpReqF$D_OUT[78:77] == 2'd0) ? dcpRespF$FULL_N : (dcpReqF$D_OUT[78:77] == 2'd1 || - !dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 || + !dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 || !lastTag[8] || dcpReqF$D_OUT[44] || dcpRespF$FULL_N) && @@ -949,34 +957,34 @@ module mkEDCPAdapter(CLK, assign IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23__ETC___d150 = (dcpReqF$D_OUT[78:77] == 2'd1) ? dcpRespF$FULL_N && - (dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d455 && + (dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 && lastTag[8] && !dcpReqF$D_OUT[76] || cpReqF$FULL_N) : - dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 && + dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 && lastTag[8] && !dcpReqF$D_OUT[44] || cpReqF$FULL_N ; - assign IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d466 = + assign IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465 = dcpRespF$D_OUT[42] ? 8'h70 : 8'h30 ; - assign bedw__h2286 = - { x__h5652, ecpReqF$D_OUT[27:20], ecpReqF$D_OUT[37:30] } ; - assign dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 = + assign bedw__h2322 = + { x__h5688, ecpReqF$D_OUT[27:20], ecpReqF$D_OUT[37:30] } ; + assign dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 = dcpReqF$D_OUT[39:32] == lastTag[7:0] ; - assign dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d455 = + assign dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 = dcpReqF$D_OUT[71:64] == lastTag[7:0] ; assign dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155 = dcpReqF$D_OUT[78:77] == 2'd0 || dcpReqF$D_OUT[78:77] == 2'd1 || - dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 && + dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 && lastTag[8] && !dcpReqF$D_OUT[44] ; assign dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23_AND_ETC___d196 = dcpReqF$D_OUT[78:77] == 2'd1 && - (!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d455 || + (!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d464 || !lastTag[8] || dcpReqF$D_OUT[76]) || dcpReqF$D_OUT[78:77] != 2'd1 && - (!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 || + (!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d463 || !lastTag[8] || dcpReqF$D_OUT[44]) ; assign eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100 = @@ -986,19 +994,19 @@ module mkEDCPAdapter(CLK, edpFsm_state_mkFSMstate == 4'd0 || edpFsm_state_mkFSMstate == 4'd5 || edpFsm_state_mkFSMstate == 4'd7 ; - assign x__h2311 = + assign x__h2347 = { ecpReqF$D_OUT[39:38] != 2'd0, ecpReqF$D_OUT[29:28] != 2'd0, ecpReqF$D_OUT[19:18] != 2'd0, ecpReqF$D_OUT[9:8] != 2'd0 } ; - assign x__h3792 = { bedw__h2286, 16'h0 } ; - assign x__h5523 = { x__h5720, 32'h0 } ; - assign x__h5564 = eDAddr | y__h5585 ; - assign x__h5619 = eMAddr | y__h5630 ; - assign x__h5652 = { ecpReqF$D_OUT[7:0], ecpReqF$D_OUT[17:10] } ; - assign x__h5720 = { ecpReqF$D_OUT[27:20], ecpReqF$D_OUT[37:30] } ; - assign y__h5585 = { 32'h0, x__h5652 } ; - assign y__h5630 = { 16'd0, bedw__h2286 } ; + assign x__h3828 = { bedw__h2322, 16'h0 } ; + assign x__h5559 = { x__h5756, 32'h0 } ; + assign x__h5600 = eDAddr | y__h5621 ; + assign x__h5655 = eMAddr | y__h5666 ; + assign x__h5688 = { ecpReqF$D_OUT[7:0], ecpReqF$D_OUT[17:10] } ; + assign x__h5756 = { ecpReqF$D_OUT[27:20], ecpReqF$D_OUT[37:30] } ; + assign y__h5621 = { 32'h0, x__h5688 } ; + assign y__h5666 = { 16'd0, bedw__h2322 } ; always@(ecpRespF$D_OUT) begin case (ecpRespF$D_OUT[39:38]) @@ -1082,17 +1090,17 @@ module mkEDCPAdapter(CLK, endcase end always@(dcpRespF$D_OUT or - IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d466) + IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465) begin case (dcpRespF$D_OUT[44:43]) 2'd0: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 = - IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d466; + IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465; 2'd1: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 = dcpRespF$D_OUT[10] ? 8'h70 : 8'h30; default: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 = - IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d466; + IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d465; endcase end @@ -1100,7 +1108,7 @@ module mkEDCPAdapter(CLK, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin doInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0; eDoReq <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1193,7 +1201,7 @@ module mkEDCPAdapter(CLK, always@(negedge CLK) begin #0; - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 && (MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 || MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 || @@ -1201,29 +1209,29 @@ module mkEDCPAdapter(CLK, WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16)) $display("Error: \"bsv/eth/EDCP.bsv\", line 237, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l237c14] and\n [RL_edpFsm_action_l238c14, RL_edpFsm_action_l239c14,\n RL_edpFsm_action_l241c16, RL_edpFsm_action_l243c16,\n RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 && (MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 || MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 || WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16)) $display("Error: \"bsv/eth/EDCP.bsv\", line 238, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l238c14] and\n [RL_edpFsm_action_l239c14, RL_edpFsm_action_l241c16,\n RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 && (MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 || WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16)) $display("Error: \"bsv/eth/EDCP.bsv\", line 239, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l239c14] and\n [RL_edpFsm_action_l241c16, RL_edpFsm_action_l243c16,\n RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 && (WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16)) $display("Error: \"bsv/eth/EDCP.bsv\", line 241, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l241c16] and\n [RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edpFsm_action_l243c16 && WILL_FIRE_RL_edpFsm_action_l244c16) $display("Error: \"bsv/eth/EDCP.bsv\", line 243, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l243c16] and\n [RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 && (MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 || MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 || diff --git a/rtl/mkEDDPAdapter.v b/rtl/mkEDDPAdapter.v index 612f7e3a..96a23538 100644 --- a/rtl/mkEDDPAdapter.v +++ b/rtl/mkEDDPAdapter.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:37:54 EDT 2012 +// On Mon Sep 24 15:03:01 EDT 2012 // // // Ports: @@ -42,7 +42,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkEDDPAdapter(CLK, @@ -313,7 +321,7 @@ module mkEDDPAdapter(CLK, CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q22, CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q21, CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q24; - wire [3 : 0] x__h1640; + wire [3 : 0] x__h1670; wire edpFsm_abort_whas__5_AND_edpFsm_abort_wget__6__ETC___d157, igPtr_1_ULE_3___d12; @@ -369,7 +377,7 @@ module mkEDDPAdapter(CLK, assign RDY_edpTxEOP = 1'd1 ; // submodule dpReqF - FIFO2 #(.width(32'd40), .guarded(32'd1)) dpReqF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) dpReqF(.RST(RST_N), .CLK(CLK), .D_IN(dpReqF$D_IN), .ENQ(dpReqF$ENQ), @@ -380,7 +388,7 @@ module mkEDDPAdapter(CLK, .EMPTY_N(dpReqF$EMPTY_N)); // submodule dpRespF - FIFO2 #(.width(32'd40), .guarded(32'd1)) dpRespF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) dpRespF(.RST(RST_N), .CLK(CLK), .D_IN(dpRespF$D_IN), .ENQ(dpRespF$ENQ), @@ -391,7 +399,7 @@ module mkEDDPAdapter(CLK, .EMPTY_N(dpRespF$EMPTY_N)); // submodule edpReqF - FIFO2 #(.width(32'd40), .guarded(32'd1)) edpReqF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) edpReqF(.RST(RST_N), .CLK(CLK), .D_IN(edpReqF$D_IN), .ENQ(edpReqF$ENQ), @@ -402,7 +410,7 @@ module mkEDDPAdapter(CLK, .EMPTY_N(edpReqF$EMPTY_N)); // submodule edpRespF - FIFO2 #(.width(32'd40), .guarded(32'd1)) edpRespF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) edpRespF(.RST(RST_N), .CLK(CLK), .D_IN(edpRespF$D_IN), .ENQ(edpRespF$ENQ), @@ -412,6 +420,10 @@ module mkEDDPAdapter(CLK, .FULL_N(edpRespF$FULL_N), .EMPTY_N(edpRespF$EMPTY_N)); + // rule RL_egress_body + assign WILL_FIRE_RL_egress_body = + edpRespF$FULL_N && dpRespF$EMPTY_N && txPayload ; + // rule RL_edpFsm_action_l91c14 assign WILL_FIRE_RL_edpFsm_action_l91c14 = edpRespF$FULL_N && edpFsm_state_mkFSMstate == 3'd1 && @@ -439,10 +451,6 @@ module mkEDDPAdapter(CLK, edpFsm_state_mkFSMstate == 3'd5) && !WILL_FIRE_RL_egress_body ; - // rule RL_egress_body - assign WILL_FIRE_RL_egress_body = - edpRespF$FULL_N && dpRespF$EMPTY_N && txPayload ; - // rule RL_edpFsm_idle_l89c3 assign WILL_FIRE_RL_edpFsm_idle_l89c3 = !edpFsm_start_reg_1_1$whas && edpFsm_state_mkFSMstate == 3'd5 ; @@ -627,7 +635,7 @@ module mkEDDPAdapter(CLK, // register igPtr assign igPtr$D_IN = - (x__h1640 == 4'd0) ? + (x__h1670 == 4'd0) ? ((igPtr == 4'd15) ? igPtr : igPtr + 4'd1) : 4'd0 ; assign igPtr$EN = edpIngress_1$whas ; @@ -726,7 +734,7 @@ module mkEDDPAdapter(CLK, edpFsm_state_mkFSMstate == 3'd5) && (!edpFsm_start_reg_1 || edpFsm_state_fired) ; assign igPtr_1_ULE_3___d12 = igPtr <= 4'd3 ; - assign x__h1640 = + assign x__h1670 = { edpReqF$D_OUT[39:38] != 2'd0, edpReqF$D_OUT[29:28] != 2'd0, edpReqF$D_OUT[19:18] != 2'd0, @@ -952,7 +960,7 @@ module mkEDDPAdapter(CLK, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin edpEgress <= `BSV_ASSIGNMENT_DELAY 1'd0; edpEgressEOP <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1030,28 +1038,28 @@ module mkEDDPAdapter(CLK, always@(negedge CLK) begin #0; - if (RST_N) - if (WILL_FIRE_RL_edpFsm_action_l90c14 && - (WILL_FIRE_RL_edpFsm_action_l91c14 || - WILL_FIRE_RL_edpFsm_action_l92c14 || - WILL_FIRE_RL_edpFsm_action_l93c14 || - edpFsm_state_mkFSMstate == 3'd4)) - $display("Error: \"bsv/eth/EDDP.bsv\", line 90, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l90c14] and\n [RL_edpFsm_action_l91c14, RL_edpFsm_action_l92c14, RL_edpFsm_action_l93c14,\n RL_edpFsm_action_l94c16] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edpFsm_action_l91c14 && (WILL_FIRE_RL_edpFsm_action_l92c14 || WILL_FIRE_RL_edpFsm_action_l93c14 || edpFsm_state_mkFSMstate == 3'd4)) $display("Error: \"bsv/eth/EDDP.bsv\", line 91, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l91c14] and\n [RL_edpFsm_action_l92c14, RL_edpFsm_action_l93c14, RL_edpFsm_action_l94c16]\n ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edpFsm_action_l92c14 && (WILL_FIRE_RL_edpFsm_action_l93c14 || edpFsm_state_mkFSMstate == 3'd4)) $display("Error: \"bsv/eth/EDDP.bsv\", line 92, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l92c14] and\n [RL_edpFsm_action_l93c14, RL_edpFsm_action_l94c16] ) fired in the same clock\n cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edpFsm_action_l93c14 && edpFsm_state_mkFSMstate == 3'd4) $display("Error: \"bsv/eth/EDDP.bsv\", line 93, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l93c14] and\n [RL_edpFsm_action_l94c16] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_edpFsm_action_l90c14 && + (WILL_FIRE_RL_edpFsm_action_l91c14 || + WILL_FIRE_RL_edpFsm_action_l92c14 || + WILL_FIRE_RL_edpFsm_action_l93c14 || + edpFsm_state_mkFSMstate == 3'd4)) + $display("Error: \"bsv/eth/EDDP.bsv\", line 90, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l90c14] and\n [RL_edpFsm_action_l91c14, RL_edpFsm_action_l92c14, RL_edpFsm_action_l93c14,\n RL_edpFsm_action_l94c16] ) fired in the same clock cycle.\n"); end // synopsys translate_on endmodule // mkEDDPAdapter diff --git a/rtl/mkFTop_n210.v b/rtl/mkFTop_n210.v index 0eccb35b..a3e1298d 100644 --- a/rtl/mkFTop_n210.v +++ b/rtl/mkFTop_n210.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:40:37 EDT 2012 +// On Mon Sep 24 15:05:48 EDT 2012 // // // Ports: @@ -63,7 +63,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkFTop_n210(sys0_clkp, @@ -665,7 +673,7 @@ module mkFTop_n210(sys0_clkp, wire gmiixo_clk$O; // ports of submodule gmiixo_rst - wire gmiixo_rst$OUT_RST_N; + wire gmiixo_rst$OUT_RST; // ports of submodule iqadc wire [66 : 0] iqadc$wtiS0_req; @@ -1354,7 +1362,7 @@ module mkFTop_n210(sys0_clkp, // submodule gbe0 mkGbeQABS #(.hasDebugLogic(1'd1)) gbe0(.CLK_gmii_rx_clk(gmii_rx_clk), .CLK_gmiixo_clk(gmiixo_clk$O), - .RST_N_gmiixo_rst(gmiixo_rst$OUT_RST_N), + .RST_N_gmiixo_rst(gmiixo_rst$OUT_RST), .CLK(clkN210$clkdv_buf), .RST_N(clkN210$clkdv_rstn), .client_response_put(gbe0$client_response_put), @@ -1409,8 +1417,8 @@ module mkFTop_n210(sys0_clkp, // submodule gmiixo_rst SyncResetA #(.RSTDELAY(32'd1)) gmiixo_rst(.CLK(gmiixo_clk$O), - .IN_RST_N(clkN210$clk0_rstn), - .OUT_RST_N(gmiixo_rst$OUT_RST_N)); + .IN_RST(clkN210$clk0_rstn), + .OUT_RST(gmiixo_rst$OUT_RST)); // submodule iqadc mkIQADCWorker #(.hasDebugLogic(1'd1)) iqadc(.CLK_sys0_clk(clkN210$clkdv_buf), @@ -2471,7 +2479,7 @@ module mkFTop_n210(sys0_clkp, always@(posedge clkN210$clkdv_buf) begin - if (!clkN210$clkdv_rstn) + if (clkN210$clkdv_rstn == `BSV_RESET_VALUE) begin dbgReg <= `BSV_ASSIGNMENT_DELAY 32'd0; tog50 <= `BSV_ASSIGNMENT_DELAY 1'd0; diff --git a/rtl/mkGMAC.v b/rtl/mkGMAC.v index e08af7ac..5940eab2 100644 --- a/rtl/mkGMAC.v +++ b/rtl/mkGMAC.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:37:57 EDT 2012 +// On Mon Sep 24 15:03:05 EDT 2012 // // // Ports: @@ -47,7 +47,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkGMAC(CLK_rxClk, @@ -360,7 +368,7 @@ module mkGMAC(CLK_rxClk, wire intr_cc$dD_OUT, intr_cc$sD_IN, intr_cc$sEN; // ports of submodule phyReset - wire phyReset$OUT_RST_N; + wire phyReset$OUT_RST; // ports of submodule rxRS_crc wire [31 : 0] rxRS_crc$complete; @@ -378,7 +386,7 @@ module mkGMAC(CLK_rxClk, wire rxRS_rxOperateS$dD_OUT, rxRS_rxOperateS$sD_IN, rxRS_rxOperateS$sEN; // ports of submodule rxRS_rxRst - wire rxRS_rxRst$OUT_RST_N; + wire rxRS_rxRst$OUT_RST; // ports of submodule txRS_crc wire [31 : 0] txRS_crc$result; @@ -490,7 +498,7 @@ module mkGMAC(CLK_rxClk, wire txRS_txOperateS$dD_OUT, txRS_txOperateS$sD_IN, txRS_txOperateS$sEN; // ports of submodule txRS_txRst - wire txRS_txRst$OUT_RST_N; + wire txRS_txRst$OUT_RST; // ports of submodule txRS_unfBit wire txRS_unfBit$dD_OUT, txRS_unfBit$sD_IN, txRS_unfBit$sEN; @@ -528,11 +536,11 @@ module mkGMAC(CLK_rxClk, MUX_txRS_ifgCnt_value$write_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h12184, v__h6338; + reg [63 : 0] v__h12366, v__h6418; reg [1 : 0] CASE_rxRS_rxFdD_OUT_BITS_9_TO_8_3_0_rxRS_rxF_ETC__q1, CASE_tx_put_BITS_9_TO_8_3_0_tx_put_BITS_9_TO_8_ETC__q2; - wire txRS_lenCnt_value_45_ULT_59___d298, - txRS_preambleCnt_value_19_ULT_7___d296; + wire txRS_lenCnt_value_45_ULT_59___d293, + txRS_preambleCnt_value_19_ULT_7___d291; // oscillator and gates for output clock CLK_gmii_tx_tx_clk assign CLK_gmii_tx_tx_clk = txRS_iobTxClk$Q ; @@ -592,7 +600,7 @@ module mkGMAC(CLK_rxClk, // submodule col_cc SyncBit #(.init(1'd0)) col_cc(.sCLK(CLK), .dCLK(CLK), - .sRST_N(phyReset$OUT_RST_N), + .sRST(phyReset$OUT_RST), .sD_IN(col_cc$sD_IN), .sEN(col_cc$sEN), .dD_OUT()); @@ -600,7 +608,7 @@ module mkGMAC(CLK_rxClk, // submodule crs_cc SyncBit #(.init(1'd0)) crs_cc(.sCLK(CLK), .dCLK(CLK), - .sRST_N(phyReset$OUT_RST_N), + .sRST(phyReset$OUT_RST), .sD_IN(crs_cc$sD_IN), .sEN(crs_cc$sEN), .dD_OUT()); @@ -608,19 +616,19 @@ module mkGMAC(CLK_rxClk, // submodule intr_cc SyncBit #(.init(1'd0)) intr_cc(.sCLK(CLK), .dCLK(CLK), - .sRST_N(phyReset$OUT_RST_N), + .sRST(phyReset$OUT_RST), .sD_IN(intr_cc$sD_IN), .sEN(intr_cc$sEN), .dD_OUT(intr_cc$dD_OUT)); // submodule phyReset SyncResetA #(.RSTDELAY(32'd7)) phyReset(.CLK(CLK), - .IN_RST_N(RST_N), - .OUT_RST_N(phyReset$OUT_RST_N)); + .IN_RST(RST_N), + .OUT_RST(phyReset$OUT_RST)); // submodule rxRS_crc mkCRC32 rxRS_crc(.CLK(CLK_rxClk), - .RST_N(rxRS_rxRst$OUT_RST_N), + .RST_N(rxRS_rxRst$OUT_RST), .add_data(rxRS_crc$add_data), .EN_add(rxRS_crc$EN_add), .EN_clear(rxRS_crc$EN_clear), @@ -635,7 +643,7 @@ module mkGMAC(CLK_rxClk, // submodule rxRS_ovfBit SyncBit #(.init(1'd0)) rxRS_ovfBit(.sCLK(CLK_rxClk), .dCLK(CLK), - .sRST_N(rxRS_rxRst$OUT_RST_N), + .sRST(rxRS_rxRst$OUT_RST), .sD_IN(rxRS_ovfBit$sD_IN), .sEN(rxRS_ovfBit$sEN), .dD_OUT(rxRS_ovfBit$dD_OUT)); @@ -645,7 +653,7 @@ module mkGMAC(CLK_rxClk, .depth(32'd8), .indxWidth(32'd3)) rxRS_rxF(.sCLK(CLK_rxClk), .dCLK(CLK), - .sRST_N(rxRS_rxRst$OUT_RST_N), + .sRST(rxRS_rxRst$OUT_RST), .sD_IN(rxRS_rxF$sD_IN), .sENQ(rxRS_rxF$sENQ), .dDEQ(rxRS_rxF$dDEQ), @@ -656,19 +664,19 @@ module mkGMAC(CLK_rxClk, // submodule rxRS_rxOperateS SyncBit #(.init(1'd0)) rxRS_rxOperateS(.sCLK(CLK), .dCLK(CLK_rxClk), - .sRST_N(RST_N), + .sRST(RST_N), .sD_IN(rxRS_rxOperateS$sD_IN), .sEN(rxRS_rxOperateS$sEN), .dD_OUT(rxRS_rxOperateS$dD_OUT)); // submodule rxRS_rxRst SyncResetA #(.RSTDELAY(32'd1)) rxRS_rxRst(.CLK(CLK_rxClk), - .IN_RST_N(RST_N), - .OUT_RST_N(rxRS_rxRst$OUT_RST_N)); + .IN_RST(RST_N), + .OUT_RST(rxRS_rxRst$OUT_RST)); // submodule txRS_crc mkCRC32 txRS_crc(.CLK(CLK_txClk), - .RST_N(txRS_txRst$OUT_RST_N), + .RST_N(txRS_txRst$OUT_RST), .add_data(txRS_crc$add_data), .EN_add(txRS_crc$EN_add), .EN_clear(txRS_crc$EN_clear), @@ -699,7 +707,7 @@ module mkGMAC(CLK_rxClk, .CLK_OUT(txRS_iobTxClk_cdi$CLK_OUT)); // submodule txRS_iobTxClk_reset - ResetInverter txRS_iobTxClk_reset(.RESET_IN(txRS_txRst$OUT_RST_N), + ResetInverter txRS_iobTxClk_reset(.RESET_IN(txRS_txRst$OUT_RST), .RESET_OUT(txRS_iobTxClk_reset$RESET_OUT)); // submodule txRS_iobTxData @@ -804,7 +812,7 @@ module mkGMAC(CLK_rxClk, .CLK_OUT(txRS_iobTxData_cdi$CLK_OUT)); // submodule txRS_iobTxData_reset - ResetInverter txRS_iobTxData_reset(.RESET_IN(txRS_txRst$OUT_RST_N), + ResetInverter txRS_iobTxData_reset(.RESET_IN(txRS_txRst$OUT_RST), .RESET_OUT(txRS_iobTxData_reset$RESET_OUT)); // submodule txRS_iobTxEna @@ -825,7 +833,7 @@ module mkGMAC(CLK_rxClk, .CLK_OUT(txRS_iobTxEna_cdi$CLK_OUT)); // submodule txRS_iobTxEna_reset - ResetInverter txRS_iobTxEna_reset(.RESET_IN(txRS_txRst$OUT_RST_N), + ResetInverter txRS_iobTxEna_reset(.RESET_IN(txRS_txRst$OUT_RST), .RESET_OUT(txRS_iobTxEna_reset$RESET_OUT)); // submodule txRS_iobTxErr @@ -846,7 +854,7 @@ module mkGMAC(CLK_rxClk, .CLK_OUT(txRS_iobTxErr_cdi$CLK_OUT)); // submodule txRS_iobTxErr_reset - ResetInverter txRS_iobTxErr_reset(.RESET_IN(txRS_txRst$OUT_RST_N), + ResetInverter txRS_iobTxErr_reset(.RESET_IN(txRS_txRst$OUT_RST), .RESET_OUT(txRS_iobTxErr_reset$RESET_OUT)); // submodule txRS_txF @@ -854,7 +862,7 @@ module mkGMAC(CLK_rxClk, .depth(32'd16), .indxWidth(32'd4)) txRS_txF(.sCLK(CLK), .dCLK(CLK_txClk), - .sRST_N(RST_N), + .sRST(RST_N), .sD_IN(txRS_txF$sD_IN), .sENQ(txRS_txF$sENQ), .dDEQ(txRS_txF$dDEQ), @@ -865,20 +873,20 @@ module mkGMAC(CLK_rxClk, // submodule txRS_txOperateS SyncBit #(.init(1'd0)) txRS_txOperateS(.sCLK(CLK), .dCLK(CLK_txClk), - .sRST_N(RST_N), + .sRST(RST_N), .sD_IN(txRS_txOperateS$sD_IN), .sEN(txRS_txOperateS$sEN), .dD_OUT(txRS_txOperateS$dD_OUT)); // submodule txRS_txRst SyncResetA #(.RSTDELAY(32'd1)) txRS_txRst(.CLK(CLK_txClk), - .IN_RST_N(RST_N), - .OUT_RST_N(txRS_txRst$OUT_RST_N)); + .IN_RST(RST_N), + .OUT_RST(txRS_txRst$OUT_RST)); // submodule txRS_unfBit SyncBit #(.init(1'd0)) txRS_unfBit(.sCLK(CLK_txClk), .dCLK(CLK), - .sRST_N(txRS_txRst$OUT_RST_N), + .sRST(txRS_txRst$OUT_RST), .sD_IN(txRS_unfBit$sD_IN), .sEN(txRS_unfBit$sEN), .dD_OUT(txRS_unfBit$dD_OUT)); @@ -917,7 +925,7 @@ module mkGMAC(CLK_rxClk, // rule RL_txRS_egress_SOF assign CAN_FIRE_RL_txRS_egress_SOF = txRS_txF$dEMPTY_N && - (txRS_preambleCnt_value_19_ULT_7___d296 || + (txRS_preambleCnt_value_19_ULT_7___d291 || txRS_preambleCnt_value == 5'd7 || txRS_txF$dEMPTY_N) && txRS_txOperateS$dD_OUT && @@ -938,7 +946,7 @@ module mkGMAC(CLK_rxClk, // rule RL_txRS_egress_EOF assign CAN_FIRE_RL_txRS_egress_EOF = txRS_txF$dEMPTY_N && - (txRS_lenCnt_value_45_ULT_59___d298 || txRS_txF$dEMPTY_N) && + (txRS_lenCnt_value_45_ULT_59___d293 || txRS_txF$dEMPTY_N) && txRS_txOperateS$dD_OUT && txRS_txActive && txRS_txF$dD_OUT[9:8] == 2'd1 ; @@ -954,13 +962,13 @@ module mkGMAC(CLK_rxClk, WILL_FIRE_RL_rxRS_ingress_noadvance && rxRS_rxActive ; assign MUX_txRS_crc$add_1__SEL_1 = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d291 && txRS_preambleCnt_value != 5'd7 ; assign MUX_txRS_crcDbgCnt_value$write_1__SEL_1 = WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd4 ; assign MUX_txRS_emitFCS$write_1__SEL_1 = WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d298 ; + !txRS_lenCnt_value_45_ULT_59___d293 ; assign MUX_txRS_ifgCnt_value$write_1__SEL_1 = WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd1 ; assign MUX_rxRS_crcDbgCnt_value$write_1__VAL_1 = @@ -1014,7 +1022,7 @@ module mkGMAC(CLK_rxClk, endcase end assign MUX_txRS_txData_1$wset_1__VAL_4 = - txRS_preambleCnt_value_19_ULT_7___d296 ? + txRS_preambleCnt_value_19_ULT_7___d291 ? 8'd85 : ((txRS_preambleCnt_value == 5'd7) ? 8'd213 : @@ -1071,7 +1079,7 @@ module mkGMAC(CLK_rxClk, txRS_txOperateS$dD_OUT && txRS_ifgCnt_value != 5'h0 ; assign txRS_lenCnt_incAction$whas = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d291 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_Body || WILL_FIRE_RL_txRS_egress_EOF || @@ -1079,7 +1087,7 @@ module mkGMAC(CLK_rxClk, assign txRS_lenCnt_decAction$whas = 1'b0 ; assign txRS_crcDbgCnt_incAction$whas = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d291 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_Body || WILL_FIRE_RL_txRS_egress_EOF ; @@ -1176,7 +1184,7 @@ module mkGMAC(CLK_rxClk, txRS_crcDbgCnt_incAction$whas && !WILL_FIRE_RL_txRS_egress_FCS ; // register txRS_doPad - assign txRS_doPad$D_IN = txRS_lenCnt_value_45_ULT_59___d298 ; + assign txRS_doPad$D_IN = txRS_lenCnt_value_45_ULT_59___d293 ; assign txRS_doPad$EN = WILL_FIRE_RL_txRS_egress_EOF ; // register txRS_emitFCS @@ -1186,7 +1194,7 @@ module mkGMAC(CLK_rxClk, MUX_txRS_emitFCS$write_1__VAL_2 ; assign txRS_emitFCS$EN = WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d298 || + !txRS_lenCnt_value_45_ULT_59___d293 || WILL_FIRE_RL_txRS_egress_FCS ; // register txRS_ifgCnt_value @@ -1202,7 +1210,7 @@ module mkGMAC(CLK_rxClk, assign txRS_isSOF$D_IN = !MUX_txRS_crc$add_1__SEL_1 ; assign txRS_isSOF$EN = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d291 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd1 ; @@ -1228,7 +1236,7 @@ module mkGMAC(CLK_rxClk, assign txRS_txActive$D_IN = !MUX_txRS_emitFCS$write_1__SEL_1 ; assign txRS_txActive$EN = WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d298 || + !txRS_lenCnt_value_45_ULT_59___d293 || WILL_FIRE_RL_txRS_egress_SOF ; // register txRS_txDV @@ -1302,7 +1310,7 @@ module mkGMAC(CLK_rxClk, MUX_txRS_crc$add_1__VAL_2 ; assign txRS_crc$EN_add = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d291 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_EOF || WILL_FIRE_RL_txRS_egress_Body ; @@ -1376,10 +1384,10 @@ module mkGMAC(CLK_rxClk, assign txRS_txF$sENQ = EN_tx_put ; assign txRS_txF$dDEQ = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d291 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d298 || + !txRS_lenCnt_value_45_ULT_59___d293 || WILL_FIRE_RL_txRS_egress_Body ; // submodule txRS_txOperateS @@ -1394,8 +1402,8 @@ module mkGMAC(CLK_rxClk, assign txRS_unfBit$sEN = txRS_txOperateS$dD_OUT ; // remaining internal signals - assign txRS_lenCnt_value_45_ULT_59___d298 = txRS_lenCnt_value < 12'd59 ; - assign txRS_preambleCnt_value_19_ULT_7___d296 = + assign txRS_lenCnt_value_45_ULT_59___d293 = txRS_lenCnt_value < 12'd59 ; + assign txRS_preambleCnt_value_19_ULT_7___d291 = txRS_preambleCnt_value < 5'd7 ; always@(rxRS_rxF$dD_OUT) begin @@ -1420,7 +1428,7 @@ module mkGMAC(CLK_rxClk, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin gmacLED <= `BSV_ASSIGNMENT_DELAY 1'd0; rxRS_rxOperateD <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1438,7 +1446,7 @@ module mkGMAC(CLK_rxClk, always@(posedge CLK_rxClk) begin - if (!rxRS_rxRst$OUT_RST_N) + if (rxRS_rxRst$OUT_RST == `BSV_RESET_VALUE) begin rxRS_crcDbgCnt_value <= `BSV_ASSIGNMENT_DELAY 12'd0; rxRS_crcEnd <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1483,7 +1491,7 @@ module mkGMAC(CLK_rxClk, always@(posedge CLK_txClk) begin - if (!txRS_txRst$OUT_RST_N) + if (txRS_txRst$OUT_RST == `BSV_RESET_VALUE) begin txRS_crcDbgCnt_value <= `BSV_ASSIGNMENT_DELAY 12'd0; txRS_doPad <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1573,16 +1581,16 @@ module mkGMAC(CLK_rxClk, always@(negedge CLK_rxClk) begin #0; - if (rxRS_rxRst$OUT_RST_N) + if (rxRS_rxRst$OUT_RST != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rxRS_ingress_noadvance) begin - v__h6338 = $time; + v__h6418 = $time; #0; end - if (rxRS_rxRst$OUT_RST_N) + if (rxRS_rxRst$OUT_RST != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rxRS_ingress_noadvance) $display("[%0d]: %m: RX FCS:%08x from %d elements", - v__h6338, + v__h6418, rxRS_crc$complete, $unsigned(rxRS_crcDbgCnt_value)); end @@ -1592,16 +1600,16 @@ module mkGMAC(CLK_rxClk, always@(negedge CLK_txClk) begin #0; - if (txRS_txRst$OUT_RST_N) + if (txRS_txRst$OUT_RST != `BSV_RESET_VALUE) if (WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd4) begin - v__h12184 = $time; + v__h12366 = $time; #0; end - if (txRS_txRst$OUT_RST_N) + if (txRS_txRst$OUT_RST != `BSV_RESET_VALUE) if (WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd4) $display("[%0d]: %m: TX FCS:%08x from %d elements", - v__h12184, + v__h12366, { txRS_crc$result[7:0], txRS_crc$result[15:8], txRS_crc$result[23:16], diff --git a/rtl/mkGbeQABS.v b/rtl/mkGbeQABS.v index 1b10db22..2ad7bfb6 100644 --- a/rtl/mkGbeQABS.v +++ b/rtl/mkGbeQABS.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:39 EDT 2012 +// On Mon Sep 24 15:03:55 EDT 2012 // // // Ports: @@ -45,7 +45,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkGbeQABS(CLK_gmii_rx_clk, @@ -411,7 +419,7 @@ module mkGbeQABS(CLK_gmii_rx_clk, wire mdi_tMDD$IO, mdi_tMDD$O; // ports of submodule phyRst - wire phyRst$ASSERT_IN, phyRst$OUT_RST_N; + wire phyRst$ASSERT_IN, phyRst$OUT_RST; // rule scheduling signals wire WILL_FIRE_RL_mdi_run_frame; @@ -438,35 +446,35 @@ module mkGbeQABS(CLK_gmii_rx_clk, CASE_gmacrx_get_BITS_9_TO_8_3_0_gmacrx_get_B_ETC__q12; wire [194 : 0] _1434766110945527031733894725304609466537681244_ETC__q17, _643371375338640__q18, - bs__h14890, - bs__h2365; - wire [15 : 0] x_data__h18088; - wire [2 : 0] d0__h1991, - d10__h1981, - d11__h1980, - d12__h1979, - d13__h1978, - d14__h1977, - d15__h1976, - d1__h1990, - d2__h1989, - d3__h1988, - d4__h1987, - d5__h1986, - d6__h1985, - d7__h1984, - d8__h1983, - d9__h1982, - pa0__h1968, - pa1__h1967, - pa2__h1966, - pa3__h1965, - pa4__h1964, - ra0__h1974, - ra1__h1973, - ra2__h1972, - ra3__h1971, - ra4__h1970; + bs__h14970, + bs__h2445; + wire [15 : 0] x_data__h18168; + wire [2 : 0] d0__h2071, + d10__h2061, + d11__h2060, + d12__h2059, + d13__h2058, + d14__h2057, + d15__h2056, + d1__h2070, + d2__h2069, + d3__h2068, + d4__h2067, + d5__h2066, + d6__h2065, + d7__h2064, + d8__h2063, + d9__h2062, + pa0__h2048, + pa1__h2047, + pa2__h2046, + pa3__h2045, + pa4__h2044, + ra0__h2054, + ra1__h2053, + ra2__h2052, + ra3__h2051, + ra4__h2050; // oscillator and gates for output clock CLK_gmii_tx_tx_clk assign CLK_gmii_tx_tx_clk = gmac$CLK_gmii_tx_tx_clk ; @@ -477,7 +485,7 @@ module mkGbeQABS(CLK_gmii_rx_clk, assign CLK_GATE_rxclkBnd = 1'b1 ; // output resets - assign RST_N_gmii_rstn = phyRst$OUT_RST_N ; + assign RST_N_gmii_rstn = phyRst$OUT_RST ; // actionvalue method client_request_get assign client_request_get = @@ -515,7 +523,7 @@ module mkGbeQABS(CLK_gmii_rx_clk, assign gmii_led = gmac$gmii_led ; // submodule eReqF - FIFO2 #(.width(32'd40), .guarded(32'd1)) eReqF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) eReqF(.RST(RST_N), .CLK(CLK), .D_IN(eReqF$D_IN), .ENQ(eReqF$ENQ), @@ -526,7 +534,7 @@ module mkGbeQABS(CLK_gmii_rx_clk, .EMPTY_N(eReqF$EMPTY_N)); // submodule eRespF - FIFO2 #(.width(32'd40), .guarded(32'd1)) eRespF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) eRespF(.RST(RST_N), .CLK(CLK), .D_IN(eRespF$D_IN), .ENQ(eRespF$ENQ), @@ -574,7 +582,7 @@ module mkGbeQABS(CLK_gmii_rx_clk, .CLK_GATE_rxclkBnd()); // submodule mdi_fRequest - FIFO2 #(.width(32'd27), .guarded(32'd1)) mdi_fRequest(.RST_N(RST_N), + FIFO2 #(.width(32'd27), .guarded(32'd1)) mdi_fRequest(.RST(RST_N), .CLK(CLK), .D_IN(mdi_fRequest$D_IN), .ENQ(mdi_fRequest$ENQ), @@ -585,7 +593,7 @@ module mkGbeQABS(CLK_gmii_rx_clk, .EMPTY_N(mdi_fRequest$EMPTY_N)); // submodule mdi_fResponse - FIFO2 #(.width(32'd17), .guarded(32'd1)) mdi_fResponse(.RST_N(RST_N), + FIFO2 #(.width(32'd17), .guarded(32'd1)) mdi_fResponse(.RST(RST_N), .CLK(CLK), .D_IN(mdi_fResponse$D_IN), .ENQ(mdi_fResponse$ENQ), @@ -597,7 +605,7 @@ module mkGbeQABS(CLK_gmii_rx_clk, // submodule mdi_rPlayIndex Counter #(.width(32'd8), .init(8'd0)) mdi_rPlayIndex(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DATA_A(mdi_rPlayIndex$DATA_A), .DATA_B(mdi_rPlayIndex$DATA_B), .DATA_C(mdi_rPlayIndex$DATA_C), @@ -610,7 +618,7 @@ module mkGbeQABS(CLK_gmii_rx_clk, // submodule mdi_rPrescaler Counter #(.width(32'd4), .init(4'd6)) mdi_rPrescaler(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DATA_A(mdi_rPrescaler$DATA_A), .DATA_B(mdi_rPrescaler$DATA_B), .DATA_C(mdi_rPrescaler$DATA_C), @@ -635,11 +643,11 @@ module mkGbeQABS(CLK_gmii_rx_clk, // submodule phyRst MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) phyRst(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(phyRst$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(phyRst$OUT_RST_N)); + .OUT_RST(phyRst$OUT_RST)); // rule RL_mdi_run_frame assign WILL_FIRE_RL_mdi_run_frame = @@ -678,11 +686,11 @@ module mkGbeQABS(CLK_gmii_rx_clk, assign mdi_rMDC$EN = WILL_FIRE_RL_mdi_run_frame ; // register mdi_rMDD - assign mdi_rMDD$D_IN = bs__h2365[mdi_rPlayIndex$Q_OUT] ; + assign mdi_rMDD$D_IN = bs__h2445[mdi_rPlayIndex$Q_OUT] ; assign mdi_rMDD$EN = WILL_FIRE_RL_mdi_run_frame ; // register mdi_rOutEn - assign mdi_rOutEn$D_IN = bs__h14890[mdi_rPlayIndex$Q_OUT] ; + assign mdi_rOutEn$D_IN = bs__h14970[mdi_rPlayIndex$Q_OUT] ; assign mdi_rOutEn$EN = WILL_FIRE_RL_mdi_run_frame ; // register mdi_rPhyAddr @@ -910,7 +918,7 @@ module mkGbeQABS(CLK_gmii_rx_clk, assign mdi_fRequest$CLR = 1'b0 ; // submodule mdi_fResponse - assign mdi_fResponse$D_IN = { 1'd1, x_data__h18088 } ; + assign mdi_fResponse$D_IN = { 1'd1, x_data__h18168 } ; assign mdi_fResponse$ENQ = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT == 8'd0 && !mdi_rWrite ; @@ -945,69 +953,69 @@ module mkGbeQABS(CLK_gmii_rx_clk, 195'h2492492492492492492492492492492492492492492492492 ; assign _643371375338640__q18 = 195'h0000000000000000000000000000000000002492492492490 ; - assign bs__h14890 = + assign bs__h14970 = mdi_rWrite ? 195'h7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8 : 195'h7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000000 ; - assign bs__h2365 = + assign bs__h2445 = { mdi_rWrite ? 108'hFFFFFFFFFFFFFFFFFFFFFFFF1C7 : 108'hFFFFFFFFFFFFFFFFFFFFFFFF1F8, - pa4__h1964, - pa3__h1965, - pa2__h1966, - pa1__h1967, - pa0__h1968, - ra4__h1970, - ra3__h1971, - ra2__h1972, - ra1__h1973, - ra0__h1974, + pa4__h2044, + pa3__h2045, + pa2__h2046, + pa1__h2047, + pa0__h2048, + ra4__h2050, + ra3__h2051, + ra2__h2052, + ra1__h2053, + ra0__h2054, 6'd56, - d15__h1976, - d14__h1977, - d13__h1978, - d12__h1979, - d11__h1980, - d10__h1981, - d9__h1982, - d8__h1983, - d7__h1984, - d6__h1985, - d5__h1986, - d4__h1987, - d3__h1988, - d2__h1989, - d1__h1990, - d0__h1991, + d15__h2056, + d14__h2057, + d13__h2058, + d12__h2059, + d11__h2060, + d10__h2061, + d9__h2062, + d8__h2063, + d7__h2064, + d6__h2065, + d5__h2066, + d4__h2067, + d3__h2068, + d2__h2069, + d1__h2070, + d0__h2071, 3'b111 } ; - assign d0__h1991 = {3{mdi_rWriteData[0]}} ; - assign d10__h1981 = {3{mdi_rWriteData[10]}} ; - assign d11__h1980 = {3{mdi_rWriteData[11]}} ; - assign d12__h1979 = {3{mdi_rWriteData[12]}} ; - assign d13__h1978 = {3{mdi_rWriteData[13]}} ; - assign d14__h1977 = {3{mdi_rWriteData[14]}} ; - assign d15__h1976 = {3{mdi_rWriteData[15]}} ; - assign d1__h1990 = {3{mdi_rWriteData[1]}} ; - assign d2__h1989 = {3{mdi_rWriteData[2]}} ; - assign d3__h1988 = {3{mdi_rWriteData[3]}} ; - assign d4__h1987 = {3{mdi_rWriteData[4]}} ; - assign d5__h1986 = {3{mdi_rWriteData[5]}} ; - assign d6__h1985 = {3{mdi_rWriteData[6]}} ; - assign d7__h1984 = {3{mdi_rWriteData[7]}} ; - assign d8__h1983 = {3{mdi_rWriteData[8]}} ; - assign d9__h1982 = {3{mdi_rWriteData[9]}} ; - assign pa0__h1968 = {3{mdi_rPhyAddr[0]}} ; - assign pa1__h1967 = {3{mdi_rPhyAddr[1]}} ; - assign pa2__h1966 = {3{mdi_rPhyAddr[2]}} ; - assign pa3__h1965 = {3{mdi_rPhyAddr[3]}} ; - assign pa4__h1964 = {3{mdi_rPhyAddr[4]}} ; - assign ra0__h1974 = {3{mdi_rRegAddr[0]}} ; - assign ra1__h1973 = {3{mdi_rRegAddr[1]}} ; - assign ra2__h1972 = {3{mdi_rRegAddr[2]}} ; - assign ra3__h1971 = {3{mdi_rRegAddr[3]}} ; - assign ra4__h1970 = {3{mdi_rRegAddr[4]}} ; - assign x_data__h18088 = + assign d0__h2071 = {3{mdi_rWriteData[0]}} ; + assign d10__h2061 = {3{mdi_rWriteData[10]}} ; + assign d11__h2060 = {3{mdi_rWriteData[11]}} ; + assign d12__h2059 = {3{mdi_rWriteData[12]}} ; + assign d13__h2058 = {3{mdi_rWriteData[13]}} ; + assign d14__h2057 = {3{mdi_rWriteData[14]}} ; + assign d15__h2056 = {3{mdi_rWriteData[15]}} ; + assign d1__h2070 = {3{mdi_rWriteData[1]}} ; + assign d2__h2069 = {3{mdi_rWriteData[2]}} ; + assign d3__h2068 = {3{mdi_rWriteData[3]}} ; + assign d4__h2067 = {3{mdi_rWriteData[4]}} ; + assign d5__h2066 = {3{mdi_rWriteData[5]}} ; + assign d6__h2065 = {3{mdi_rWriteData[6]}} ; + assign d7__h2064 = {3{mdi_rWriteData[7]}} ; + assign d8__h2063 = {3{mdi_rWriteData[8]}} ; + assign d9__h2062 = {3{mdi_rWriteData[9]}} ; + assign pa0__h2048 = {3{mdi_rPhyAddr[0]}} ; + assign pa1__h2047 = {3{mdi_rPhyAddr[1]}} ; + assign pa2__h2046 = {3{mdi_rPhyAddr[2]}} ; + assign pa3__h2045 = {3{mdi_rPhyAddr[3]}} ; + assign pa4__h2044 = {3{mdi_rPhyAddr[4]}} ; + assign ra0__h2054 = {3{mdi_rRegAddr[0]}} ; + assign ra1__h2053 = {3{mdi_rRegAddr[1]}} ; + assign ra2__h2052 = {3{mdi_rRegAddr[2]}} ; + assign ra3__h2051 = {3{mdi_rRegAddr[3]}} ; + assign ra4__h2050 = {3{mdi_rRegAddr[4]}} ; + assign x_data__h18168 = { mdi_vrReadData_15, mdi_vrReadData_14, mdi_vrReadData_13, @@ -1173,7 +1181,7 @@ module mkGbeQABS(CLK_gmii_rx_clk, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin ethEgress <= `BSV_ASSIGNMENT_DELAY 1'd0; ethIngress <= `BSV_ASSIGNMENT_DELAY 1'd0; diff --git a/rtl/mkGbeWrk.v b/rtl/mkGbeWrk.v index 67bd9192..329b5430 100644 --- a/rtl/mkGbeWrk.v +++ b/rtl/mkGbeWrk.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:14 EDT 2012 +// On Mon Sep 24 15:03:26 EDT 2012 // // // Ports: @@ -30,7 +30,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkGbeWrk(wciS0_Clk, @@ -255,8 +263,8 @@ module mkGbeWrk(wciS0_Clk, MUX_wci_wslv_respF_q_1$write_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h3618, v__h3792, v__h3936; - reg [31 : 0] g_data__h5125; + reg [63 : 0] v__h3696, v__h3871, v__h4015; + reg [31 : 0] g_data__h5221; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -290,7 +298,7 @@ module mkGbeWrk(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -421,7 +429,7 @@ module mkGbeWrk(wciS0_Clk, 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h5125 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h5221 } ; // inlined wires assign wci_wslv_wciReq$wget = @@ -625,11 +633,11 @@ module mkGbeWrk(wciS0_Clk, always@(wci_wslv_reqF$D_OUT or ctlReg or dgdpEgressCnt_arg or r10 or r14) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h5125 = ctlReg; - 8'h0C: g_data__h5125 = dgdpEgressCnt_arg; - 8'h10: g_data__h5125 = r10; - 8'h14: g_data__h5125 = r14; - default: g_data__h5125 = 32'd0; + 8'h0: g_data__h5221 = ctlReg; + 8'h0C: g_data__h5221 = dgdpEgressCnt_arg; + 8'h10: g_data__h5221 = r10; + 8'h14: g_data__h5221 = r14; + default: g_data__h5221 = 32'd0; endcase end @@ -637,7 +645,7 @@ module mkGbeWrk(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin r10 <= `BSV_ASSIGNMENT_DELAY 32'd0; r14 <= `BSV_ASSIGNMENT_DELAY 32'd0; @@ -690,8 +698,8 @@ module mkGbeWrk(wciS0_Clk, if (ctlReg$EN) ctlReg <= `BSV_ASSIGNMENT_DELAY ctlReg$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; end @@ -733,70 +741,70 @@ module mkGbeWrk(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3618 = $time; + v__h3696 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3618, + v__h3696, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/eth/GbeWrk.bsv\", line 43, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/eth/GbeWrk.bsv\", line 43, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/eth/GbeWrk.bsv\", line 43, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/eth/GbeWrk.bsv\", line 43, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/eth/GbeWrk.bsv\", line 43, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/eth/GbeWrk.bsv\", line 43, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/eth/GbeWrk.bsv\", line 43, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/eth/GbeWrk.bsv\", line 43, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/eth/GbeWrk.bsv\", line 43, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/eth/GbeWrk.bsv\", line 43, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3936 = $time; + v__h4015 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3936, + v__h4015, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3792 = $time; + v__h3871 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3792, + v__h3871, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkIQADCWorker.v b/rtl/mkIQADCWorker.v index 138a4fb9..dc797377 100644 --- a/rtl/mkIQADCWorker.v +++ b/rtl/mkIQADCWorker.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:48 EDT 2012 +// On Mon Sep 24 15:04:06 EDT 2012 // // // Ports: @@ -59,7 +59,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkIQADCWorker(CLK_sys0_clk, @@ -942,7 +950,7 @@ module mkIQADCWorker(CLK_sys0_clk, adcCore_sampF_memory$WEB; // ports of submodule adcCore_sdrRst - wire adcCore_sdrRst$OUT_RST_N; + wire adcCore_sdrRst$OUT_RST; // ports of submodule adcCore_spiI_cd wire adcCore_spiI_cd$CLK_OUT, adcCore_spiI_cd$PREEDGE; @@ -954,7 +962,7 @@ module mkIQADCWorker(CLK_sys0_clk, wire adcCore_spiI_reqF_dCombinedReset$RST_OUT; // ports of submodule adcCore_spiI_reqF_dCrossedsReset - wire adcCore_spiI_reqF_dCrossedsReset$OUT_RST_N; + wire adcCore_spiI_reqF_dCrossedsReset$OUT_RST; // ports of submodule adcCore_spiI_reqF_dInReset wire adcCore_spiI_reqF_dInReset$VAL; @@ -963,7 +971,7 @@ module mkIQADCWorker(CLK_sys0_clk, wire adcCore_spiI_reqF_sCombinedReset$RST_OUT; // ports of submodule adcCore_spiI_reqF_sCrosseddReset - wire adcCore_spiI_reqF_sCrosseddReset$OUT_RST_N; + wire adcCore_spiI_reqF_sCrosseddReset$OUT_RST; // ports of submodule adcCore_spiI_reqF_sInReset wire adcCore_spiI_reqF_sInReset$VAL; @@ -972,7 +980,7 @@ module mkIQADCWorker(CLK_sys0_clk, wire adcCore_spiI_respF_dCombinedReset$RST_OUT; // ports of submodule adcCore_spiI_respF_dCrossedsReset - wire adcCore_spiI_respF_dCrossedsReset$OUT_RST_N; + wire adcCore_spiI_respF_dCrossedsReset$OUT_RST; // ports of submodule adcCore_spiI_respF_dInReset wire adcCore_spiI_respF_dInReset$VAL; @@ -981,13 +989,13 @@ module mkIQADCWorker(CLK_sys0_clk, wire adcCore_spiI_respF_sCombinedReset$RST_OUT; // ports of submodule adcCore_spiI_respF_sCrosseddReset - wire adcCore_spiI_respF_sCrosseddReset$OUT_RST_N; + wire adcCore_spiI_respF_sCrosseddReset$OUT_RST; // ports of submodule adcCore_spiI_respF_sInReset wire adcCore_spiI_respF_sInReset$VAL; // ports of submodule adcCore_spiI_slowReset - wire adcCore_spiI_slowReset$OUT_RST_N; + wire adcCore_spiI_slowReset$OUT_RST; // ports of submodule adcCore_statsCC wire [127 : 0] adcCore_statsCC$dD_OUT, adcCore_statsCC$sD_IN; @@ -1095,43 +1103,43 @@ module mkIQADCWorker(CLK_sys0_clk, MUX_wsiM_reqFifo_q_1$write_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h3622, v__h3796, v__h3940, v__h62194, v__h62680; - reg [31 : 0] IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188, - x1_data__h14312; + reg [63 : 0] v__h3700, v__h3875, v__h4019, v__h62822, v__h63319; + reg [31 : 0] IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190, + x1_data__h14550; reg CASE_adcCore_colGate_avgPhase_0b1_0_1_1_1_2_1__ETC__q2; wire [63 : 0] wti_nowReq_BITS_63_TO_0__q1; - wire [31 : 0] IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1407, - IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1404, - IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1405, - IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d1402, - IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d1403, - adcStatusLs__h62461, - avgDataBW__h14621, - d_data__h14708, - rdat__h62664, - rdat__h62743, - rdat__h62825, - rdat__h62845, - x__h20365; - wire [17 : 0] x__h14971, - x__h14981, - x__h15047, - x__h15121, - x__h15131, - x__h7331, - y__h15132, - y__h15134, - y__h8736; - wire [11 : 0] x_burstLength__h61311; - wire [10 : 0] adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240, - x__h17225, - x__h19509, - x__h22936, - x_dReadBin__h21322, - x_sReadBin__h21319, - y__h18112, - y__h20396; - wire [9 : 0] x2__h22905; + wire [31 : 0] IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1412, + IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1413, + IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1409, + IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1410, + IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d1407, + adcStatusLs__h63100, + avgDataBW__h14863, + d_data__h14950, + rdat__h63303, + rdat__h63382, + rdat__h63464, + rdat__h63484, + x__h8844; + wire [17 : 0] x__h15215, + x__h15225, + x__h15291, + x__h15365, + x__h15375, + x__h7477, + y__h15376, + y__h15378, + y__h8882; + wire [11 : 0] x_burstLength__h61936; + wire [10 : 0] adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244, + x__h17544, + x__h19846, + x__h23273, + x_dReadBin__h21659, + x_sReadBin__h21656, + y__h18431, + y__h20733; + wire [9 : 0] x2__h23242; wire [7 : 0] adcCore_spiI_reqS_BITS_15_TO_8__q3, adcCore_spiI_reqS_BITS_7_TO_0__q4; wire NOT_adcCore_sampF_rRdPtr_rsCounter_48_EQ_adcCo_ETC___d1051, @@ -1139,91 +1147,91 @@ module mkIQADCWorker(CLK_sys0_clk, adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d379, adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d390, adcCore_colGate_sampF_RDY_first__93_AND_NOT_ad_ETC___d750, - adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1304, + adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1306, adcCore_iseqFsm_abort_whas__69_AND_adcCore_ise_ETC___d941, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1234, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1235, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1236, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1237, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1238, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1239, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1241, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1242, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1243, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1257, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1258, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1259, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1260, adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1261, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1344, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1231, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1232, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1233, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1250, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1347, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1236, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1237, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1238, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1239, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1240, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1251, adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253, adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1258, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1259, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1305, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1343, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1226, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1227, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1228, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1229, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1249, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1251, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1268, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1256, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1307, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1295, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1234, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1250, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1252, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1255, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1266, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1267, adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1218, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1242, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1243, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1244, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1247, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1230, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1231, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1245, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1246, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1255, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1267, - fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1342, - wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d1097, - z__h18156, - z__h18163, - z__h18170, - z__h18177, - z__h18184, - z__h18191, - z__h18198, - z__h18205, - z__h18212, - z__h20440, - z__h20447, - z__h20454, - z__h20461, - z__h20468, - z__h20475, - z__h20482, - z__h20489, - z__h20496, - z__h7351, - z__h7358, - z__h7365, - z__h7372, - z__h7379, - z__h7386, - z__h7393, - z__h7400, - z__h7407, - z__h7414, - z__h7421, - z__h7428, - z__h7435, - z__h7442, - z__h7449, - z__h7456; + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1262, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1264, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1265, + fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1216, + wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d1098, + z__h18475, + z__h18482, + z__h18489, + z__h18496, + z__h18503, + z__h18510, + z__h18517, + z__h18524, + z__h18531, + z__h20777, + z__h20784, + z__h20791, + z__h20798, + z__h20805, + z__h20812, + z__h20819, + z__h20826, + z__h20833, + z__h7497, + z__h7504, + z__h7511, + z__h7518, + z__h7525, + z__h7532, + z__h7539, + z__h7546, + z__h7553, + z__h7560, + z__h7567, + z__h7574, + z__h7581, + z__h7588, + z__h7595, + z__h7602; // oscillator and gates for output clock CLK_adc_sclk assign CLK_adc_sclk = adcCore_spiI_cd$CLK_OUT ; @@ -1238,8 +1246,8 @@ module mkIQADCWorker(CLK_sys0_clk, assign CLK_GATE_adcSdrClk = 1'd1 ; // output resets - assign RST_N_adc_rst = adcCore_spiI_slowReset$OUT_RST_N ; - assign RST_N_adcSdrRst = adcCore_sdrRst$OUT_RST_N ; + assign RST_N_adc_rst = adcCore_spiI_slowReset$OUT_RST ; + assign RST_N_adcSdrRst = adcCore_sdrRst$OUT_RST ; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1304,7 +1312,7 @@ module mkIQADCWorker(CLK_sys0_clk, SyncRegister #(.width(32'd1), .init(1'd0)) adcCore_acquireD(.sCLK(wciS0_Clk), .dCLK(CLK_adc_clock), - .sRST_N(wciS0_MReset_n), + .sRST(wciS0_MReset_n), .sD_IN(adcCore_acquireD$sD_IN), .sEN(adcCore_acquireD$sEN), .dD_OUT(adcCore_acquireD$dD_OUT), @@ -1314,7 +1322,7 @@ module mkIQADCWorker(CLK_sys0_clk, SyncRegister #(.width(32'd1), .init(1'd0)) adcCore_averageD(.sCLK(wciS0_Clk), .dCLK(CLK_adc_clock), - .sRST_N(wciS0_MReset_n), + .sRST(wciS0_MReset_n), .sD_IN(adcCore_averageD$sD_IN), .sEN(adcCore_averageD$sEN), .dD_OUT(adcCore_averageD$dD_OUT), @@ -1323,7 +1331,7 @@ module mkIQADCWorker(CLK_sys0_clk, // submodule adcCore_colGate_sampF arSRLFIFOD #(.width(32'd39), .l2depth(32'd4)) adcCore_colGate_sampF(.CLK(CLK_adc_clock), - .RST_N(adcCore_sdrRst$OUT_RST_N), + .RST_N(adcCore_sdrRst$OUT_RST), .D_IN(adcCore_colGate_sampF$D_IN), .CLR(adcCore_colGate_sampF$CLR), .DEQ(adcCore_colGate_sampF$DEQ), @@ -1336,7 +1344,7 @@ module mkIQADCWorker(CLK_sys0_clk, SyncRegister #(.width(32'd16), .init(16'd0)) adcCore_maxBurstLengthR(.sCLK(wciS0_Clk), .dCLK(CLK_adc_clock), - .sRST_N(wciS0_MReset_n), + .sRST(wciS0_MReset_n), .sD_IN(adcCore_maxBurstLengthR$sD_IN), .sEN(adcCore_maxBurstLengthR$sEN), .dD_OUT(adcCore_maxBurstLengthR$dD_OUT), @@ -1346,29 +1354,28 @@ module mkIQADCWorker(CLK_sys0_clk, SyncRegister #(.width(32'd1), .init(1'd0)) adcCore_operateD(.sCLK(wciS0_Clk), .dCLK(CLK_adc_clock), - .sRST_N(wciS0_MReset_n), + .sRST(wciS0_MReset_n), .sD_IN(adcCore_operateD$sD_IN), .sEN(adcCore_operateD$sEN), .dD_OUT(adcCore_operateD$dD_OUT), .sRDY(adcCore_operateD$sRDY)); // submodule adcCore_reqF - FIFO2 #(.width(32'd17), - .guarded(32'd1)) adcCore_reqF(.RST_N(wciS0_MReset_n), - .CLK(wciS0_Clk), - .D_IN(adcCore_reqF$D_IN), - .ENQ(adcCore_reqF$ENQ), - .DEQ(adcCore_reqF$DEQ), - .CLR(adcCore_reqF$CLR), - .D_OUT(adcCore_reqF$D_OUT), - .FULL_N(adcCore_reqF$FULL_N), - .EMPTY_N(adcCore_reqF$EMPTY_N)); + FIFO2 #(.width(32'd17), .guarded(32'd1)) adcCore_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(adcCore_reqF$D_IN), + .ENQ(adcCore_reqF$ENQ), + .DEQ(adcCore_reqF$DEQ), + .CLR(adcCore_reqF$CLR), + .D_OUT(adcCore_reqF$D_OUT), + .FULL_N(adcCore_reqF$FULL_N), + .EMPTY_N(adcCore_reqF$EMPTY_N)); // submodule adcCore_sampCC SyncRegister #(.width(32'd32), .init(32'd0)) adcCore_sampCC(.sCLK(CLK_adc_clock), .dCLK(wciS0_Clk), - .sRST_N(adcCore_sdrRst$OUT_RST_N), + .sRST(adcCore_sdrRst$OUT_RST), .sD_IN(adcCore_sampCC$sD_IN), .sEN(adcCore_sampCC$sEN), .dD_OUT(adcCore_sampCC$dD_OUT), @@ -1393,15 +1400,15 @@ module mkIQADCWorker(CLK_sys0_clk, // submodule adcCore_sdrRst SyncResetA #(.RSTDELAY(32'd1)) adcCore_sdrRst(.CLK(CLK_adc_clock), - .IN_RST_N(wciS0_MReset_n), - .OUT_RST_N(adcCore_sdrRst$OUT_RST_N)); + .IN_RST(wciS0_MReset_n), + .OUT_RST(adcCore_sdrRst$OUT_RST)); // submodule adcCore_spiI_cd ClockDiv #(.width(32'd3), .lower(32'd0), .upper(32'd7), .offset(32'd0)) adcCore_spiI_cd(.CLK_IN(wciS0_Clk), - .RST_N(wciS0_MReset_n), + .RST(wciS0_MReset_n), .PREEDGE(adcCore_spiI_cd$PREEDGE), .CLK_OUT(adcCore_spiI_cd$CLK_OUT)); @@ -1411,13 +1418,13 @@ module mkIQADCWorker(CLK_sys0_clk, .CLK_OUT(adcCore_spiI_cinv$CLK_OUT)); // submodule adcCore_spiI_reqF_dCombinedReset - ResetEither adcCore_spiI_reqF_dCombinedReset(.A_RST(adcCore_spiI_slowReset$OUT_RST_N), - .B_RST(adcCore_spiI_reqF_dCrossedsReset$OUT_RST_N), + ResetEither adcCore_spiI_reqF_dCombinedReset(.A_RST(adcCore_spiI_slowReset$OUT_RST), + .B_RST(adcCore_spiI_reqF_dCrossedsReset$OUT_RST), .RST_OUT(adcCore_spiI_reqF_dCombinedReset$RST_OUT)); // submodule adcCore_spiI_reqF_dCrossedsReset - SyncReset0 adcCore_spiI_reqF_dCrossedsReset(.IN_RST_N(wciS0_MReset_n), - .OUT_RST_N(adcCore_spiI_reqF_dCrossedsReset$OUT_RST_N)); + SyncReset0 adcCore_spiI_reqF_dCrossedsReset(.IN_RST(wciS0_MReset_n), + .OUT_RST(adcCore_spiI_reqF_dCrossedsReset$OUT_RST)); // submodule adcCore_spiI_reqF_dInReset ResetToBool adcCore_spiI_reqF_dInReset(.RST(adcCore_spiI_reqF_dCombinedReset$RST_OUT), @@ -1425,12 +1432,12 @@ module mkIQADCWorker(CLK_sys0_clk, // submodule adcCore_spiI_reqF_sCombinedReset ResetEither adcCore_spiI_reqF_sCombinedReset(.A_RST(wciS0_MReset_n), - .B_RST(adcCore_spiI_reqF_sCrosseddReset$OUT_RST_N), + .B_RST(adcCore_spiI_reqF_sCrosseddReset$OUT_RST), .RST_OUT(adcCore_spiI_reqF_sCombinedReset$RST_OUT)); // submodule adcCore_spiI_reqF_sCrosseddReset - SyncReset0 adcCore_spiI_reqF_sCrosseddReset(.IN_RST_N(adcCore_spiI_slowReset$OUT_RST_N), - .OUT_RST_N(adcCore_spiI_reqF_sCrosseddReset$OUT_RST_N)); + SyncReset0 adcCore_spiI_reqF_sCrosseddReset(.IN_RST(adcCore_spiI_slowReset$OUT_RST), + .OUT_RST(adcCore_spiI_reqF_sCrosseddReset$OUT_RST)); // submodule adcCore_spiI_reqF_sInReset ResetToBool adcCore_spiI_reqF_sInReset(.RST(adcCore_spiI_reqF_sCombinedReset$RST_OUT), @@ -1438,25 +1445,25 @@ module mkIQADCWorker(CLK_sys0_clk, // submodule adcCore_spiI_respF_dCombinedReset ResetEither adcCore_spiI_respF_dCombinedReset(.A_RST(wciS0_MReset_n), - .B_RST(adcCore_spiI_respF_dCrossedsReset$OUT_RST_N), + .B_RST(adcCore_spiI_respF_dCrossedsReset$OUT_RST), .RST_OUT(adcCore_spiI_respF_dCombinedReset$RST_OUT)); // submodule adcCore_spiI_respF_dCrossedsReset - SyncReset0 adcCore_spiI_respF_dCrossedsReset(.IN_RST_N(adcCore_spiI_slowReset$OUT_RST_N), - .OUT_RST_N(adcCore_spiI_respF_dCrossedsReset$OUT_RST_N)); + SyncReset0 adcCore_spiI_respF_dCrossedsReset(.IN_RST(adcCore_spiI_slowReset$OUT_RST), + .OUT_RST(adcCore_spiI_respF_dCrossedsReset$OUT_RST)); // submodule adcCore_spiI_respF_dInReset ResetToBool adcCore_spiI_respF_dInReset(.RST(adcCore_spiI_respF_dCombinedReset$RST_OUT), .VAL(adcCore_spiI_respF_dInReset$VAL)); // submodule adcCore_spiI_respF_sCombinedReset - ResetEither adcCore_spiI_respF_sCombinedReset(.A_RST(adcCore_spiI_slowReset$OUT_RST_N), - .B_RST(adcCore_spiI_respF_sCrosseddReset$OUT_RST_N), + ResetEither adcCore_spiI_respF_sCombinedReset(.A_RST(adcCore_spiI_slowReset$OUT_RST), + .B_RST(adcCore_spiI_respF_sCrosseddReset$OUT_RST), .RST_OUT(adcCore_spiI_respF_sCombinedReset$RST_OUT)); // submodule adcCore_spiI_respF_sCrosseddReset - SyncReset0 adcCore_spiI_respF_sCrosseddReset(.IN_RST_N(wciS0_MReset_n), - .OUT_RST_N(adcCore_spiI_respF_sCrosseddReset$OUT_RST_N)); + SyncReset0 adcCore_spiI_respF_sCrosseddReset(.IN_RST(wciS0_MReset_n), + .OUT_RST(adcCore_spiI_respF_sCrosseddReset$OUT_RST)); // submodule adcCore_spiI_respF_sInReset ResetToBool adcCore_spiI_respF_sInReset(.RST(adcCore_spiI_respF_sCombinedReset$RST_OUT), @@ -1464,14 +1471,14 @@ module mkIQADCWorker(CLK_sys0_clk, // submodule adcCore_spiI_slowReset SyncResetA #(.RSTDELAY(32'd1)) adcCore_spiI_slowReset(.CLK(adcCore_spiI_cd$CLK_OUT), - .IN_RST_N(wciS0_MReset_n), - .OUT_RST_N(adcCore_spiI_slowReset$OUT_RST_N)); + .IN_RST(wciS0_MReset_n), + .OUT_RST(adcCore_spiI_slowReset$OUT_RST)); // submodule adcCore_statsCC SyncRegister #(.width(32'd128), .init(128'd0)) adcCore_statsCC(.sCLK(CLK_adc_clock), .dCLK(wciS0_Clk), - .sRST_N(adcCore_sdrRst$OUT_RST_N), + .sRST(adcCore_sdrRst$OUT_RST), .sD_IN(adcCore_statsCC$sD_IN), .sEN(adcCore_statsCC$sEN), .dD_OUT(adcCore_statsCC$dD_OUT), @@ -1481,7 +1488,7 @@ module mkIQADCWorker(CLK_sys0_clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -1502,7 +1509,7 @@ module mkIQADCWorker(CLK_sys0_clk, // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = wci_wslv_respF_c_r != 2'd2 && - wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d1097 && + wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d1098 && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -1793,18 +1800,18 @@ module mkIQADCWorker(CLK_sys0_clk, { 2'd2, adcCore_colGate_timeMesg == 3'h1, 4'd15, - x1_data__h14312 } ; + x1_data__h14550 } ; assign MUX_adcCore_colGate_sampF$enq_1__VAL_3 = { 2'd0, - adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1304, + adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1306, 4'd15, - d_data__h14708 } ; + d_data__h14950 } ; assign MUX_adcCore_colGate_syncMesg$write_1__VAL_1 = adcCore_colGate_syncMesg - 2'd1 ; assign MUX_adcCore_colGate_timeMesg$write_1__VAL_1 = adcCore_colGate_timeMesg - 3'd1 ; assign MUX_adcCore_colGate_uprollCnt$write_1__VAL_2 = - adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1304 ? + adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1306 ? 16'd0 : adcCore_colGate_uprollCnt + 16'd1 ; assign MUX_adcCore_iseqFsm_jj_delay_count$write_1__VAL_1 = @@ -1817,13 +1824,13 @@ module mkIQADCWorker(CLK_sys0_clk, assign MUX_adcCore_reqF$enq_1__VAL_2 = { 1'd1, wci_wslv_reqF$D_OUT[41:34], 8'd0 } ; assign MUX_adcCore_sampF_rRdPtr_rsCounter$write_1__VAL_1 = - (~adcCore_sampF_rRdPtr_rsCounter[x__h20365[3:0]]) ? - adcCore_sampF_rRdPtr_rsCounter | x__h19509 : - adcCore_sampF_rRdPtr_rsCounter & y__h20396 ; + (~adcCore_sampF_rRdPtr_rsCounter[IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1412[3:0]]) ? + adcCore_sampF_rRdPtr_rsCounter | x__h19846 : + adcCore_sampF_rRdPtr_rsCounter & y__h20733 ; assign MUX_adcCore_sampF_rWrPtr_rsCounter$write_1__VAL_1 = - (~adcCore_sampF_rWrPtr_rsCounter[IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1404[3:0]]) ? - adcCore_sampF_rWrPtr_rsCounter | x__h17225 : - adcCore_sampF_rWrPtr_rsCounter & y__h18112 ; + (~adcCore_sampF_rWrPtr_rsCounter[IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1409[3:0]]) ? + adcCore_sampF_rWrPtr_rsCounter | x__h17544 : + adcCore_sampF_rWrPtr_rsCounter & y__h18431 ; assign MUX_adcCore_spiI_dPos$write_1__VAL_1 = (adcCore_spiI_dPos == 3'd0) ? adcCore_spiI_dPos : @@ -1843,9 +1850,9 @@ module mkIQADCWorker(CLK_sys0_clk, assign MUX_adcCore_spiI_sdoR_1$wset_1__VAL_2 = adcCore_spiI_reqS_BITS_7_TO_0__q4[adcCore_spiI_dPos] ; assign MUX_fcAdc_grayCounter_rsCounter$write_1__VAL_1 = - (~fcAdc_grayCounter_rsCounter[IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d1403[4:0]]) ? - fcAdc_grayCounter_rsCounter | x__h7331 : - fcAdc_grayCounter_rsCounter & y__h8736 ; + (~fcAdc_grayCounter_rsCounter[x__h8844[4:0]]) ? + fcAdc_grayCounter_rsCounter | x__h7477 : + fcAdc_grayCounter_rsCounter & y__h8882 ; assign MUX_oneKHz_value$write_1__VAL_1 = (oneKHz_value == 18'd99999) ? 18'd0 : oneKHz_value + 18'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = @@ -1887,7 +1894,7 @@ module mkIQADCWorker(CLK_sys0_clk, 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 26'd16777216, adcCore_spiI_respS } ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, rdat__h62664 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, rdat__h63303 } ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; @@ -1900,7 +1907,7 @@ module mkIQADCWorker(CLK_sys0_clk, { 3'd1, adcCore_sampF_memory$DOB[36], 1'd0, - x_burstLength__h61311, + x_burstLength__h61936, adcCore_sampF_memory$DOB[31:0], 10'd960, adcCore_sampF_memory$DOB[38:37] } ; @@ -2121,7 +2128,7 @@ module mkIQADCWorker(CLK_sys0_clk, // register adcCore_colGate_avgEven assign adcCore_colGate_avgEven$D_IN = - (adcCore_colGate_avgPhase == 2'd0) ? x__h15047 : x__h14971 ; + (adcCore_colGate_avgPhase == 2'd0) ? x__h15291 : x__h15215 ; assign adcCore_colGate_avgEven$EN = WILL_FIRE_RL_adcCore_colGate_form_avg4_sample && (adcCore_colGate_avgPhase == 2'd0 || @@ -2129,7 +2136,7 @@ module mkIQADCWorker(CLK_sys0_clk, // register adcCore_colGate_avgOdd assign adcCore_colGate_avgOdd$D_IN = - (adcCore_colGate_avgPhase == 2'd2) ? x__h15047 : x__h15121 ; + (adcCore_colGate_avgPhase == 2'd2) ? x__h15291 : x__h15365 ; assign adcCore_colGate_avgOdd$EN = WILL_FIRE_RL_adcCore_colGate_form_avg4_sample && (adcCore_colGate_avgPhase == 2'd2 || @@ -2560,23 +2567,23 @@ module mkIQADCWorker(CLK_sys0_clk, // register fcAdc_countNow assign fcAdc_countNow$D_IN = { fcAdc_grayCounter_rdCounter[17], - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1255, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1218, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1243, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1247, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1244, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1267, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1242, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1246, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1264, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1265, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225 ^ + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1245, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1231, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1230, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1262, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1262 ^ fcAdc_grayCounter_rdCounter[0] } ; assign fcAdc_countNow$EN = fcAdc_pulseAction ; @@ -2991,19 +2998,19 @@ module mkIQADCWorker(CLK_sys0_clk, // submodule adcCore_sampF_memory assign adcCore_sampF_memory$ADDRA = - { adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1227, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1226, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1228, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1268, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1249, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1251, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1229, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230 ^ + { adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1255, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1250, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1234, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1252, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1266, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1267, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1267 ^ adcCore_sampF_rWrPtr_rsCounter[0] } ; assign adcCore_sampF_memory$ADDRB = - adcCore_sampF_pwDequeue$whas ? x__h22936[9:0] : x2__h22905 ; + adcCore_sampF_pwDequeue$whas ? x__h23273[9:0] : x2__h23242 ; assign adcCore_sampF_memory$DIA = { adcCore_sampF_pwEnqueue$whas ? adcCore_colGate_sampF$D_OUT[38:37] : @@ -3034,7 +3041,11 @@ module mkIQADCWorker(CLK_sys0_clk, assign wci_wslv_reqF$CLR = 1'b0 ; // remaining internal signals - assign IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1407 = + assign IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1412 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1347 ? + IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1413 : + 32'd0 ; + assign IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1413 = (adcCore_sampF_rRdPtr_rsCounter[0] || adcCore_sampF_rRdPtr_rsCounter[1] || adcCore_sampF_rRdPtr_rsCounter[2] || @@ -3069,11 +3080,11 @@ module mkIQADCWorker(CLK_sys0_clk, 32'd11 : 32'd12))))))))))) : 32'd10 ; - assign IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1404 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1343 ? - IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1405 : + assign IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1409 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1295 ? + IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1410 : 32'd0 ; - assign IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1405 = + assign IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1410 = (adcCore_sampF_rWrPtr_rsCounter[0] || adcCore_sampF_rWrPtr_rsCounter[1] || adcCore_sampF_rWrPtr_rsCounter[2] || @@ -3108,7 +3119,7 @@ module mkIQADCWorker(CLK_sys0_clk, 32'd11 : 32'd12))))))))))) : 32'd10 ; - assign IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d1402 = + assign IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d1407 = (fcAdc_grayCounter_rsCounter[0] || fcAdc_grayCounter_rsCounter[1] || fcAdc_grayCounter_rsCounter[2] || @@ -3164,10 +3175,6 @@ module mkIQADCWorker(CLK_sys0_clk, 32'd18 : 32'd19)))))))))))))))))) : 32'd17 ; - assign IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d1403 = - fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1342 ? - IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d1402 : - 32'd0 ; assign NOT_adcCore_sampF_rRdPtr_rsCounter_48_EQ_adcCo_ETC___d1051 = adcCore_sampF_rRdPtr_rsCounter != adcCore_sampF_rWrPtr_rdCounter ; @@ -3186,124 +3193,124 @@ module mkIQADCWorker(CLK_sys0_clk, assign adcCore_colGate_sampF_RDY_first__93_AND_NOT_ad_ETC___d750 = adcCore_colGate_sampF$EMPTY_N && adcCore_sampF_rWrPtr_rsCounter != - { adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[10], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[10] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[9], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[9] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[8], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[8] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[7], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[7] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[6], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[6] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[5], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[5] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[4], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[4] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[3], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[3] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[2], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[2] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[1], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[1] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[0] } ; - assign adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1304 = + { adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[10], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[10] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[9], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[9] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[8], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[8] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[7], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[7] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[6], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[6] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[5], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[5] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[4], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[4] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[3], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[3] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[2], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[2] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[1], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[1] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244[0] } ; + assign adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1306 = adcCore_colGate_uprollCnt == adcCore_maxBurstLengthR$dD_OUT - 16'd1 ; assign adcCore_iseqFsm_abort_whas__69_AND_adcCore_ise_ETC___d941 = (adcCore_iseqFsm_state_mkFSMstate == 4'd0 || adcCore_iseqFsm_state_mkFSMstate == 4'd10) && (!adcCore_iseqFsm_start_reg_1 || adcCore_iseqFsm_state_fired) ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240 = - x_dReadBin__h21322 + 11'd512 ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1234 = + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1244 = + x_dReadBin__h21659 + 11'd512 ; + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1241 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1242 ^ + adcCore_sampF_rRdPtr_rdCounter[7] ; + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1242 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1257 ^ + adcCore_sampF_rRdPtr_rdCounter[8] ; + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1243 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1241 ^ + adcCore_sampF_rRdPtr_rdCounter[6] ; + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1261 ^ + adcCore_sampF_rRdPtr_rdCounter[1] ; + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1257 = adcCore_sampF_rRdPtr_rdCounter[10] ^ adcCore_sampF_rRdPtr_rdCounter[9] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1235 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263 ^ + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1258 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1243 ^ adcCore_sampF_rRdPtr_rdCounter[5] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1236 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1235 ^ + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1259 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1258 ^ adcCore_sampF_rRdPtr_rdCounter[4] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1237 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1236 ^ + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1260 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1259 ^ adcCore_sampF_rRdPtr_rdCounter[3] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1238 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1237 ^ - adcCore_sampF_rRdPtr_rdCounter[2] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1239 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1238 ^ - adcCore_sampF_rRdPtr_rdCounter[1] ; assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1261 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1234 ^ - adcCore_sampF_rRdPtr_rdCounter[8] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1261 ^ - adcCore_sampF_rRdPtr_rdCounter[7] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262 ^ - adcCore_sampF_rRdPtr_rdCounter[6] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1344 = - z__h20496 ^ adcCore_sampF_rRdPtr_rsCounter[10] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1231 = - adcCore_sampF_rRdPtr_rsCounter[10] ^ - adcCore_sampF_rRdPtr_rsCounter[9] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1232 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1231 ^ - adcCore_sampF_rRdPtr_rsCounter[8] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1233 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260 ^ - adcCore_sampF_rRdPtr_rsCounter[1] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1250 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254 ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1260 ^ + adcCore_sampF_rRdPtr_rdCounter[2] ; + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1347 = + z__h20833 ^ adcCore_sampF_rRdPtr_rsCounter[10] ; + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1236 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253 ^ adcCore_sampF_rRdPtr_rsCounter[6] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1250 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1237 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1236 ^ adcCore_sampF_rRdPtr_rsCounter[5] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1232 ^ - adcCore_sampF_rRdPtr_rsCounter[7] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1258 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1238 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1237 ^ adcCore_sampF_rRdPtr_rsCounter[4] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1259 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1258 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1239 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1238 ^ adcCore_sampF_rRdPtr_rsCounter[3] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1259 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1240 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1239 ^ adcCore_sampF_rRdPtr_rsCounter[2] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1305 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1233 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1251 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254 ^ + adcCore_sampF_rRdPtr_rsCounter[8] ; + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1251 ^ + adcCore_sampF_rRdPtr_rsCounter[7] ; + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254 = + adcCore_sampF_rRdPtr_rsCounter[10] ^ + adcCore_sampF_rRdPtr_rsCounter[9] ; + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1256 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1240 ^ + adcCore_sampF_rRdPtr_rsCounter[1] ; + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1307 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1256 ^ adcCore_sampF_rRdPtr_rsCounter[0] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1343 = - z__h18212 ^ adcCore_sampF_rWrPtr_rsCounter[10] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1226 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1227 ^ - adcCore_sampF_rWrPtr_rsCounter[7] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1227 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256 ^ + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1295 = + z__h18531 ^ adcCore_sampF_rWrPtr_rsCounter[10] ; + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232 = + adcCore_sampF_rWrPtr_rsCounter[10] ^ + adcCore_sampF_rWrPtr_rsCounter[9] ; + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232 ^ adcCore_sampF_rWrPtr_rsCounter[8] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1228 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1226 ^ - adcCore_sampF_rWrPtr_rsCounter[6] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1229 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1251 ^ + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1234 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1250 ^ + adcCore_sampF_rWrPtr_rsCounter[5] ; + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1266 ^ adcCore_sampF_rWrPtr_rsCounter[2] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1229 ^ - adcCore_sampF_rWrPtr_rsCounter[1] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1249 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1268 ^ + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1250 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1255 ^ + adcCore_sampF_rWrPtr_rsCounter[6] ; + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1252 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1234 ^ adcCore_sampF_rWrPtr_rsCounter[4] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1251 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1249 ^ + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1255 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233 ^ + adcCore_sampF_rWrPtr_rsCounter[7] ; + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1266 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1252 ^ adcCore_sampF_rWrPtr_rsCounter[3] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256 = - adcCore_sampF_rWrPtr_rsCounter[10] ^ - adcCore_sampF_rWrPtr_rsCounter[9] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1268 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1228 ^ - adcCore_sampF_rWrPtr_rsCounter[5] ; + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1267 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235 ^ + adcCore_sampF_rWrPtr_rsCounter[1] ; assign adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919 = adcCore_spiI_reqF_head_wrapped == adcCore_spiI_reqF_tail_wrapped && @@ -3311,7 +3318,7 @@ module mkIQADCWorker(CLK_sys0_clk, adcCore_spiI_cd$PREEDGE ; assign adcCore_spiI_reqS_BITS_15_TO_8__q3 = adcCore_spiI_reqS[15:8] ; assign adcCore_spiI_reqS_BITS_7_TO_0__q4 = adcCore_spiI_reqS[7:0] ; - assign adcStatusLs__h62461 = + assign adcStatusLs__h63100 = { 27'd0, splitReadInFlight, initOpInFlight, @@ -3319,172 +3326,172 @@ module mkIQADCWorker(CLK_sys0_clk, adcCore_iseqFsm_abort_whas__69_AND_adcCore_ise_ETC___d941 && !adcCore_iseqFsm_start_reg, 1'b1 } ; - assign avgDataBW__h14621 = + assign avgDataBW__h14863 = { adcCore_colGate_avgOdd[17:2], adcCore_colGate_avgEven[17:2] } ; - assign d_data__h14708 = - adcCore_averageD$dD_OUT ? avgDataBW__h14621 : adcCore_samp ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1218 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1255 ^ - fcAdc_grayCounter_rdCounter[15] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1218 ^ + assign d_data__h14950 = + adcCore_averageD$dD_OUT ? avgDataBW__h14863 : adcCore_samp ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222 = + fcAdc_grayCounter_rdCounter[17] ^ + fcAdc_grayCounter_rdCounter[16] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1246 ^ fcAdc_grayCounter_rdCounter[14] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1247 ^ + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1264 ^ fcAdc_grayCounter_rdCounter[11] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266 ^ + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1265 ^ + fcAdc_grayCounter_rdCounter[9] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225 ^ fcAdc_grayCounter_rdCounter[8] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224 ^ + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226 ^ + fcAdc_grayCounter_rdCounter[7] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229 ^ fcAdc_grayCounter_rdCounter[3] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222 ^ - fcAdc_grayCounter_rdCounter[2] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248 ^ + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1231 ^ fcAdc_grayCounter_rdCounter[4] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223 ^ - fcAdc_grayCounter_rdCounter[1] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1242 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1267 ^ + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1230 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228 ^ + fcAdc_grayCounter_rdCounter[2] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1231 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1245 ^ + fcAdc_grayCounter_rdCounter[5] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1245 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227 ^ fcAdc_grayCounter_rdCounter[6] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1243 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219 ^ + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1246 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222 ^ + fcAdc_grayCounter_rdCounter[15] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223 ^ fcAdc_grayCounter_rdCounter[13] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1244 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220 ^ - fcAdc_grayCounter_rdCounter[10] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1247 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1243 ^ + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1262 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1230 ^ + fcAdc_grayCounter_rdCounter[1] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1264 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248 ^ fcAdc_grayCounter_rdCounter[12] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1242 ^ - fcAdc_grayCounter_rdCounter[5] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1255 = - fcAdc_grayCounter_rdCounter[17] ^ - fcAdc_grayCounter_rdCounter[16] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1244 ^ - fcAdc_grayCounter_rdCounter[9] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1267 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221 ^ - fcAdc_grayCounter_rdCounter[7] ; - assign fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1342 = - z__h7456 ^ fcAdc_grayCounter_rsCounter[17] ; - assign rdat__h62664 = + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1265 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224 ^ + fcAdc_grayCounter_rdCounter[10] ; + assign fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1216 = + z__h7602 ^ fcAdc_grayCounter_rsCounter[17] ; + assign rdat__h63303 = (wci_wslv_reqF$D_OUT[43:42] == 2'b0) ? - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 : + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 : 32'd0 ; - assign rdat__h62743 = { 24'd0, wsiM_statusR } ; - assign rdat__h62825 = { 14'd0, fcAdc_frequency } ; - assign rdat__h62845 = { 24'd0, spiResp } ; - assign wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d1097 = + assign rdat__h63382 = { 24'd0, wsiM_statusR } ; + assign rdat__h63464 = { 14'd0, fcAdc_frequency } ; + assign rdat__h63484 = { 24'd0, spiResp } ; + assign wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d1098 = wci_wslv_reqF$EMPTY_N && ((wci_wslv_reqF$D_OUT[43:42] == 2'b0) ? wci_wslv_reqF$D_OUT[39:32] != 8'h28 || adcCore_reqF$FULL_N : wci_wslv_reqF$D_OUT[43:42] != 2'b01 || adcCore_reqF$FULL_N) ; assign wti_nowReq_BITS_63_TO_0__q1 = wti_nowReq[63:0] ; - assign x2__h22905 = - { adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1231, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1232, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1250, + assign x2__h23242 = + { adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1251, adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1258, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1259, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1233, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1305 } ; - assign x__h14971 = x__h14981 + y__h15132 ; - assign x__h14981 = adcCore_colGate_avgEven + y__h15134 ; - assign x__h15047 = y__h15134 + y__h15132 ; - assign x__h15121 = x__h15131 + y__h15132 ; - assign x__h15131 = adcCore_colGate_avgOdd + y__h15134 ; - assign x__h17225 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1236, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1237, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1238, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1239, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1240, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1256, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1307 } ; + assign x__h15215 = x__h15225 + y__h15376 ; + assign x__h15225 = adcCore_colGate_avgEven + y__h15378 ; + assign x__h15291 = y__h15378 + y__h15376 ; + assign x__h15365 = x__h15375 + y__h15376 ; + assign x__h15375 = adcCore_colGate_avgOdd + y__h15378 ; + assign x__h17544 = 11'd1 << - IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1404 ; - assign x__h19509 = 11'd1 << x__h20365 ; - assign x__h20365 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1344 ? - IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1407 : + IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1409 ; + assign x__h19846 = + 11'd1 << + IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1412 ; + assign x__h23273 = x_sReadBin__h21656 + 11'd1 ; + assign x__h7477 = 18'd1 << x__h8844 ; + assign x__h8844 = + fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1216 ? + IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d1407 : 32'd0 ; - assign x__h22936 = x_sReadBin__h21319 + 11'd1 ; - assign x__h7331 = - 18'd1 << - IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d1403 ; - assign x_burstLength__h61311 = + assign x_burstLength__h61936 = adcCore_sampF_memory$DOB[36] ? 12'd1 : 12'd4095 ; - assign x_dReadBin__h21322 = + assign x_dReadBin__h21659 = { adcCore_sampF_rRdPtr_rdCounter[10], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1234, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1257, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1242, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1241, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1243, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1258, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1259, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1260, adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1261, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1235, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1236, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1237, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1238, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1239, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1239 ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249 ^ adcCore_sampF_rRdPtr_rdCounter[0] } ; - assign x_sReadBin__h21319 = + assign x_sReadBin__h21656 = { adcCore_sampF_rRdPtr_rsCounter[10], - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1231, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1232, adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1250, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1251, adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1258, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1259, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1233, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1305 } ; - assign y__h15132 = { 2'd0, adcCore_samp[15:0] } ; - assign y__h15134 = { 2'd0, adcCore_samp[31:16] } ; - assign y__h18112 = ~x__h17225 ; - assign y__h20396 = ~x__h19509 ; - assign y__h8736 = ~x__h7331 ; - assign z__h18156 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1236, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1237, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1238, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1239, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1240, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1256, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1307 } ; + assign y__h15376 = { 2'd0, adcCore_samp[15:0] } ; + assign y__h15378 = { 2'd0, adcCore_samp[31:16] } ; + assign y__h18431 = ~x__h17544 ; + assign y__h20733 = ~x__h19846 ; + assign y__h8882 = ~x__h7477 ; + assign z__h18475 = adcCore_sampF_rWrPtr_rsCounter[0] ^ adcCore_sampF_rWrPtr_rsCounter[1] ; - assign z__h18163 = z__h18156 ^ adcCore_sampF_rWrPtr_rsCounter[2] ; - assign z__h18170 = z__h18163 ^ adcCore_sampF_rWrPtr_rsCounter[3] ; - assign z__h18177 = z__h18170 ^ adcCore_sampF_rWrPtr_rsCounter[4] ; - assign z__h18184 = z__h18177 ^ adcCore_sampF_rWrPtr_rsCounter[5] ; - assign z__h18191 = z__h18184 ^ adcCore_sampF_rWrPtr_rsCounter[6] ; - assign z__h18198 = z__h18191 ^ adcCore_sampF_rWrPtr_rsCounter[7] ; - assign z__h18205 = z__h18198 ^ adcCore_sampF_rWrPtr_rsCounter[8] ; - assign z__h18212 = z__h18205 ^ adcCore_sampF_rWrPtr_rsCounter[9] ; - assign z__h20440 = + assign z__h18482 = z__h18475 ^ adcCore_sampF_rWrPtr_rsCounter[2] ; + assign z__h18489 = z__h18482 ^ adcCore_sampF_rWrPtr_rsCounter[3] ; + assign z__h18496 = z__h18489 ^ adcCore_sampF_rWrPtr_rsCounter[4] ; + assign z__h18503 = z__h18496 ^ adcCore_sampF_rWrPtr_rsCounter[5] ; + assign z__h18510 = z__h18503 ^ adcCore_sampF_rWrPtr_rsCounter[6] ; + assign z__h18517 = z__h18510 ^ adcCore_sampF_rWrPtr_rsCounter[7] ; + assign z__h18524 = z__h18517 ^ adcCore_sampF_rWrPtr_rsCounter[8] ; + assign z__h18531 = z__h18524 ^ adcCore_sampF_rWrPtr_rsCounter[9] ; + assign z__h20777 = adcCore_sampF_rRdPtr_rsCounter[0] ^ adcCore_sampF_rRdPtr_rsCounter[1] ; - assign z__h20447 = z__h20440 ^ adcCore_sampF_rRdPtr_rsCounter[2] ; - assign z__h20454 = z__h20447 ^ adcCore_sampF_rRdPtr_rsCounter[3] ; - assign z__h20461 = z__h20454 ^ adcCore_sampF_rRdPtr_rsCounter[4] ; - assign z__h20468 = z__h20461 ^ adcCore_sampF_rRdPtr_rsCounter[5] ; - assign z__h20475 = z__h20468 ^ adcCore_sampF_rRdPtr_rsCounter[6] ; - assign z__h20482 = z__h20475 ^ adcCore_sampF_rRdPtr_rsCounter[7] ; - assign z__h20489 = z__h20482 ^ adcCore_sampF_rRdPtr_rsCounter[8] ; - assign z__h20496 = z__h20489 ^ adcCore_sampF_rRdPtr_rsCounter[9] ; - assign z__h7351 = + assign z__h20784 = z__h20777 ^ adcCore_sampF_rRdPtr_rsCounter[2] ; + assign z__h20791 = z__h20784 ^ adcCore_sampF_rRdPtr_rsCounter[3] ; + assign z__h20798 = z__h20791 ^ adcCore_sampF_rRdPtr_rsCounter[4] ; + assign z__h20805 = z__h20798 ^ adcCore_sampF_rRdPtr_rsCounter[5] ; + assign z__h20812 = z__h20805 ^ adcCore_sampF_rRdPtr_rsCounter[6] ; + assign z__h20819 = z__h20812 ^ adcCore_sampF_rRdPtr_rsCounter[7] ; + assign z__h20826 = z__h20819 ^ adcCore_sampF_rRdPtr_rsCounter[8] ; + assign z__h20833 = z__h20826 ^ adcCore_sampF_rRdPtr_rsCounter[9] ; + assign z__h7497 = fcAdc_grayCounter_rsCounter[0] ^ fcAdc_grayCounter_rsCounter[1] ; - assign z__h7358 = z__h7351 ^ fcAdc_grayCounter_rsCounter[2] ; - assign z__h7365 = z__h7358 ^ fcAdc_grayCounter_rsCounter[3] ; - assign z__h7372 = z__h7365 ^ fcAdc_grayCounter_rsCounter[4] ; - assign z__h7379 = z__h7372 ^ fcAdc_grayCounter_rsCounter[5] ; - assign z__h7386 = z__h7379 ^ fcAdc_grayCounter_rsCounter[6] ; - assign z__h7393 = z__h7386 ^ fcAdc_grayCounter_rsCounter[7] ; - assign z__h7400 = z__h7393 ^ fcAdc_grayCounter_rsCounter[8] ; - assign z__h7407 = z__h7400 ^ fcAdc_grayCounter_rsCounter[9] ; - assign z__h7414 = z__h7407 ^ fcAdc_grayCounter_rsCounter[10] ; - assign z__h7421 = z__h7414 ^ fcAdc_grayCounter_rsCounter[11] ; - assign z__h7428 = z__h7421 ^ fcAdc_grayCounter_rsCounter[12] ; - assign z__h7435 = z__h7428 ^ fcAdc_grayCounter_rsCounter[13] ; - assign z__h7442 = z__h7435 ^ fcAdc_grayCounter_rsCounter[14] ; - assign z__h7449 = z__h7442 ^ fcAdc_grayCounter_rsCounter[15] ; - assign z__h7456 = z__h7449 ^ fcAdc_grayCounter_rsCounter[16] ; + assign z__h7504 = z__h7497 ^ fcAdc_grayCounter_rsCounter[2] ; + assign z__h7511 = z__h7504 ^ fcAdc_grayCounter_rsCounter[3] ; + assign z__h7518 = z__h7511 ^ fcAdc_grayCounter_rsCounter[4] ; + assign z__h7525 = z__h7518 ^ fcAdc_grayCounter_rsCounter[5] ; + assign z__h7532 = z__h7525 ^ fcAdc_grayCounter_rsCounter[6] ; + assign z__h7539 = z__h7532 ^ fcAdc_grayCounter_rsCounter[7] ; + assign z__h7546 = z__h7539 ^ fcAdc_grayCounter_rsCounter[8] ; + assign z__h7553 = z__h7546 ^ fcAdc_grayCounter_rsCounter[9] ; + assign z__h7560 = z__h7553 ^ fcAdc_grayCounter_rsCounter[10] ; + assign z__h7567 = z__h7560 ^ fcAdc_grayCounter_rsCounter[11] ; + assign z__h7574 = z__h7567 ^ fcAdc_grayCounter_rsCounter[12] ; + assign z__h7581 = z__h7574 ^ fcAdc_grayCounter_rsCounter[13] ; + assign z__h7588 = z__h7581 ^ fcAdc_grayCounter_rsCounter[14] ; + assign z__h7595 = z__h7588 ^ fcAdc_grayCounter_rsCounter[15] ; + assign z__h7602 = z__h7595 ^ fcAdc_grayCounter_rsCounter[16] ; always@(adcCore_colGate_timeMesg or adcCore_colGate_dwellFails or adcCore_colGate_dwellStarts or @@ -3492,82 +3499,82 @@ module mkIQADCWorker(CLK_sys0_clk, adcCore_colGate_dropCount or wti_nowReq_BITS_63_TO_0__q1) begin case (adcCore_colGate_timeMesg) - 3'h1: x1_data__h14312 = adcCore_colGate_dwellStarts; - 3'h3: x1_data__h14312 = adcCore_colGate_sampCount; - 3'h4: x1_data__h14312 = adcCore_colGate_dropCount; - 3'h5: x1_data__h14312 = wti_nowReq_BITS_63_TO_0__q1[31:0]; - 3'h6: x1_data__h14312 = wti_nowReq_BITS_63_TO_0__q1[63:32]; - default: x1_data__h14312 = adcCore_colGate_dwellFails; + 3'h1: x1_data__h14550 = adcCore_colGate_dwellStarts; + 3'h3: x1_data__h14550 = adcCore_colGate_sampCount; + 3'h4: x1_data__h14550 = adcCore_colGate_dropCount; + 3'h5: x1_data__h14550 = wti_nowReq_BITS_63_TO_0__q1[31:0]; + 3'h6: x1_data__h14550 = wti_nowReq_BITS_63_TO_0__q1[63:32]; + default: x1_data__h14550 = adcCore_colGate_dwellFails; endcase end always@(wci_wslv_reqF$D_OUT or - rdat__h62743 or - adcStatusLs__h62461 or + rdat__h63382 or + adcStatusLs__h63100 or maxMesgLength or adcControl or - rdat__h62825 or + rdat__h63464 or adcCore_statsCC$dD_OUT or adcCore_sampCC$dD_OUT or - rdat__h62845 or + rdat__h63484 or mesgCount or lastOverflowMesg or wsiM_extStatusW$wget or overflowCountD) begin case (wci_wslv_reqF$D_OUT[39:32]) 8'h0: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = - rdat__h62743; + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = + rdat__h63382; 8'h04: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = - adcStatusLs__h62461; + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = + adcStatusLs__h63100; 8'h08: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = maxMesgLength; 8'h0C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = adcControl; 8'h10: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = 32'h20120625; 8'h14: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = - rdat__h62825; + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = + rdat__h63464; 8'h18: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = adcCore_statsCC$dD_OUT[95:64]; 8'h1C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = adcCore_sampCC$dD_OUT; 8'h30: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = - rdat__h62845; + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = + rdat__h63484; 8'h34: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = mesgCount; 8'h3C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = adcCore_statsCC$dD_OUT[63:32]; 8'h40: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = adcCore_statsCC$dD_OUT[31:0]; 8'h44: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = lastOverflowMesg; 8'h50: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = wsiM_extStatusW$wget[95:64]; 8'h54: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = wsiM_extStatusW$wget[63:32]; 8'h58: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = wsiM_extStatusW$wget[31:0]; 8'h5C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = adcCore_statsCC$dD_OUT[127:96]; 8'h60: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = overflowCountD; - default: IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1188 = + default: IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 = 32'd0; endcase end @@ -3583,7 +3590,7 @@ module mkIQADCWorker(CLK_sys0_clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin adcControl <= `BSV_ASSIGNMENT_DELAY 32'd0; adcCore_acquireDReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -3766,7 +3773,7 @@ module mkIQADCWorker(CLK_sys0_clk, always@(posedge CLK_adc_clock) begin - if (!adcCore_sdrRst$OUT_RST_N) + if (adcCore_sdrRst$OUT_RST == `BSV_RESET_VALUE) begin adcCore_colGate_avgEven <= `BSV_ASSIGNMENT_DELAY 18'd0; adcCore_colGate_avgOdd <= `BSV_ASSIGNMENT_DELAY 18'd0; @@ -3847,7 +3854,7 @@ module mkIQADCWorker(CLK_sys0_clk, always@(posedge adcCore_spiI_cd$CLK_OUT) begin - if (!adcCore_spiI_slowReset$OUT_RST_N) + if (adcCore_spiI_slowReset$OUT_RST == `BSV_RESET_VALUE) begin adcCore_spiI_cGate <= `BSV_ASSIGNMENT_DELAY 1'd0; adcCore_spiI_csbR <= `BSV_ASSIGNMENT_DELAY 1'b1; @@ -3910,8 +3917,8 @@ module mkIQADCWorker(CLK_sys0_clk, adcCore_spiI_sdiP <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_sdiP$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin adcCore_sampF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0; adcCore_sampF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0; @@ -3946,8 +3953,8 @@ module mkIQADCWorker(CLK_sys0_clk, wsiM_isReset_isInReset$D_IN; end - always@(posedge CLK_adc_clock or negedge adcCore_sdrRst$OUT_RST_N) - if (!adcCore_sdrRst$OUT_RST_N) + always@(posedge CLK_adc_clock or `BSV_RESET_EDGE adcCore_sdrRst$OUT_RST) + if (adcCore_sdrRst$OUT_RST == `BSV_RESET_VALUE) begin adcCore_sampF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0; adcCore_sampF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0; @@ -3970,12 +3977,17 @@ module mkIQADCWorker(CLK_sys0_clk, wti_isReset_isInReset$D_IN; end - always@(posedge CLK_adcCaptureClk) - begin - if (fcAdc_grayCounter_rsCounter$EN) - fcAdc_grayCounter_rsCounter <= `BSV_ASSIGNMENT_DELAY - fcAdc_grayCounter_rsCounter$D_IN; - end + always@(posedge CLK_adcCaptureClk or `BSV_RESET_EDGE !`BSV_RESET_VALUE) + if (!`BSV_RESET_VALUE == `BSV_RESET_VALUE) + begin + fcAdc_grayCounter_rsCounter <= `BSV_ASSIGNMENT_DELAY 18'd0; + end + else + begin + if (fcAdc_grayCounter_rsCounter$EN) + fcAdc_grayCounter_rsCounter <= `BSV_ASSIGNMENT_DELAY + fcAdc_grayCounter_rsCounter$D_IN; + end // synopsys translate_off `ifdef BSV_NO_INITIAL_BLOCKS @@ -4098,50 +4110,50 @@ module mkIQADCWorker(CLK_sys0_clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h62194 = $time; + v__h62822 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h62194, + v__h62822, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3622 = $time; + v__h3700 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3622, + v__h3700, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && MUX_splitReadInFlight$write_1__PSEL_1) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_get_adc_resp] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && MUX_splitReadInFlight$write_1__PSEL_1) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_get_adc_resp] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_OrE && MUX_splitReadInFlight$write_1__PSEL_1) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 74: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_OrE] and\n [RL_get_adc_resp] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (adcCore_iseqFsm_state_mkFSMstate == 4'd1 && (adcCore_iseqFsm_state_mkFSMstate == 4'd2 || WILL_FIRE_RL_adcCore_iseqFsm_action_np || @@ -4152,7 +4164,7 @@ module mkIQADCWorker(CLK_sys0_clk, WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 || WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)) $display("Error: \"bsv/dev/TI62P4X.bsv\", line 139, column 12: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l139c12] and\n [RL_adcCore_iseqFsm_action_d_init_np, RL_adcCore_iseqFsm_action_np,\n RL_adcCore_iseqFsm_action_l141c9, RL_adcCore_iseqFsm_action_l142c9,\n RL_adcCore_iseqFsm_action_l143c9, RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (adcCore_iseqFsm_state_mkFSMstate == 4'd2 && (WILL_FIRE_RL_adcCore_iseqFsm_action_np || WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 || @@ -4162,7 +4174,7 @@ module mkIQADCWorker(CLK_sys0_clk, WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 || WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)) $display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_d_init_np] and [RL_adcCore_iseqFsm_action_np,\n RL_adcCore_iseqFsm_action_l141c9, RL_adcCore_iseqFsm_action_l142c9,\n RL_adcCore_iseqFsm_action_l143c9, RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_adcCore_iseqFsm_action_np && (WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 || WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 || @@ -4171,7 +4183,14 @@ module mkIQADCWorker(CLK_sys0_clk, WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 || WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)) $display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_adcCore_iseqFsm_action_np]\n and [RL_adcCore_iseqFsm_action_l141c9, RL_adcCore_iseqFsm_action_l142c9,\n RL_adcCore_iseqFsm_action_l143c9, RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 && + (WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 || + WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 || + WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 || + WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)) + $display("Error: \"bsv/dev/TI62P4X.bsv\", line 142, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l142c9] and [RL_adcCore_iseqFsm_action_l143c9,\n RL_adcCore_iseqFsm_action_l144c9, RL_adcCore_iseqFsm_action_l145c9,\n RL_adcCore_iseqFsm_action_l146c9] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 && (WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 || WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 || @@ -4179,94 +4198,87 @@ module mkIQADCWorker(CLK_sys0_clk, WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 || WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)) $display("Error: \"bsv/dev/TI62P4X.bsv\", line 141, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l141c9] and [RL_adcCore_iseqFsm_action_l142c9,\n RL_adcCore_iseqFsm_action_l143c9, RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 && (WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 || WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 || WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)) $display("Error: \"bsv/dev/TI62P4X.bsv\", line 143, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l143c9] and [RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n"); - if (wciS0_MReset_n) - if (WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 && - (WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 || - WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 || - WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 || - WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)) - $display("Error: \"bsv/dev/TI62P4X.bsv\", line 142, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l142c9] and [RL_adcCore_iseqFsm_action_l143c9,\n RL_adcCore_iseqFsm_action_l144c9, RL_adcCore_iseqFsm_action_l145c9,\n RL_adcCore_iseqFsm_action_l146c9] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 && (WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 || WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)) $display("Error: \"bsv/dev/TI62P4X.bsv\", line 144, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l144c9] and [RL_adcCore_iseqFsm_action_l145c9,\n RL_adcCore_iseqFsm_action_l146c9] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 && WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9) $display("Error: \"bsv/dev/TI62P4X.bsv\", line 145, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l145c9] and [RL_adcCore_iseqFsm_action_l146c9] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h62680 = $time; + v__h63319 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h62680, + v__h63319, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - rdat__h62664); - if (wciS0_MReset_n) + rdat__h63303); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && MUX_splitReadInFlight$write_1__PSEL_1) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_get_adc_resp] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && MUX_splitReadInFlight$write_1__PSEL_1) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_get_adc_resp] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3940 = $time; + v__h4019 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3940, + v__h4019, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3796 = $time; + v__h3875 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3796, + v__h3875, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_adcCore_iseqFsm_action_l138c12 && (adcCore_iseqFsm_state_mkFSMstate == 4'd1 || adcCore_iseqFsm_state_mkFSMstate == 4'd2 || diff --git a/rtl/mkLedN210.v b/rtl/mkLedN210.v index 736392af..8fbf09d0 100644 --- a/rtl/mkLedN210.v +++ b/rtl/mkLedN210.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:37:41 EDT 2012 +// On Mon Sep 24 15:02:47 EDT 2012 // // // Ports: @@ -19,7 +19,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkLedN210(CLK, @@ -61,7 +69,7 @@ module mkLedN210(CLK, // remaining internal signals reg [4 : 0] CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1; - wire [4 : 0] x__h603, x__h604; + wire [4 : 0] x__h621, x__h622; // action method ledDrive assign RDY_ledDrive = 1'd1 ; @@ -70,7 +78,7 @@ module mkLedN210(CLK, assign led = doInit ? CASE_freeCnt_BITS_25_TO_23_3_0_IF_freeCnt_BIT__ETC__q1 : - ~x__h603 ; + ~x__h621 ; // register doInit assign doInit$D_IN = 1'd0 ; @@ -85,8 +93,8 @@ module mkLedN210(CLK, assign ledReg$EN = EN_ledDrive ; // remaining internal signals - assign x__h603 = x__h604 | ledReg ; - assign x__h604 = freeCnt[23] ? 5'h01 : 5'h0 ; + assign x__h621 = x__h622 | ledReg ; + assign x__h622 = freeCnt[23] ? 5'h01 : 5'h0 ; always@(freeCnt) begin case (freeCnt[25:23]) @@ -103,7 +111,7 @@ module mkLedN210(CLK, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin doInit <= `BSV_ASSIGNMENT_DELAY 1'd1; freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; diff --git a/rtl/mkOCCP.v b/rtl/mkOCCP.v index 612e2466..9c6fcc24 100644 --- a/rtl/mkOCCP.v +++ b/rtl/mkOCCP.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:39:57 EDT 2012 +// On Mon Sep 24 15:05:05 EDT 2012 // // // Ports: @@ -196,7 +196,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkOCCP(pciDevice, @@ -3337,49 +3345,49 @@ module mkOCCP(pciDevice, timeServ_setRefF$sFULL_N; // ports of submodule wci_mReset - wire wci_mReset$ASSERT_IN, wci_mReset$OUT_RST_N; + wire wci_mReset$ASSERT_IN, wci_mReset$OUT_RST; // ports of submodule wci_mReset_1 - wire wci_mReset_1$ASSERT_IN, wci_mReset_1$OUT_RST_N; + wire wci_mReset_1$ASSERT_IN, wci_mReset_1$OUT_RST; // ports of submodule wci_mReset_10 - wire wci_mReset_10$ASSERT_IN, wci_mReset_10$OUT_RST_N; + wire wci_mReset_10$ASSERT_IN, wci_mReset_10$OUT_RST; // ports of submodule wci_mReset_11 - wire wci_mReset_11$ASSERT_IN, wci_mReset_11$OUT_RST_N; + wire wci_mReset_11$ASSERT_IN, wci_mReset_11$OUT_RST; // ports of submodule wci_mReset_12 - wire wci_mReset_12$ASSERT_IN, wci_mReset_12$OUT_RST_N; + wire wci_mReset_12$ASSERT_IN, wci_mReset_12$OUT_RST; // ports of submodule wci_mReset_13 - wire wci_mReset_13$ASSERT_IN, wci_mReset_13$OUT_RST_N; + wire wci_mReset_13$ASSERT_IN, wci_mReset_13$OUT_RST; // ports of submodule wci_mReset_14 - wire wci_mReset_14$ASSERT_IN, wci_mReset_14$OUT_RST_N; + wire wci_mReset_14$ASSERT_IN, wci_mReset_14$OUT_RST; // ports of submodule wci_mReset_2 - wire wci_mReset_2$ASSERT_IN, wci_mReset_2$OUT_RST_N; + wire wci_mReset_2$ASSERT_IN, wci_mReset_2$OUT_RST; // ports of submodule wci_mReset_3 - wire wci_mReset_3$ASSERT_IN, wci_mReset_3$OUT_RST_N; + wire wci_mReset_3$ASSERT_IN, wci_mReset_3$OUT_RST; // ports of submodule wci_mReset_4 - wire wci_mReset_4$ASSERT_IN, wci_mReset_4$OUT_RST_N; + wire wci_mReset_4$ASSERT_IN, wci_mReset_4$OUT_RST; // ports of submodule wci_mReset_5 - wire wci_mReset_5$ASSERT_IN, wci_mReset_5$OUT_RST_N; + wire wci_mReset_5$ASSERT_IN, wci_mReset_5$OUT_RST; // ports of submodule wci_mReset_6 - wire wci_mReset_6$ASSERT_IN, wci_mReset_6$OUT_RST_N; + wire wci_mReset_6$ASSERT_IN, wci_mReset_6$OUT_RST; // ports of submodule wci_mReset_7 - wire wci_mReset_7$ASSERT_IN, wci_mReset_7$OUT_RST_N; + wire wci_mReset_7$ASSERT_IN, wci_mReset_7$OUT_RST; // ports of submodule wci_mReset_8 - wire wci_mReset_8$ASSERT_IN, wci_mReset_8$OUT_RST_N; + wire wci_mReset_8$ASSERT_IN, wci_mReset_8$OUT_RST; // ports of submodule wci_mReset_9 - wire wci_mReset_9$ASSERT_IN, wci_mReset_9$OUT_RST_N; + wire wci_mReset_9$ASSERT_IN, wci_mReset_9$OUT_RST; // ports of submodule wci_respF reg [33 : 0] wci_respF$D_IN; @@ -4255,263 +4263,263 @@ module mkOCCP(pciDevice, MUX_wrkAct$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h103101, - v__h103154, - v__h11627, - v__h11717, - v__h11806, - v__h12030, - v__h12120, - v__h12209, - v__h12438, - v__h12528, - v__h12617, - v__h15929, - v__h16019, - v__h16108, - v__h16332, - v__h16422, - v__h16511, - v__h16740, - v__h16830, - v__h16919, - v__h20231, - v__h20321, - v__h20410, - v__h20634, - v__h20724, - v__h20813, - v__h21042, - v__h21132, - v__h21221, - v__h24533, - v__h24623, - v__h24712, - v__h24936, - v__h25026, - v__h25115, - v__h25344, - v__h25434, - v__h25523, - v__h28835, - v__h28925, - v__h29014, - v__h29238, - v__h29328, - v__h29417, - v__h29646, - v__h29736, - v__h29825, - v__h33137, - v__h33227, - v__h33316, - v__h33540, - v__h33630, - v__h33719, - v__h33948, - v__h34038, - v__h34127, - v__h37439, - v__h37529, - v__h37618, - v__h37842, - v__h37932, - v__h38021, - v__h38250, - v__h38340, - v__h38429, - v__h41741, - v__h41831, - v__h41920, - v__h42144, - v__h42234, - v__h42323, - v__h42552, - v__h42642, - v__h42731, - v__h46043, - v__h46133, - v__h46222, - v__h46446, - v__h46536, - v__h46625, - v__h46854, - v__h46944, - v__h47033, - v__h50345, - v__h50435, - v__h50524, - v__h50748, - v__h50838, - v__h50927, - v__h51156, - v__h51246, - v__h51335, - v__h54647, - v__h54737, - v__h54826, - v__h55050, - v__h55140, - v__h55229, - v__h55458, - v__h55548, - v__h55637, - v__h58949, - v__h59039, - v__h59128, - v__h59352, - v__h59442, - v__h59531, - v__h59760, - v__h59850, - v__h59939, - v__h63251, - v__h63341, - v__h63430, - v__h63654, - v__h63744, - v__h63833, - v__h64062, - v__h64152, - v__h64241, - v__h67553, - v__h67643, - v__h67732, - v__h67956, - v__h68046, - v__h68135, - v__h68364, - v__h68454, - v__h68543, - v__h71855, - v__h71945, - v__h72034, - v__h72258, - v__h72348, - v__h72437, - v__h72666, - v__h72756, - v__h72845, - v__h77130, - v__h77788, - v__h78433, - v__h79078, - v__h79723, - v__h80368, - v__h81013, - v__h81658, - v__h82303, - v__h82948, - v__h83593, - v__h84238, - v__h84883, - v__h85528, - v__h86173, - v__h94113, - v__h94185, - v__h94257, - v__h94329, - v__h94401, - v__h94473, - v__h94545, - v__h94617, - v__h94689, - v__h94761, - v__h94833, - v__h94905, - v__h94977, - v__h95049, - v__h95121; + reg [63 : 0] v__h105472, + v__h105525, + v__h12056, + v__h12146, + v__h12235, + v__h12459, + v__h12549, + v__h12638, + v__h12867, + v__h12957, + v__h13046, + v__h16496, + v__h16586, + v__h16675, + v__h16899, + v__h16989, + v__h17078, + v__h17307, + v__h17397, + v__h17486, + v__h20936, + v__h21026, + v__h21115, + v__h21339, + v__h21429, + v__h21518, + v__h21747, + v__h21837, + v__h21926, + v__h25376, + v__h25466, + v__h25555, + v__h25779, + v__h25869, + v__h25958, + v__h26187, + v__h26277, + v__h26366, + v__h29816, + v__h29906, + v__h29995, + v__h30219, + v__h30309, + v__h30398, + v__h30627, + v__h30717, + v__h30806, + v__h34256, + v__h34346, + v__h34435, + v__h34659, + v__h34749, + v__h34838, + v__h35067, + v__h35157, + v__h35246, + v__h38696, + v__h38786, + v__h38875, + v__h39099, + v__h39189, + v__h39278, + v__h39507, + v__h39597, + v__h39686, + v__h43136, + v__h43226, + v__h43315, + v__h43539, + v__h43629, + v__h43718, + v__h43947, + v__h44037, + v__h44126, + v__h47576, + v__h47666, + v__h47755, + v__h47979, + v__h48069, + v__h48158, + v__h48387, + v__h48477, + v__h48566, + v__h52016, + v__h52106, + v__h52195, + v__h52419, + v__h52509, + v__h52598, + v__h52827, + v__h52917, + v__h53006, + v__h56456, + v__h56546, + v__h56635, + v__h56859, + v__h56949, + v__h57038, + v__h57267, + v__h57357, + v__h57446, + v__h60896, + v__h60986, + v__h61075, + v__h61299, + v__h61389, + v__h61478, + v__h61707, + v__h61797, + v__h61886, + v__h65336, + v__h65426, + v__h65515, + v__h65739, + v__h65829, + v__h65918, + v__h66147, + v__h66237, + v__h66326, + v__h69776, + v__h69866, + v__h69955, + v__h70179, + v__h70269, + v__h70358, + v__h70587, + v__h70677, + v__h70766, + v__h74216, + v__h74306, + v__h74395, + v__h74619, + v__h74709, + v__h74798, + v__h75027, + v__h75117, + v__h75206, + v__h79501, + v__h80159, + v__h80804, + v__h81449, + v__h82094, + v__h82739, + v__h83384, + v__h84029, + v__h84674, + v__h85319, + v__h85964, + v__h86609, + v__h87254, + v__h87899, + v__h88544, + v__h96484, + v__h96556, + v__h96628, + v__h96700, + v__h96772, + v__h96844, + v__h96916, + v__h96988, + v__h97060, + v__h97132, + v__h97204, + v__h97276, + v__h97348, + v__h97420, + v__h97492; reg [31 : 0] CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3, IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d6132, IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d6131, - rtnData__h109398; - reg IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130; + rtnData__h112042; + reg IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100; wire [49 : 0] _281474976710656_MINUS_timeServ_delSecond__q1, - x__h3445, - x__h4160, - x__h4388; - wire [47 : 0] x_f__h4586; + x__h3699, + x__h4420, + x__h4648; + wire [47 : 0] x_f__h4847; wire [32 : 0] IF_adminResp2F_notEmpty__304_THEN_adminResp2F__ETC___d2342; - wire [31 : 0] cpStatus__h73568, - crr_data__h74230, - toCount__h11335, - toCount__h15643, - toCount__h19945, - toCount__h24247, - toCount__h28549, - toCount__h32851, - toCount__h37153, - toCount__h41455, - toCount__h45757, - toCount__h50059, - toCount__h54361, - toCount__h58663, - toCount__h62965, - toCount__h67267, - toCount__h71569, - wciAddr__h75955, - wciAddr__h76023, - wciAddr__h76089, - wciAddr__h76155, - wciAddr__h76221, - wciAddr__h76287, - wciAddr__h76353, - wciAddr__h76419, - wciAddr__h76485, - wciAddr__h76551, - wciAddr__h76617, - wciAddr__h76683, - wciAddr__h76749, - wciAddr__h76815, - wciAddr__h76881, - x__h11494, - x__h15799, - x__h20101, - x__h24403, - x__h28705, - x__h33007, - x__h37309, - x__h41611, - x__h4453, - x__h45913, - x__h50215, - x__h54517, - x__h58819, - x__h63121, - x__h67423, - x__h71725, - x_addr__h95534, - x_data__h101740, - x_data__h101746, - x_data__h101793, - x_data__h101799, - x_data__h101846, - x_data__h101852, - x_data__h101899, - x_data__h101905, - x_data__h101952, - x_data__h101958, - x_data__h102005, - x_data__h102011, - x_data__h102058, - x_data__h102064, - x_data__h102111, - x_data__h102117, - x_data__h102164, - x_data__h102170, - x_data__h102217, - x_data__h102223, - x_data__h102270, - x_data__h102276, - x_data__h102323, - x_data__h102329, - x_data__h102376, - x_data__h102382, - x_data__h102429, - x_data__h102435, - x_data__h102482, - x_data__h102488; + wire [31 : 0] cpStatus__h75931, + crr_data__h76601, + toCount__h11763, + toCount__h16209, + toCount__h20649, + toCount__h25089, + toCount__h29529, + toCount__h33969, + toCount__h38409, + toCount__h42849, + toCount__h47289, + toCount__h51729, + toCount__h56169, + toCount__h60609, + toCount__h65049, + toCount__h69489, + toCount__h73929, + wciAddr__h78326, + wciAddr__h78394, + wciAddr__h78460, + wciAddr__h78526, + wciAddr__h78592, + wciAddr__h78658, + wciAddr__h78724, + wciAddr__h78790, + wciAddr__h78856, + wciAddr__h78922, + wciAddr__h78988, + wciAddr__h79054, + wciAddr__h79120, + wciAddr__h79186, + wciAddr__h79252, + x__h11923, + x__h16366, + x__h20806, + x__h25246, + x__h29686, + x__h34126, + x__h38566, + x__h43006, + x__h4714, + x__h47446, + x__h51886, + x__h56326, + x__h60766, + x__h65206, + x__h69646, + x__h74086, + x_addr__h97905, + x_data__h104111, + x_data__h104117, + x_data__h104164, + x_data__h104170, + x_data__h104217, + x_data__h104223, + x_data__h104270, + x_data__h104276, + x_data__h104323, + x_data__h104329, + x_data__h104376, + x_data__h104382, + x_data__h104429, + x_data__h104435, + x_data__h104482, + x_data__h104488, + x_data__h104535, + x_data__h104541, + x_data__h104588, + x_data__h104594, + x_data__h104641, + x_data__h104647, + x_data__h104694, + x_data__h104700, + x_data__h104747, + x_data__h104753, + x_data__h104800, + x_data__h104806, + x_data__h104853, + x_data__h104859; wire [26 : 0] IF_wci_lastControlOp_10_713_BIT_3_714_THEN_wci_ETC___d1728, IF_wci_lastControlOp_11_853_BIT_3_854_THEN_wci_ETC___d1868, IF_wci_lastControlOp_12_993_BIT_3_994_THEN_wci_ETC___d2008, @@ -4527,14 +4535,14 @@ module mkOCCP(pciDevice, IF_wci_lastControlOp_7_293_BIT_3_294_THEN_wci__ETC___d1308, IF_wci_lastControlOp_8_433_BIT_3_434_THEN_wci__ETC___d1448, IF_wci_lastControlOp_9_573_BIT_3_574_THEN_wci__ETC___d1588; - wire [23 : 0] bAddr__h109903, bAddr__h110451; + wire [23 : 0] bAddr__h112551, bAddr__h113011; wire [21 : 0] _281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2; - wire [14 : 0] x__h103324, x__h103873; - wire [4 : 0] x__h95536; - wire [3 : 0] _theResult_____1__h74424, - _theResult_____1__h74442, - wn___1__h75213, - wn__h74423; + wire [14 : 0] x__h105695, x__h106244; + wire [4 : 0] x__h97907; + wire [3 : 0] _theResult_____1__h76795, + _theResult_____1__h76813, + wn___1__h77584, + wn__h76794; wire [2 : 0] rom_serverAdapter_cnt_29_PLUS_IF_rom_serverAda_ETC___d135; wire IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d3903, IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d3912, @@ -4581,7 +4589,7 @@ module mkOCCP(pciDevice, IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4969, IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4978, IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4988, - IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5440, + IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d6037, NOT_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_649_ETC___d2712, NOT_cpReq_363_BITS_64_TO_62_364_EQ_0_852_857_A_ETC___d5044, NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d3947, @@ -4681,23 +4689,23 @@ module mkOCCP(pciDevice, cpReq_363_BIT_36_910_AND_NOT_wci_busy_9_496_45_ETC___d3474, timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d61, timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d70, - timeServ_refFromRise_3_ULE_199800000___d5430, - timeServ_refFromRise_3_ULT_200200000___d5853, - wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864, - wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865, - wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866, - wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867, - wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868, - wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855, - wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854, - wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856, - wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857, - wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858, - wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859, - wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860, - wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861, - wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862, - wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863, + timeServ_refFromRise_3_ULE_199800000___d5433, + timeServ_refFromRise_3_ULT_200200000___d5848, + wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858, + wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859, + wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860, + wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861, + wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862, + wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850, + wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849, + wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453, + wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851, + wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852, + wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853, + wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854, + wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855, + wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856, + wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857, wci_wReset_n_10_616_AND_NOT_wci_busy_10_636_51_ETC___d3515, wci_wReset_n_11_756_AND_NOT_wci_busy_11_776_57_ETC___d3577, wci_wReset_n_12_896_AND_NOT_wci_busy_12_916_63_ETC___d3639, @@ -4730,21 +4738,21 @@ module mkOCCP(pciDevice, wci_wciResponse_wget__23_BITS_33_TO_32_24_EQ_0_ETC___d252; // output resets - assign RST_N_wci_Vm_0 = wci_mReset$OUT_RST_N ; - assign RST_N_wci_Vm_1 = wci_mReset_1$OUT_RST_N ; - assign RST_N_wci_Vm_2 = wci_mReset_2$OUT_RST_N ; - assign RST_N_wci_Vm_3 = wci_mReset_3$OUT_RST_N ; - assign RST_N_wci_Vm_4 = wci_mReset_4$OUT_RST_N ; - assign RST_N_wci_Vm_5 = wci_mReset_5$OUT_RST_N ; - assign RST_N_wci_Vm_6 = wci_mReset_6$OUT_RST_N ; - assign RST_N_wci_Vm_7 = wci_mReset_7$OUT_RST_N ; - assign RST_N_wci_Vm_8 = wci_mReset_8$OUT_RST_N ; - assign RST_N_wci_Vm_9 = wci_mReset_9$OUT_RST_N ; - assign RST_N_wci_Vm_10 = wci_mReset_10$OUT_RST_N ; - assign RST_N_wci_Vm_11 = wci_mReset_11$OUT_RST_N ; - assign RST_N_wci_Vm_12 = wci_mReset_12$OUT_RST_N ; - assign RST_N_wci_Vm_13 = wci_mReset_13$OUT_RST_N ; - assign RST_N_wci_Vm_14 = wci_mReset_14$OUT_RST_N ; + assign RST_N_wci_Vm_0 = wci_mReset$OUT_RST ; + assign RST_N_wci_Vm_1 = wci_mReset_1$OUT_RST ; + assign RST_N_wci_Vm_2 = wci_mReset_2$OUT_RST ; + assign RST_N_wci_Vm_3 = wci_mReset_3$OUT_RST ; + assign RST_N_wci_Vm_4 = wci_mReset_4$OUT_RST ; + assign RST_N_wci_Vm_5 = wci_mReset_5$OUT_RST ; + assign RST_N_wci_Vm_6 = wci_mReset_6$OUT_RST ; + assign RST_N_wci_Vm_7 = wci_mReset_7$OUT_RST ; + assign RST_N_wci_Vm_8 = wci_mReset_8$OUT_RST ; + assign RST_N_wci_Vm_9 = wci_mReset_9$OUT_RST ; + assign RST_N_wci_Vm_10 = wci_mReset_10$OUT_RST ; + assign RST_N_wci_Vm_11 = wci_mReset_11$OUT_RST ; + assign RST_N_wci_Vm_12 = wci_mReset_12$OUT_RST ; + assign RST_N_wci_Vm_13 = wci_mReset_13$OUT_RST ; + assign RST_N_wci_Vm_14 = wci_mReset_14$OUT_RST ; // action method server_request_put assign RDY_server_request_put = cpReqF$FULL_N ; @@ -5076,7 +5084,7 @@ module mkOCCP(pciDevice, assign led = scratch24[1:0] ; // submodule adminResp1F - FIFO1 #(.width(32'd33), .guarded(32'd1)) adminResp1F(.RST_N(RST_N), + FIFO1 #(.width(32'd33), .guarded(32'd1)) adminResp1F(.RST(RST_N), .CLK(CLK), .D_IN(adminResp1F$D_IN), .ENQ(adminResp1F$ENQ), @@ -5087,7 +5095,7 @@ module mkOCCP(pciDevice, .EMPTY_N(adminResp1F$EMPTY_N)); // submodule adminResp2F - FIFO1 #(.width(32'd33), .guarded(32'd1)) adminResp2F(.RST_N(RST_N), + FIFO1 #(.width(32'd33), .guarded(32'd1)) adminResp2F(.RST(RST_N), .CLK(CLK), .D_IN(adminResp2F$D_IN), .ENQ(adminResp2F$ENQ), @@ -5098,7 +5106,7 @@ module mkOCCP(pciDevice, .EMPTY_N(adminResp2F$EMPTY_N)); // submodule adminResp3F - FIFO1 #(.width(32'd33), .guarded(32'd1)) adminResp3F(.RST_N(RST_N), + FIFO1 #(.width(32'd33), .guarded(32'd1)) adminResp3F(.RST(RST_N), .CLK(CLK), .D_IN(adminResp3F$D_IN), .ENQ(adminResp3F$ENQ), @@ -5109,7 +5117,7 @@ module mkOCCP(pciDevice, .EMPTY_N(adminResp3F$EMPTY_N)); // submodule adminResp4F - FIFO1 #(.width(32'd33), .guarded(32'd1)) adminResp4F(.RST_N(RST_N), + FIFO1 #(.width(32'd33), .guarded(32'd1)) adminResp4F(.RST(RST_N), .CLK(CLK), .D_IN(adminResp4F$D_IN), .ENQ(adminResp4F$ENQ), @@ -5120,7 +5128,7 @@ module mkOCCP(pciDevice, .EMPTY_N(adminResp4F$EMPTY_N)); // submodule adminRespF - FIFO1 #(.width(32'd33), .guarded(32'd1)) adminRespF(.RST_N(RST_N), + FIFO1 #(.width(32'd33), .guarded(32'd1)) adminRespF(.RST(RST_N), .CLK(CLK), .D_IN(adminRespF$D_IN), .ENQ(adminRespF$ENQ), @@ -5131,7 +5139,7 @@ module mkOCCP(pciDevice, .EMPTY_N(adminRespF$EMPTY_N)); // submodule cpReqF - FIFO2 #(.width(32'd59), .guarded(32'd1)) cpReqF(.RST_N(RST_N), + FIFO2 #(.width(32'd59), .guarded(32'd1)) cpReqF(.RST(RST_N), .CLK(CLK), .D_IN(cpReqF$D_IN), .ENQ(cpReqF$ENQ), @@ -5142,7 +5150,7 @@ module mkOCCP(pciDevice, .EMPTY_N(cpReqF$EMPTY_N)); // submodule cpRespF - FIFO2 #(.width(32'd40), .guarded(32'd1)) cpRespF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) cpRespF(.RST(RST_N), .CLK(CLK), .D_IN(cpRespF$D_IN), .ENQ(cpRespF$ENQ), @@ -5176,7 +5184,7 @@ module mkOCCP(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) rom_serverAdapter_outDataCore(.RST_N(RST_N), + .guarded(32'd1)) rom_serverAdapter_outDataCore(.RST(RST_N), .CLK(CLK), .D_IN(rom_serverAdapter_outDataCore$D_IN), .ENQ(rom_serverAdapter_outDataCore$ENQ), @@ -5189,7 +5197,7 @@ module mkOCCP(pciDevice, // submodule timeServ_disableServo SyncRegister #(.width(32'd1), .init(1'd0)) timeServ_disableServo(.sCLK(CLK), .dCLK(CLK_time_clk), - .sRST_N(RST_N), + .sRST(RST_N), .sD_IN(timeServ_disableServo$sD_IN), .sEN(timeServ_disableServo$sEN), .dD_OUT(timeServ_disableServo$dD_OUT), @@ -5199,7 +5207,7 @@ module mkOCCP(pciDevice, SyncRegister #(.width(32'd64), .init(64'd0)) timeServ_nowInCC(.sCLK(CLK_time_clk), .dCLK(CLK), - .sRST_N(RST_N_time_rst), + .sRST(RST_N_time_rst), .sD_IN(timeServ_nowInCC$sD_IN), .sEN(timeServ_nowInCC$sEN), .dD_OUT(timeServ_nowInCC$dD_OUT), @@ -5209,7 +5217,7 @@ module mkOCCP(pciDevice, SyncRegister #(.width(32'd1), .init(1'd0)) timeServ_ppsDisablePPS(.sCLK(CLK), .dCLK(CLK_time_clk), - .sRST_N(RST_N), + .sRST(RST_N), .sD_IN(timeServ_ppsDisablePPS$sD_IN), .sEN(timeServ_ppsDisablePPS$sEN), .dD_OUT(timeServ_ppsDisablePPS$dD_OUT), @@ -5219,7 +5227,7 @@ module mkOCCP(pciDevice, SyncRegister #(.width(32'd1), .init(1'd0)) timeServ_ppsLostCC(.sCLK(CLK_time_clk), .dCLK(CLK), - .sRST_N(RST_N_time_rst), + .sRST(RST_N_time_rst), .sD_IN(timeServ_ppsLostCC$sD_IN), .sEN(timeServ_ppsLostCC$sEN), .dD_OUT(timeServ_ppsLostCC$dD_OUT), @@ -5229,7 +5237,7 @@ module mkOCCP(pciDevice, SyncRegister #(.width(32'd1), .init(1'd0)) timeServ_ppsOKCC(.sCLK(CLK_time_clk), .dCLK(CLK), - .sRST_N(RST_N_time_rst), + .sRST(RST_N_time_rst), .sD_IN(timeServ_ppsOKCC$sD_IN), .sEN(timeServ_ppsOKCC$sEN), .dD_OUT(timeServ_ppsOKCC$dD_OUT), @@ -5238,7 +5246,7 @@ module mkOCCP(pciDevice, // submodule timeServ_ppsOutMode SyncRegister #(.width(32'd2), .init(2'd0)) timeServ_ppsOutMode(.sCLK(CLK), .dCLK(CLK_time_clk), - .sRST_N(RST_N), + .sRST(RST_N), .sD_IN(timeServ_ppsOutMode$sD_IN), .sEN(timeServ_ppsOutMode$sEN), .dD_OUT(timeServ_ppsOutMode$dD_OUT), @@ -5248,7 +5256,7 @@ module mkOCCP(pciDevice, SyncRegister #(.width(32'd28), .init(28'd0)) timeServ_refPerPPS(.sCLK(CLK_time_clk), .dCLK(CLK), - .sRST_N(RST_N_time_rst), + .sRST(RST_N_time_rst), .sD_IN(timeServ_refPerPPS$sD_IN), .sEN(timeServ_refPerPPS$sEN), .dD_OUT(timeServ_refPerPPS$dD_OUT), @@ -5258,7 +5266,7 @@ module mkOCCP(pciDevice, SyncRegister #(.width(32'd8), .init(8'd0)) timeServ_rollingPPSIn(.sCLK(CLK_time_clk), .dCLK(CLK), - .sRST_N(RST_N_time_rst), + .sRST(RST_N_time_rst), .sD_IN(timeServ_rollingPPSIn$sD_IN), .sEN(timeServ_rollingPPSIn$sEN), .dD_OUT(timeServ_rollingPPSIn$dD_OUT), @@ -5269,7 +5277,7 @@ module mkOCCP(pciDevice, .depth(32'd2), .indxWidth(32'd1)) timeServ_setRefF(.sCLK(CLK), .dCLK(CLK_time_clk), - .sRST_N(RST_N), + .sRST(RST_N), .sD_IN(timeServ_setRefF$sD_IN), .sENQ(timeServ_setRefF$sENQ), .dDEQ(timeServ_setRefF$dDEQ), @@ -5279,126 +5287,126 @@ module mkOCCP(pciDevice, // submodule wci_mReset MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset$OUT_RST_N)); + .OUT_RST(wci_mReset$OUT_RST)); // submodule wci_mReset_1 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_1(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_1$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_1$OUT_RST_N)); + .OUT_RST(wci_mReset_1$OUT_RST)); // submodule wci_mReset_10 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_10(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_10$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_10$OUT_RST_N)); + .OUT_RST(wci_mReset_10$OUT_RST)); // submodule wci_mReset_11 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_11(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_11$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_11$OUT_RST_N)); + .OUT_RST(wci_mReset_11$OUT_RST)); // submodule wci_mReset_12 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_12(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_12$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_12$OUT_RST_N)); + .OUT_RST(wci_mReset_12$OUT_RST)); // submodule wci_mReset_13 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_13(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_13$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_13$OUT_RST_N)); + .OUT_RST(wci_mReset_13$OUT_RST)); // submodule wci_mReset_14 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_14(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_14$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_14$OUT_RST_N)); + .OUT_RST(wci_mReset_14$OUT_RST)); // submodule wci_mReset_2 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_2(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_2$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_2$OUT_RST_N)); + .OUT_RST(wci_mReset_2$OUT_RST)); // submodule wci_mReset_3 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_3(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_3$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_3$OUT_RST_N)); + .OUT_RST(wci_mReset_3$OUT_RST)); // submodule wci_mReset_4 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_4(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_4$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_4$OUT_RST_N)); + .OUT_RST(wci_mReset_4$OUT_RST)); // submodule wci_mReset_5 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_5(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_5$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_5$OUT_RST_N)); + .OUT_RST(wci_mReset_5$OUT_RST)); // submodule wci_mReset_6 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_6(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_6$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_6$OUT_RST_N)); + .OUT_RST(wci_mReset_6$OUT_RST)); // submodule wci_mReset_7 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_7(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_7$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_7$OUT_RST_N)); + .OUT_RST(wci_mReset_7$OUT_RST)); // submodule wci_mReset_8 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_8(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_8$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_8$OUT_RST_N)); + .OUT_RST(wci_mReset_8$OUT_RST)); // submodule wci_mReset_9 MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_9(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(wci_mReset_9$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(wci_mReset_9$OUT_RST_N)); + .OUT_RST(wci_mReset_9$OUT_RST)); // submodule wci_respF - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF$D_IN), .ENQ(wci_respF$ENQ), @@ -5409,7 +5417,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF$EMPTY_N)); // submodule wci_respF_1 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_1(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_1(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_1$D_IN), .ENQ(wci_respF_1$ENQ), @@ -5420,7 +5428,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_1$EMPTY_N)); // submodule wci_respF_10 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_10(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_10(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_10$D_IN), .ENQ(wci_respF_10$ENQ), @@ -5431,7 +5439,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_10$EMPTY_N)); // submodule wci_respF_11 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_11(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_11(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_11$D_IN), .ENQ(wci_respF_11$ENQ), @@ -5442,7 +5450,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_11$EMPTY_N)); // submodule wci_respF_12 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_12(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_12(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_12$D_IN), .ENQ(wci_respF_12$ENQ), @@ -5453,7 +5461,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_12$EMPTY_N)); // submodule wci_respF_13 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_13(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_13(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_13$D_IN), .ENQ(wci_respF_13$ENQ), @@ -5464,7 +5472,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_13$EMPTY_N)); // submodule wci_respF_14 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_14(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_14(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_14$D_IN), .ENQ(wci_respF_14$ENQ), @@ -5475,7 +5483,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_14$EMPTY_N)); // submodule wci_respF_2 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_2(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_2(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_2$D_IN), .ENQ(wci_respF_2$ENQ), @@ -5486,7 +5494,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_2$EMPTY_N)); // submodule wci_respF_3 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_3(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_3(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_3$D_IN), .ENQ(wci_respF_3$ENQ), @@ -5497,7 +5505,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_3$EMPTY_N)); // submodule wci_respF_4 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_4(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_4(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_4$D_IN), .ENQ(wci_respF_4$ENQ), @@ -5508,7 +5516,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_4$EMPTY_N)); // submodule wci_respF_5 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_5(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_5(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_5$D_IN), .ENQ(wci_respF_5$ENQ), @@ -5519,7 +5527,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_5$EMPTY_N)); // submodule wci_respF_6 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_6(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_6(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_6$D_IN), .ENQ(wci_respF_6$ENQ), @@ -5530,7 +5538,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_6$EMPTY_N)); // submodule wci_respF_7 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_7(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_7(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_7$D_IN), .ENQ(wci_respF_7$ENQ), @@ -5541,7 +5549,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_7$EMPTY_N)); // submodule wci_respF_8 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_8(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_8(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_8$D_IN), .ENQ(wci_respF_8$ENQ), @@ -5552,7 +5560,7 @@ module mkOCCP(pciDevice, .EMPTY_N(wci_respF_8$EMPTY_N)); // submodule wci_respF_9 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_9(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_9(.RST(RST_N), .CLK(CLK), .D_IN(wci_respF_9$D_IN), .ENQ(wci_respF_9$ENQ), @@ -5572,16 +5580,6 @@ module mkOCCP(pciDevice, adminRespF$FULL_N && adminResp3F$EMPTY_N : !adminResp4F$EMPTY_N || adminRespF$FULL_N)) ; - // rule RL_cpDispatch_F_T_T_T - assign CAN_FIRE_RL_cpDispatch_F_T_T_T = - cpReq[64:62] == 3'd2 && - cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && - cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && - adminResp1F$FULL_N && - !dispatched ; - assign WILL_FIRE_RL_cpDispatch_F_T_T_T = - CAN_FIRE_RL_cpDispatch_F_T_T_T && !WILL_FIRE_RL_responseAdminRd ; - // rule RL_cpDispatch_T_T assign WILL_FIRE_RL_cpDispatch_T_T = cpReq[64:62] == 3'd1 && cpReq[11:4] == 8'h20 && !dispatched ; @@ -5634,6 +5632,16 @@ module mkOCCP(pciDevice, cpReq[11:4] != 8'h4C && !dispatched ; + // rule RL_cpDispatch_F_T_T_T + assign CAN_FIRE_RL_cpDispatch_F_T_T_T = + cpReq[64:62] == 3'd2 && + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && + adminResp1F$FULL_N && + !dispatched ; + assign WILL_FIRE_RL_cpDispatch_F_T_T_T = + CAN_FIRE_RL_cpDispatch_F_T_T_T && !WILL_FIRE_RL_responseAdminRd ; + // rule RL_cpDispatch_F_T_T_F_T_T assign CAN_FIRE_RL_cpDispatch_F_T_T_F_T_T = cpReq[64:62] == 3'd2 && @@ -5699,14 +5707,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd0 && cpReq[61:60] == 2'd2 && !wci_wReset_n && NOT_wci_busy_36_872_AND_wci_wReset_n_16_OR_wci_ETC___d2890 ; // rule RL_cpDispatch_F_F_T_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd0 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy && @@ -5715,14 +5723,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd0 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d2939 ; // rule RL_cpDispatch_F_F_T_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd0 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -5730,14 +5738,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd1 && cpReq[61:60] == 2'd2 && !wci_wReset_n_1 && NOT_wci_busy_1_76_954_AND_wci_wReset_n_1_56_OR_ETC___d2967 ; // rule RL_cpDispatch_F_F_T_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd1 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_1 && @@ -5746,21 +5754,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd1 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3004 ; - // rule RL_cpDispatch_F_F_T_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd2 && - cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3066 ; - // rule RL_cpDispatch_F_F_T_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd1 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -5768,23 +5769,30 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd2 && cpReq[61:60] == 2'd2 && !wci_wReset_n_2 && NOT_wci_busy_2_16_016_AND_wci_wReset_n_2_96_OR_ETC___d3029 ; // rule RL_cpDispatch_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd2 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_2 && wci_respF_2$FULL_N && !dispatched ; + // rule RL_cpDispatch_F_F_T_F_F_T_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd2 && + cpReq[61:60] != 2'd2 && + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3066 ; + // rule RL_cpDispatch_F_F_T_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd2 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -5792,14 +5800,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd3 && cpReq[61:60] == 2'd2 && !wci_wReset_n_3 && NOT_wci_busy_3_56_078_AND_wci_wReset_n_3_36_OR_ETC___d3091 ; // rule RL_cpDispatch_F_F_T_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd3 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_3 && @@ -5808,14 +5816,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd3 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3128 ; // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd3 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -5823,14 +5831,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd4 && cpReq[61:60] == 2'd2 && !wci_wReset_n_4 && NOT_wci_busy_4_96_140_AND_wci_wReset_n_4_76_OR_ETC___d3153 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd4 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_4 && @@ -5839,14 +5847,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd4 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3190 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd4 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -5854,45 +5862,45 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd5 && cpReq[61:60] == 2'd2 && !wci_wReset_n_5 && NOT_wci_busy_5_36_202_AND_wci_wReset_n_5_16_OR_ETC___d3215 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd5 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_5 && wci_respF_5$FULL_N && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd6 && - cpReq[61:60] == 2'd2 && - !wci_wReset_n_6 && - NOT_wci_busy_6_076_264_AND_wci_wReset_n_6_056__ETC___d3277 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd5 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3252 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd5 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3257 ; + // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd6 && + cpReq[61:60] == 2'd2 && + !wci_wReset_n_6 && + NOT_wci_busy_6_076_264_AND_wci_wReset_n_6_056__ETC___d3277 ; + // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd6 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_6 && @@ -5901,14 +5909,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd6 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3314 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd6 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -5916,14 +5924,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd7 && cpReq[61:60] == 2'd2 && !wci_wReset_n_7 && NOT_wci_busy_7_216_326_AND_wci_wReset_n_7_196__ETC___d3339 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd7 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_7 && @@ -5932,14 +5940,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd7 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3376 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd7 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -5947,14 +5955,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd8 && cpReq[61:60] == 2'd2 && !wci_wReset_n_8 && NOT_wci_busy_8_356_388_AND_wci_wReset_n_8_336__ETC___d3401 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd8 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_8 && @@ -5963,14 +5971,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd8 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3438 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd8 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -5978,14 +5986,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd9 && cpReq[61:60] == 2'd2 && !wci_wReset_n_9 && NOT_wci_busy_9_496_450_AND_wci_wReset_n_9_476__ETC___d3463 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd9 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_9 && @@ -5994,14 +6002,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd9 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3500 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd9 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -6009,30 +6017,30 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd10 && cpReq[61:60] == 2'd2 && !wci_wReset_n_10 && NOT_wci_busy_10_636_512_AND_wci_wReset_n_10_61_ETC___d3525 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd10 && - cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3562 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd10 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_10 && wci_respF_10$FULL_N && !dispatched ; + // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd10 && + cpReq[61:60] != 2'd2 && + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3562 ; + // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd10 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -6040,14 +6048,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd11 && cpReq[61:60] == 2'd2 && !wci_wReset_n_11 && NOT_wci_busy_11_776_574_AND_wci_wReset_n_11_75_ETC___d3587 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd11 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_11 && @@ -6056,14 +6064,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd11 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3624 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd11 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -6071,14 +6079,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd12 && cpReq[61:60] == 2'd2 && !wci_wReset_n_12 && NOT_wci_busy_12_916_636_AND_wci_wReset_n_12_89_ETC___d3649 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd12 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_12 && @@ -6087,14 +6095,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd12 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3686 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd12 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -6102,14 +6110,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd13 && cpReq[61:60] == 2'd2 && !wci_wReset_n_13 && NOT_wci_busy_13_056_698_AND_wci_wReset_n_13_03_ETC___d3711 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd13 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_13 && @@ -6118,14 +6126,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd13 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3748 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd13 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && @@ -6133,14 +6141,14 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd14 && cpReq[61:60] == 2'd2 && !wci_wReset_n_14 && NOT_wci_busy_14_196_760_AND_wci_wReset_n_14_17_ETC___d3773 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd14 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_busy_14 && @@ -6149,47 +6157,36 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd14 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3810 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd14 && cpReq[61:60] != 2'd2 && (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h9 && NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3815 ; - // rule RL_cpDispatch_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd0 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n && - NOT_wci_busy_36_872_AND_wci_wReset_n_16_OR_wci_ETC___d2890 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 != 4'd0 && - _theResult_____1__h74424 != 4'd1 && - _theResult_____1__h74424 != 4'd2 && - _theResult_____1__h74424 != 4'd3 && - _theResult_____1__h74424 != 4'd4 && - _theResult_____1__h74424 != 4'd5 && - _theResult_____1__h74424 != 4'd6 && - _theResult_____1__h74424 != 4'd7 && - _theResult_____1__h74424 != 4'd8 && - _theResult_____1__h74424 != 4'd9 && - _theResult_____1__h74424 != 4'd10 && - _theResult_____1__h74424 != 4'd11 && - _theResult_____1__h74424 != 4'd12 && - _theResult_____1__h74424 != 4'd13 && - _theResult_____1__h74424 != 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 != 4'd0 && + _theResult_____1__h76795 != 4'd1 && + _theResult_____1__h76795 != 4'd2 && + _theResult_____1__h76795 != 4'd3 && + _theResult_____1__h76795 != 4'd4 && + _theResult_____1__h76795 != 4'd5 && + _theResult_____1__h76795 != 4'd6 && + _theResult_____1__h76795 != 4'd7 && + _theResult_____1__h76795 != 4'd8 && + _theResult_____1__h76795 != 4'd9 && + _theResult_____1__h76795 != 4'd10 && + _theResult_____1__h76795 != 4'd11 && + _theResult_____1__h76795 != 4'd12 && + _theResult_____1__h76795 != 4'd13 && + _theResult_____1__h76795 != 4'd14 && !dispatched ; // rule RL_cpDispatch_F_F_F_T @@ -6201,11 +6198,22 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd0 && + _theResult_____1__h76813 == 4'd0 && cpReq[37:36] == 2'd2 && !wci_wReset_n && NOT_wci_busy_36_872_AND_wci_wReset_n_16_OR_wci_ETC___d2890 ; + // rule RL_cpDispatch_F_F_F_F_T_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F = + cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && + cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h76813 == 4'd0 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_wReset_n && + NOT_wci_busy_36_872_AND_wci_wReset_n_16_OR_wci_ETC___d2890 ; + // rule RL_cpDispatch_F_F_F_F_T_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && @@ -6232,7 +6240,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd0 && + _theResult_____1__h76813 == 4'd0 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d2939 ; @@ -6247,7 +6255,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd1 && + _theResult_____1__h76813 == 4'd1 && cpReq[37:36] == 2'd2 && !wci_wReset_n_1 && NOT_wci_busy_1_76_954_AND_wci_wReset_n_1_56_OR_ETC___d2967 ; @@ -6257,7 +6265,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd1 && + _theResult_____1__h76813 == 4'd1 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_1 && @@ -6270,26 +6278,26 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd0 && IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d3981 ; - // rule RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_F_T_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4000 ; + IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d3990 ; - // rule RL_cpDispatch_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d3990 ; + IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4000 ; // rule RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd1 && + _theResult_____1__h76813 == 4'd1 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3004 ; @@ -6304,7 +6312,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd2 && + _theResult_____1__h76813 == 4'd2 && cpReq[37:36] == 2'd2 && !wci_wReset_n_2 && NOT_wci_busy_2_16_016_AND_wci_wReset_n_2_96_OR_ETC___d3029 ; @@ -6314,7 +6322,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd2 && + _theResult_____1__h76813 == 4'd2 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_2 && @@ -6346,7 +6354,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd2 && + _theResult_____1__h76813 == 4'd2 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3066 ; @@ -6361,7 +6369,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd3 && + _theResult_____1__h76813 == 4'd3 && cpReq[37:36] == 2'd2 && !wci_wReset_n_3 && NOT_wci_busy_3_56_078_AND_wci_wReset_n_3_36_OR_ETC___d3091 ; @@ -6371,7 +6379,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd3 && + _theResult_____1__h76813 == 4'd3 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_3 && @@ -6384,26 +6392,26 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd0 && IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4133 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4152 ; + IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4142 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4142 ; + IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4152 ; // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd3 && + _theResult_____1__h76813 == 4'd3 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3128 ; @@ -6418,7 +6426,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd4 && + _theResult_____1__h76813 == 4'd4 && cpReq[37:36] == 2'd2 && !wci_wReset_n_4 && NOT_wci_busy_4_96_140_AND_wci_wReset_n_4_76_OR_ETC___d3153 ; @@ -6428,7 +6436,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd4 && + _theResult_____1__h76813 == 4'd4 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_4 && @@ -6460,7 +6468,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd4 && + _theResult_____1__h76813 == 4'd4 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3190 ; @@ -6475,7 +6483,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd5 && + _theResult_____1__h76813 == 4'd5 && cpReq[37:36] == 2'd2 && !wci_wReset_n_5 && NOT_wci_busy_5_36_202_AND_wci_wReset_n_5_16_OR_ETC___d3215 ; @@ -6485,17 +6493,12 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd5 && + _theResult_____1__h76813 == 4'd5 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_5 && NOT_wci_busy_5_36_202_AND_wci_wReset_n_5_16_OR_ETC___d3215 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4327 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && @@ -6522,17 +6525,22 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd5 && + _theResult_____1__h76813 == 4'd5 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3252 ; + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = + cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4327 ; + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd6 && + _theResult_____1__h76813 == 4'd6 && cpReq[37:36] == 2'd2 && !wci_wReset_n_6 && NOT_wci_busy_6_076_264_AND_wci_wReset_n_6_056__ETC___d3277 ; @@ -6542,7 +6550,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd6 && + _theResult_____1__h76813 == 4'd6 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_6 && @@ -6574,7 +6582,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd6 && + _theResult_____1__h76813 == 4'd6 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3314 ; @@ -6589,7 +6597,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd7 && + _theResult_____1__h76813 == 4'd7 && cpReq[37:36] == 2'd2 && !wci_wReset_n_7 && NOT_wci_busy_7_216_326_AND_wci_wReset_n_7_196__ETC___d3339 ; @@ -6599,7 +6607,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd7 && + _theResult_____1__h76813 == 4'd7 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_7 && @@ -6631,7 +6639,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd7 && + _theResult_____1__h76813 == 4'd7 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3376 ; @@ -6646,29 +6654,29 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd8 && + _theResult_____1__h76813 == 4'd8 && cpReq[37:36] == 2'd2 && !wci_wReset_n_8 && NOT_wci_busy_8_356_388_AND_wci_wReset_n_8_336__ETC___d3401 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4513 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd8 && + _theResult_____1__h76813 == 4'd8 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_8 && NOT_wci_busy_8_356_388_AND_wci_wReset_n_8_336__ETC___d3401 ; + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = + cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && + cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4513 ; + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && @@ -6688,7 +6696,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd8 && + _theResult_____1__h76813 == 4'd8 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3438 ; @@ -6703,24 +6711,17 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd9 && + _theResult_____1__h76813 == 4'd9 && cpReq[37:36] == 2'd2 && !wci_wReset_n_9 && NOT_wci_busy_9_496_450_AND_wci_wReset_n_9_476__ETC___d3463 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4665 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd9 && + _theResult_____1__h76813 == 4'd9 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_9 && @@ -6752,7 +6753,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd9 && + _theResult_____1__h76813 == 4'd9 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3500 ; @@ -6762,26 +6763,33 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4631 ; + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = + cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && + cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h76813 == 4'd10 && + cpReq[37:36] == 2'd2 && + !wci_wReset_n_10 && + NOT_wci_busy_10_636_512_AND_wci_wReset_n_10_61_ETC___d3525 ; + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd10 && + _theResult_____1__h76813 == 4'd10 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_10 && NOT_wci_busy_10_636_512_AND_wci_wReset_n_10_61_ETC___d3525 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd10 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_10 && - NOT_wci_busy_10_636_512_AND_wci_wReset_n_10_61_ETC___d3525 ; + IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4665 ; // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = @@ -6802,7 +6810,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd10 && + _theResult_____1__h76813 == 4'd10 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3562 ; @@ -6817,7 +6825,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd11 && + _theResult_____1__h76813 == 4'd11 && cpReq[37:36] == 2'd2 && !wci_wReset_n_11 && NOT_wci_busy_11_776_574_AND_wci_wReset_n_11_75_ETC___d3587 ; @@ -6827,19 +6835,12 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd11 && + _theResult_____1__h76813 == 4'd11 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_11 && NOT_wci_busy_11_776_574_AND_wci_wReset_n_11_75_ETC___d3587 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4760 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && @@ -6854,12 +6855,19 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd0 && IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4750 ; + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && + cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4760 ; + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd11 && + _theResult_____1__h76813 == 4'd11 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3624 ; @@ -6874,7 +6882,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd12 && + _theResult_____1__h76813 == 4'd12 && cpReq[37:36] == 2'd2 && !wci_wReset_n_12 && NOT_wci_busy_12_916_636_AND_wci_wReset_n_12_89_ETC___d3649 ; @@ -6884,7 +6892,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd12 && + _theResult_____1__h76813 == 4'd12 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_12 && @@ -6904,46 +6912,46 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd0 && IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4826 ; + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && + cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4836 ; + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd12 && + _theResult_____1__h76813 == 4'd12 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3686 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4836 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4859 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd13 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && + _theResult_____1__h76813 == 4'd13 && + cpReq[37:36] == 2'd2 && !wci_wReset_n_13 && NOT_wci_busy_13_056_698_AND_wci_wReset_n_13_03_ETC___d3711 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = + // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd13 && - cpReq[37:36] == 2'd2 && + _theResult_____1__h76813 == 4'd13 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && !wci_wReset_n_13 && NOT_wci_busy_13_056_698_AND_wci_wReset_n_13_03_ETC___d3711 ; @@ -6973,7 +6981,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd13 && + _theResult_____1__h76813 == 4'd13 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3748 ; @@ -6988,7 +6996,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd14 && + _theResult_____1__h76813 == 4'd14 && cpReq[37:36] == 2'd2 && !wci_wReset_n_14 && NOT_wci_busy_14_196_760_AND_wci_wReset_n_14_17_ETC___d3773 ; @@ -6998,7 +7006,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd14 && + _theResult_____1__h76813 == 4'd14 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && !wci_wReset_n_14 && @@ -7030,7 +7038,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd14 && + _theResult_____1__h76813 == 4'd14 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_AND_NOT_w_ETC___d3810 ; @@ -7048,7 +7056,7 @@ module mkOCCP(pciDevice, // rule RL_completeWorkerWrite assign WILL_FIRE_RL_completeWorkerWrite = - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 && + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 && cpReq[64:62] == 3'd3 && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F && @@ -7061,8 +7069,8 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && @@ -7076,13 +7084,13 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F && @@ -7090,12 +7098,12 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F && @@ -7119,13 +7127,13 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T && @@ -7136,19 +7144,19 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T && @@ -7176,12 +7184,12 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F && !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T && !WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F && @@ -7190,7 +7198,7 @@ module mkOCCP(pciDevice, // rule RL_completeWorkerRead assign WILL_FIRE_RL_completeWorkerRead = cpRespF$FULL_N && - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 && + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 && cpReq[64:62] != 3'd0 && cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && @@ -7209,8 +7217,8 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && @@ -7220,13 +7228,13 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && @@ -7236,8 +7244,8 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && @@ -7252,8 +7260,8 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && @@ -7263,24 +7271,24 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T && @@ -7295,8 +7303,8 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T && @@ -7306,31 +7314,31 @@ module mkOCCP(pciDevice, !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T && !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F && !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T && !WILL_FIRE_RL_responseAdminRd ; // rule RL_reqRcv @@ -7359,7 +7367,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd0 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7367,7 +7375,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd0 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7375,13 +7383,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd0 && cpReq[61:60] == 2'd2 && wci_wReset_n_16_AND_NOT_wci_busy_36_872_AND_NO_ETC___d2875 ; // rule RL_cpDispatch_F_F_T_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd0 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7389,7 +7397,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd0 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd0 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7400,7 +7408,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd0 && + _theResult_____1__h76813 == 4'd0 && cpReq[37:36] == 2'd2 && wci_wReset_n_16_AND_NOT_wci_busy_36_872_AND_NO_ETC___d2875 ; @@ -7409,14 +7417,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd0 && + _theResult_____1__h76813 == 4'd0 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_16_AND_NOT_wci_busy_36_872_AND_NO_ETC___d2875 ; // rule RL_cpDispatch_F_F_T_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd1 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7424,7 +7432,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd1 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7432,13 +7440,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd1 && cpReq[61:60] == 2'd2 && wci_wReset_n_1_56_AND_NOT_wci_busy_1_76_954_AN_ETC___d2957 ; // rule RL_cpDispatch_F_F_T_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd1 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7446,7 +7454,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd1 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd1 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7457,7 +7465,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd1 && + _theResult_____1__h76813 == 4'd1 && cpReq[37:36] == 2'd2 && wci_wReset_n_1_56_AND_NOT_wci_busy_1_76_954_AN_ETC___d2957 ; @@ -7466,14 +7474,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd1 && + _theResult_____1__h76813 == 4'd1 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_1_56_AND_NOT_wci_busy_1_76_954_AN_ETC___d2957 ; // rule RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd2 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7481,7 +7489,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd2 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7489,13 +7497,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd2 && cpReq[61:60] == 2'd2 && wci_wReset_n_2_96_AND_NOT_wci_busy_2_16_016_AN_ETC___d3019 ; // rule RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd2 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7503,7 +7511,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd2 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd2 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7514,7 +7522,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd2 && + _theResult_____1__h76813 == 4'd2 && cpReq[37:36] == 2'd2 && wci_wReset_n_2_96_AND_NOT_wci_busy_2_16_016_AN_ETC___d3019 ; @@ -7523,14 +7531,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd2 && + _theResult_____1__h76813 == 4'd2 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_2_96_AND_NOT_wci_busy_2_16_016_AN_ETC___d3019 ; // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd3 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7538,7 +7546,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd3 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7546,13 +7554,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd3 && cpReq[61:60] == 2'd2 && wci_wReset_n_3_36_AND_NOT_wci_busy_3_56_078_AN_ETC___d3081 ; // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd3 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7560,7 +7568,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd3 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd3 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7571,7 +7579,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd3 && + _theResult_____1__h76813 == 4'd3 && cpReq[37:36] == 2'd2 && wci_wReset_n_3_36_AND_NOT_wci_busy_3_56_078_AN_ETC___d3081 ; @@ -7580,14 +7588,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd3 && + _theResult_____1__h76813 == 4'd3 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_3_36_AND_NOT_wci_busy_3_56_078_AN_ETC___d3081 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd4 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7595,7 +7603,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd4 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7603,13 +7611,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd4 && cpReq[61:60] == 2'd2 && wci_wReset_n_4_76_AND_NOT_wci_busy_4_96_140_AN_ETC___d3143 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd4 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7617,7 +7625,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd4 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd4 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7628,7 +7636,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd4 && + _theResult_____1__h76813 == 4'd4 && cpReq[37:36] == 2'd2 && wci_wReset_n_4_76_AND_NOT_wci_busy_4_96_140_AN_ETC___d3143 ; @@ -7637,14 +7645,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd4 && + _theResult_____1__h76813 == 4'd4 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_4_76_AND_NOT_wci_busy_4_96_140_AN_ETC___d3143 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd5 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7652,7 +7660,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd5 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7660,13 +7668,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd5 && cpReq[61:60] == 2'd2 && wci_wReset_n_5_16_AND_NOT_wci_busy_5_36_202_AN_ETC___d3205 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd5 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7674,7 +7682,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd5 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd5 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7685,7 +7693,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd5 && + _theResult_____1__h76813 == 4'd5 && cpReq[37:36] == 2'd2 && wci_wReset_n_5_16_AND_NOT_wci_busy_5_36_202_AN_ETC___d3205 ; @@ -7694,14 +7702,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd5 && + _theResult_____1__h76813 == 4'd5 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_5_16_AND_NOT_wci_busy_5_36_202_AN_ETC___d3205 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd6 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7709,7 +7717,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd6 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7717,13 +7725,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd6 && cpReq[61:60] == 2'd2 && wci_wReset_n_6_056_AND_NOT_wci_busy_6_076_264__ETC___d3267 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd6 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7731,7 +7739,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd6 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd6 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7742,7 +7750,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd6 && + _theResult_____1__h76813 == 4'd6 && cpReq[37:36] == 2'd2 && wci_wReset_n_6_056_AND_NOT_wci_busy_6_076_264__ETC___d3267 ; @@ -7751,14 +7759,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd6 && + _theResult_____1__h76813 == 4'd6 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_6_056_AND_NOT_wci_busy_6_076_264__ETC___d3267 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd7 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7766,7 +7774,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd7 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7774,13 +7782,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd7 && cpReq[61:60] == 2'd2 && wci_wReset_n_7_196_AND_NOT_wci_busy_7_216_326__ETC___d3329 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd7 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7788,7 +7796,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd7 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd7 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7799,7 +7807,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd7 && + _theResult_____1__h76813 == 4'd7 && cpReq[37:36] == 2'd2 && wci_wReset_n_7_196_AND_NOT_wci_busy_7_216_326__ETC___d3329 ; @@ -7808,14 +7816,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd7 && + _theResult_____1__h76813 == 4'd7 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_7_196_AND_NOT_wci_busy_7_216_326__ETC___d3329 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd8 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7823,7 +7831,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd8 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7831,13 +7839,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd8 && cpReq[61:60] == 2'd2 && wci_wReset_n_8_336_AND_NOT_wci_busy_8_356_388__ETC___d3391 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd8 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7845,7 +7853,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd8 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd8 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7856,7 +7864,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd8 && + _theResult_____1__h76813 == 4'd8 && cpReq[37:36] == 2'd2 && wci_wReset_n_8_336_AND_NOT_wci_busy_8_356_388__ETC___d3391 ; @@ -7865,14 +7873,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd8 && + _theResult_____1__h76813 == 4'd8 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_8_336_AND_NOT_wci_busy_8_356_388__ETC___d3391 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd9 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7880,7 +7888,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd9 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7888,13 +7896,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd9 && cpReq[61:60] == 2'd2 && wci_wReset_n_9_476_AND_NOT_wci_busy_9_496_450__ETC___d3453 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd9 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7902,7 +7910,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd9 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd9 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7913,7 +7921,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd9 && + _theResult_____1__h76813 == 4'd9 && cpReq[37:36] == 2'd2 && wci_wReset_n_9_476_AND_NOT_wci_busy_9_496_450__ETC___d3453 ; @@ -7922,14 +7930,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd9 && + _theResult_____1__h76813 == 4'd9 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_9_476_AND_NOT_wci_busy_9_496_450__ETC___d3453 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd10 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7937,7 +7945,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd10 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7945,13 +7953,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd10 && cpReq[61:60] == 2'd2 && wci_wReset_n_10_616_AND_NOT_wci_busy_10_636_51_ETC___d3515 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd10 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7959,7 +7967,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd10 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd10 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -7970,7 +7978,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd10 && + _theResult_____1__h76813 == 4'd10 && cpReq[37:36] == 2'd2 && wci_wReset_n_10_616_AND_NOT_wci_busy_10_636_51_ETC___d3515 ; @@ -7979,14 +7987,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd10 && + _theResult_____1__h76813 == 4'd10 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_10_616_AND_NOT_wci_busy_10_636_51_ETC___d3515 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd11 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -7994,7 +8002,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd11 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -8002,13 +8010,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd11 && cpReq[61:60] == 2'd2 && wci_wReset_n_11_756_AND_NOT_wci_busy_11_776_57_ETC___d3577 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd11 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -8016,7 +8024,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd11 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd11 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -8027,7 +8035,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd11 && + _theResult_____1__h76813 == 4'd11 && cpReq[37:36] == 2'd2 && wci_wReset_n_11_756_AND_NOT_wci_busy_11_776_57_ETC___d3577 ; @@ -8036,14 +8044,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd11 && + _theResult_____1__h76813 == 4'd11 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_11_756_AND_NOT_wci_busy_11_776_57_ETC___d3577 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd12 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -8051,7 +8059,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd12 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -8059,13 +8067,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd12 && cpReq[61:60] == 2'd2 && wci_wReset_n_12_896_AND_NOT_wci_busy_12_916_63_ETC___d3639 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd12 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -8073,7 +8081,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd12 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd12 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -8084,7 +8092,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd12 && + _theResult_____1__h76813 == 4'd12 && cpReq[37:36] == 2'd2 && wci_wReset_n_12_896_AND_NOT_wci_busy_12_916_63_ETC___d3639 ; @@ -8093,14 +8101,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd12 && + _theResult_____1__h76813 == 4'd12 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_12_896_AND_NOT_wci_busy_12_916_63_ETC___d3639 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd13 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -8108,7 +8116,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd13 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -8116,13 +8124,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd13 && cpReq[61:60] == 2'd2 && wci_wReset_n_13_036_AND_NOT_wci_busy_13_056_69_ETC___d3701 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd13 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -8130,7 +8138,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd13 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd13 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -8141,7 +8149,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd13 && + _theResult_____1__h76813 == 4'd13 && cpReq[37:36] == 2'd2 && wci_wReset_n_13_036_AND_NOT_wci_busy_13_056_69_ETC___d3701 ; @@ -8150,14 +8158,14 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd13 && + _theResult_____1__h76813 == 4'd13 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_13_036_AND_NOT_wci_busy_13_056_69_ETC___d3701 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd14 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -8165,7 +8173,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd14 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -8173,13 +8181,13 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd14 && cpReq[61:60] == 2'd2 && wci_wReset_n_14_176_AND_NOT_wci_busy_14_196_76_ETC___d3763 ; // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd14 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && cpReq[37] && @@ -8187,7 +8195,7 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h74424 == 4'd14 && + cpReq[64:62] == 3'd3 && _theResult_____1__h76795 == 4'd14 && cpReq[61:60] != 2'd2 && cpReq[9:6] == 4'h9 && !cpReq[37] && @@ -8198,7 +8206,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd14 && + _theResult_____1__h76813 == 4'd14 && cpReq[37:36] == 2'd2 && wci_wReset_n_14_176_AND_NOT_wci_busy_14_196_76_ETC___d3763 ; @@ -8207,7 +8215,7 @@ module mkOCCP(pciDevice, cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd14 && + _theResult_____1__h76813 == 4'd14 && cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 && wci_wReset_n_14_176_AND_NOT_wci_busy_14_196_76_ETC___d3763 ; @@ -8218,7 +8226,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy assign WILL_FIRE_RL_wci_wrkBusy = ((wci_wciResponse$wget[33:32] == 2'd0) ? - wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 || + wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 || wci_respF$FULL_N : wci_respF$FULL_N) && wci_busy ; @@ -8242,7 +8250,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_1 assign WILL_FIRE_RL_wci_wrkBusy_1 = ((wci_wciResponse_1$wget[33:32] == 2'd0) ? - wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 || + wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 || wci_respF_1$FULL_N : wci_respF_1$FULL_N) && wci_busy_1 ; @@ -8266,7 +8274,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_2 assign WILL_FIRE_RL_wci_wrkBusy_2 = ((wci_wciResponse_2$wget[33:32] == 2'd0) ? - wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 || + wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 || wci_respF_2$FULL_N : wci_respF_2$FULL_N) && wci_busy_2 ; @@ -8290,7 +8298,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_3 assign WILL_FIRE_RL_wci_wrkBusy_3 = ((wci_wciResponse_3$wget[33:32] == 2'd0) ? - wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 || + wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 || wci_respF_3$FULL_N : wci_respF_3$FULL_N) && wci_busy_3 ; @@ -8314,7 +8322,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_4 assign WILL_FIRE_RL_wci_wrkBusy_4 = ((wci_wciResponse_4$wget[33:32] == 2'd0) ? - wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 || + wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 || wci_respF_4$FULL_N : wci_respF_4$FULL_N) && wci_busy_4 ; @@ -8338,7 +8346,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_5 assign WILL_FIRE_RL_wci_wrkBusy_5 = ((wci_wciResponse_5$wget[33:32] == 2'd0) ? - wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 || + wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 || wci_respF_5$FULL_N : wci_respF_5$FULL_N) && wci_busy_5 ; @@ -8362,7 +8370,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_6 assign WILL_FIRE_RL_wci_wrkBusy_6 = ((wci_wciResponse_6$wget[33:32] == 2'd0) ? - wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 || + wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 || wci_respF_6$FULL_N : wci_respF_6$FULL_N) && wci_busy_6 ; @@ -8386,7 +8394,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_7 assign WILL_FIRE_RL_wci_wrkBusy_7 = ((wci_wciResponse_7$wget[33:32] == 2'd0) ? - wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 || + wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 || wci_respF_7$FULL_N : wci_respF_7$FULL_N) && wci_busy_7 ; @@ -8410,7 +8418,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_8 assign WILL_FIRE_RL_wci_wrkBusy_8 = ((wci_wciResponse_8$wget[33:32] == 2'd0) ? - wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 || + wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 || wci_respF_8$FULL_N : wci_respF_8$FULL_N) && wci_busy_8 ; @@ -8434,7 +8442,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_9 assign WILL_FIRE_RL_wci_wrkBusy_9 = ((wci_wciResponse_9$wget[33:32] == 2'd0) ? - wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 || + wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 || wci_respF_9$FULL_N : wci_respF_9$FULL_N) && wci_busy_9 ; @@ -8458,7 +8466,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_10 assign WILL_FIRE_RL_wci_wrkBusy_10 = ((wci_wciResponse_10$wget[33:32] == 2'd0) ? - wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 || + wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 || wci_respF_10$FULL_N : wci_respF_10$FULL_N) && wci_busy_10 ; @@ -8482,7 +8490,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_11 assign WILL_FIRE_RL_wci_wrkBusy_11 = ((wci_wciResponse_11$wget[33:32] == 2'd0) ? - wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 || + wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 || wci_respF_11$FULL_N : wci_respF_11$FULL_N) && wci_busy_11 ; @@ -8506,7 +8514,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_12 assign WILL_FIRE_RL_wci_wrkBusy_12 = ((wci_wciResponse_12$wget[33:32] == 2'd0) ? - wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 || + wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 || wci_respF_12$FULL_N : wci_respF_12$FULL_N) && wci_busy_12 ; @@ -8530,7 +8538,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_13 assign WILL_FIRE_RL_wci_wrkBusy_13 = ((wci_wciResponse_13$wget[33:32] == 2'd0) ? - wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 || + wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 || wci_respF_13$FULL_N : wci_respF_13$FULL_N) && wci_busy_13 ; @@ -8554,7 +8562,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_14 assign WILL_FIRE_RL_wci_wrkBusy_14 = ((wci_wciResponse_14$wget[33:32] == 2'd0) ? - wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 || + wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 || wci_respF_14$FULL_N : wci_respF_14$FULL_N) && wci_busy_14 ; @@ -8578,7 +8586,7 @@ module mkOCCP(pciDevice, // inputs to muxes for submodule ports assign MUX_wci_busy$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 || + (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 || wci_wciResponse$wget[33:32] != 2'd0) ; assign MUX_wci_busy$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T || @@ -8586,7 +8594,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T ; assign MUX_wci_busy_1$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 || + (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 || wci_wciResponse_1$wget[33:32] != 2'd0) ; assign MUX_wci_busy_1$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T || @@ -8594,7 +8602,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T ; assign MUX_wci_busy_10$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 || + (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 || wci_wciResponse_10$wget[33:32] != 2'd0) ; assign MUX_wci_busy_10$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8602,7 +8610,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_11$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 || + (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 || wci_wciResponse_11$wget[33:32] != 2'd0) ; assign MUX_wci_busy_11$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8610,7 +8618,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_12$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 || + (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 || wci_wciResponse_12$wget[33:32] != 2'd0) ; assign MUX_wci_busy_12$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8618,7 +8626,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_13$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 || + (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 || wci_wciResponse_13$wget[33:32] != 2'd0) ; assign MUX_wci_busy_13$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8626,7 +8634,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_14$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 || + (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 || wci_wciResponse_14$wget[33:32] != 2'd0) ; assign MUX_wci_busy_14$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8634,7 +8642,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_2$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 || + (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 || wci_wciResponse_2$wget[33:32] != 2'd0) ; assign MUX_wci_busy_2$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T || @@ -8642,7 +8650,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T ; assign MUX_wci_busy_3$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 || + (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 || wci_wciResponse_3$wget[33:32] != 2'd0) ; assign MUX_wci_busy_3$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T || @@ -8650,7 +8658,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T ; assign MUX_wci_busy_4$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 || + (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 || wci_wciResponse_4$wget[33:32] != 2'd0) ; assign MUX_wci_busy_4$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8658,7 +8666,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T ; assign MUX_wci_busy_5$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 || + (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 || wci_wciResponse_5$wget[33:32] != 2'd0) ; assign MUX_wci_busy_5$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8666,7 +8674,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_6$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 || + (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 || wci_wciResponse_6$wget[33:32] != 2'd0) ; assign MUX_wci_busy_6$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8674,7 +8682,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_7$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 || + (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 || wci_wciResponse_7$wget[33:32] != 2'd0) ; assign MUX_wci_busy_7$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8682,7 +8690,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_8$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 || + (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 || wci_wciResponse_8$wget[33:32] != 2'd0) ; assign MUX_wci_busy_8$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8690,7 +8698,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_9$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 || + (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 || wci_wciResponse_9$wget[33:32] != 2'd0) ; assign MUX_wci_busy_9$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -9453,16 +9461,16 @@ module mkOCCP(pciDevice, 2'd0 : ((cpReqF$D_OUT[25:22] == 4'd0) ? 2'd1 : 2'd2), cpReqF$D_OUT[33:26], - bAddr__h110451, + bAddr__h113011, cpReqF$D_OUT[3:0] } : { (cpReqF$D_OUT[57:50] == 8'd0) ? 5'd4 : ((cpReqF$D_OUT[57:54] == 4'd0) ? 5'd13 : 5'd14), cpReqF$D_OUT[31:0], - bAddr__h109903, + bAddr__h112551, cpReqF$D_OUT[35:32] } ; - assign MUX_cpRespF$enq_1__VAL_1 = { seqTag, crr_data__h74230 } ; - assign MUX_cpRespF$enq_1__VAL_2 = { cpReq[35:28], rtnData__h109398 } ; + assign MUX_cpRespF$enq_1__VAL_1 = { seqTag, crr_data__h76601 } ; + assign MUX_cpRespF$enq_1__VAL_2 = { cpReq[35:28], rtnData__h112042 } ; assign MUX_readCntReg$write_1__VAL_2 = readCntReg + 32'd1 ; always@(wci_reqPend or wci_reqERR) begin @@ -9811,11 +9819,11 @@ module mkOCCP(pciDevice, MUX_wci_reqF_10_q_0$write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_wci_reqF_10_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76617, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78988, cpReq[59:28] } ; assign MUX_wci_reqF_10_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76617, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78988, 32'hAAAAAAAA } ; assign MUX_wci_reqF_10_x_wire$wset_1__VAL_3 = - { 8'd79, x_addr__h95534, 32'hAAAAAAAA } ; + { 8'd79, x_addr__h97905, 32'hAAAAAAAA } ; assign MUX_wci_reqF_11_c_r$write_1__VAL_1 = wci_reqF_11_c_r + 1'd1 ; assign MUX_wci_reqF_11_c_r$write_1__VAL_2 = wci_reqF_11_c_r - 1'd1 ; always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T or @@ -9844,9 +9852,9 @@ module mkOCCP(pciDevice, MUX_wci_reqF_11_q_0$write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_wci_reqF_11_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76683, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h79054, cpReq[59:28] } ; assign MUX_wci_reqF_11_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76683, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h79054, 32'hAAAAAAAA } ; assign MUX_wci_reqF_12_c_r$write_1__VAL_1 = wci_reqF_12_c_r + 1'd1 ; assign MUX_wci_reqF_12_c_r$write_1__VAL_2 = wci_reqF_12_c_r - 1'd1 ; always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or @@ -9875,9 +9883,9 @@ module mkOCCP(pciDevice, MUX_wci_reqF_12_q_0$write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_wci_reqF_12_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76749, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h79120, cpReq[59:28] } ; assign MUX_wci_reqF_12_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76749, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h79120, 32'hAAAAAAAA } ; assign MUX_wci_reqF_13_c_r$write_1__VAL_1 = wci_reqF_13_c_r + 1'd1 ; assign MUX_wci_reqF_13_c_r$write_1__VAL_2 = wci_reqF_13_c_r - 1'd1 ; always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or @@ -9906,9 +9914,9 @@ module mkOCCP(pciDevice, MUX_wci_reqF_13_q_0$write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_wci_reqF_13_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76815, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h79186, cpReq[59:28] } ; assign MUX_wci_reqF_13_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76815, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h79186, 32'hAAAAAAAA } ; assign MUX_wci_reqF_14_c_r$write_1__VAL_1 = wci_reqF_14_c_r + 1'd1 ; assign MUX_wci_reqF_14_c_r$write_1__VAL_2 = wci_reqF_14_c_r - 1'd1 ; always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or @@ -9937,9 +9945,9 @@ module mkOCCP(pciDevice, MUX_wci_reqF_14_q_0$write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_wci_reqF_14_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76881, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h79252, cpReq[59:28] } ; assign MUX_wci_reqF_14_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76881, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h79252, 32'hAAAAAAAA } ; assign MUX_wci_reqF_1_c_r$write_1__VAL_1 = wci_reqF_1_c_r + 1'd1 ; assign MUX_wci_reqF_1_c_r$write_1__VAL_2 = wci_reqF_1_c_r - 1'd1 ; assign MUX_wci_reqF_1_q_0$write_1__VAL_1 = @@ -9968,9 +9976,9 @@ module mkOCCP(pciDevice, endcase end assign MUX_wci_reqF_1_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76023, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78394, cpReq[59:28] } ; assign MUX_wci_reqF_1_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76023, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78394, 32'hAAAAAAAA } ; assign MUX_wci_reqF_2_c_r$write_1__VAL_1 = wci_reqF_2_c_r + 1'd1 ; assign MUX_wci_reqF_2_c_r$write_1__VAL_2 = wci_reqF_2_c_r - 1'd1 ; assign MUX_wci_reqF_2_q_0$write_1__VAL_1 = @@ -9999,9 +10007,9 @@ module mkOCCP(pciDevice, endcase end assign MUX_wci_reqF_2_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76089, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78460, cpReq[59:28] } ; assign MUX_wci_reqF_2_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76089, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78460, 32'hAAAAAAAA } ; assign MUX_wci_reqF_3_c_r$write_1__VAL_1 = wci_reqF_3_c_r + 1'd1 ; assign MUX_wci_reqF_3_c_r$write_1__VAL_2 = wci_reqF_3_c_r - 1'd1 ; assign MUX_wci_reqF_3_q_0$write_1__VAL_1 = @@ -10030,9 +10038,9 @@ module mkOCCP(pciDevice, endcase end assign MUX_wci_reqF_3_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76155, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78526, cpReq[59:28] } ; assign MUX_wci_reqF_3_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76155, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78526, 32'hAAAAAAAA } ; assign MUX_wci_reqF_4_c_r$write_1__VAL_1 = wci_reqF_4_c_r + 1'd1 ; assign MUX_wci_reqF_4_c_r$write_1__VAL_2 = wci_reqF_4_c_r - 1'd1 ; assign MUX_wci_reqF_4_q_0$write_1__VAL_1 = @@ -10061,9 +10069,9 @@ module mkOCCP(pciDevice, endcase end assign MUX_wci_reqF_4_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76221, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78592, cpReq[59:28] } ; assign MUX_wci_reqF_4_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76221, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78592, 32'hAAAAAAAA } ; assign MUX_wci_reqF_5_c_r$write_1__VAL_1 = wci_reqF_5_c_r + 1'd1 ; assign MUX_wci_reqF_5_c_r$write_1__VAL_2 = wci_reqF_5_c_r - 1'd1 ; assign MUX_wci_reqF_5_q_0$write_1__VAL_1 = @@ -10092,9 +10100,9 @@ module mkOCCP(pciDevice, endcase end assign MUX_wci_reqF_5_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76287, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78658, cpReq[59:28] } ; assign MUX_wci_reqF_5_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76287, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78658, 32'hAAAAAAAA } ; assign MUX_wci_reqF_6_c_r$write_1__VAL_1 = wci_reqF_6_c_r + 1'd1 ; assign MUX_wci_reqF_6_c_r$write_1__VAL_2 = wci_reqF_6_c_r - 1'd1 ; assign MUX_wci_reqF_6_q_0$write_1__VAL_1 = @@ -10123,9 +10131,9 @@ module mkOCCP(pciDevice, endcase end assign MUX_wci_reqF_6_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76353, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78724, cpReq[59:28] } ; assign MUX_wci_reqF_6_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76353, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78724, 32'hAAAAAAAA } ; assign MUX_wci_reqF_7_c_r$write_1__VAL_1 = wci_reqF_7_c_r + 1'd1 ; assign MUX_wci_reqF_7_c_r$write_1__VAL_2 = wci_reqF_7_c_r - 1'd1 ; assign MUX_wci_reqF_7_q_0$write_1__VAL_1 = @@ -10154,9 +10162,9 @@ module mkOCCP(pciDevice, endcase end assign MUX_wci_reqF_7_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76419, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78790, cpReq[59:28] } ; assign MUX_wci_reqF_7_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76419, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78790, 32'hAAAAAAAA } ; assign MUX_wci_reqF_8_c_r$write_1__VAL_1 = wci_reqF_8_c_r + 1'd1 ; assign MUX_wci_reqF_8_c_r$write_1__VAL_2 = wci_reqF_8_c_r - 1'd1 ; assign MUX_wci_reqF_8_q_0$write_1__VAL_1 = @@ -10185,9 +10193,9 @@ module mkOCCP(pciDevice, endcase end assign MUX_wci_reqF_8_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76485, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78856, cpReq[59:28] } ; assign MUX_wci_reqF_8_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76485, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78856, 32'hAAAAAAAA } ; assign MUX_wci_reqF_9_c_r$write_1__VAL_1 = wci_reqF_9_c_r + 1'd1 ; assign MUX_wci_reqF_9_c_r$write_1__VAL_2 = wci_reqF_9_c_r - 1'd1 ; assign MUX_wci_reqF_9_q_0$write_1__VAL_1 = @@ -10216,9 +10224,9 @@ module mkOCCP(pciDevice, endcase end assign MUX_wci_reqF_9_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h76551, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78922, cpReq[59:28] } ; assign MUX_wci_reqF_9_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h76551, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78922, 32'hAAAAAAAA } ; assign MUX_wci_reqF_c_r$write_1__VAL_1 = wci_reqF_c_r + 1'd1 ; assign MUX_wci_reqF_c_r$write_1__VAL_2 = wci_reqF_c_r - 1'd1 ; assign MUX_wci_reqF_q_0$write_1__VAL_1 = @@ -10245,9 +10253,9 @@ module mkOCCP(pciDevice, endcase end assign MUX_wci_reqF_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h75955, cpReq[59:28] } ; + { 4'd3, cpReq[3:0], wciAddr__h78326, cpReq[59:28] } ; assign MUX_wci_reqF_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h75955, 32'hAAAAAAAA } ; + { 4'd5, cpReq[3:0], wciAddr__h78326, 32'hAAAAAAAA } ; always@(wci_reqPend or wci_reqTO) begin case (wci_reqPend) @@ -10402,209 +10410,209 @@ module mkOCCP(pciDevice, 34'h1C0DE4203 : wci_wciResponse$wget ; assign MUX_wci_respF$enq_1__VAL_2 = { 2'd1, wci_wStatus } ; - assign MUX_wci_respF$enq_1__VAL_3 = { 2'd1, x_data__h101740 } ; - assign MUX_wci_respF$enq_1__VAL_4 = { 2'd1, x_data__h101746 } ; + assign MUX_wci_respF$enq_1__VAL_3 = { 2'd1, x_data__h104111 } ; + assign MUX_wci_respF$enq_1__VAL_4 = { 2'd1, x_data__h104117 } ; assign MUX_wci_respF$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow } ; assign MUX_wci_respF_1$enq_1__VAL_1 = (wci_wciResponse_1$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_1$wget ; assign MUX_wci_respF_1$enq_1__VAL_2 = { 2'd1, wci_wStatus_1 } ; - assign MUX_wci_respF_1$enq_1__VAL_3 = { 2'd1, x_data__h101793 } ; - assign MUX_wci_respF_1$enq_1__VAL_4 = { 2'd1, x_data__h101799 } ; + assign MUX_wci_respF_1$enq_1__VAL_3 = { 2'd1, x_data__h104164 } ; + assign MUX_wci_respF_1$enq_1__VAL_4 = { 2'd1, x_data__h104170 } ; assign MUX_wci_respF_1$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_1 } ; assign MUX_wci_respF_10$enq_1__VAL_1 = (wci_wciResponse_10$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_10$wget ; assign MUX_wci_respF_10$enq_1__VAL_2 = { 2'd1, wci_wStatus_10 } ; - assign MUX_wci_respF_10$enq_1__VAL_3 = { 2'd1, x_data__h102270 } ; - assign MUX_wci_respF_10$enq_1__VAL_4 = { 2'd1, x_data__h102276 } ; + assign MUX_wci_respF_10$enq_1__VAL_3 = { 2'd1, x_data__h104641 } ; + assign MUX_wci_respF_10$enq_1__VAL_4 = { 2'd1, x_data__h104647 } ; assign MUX_wci_respF_10$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_10 } ; assign MUX_wci_respF_11$enq_1__VAL_1 = (wci_wciResponse_11$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_11$wget ; assign MUX_wci_respF_11$enq_1__VAL_2 = { 2'd1, wci_wStatus_11 } ; - assign MUX_wci_respF_11$enq_1__VAL_3 = { 2'd1, x_data__h102323 } ; - assign MUX_wci_respF_11$enq_1__VAL_4 = { 2'd1, x_data__h102329 } ; + assign MUX_wci_respF_11$enq_1__VAL_3 = { 2'd1, x_data__h104694 } ; + assign MUX_wci_respF_11$enq_1__VAL_4 = { 2'd1, x_data__h104700 } ; assign MUX_wci_respF_11$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_11 } ; assign MUX_wci_respF_12$enq_1__VAL_1 = (wci_wciResponse_12$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_12$wget ; assign MUX_wci_respF_12$enq_1__VAL_2 = { 2'd1, wci_wStatus_12 } ; - assign MUX_wci_respF_12$enq_1__VAL_3 = { 2'd1, x_data__h102376 } ; - assign MUX_wci_respF_12$enq_1__VAL_4 = { 2'd1, x_data__h102382 } ; + assign MUX_wci_respF_12$enq_1__VAL_3 = { 2'd1, x_data__h104747 } ; + assign MUX_wci_respF_12$enq_1__VAL_4 = { 2'd1, x_data__h104753 } ; assign MUX_wci_respF_12$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_12 } ; assign MUX_wci_respF_13$enq_1__VAL_1 = (wci_wciResponse_13$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_13$wget ; assign MUX_wci_respF_13$enq_1__VAL_2 = { 2'd1, wci_wStatus_13 } ; - assign MUX_wci_respF_13$enq_1__VAL_3 = { 2'd1, x_data__h102429 } ; - assign MUX_wci_respF_13$enq_1__VAL_4 = { 2'd1, x_data__h102435 } ; + assign MUX_wci_respF_13$enq_1__VAL_3 = { 2'd1, x_data__h104800 } ; + assign MUX_wci_respF_13$enq_1__VAL_4 = { 2'd1, x_data__h104806 } ; assign MUX_wci_respF_13$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_13 } ; assign MUX_wci_respF_14$enq_1__VAL_1 = (wci_wciResponse_14$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_14$wget ; assign MUX_wci_respF_14$enq_1__VAL_2 = { 2'd1, wci_wStatus_14 } ; - assign MUX_wci_respF_14$enq_1__VAL_3 = { 2'd1, x_data__h102482 } ; - assign MUX_wci_respF_14$enq_1__VAL_4 = { 2'd1, x_data__h102488 } ; + assign MUX_wci_respF_14$enq_1__VAL_3 = { 2'd1, x_data__h104853 } ; + assign MUX_wci_respF_14$enq_1__VAL_4 = { 2'd1, x_data__h104859 } ; assign MUX_wci_respF_14$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_14 } ; assign MUX_wci_respF_2$enq_1__VAL_1 = (wci_wciResponse_2$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_2$wget ; assign MUX_wci_respF_2$enq_1__VAL_2 = { 2'd1, wci_wStatus_2 } ; - assign MUX_wci_respF_2$enq_1__VAL_3 = { 2'd1, x_data__h101846 } ; - assign MUX_wci_respF_2$enq_1__VAL_4 = { 2'd1, x_data__h101852 } ; + assign MUX_wci_respF_2$enq_1__VAL_3 = { 2'd1, x_data__h104217 } ; + assign MUX_wci_respF_2$enq_1__VAL_4 = { 2'd1, x_data__h104223 } ; assign MUX_wci_respF_2$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_2 } ; assign MUX_wci_respF_3$enq_1__VAL_1 = (wci_wciResponse_3$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_3$wget ; assign MUX_wci_respF_3$enq_1__VAL_2 = { 2'd1, wci_wStatus_3 } ; - assign MUX_wci_respF_3$enq_1__VAL_3 = { 2'd1, x_data__h101899 } ; - assign MUX_wci_respF_3$enq_1__VAL_4 = { 2'd1, x_data__h101905 } ; + assign MUX_wci_respF_3$enq_1__VAL_3 = { 2'd1, x_data__h104270 } ; + assign MUX_wci_respF_3$enq_1__VAL_4 = { 2'd1, x_data__h104276 } ; assign MUX_wci_respF_3$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_3 } ; assign MUX_wci_respF_4$enq_1__VAL_1 = (wci_wciResponse_4$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_4$wget ; assign MUX_wci_respF_4$enq_1__VAL_2 = { 2'd1, wci_wStatus_4 } ; - assign MUX_wci_respF_4$enq_1__VAL_3 = { 2'd1, x_data__h101952 } ; - assign MUX_wci_respF_4$enq_1__VAL_4 = { 2'd1, x_data__h101958 } ; + assign MUX_wci_respF_4$enq_1__VAL_3 = { 2'd1, x_data__h104323 } ; + assign MUX_wci_respF_4$enq_1__VAL_4 = { 2'd1, x_data__h104329 } ; assign MUX_wci_respF_4$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_4 } ; assign MUX_wci_respF_5$enq_1__VAL_1 = (wci_wciResponse_5$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_5$wget ; assign MUX_wci_respF_5$enq_1__VAL_2 = { 2'd1, wci_wStatus_5 } ; - assign MUX_wci_respF_5$enq_1__VAL_3 = { 2'd1, x_data__h102005 } ; - assign MUX_wci_respF_5$enq_1__VAL_4 = { 2'd1, x_data__h102011 } ; + assign MUX_wci_respF_5$enq_1__VAL_3 = { 2'd1, x_data__h104376 } ; + assign MUX_wci_respF_5$enq_1__VAL_4 = { 2'd1, x_data__h104382 } ; assign MUX_wci_respF_5$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_5 } ; assign MUX_wci_respF_6$enq_1__VAL_1 = (wci_wciResponse_6$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_6$wget ; assign MUX_wci_respF_6$enq_1__VAL_2 = { 2'd1, wci_wStatus_6 } ; - assign MUX_wci_respF_6$enq_1__VAL_3 = { 2'd1, x_data__h102058 } ; - assign MUX_wci_respF_6$enq_1__VAL_4 = { 2'd1, x_data__h102064 } ; + assign MUX_wci_respF_6$enq_1__VAL_3 = { 2'd1, x_data__h104429 } ; + assign MUX_wci_respF_6$enq_1__VAL_4 = { 2'd1, x_data__h104435 } ; assign MUX_wci_respF_6$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_6 } ; assign MUX_wci_respF_7$enq_1__VAL_1 = (wci_wciResponse_7$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_7$wget ; assign MUX_wci_respF_7$enq_1__VAL_2 = { 2'd1, wci_wStatus_7 } ; - assign MUX_wci_respF_7$enq_1__VAL_3 = { 2'd1, x_data__h102111 } ; - assign MUX_wci_respF_7$enq_1__VAL_4 = { 2'd1, x_data__h102117 } ; + assign MUX_wci_respF_7$enq_1__VAL_3 = { 2'd1, x_data__h104482 } ; + assign MUX_wci_respF_7$enq_1__VAL_4 = { 2'd1, x_data__h104488 } ; assign MUX_wci_respF_7$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_7 } ; assign MUX_wci_respF_8$enq_1__VAL_1 = (wci_wciResponse_8$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_8$wget ; assign MUX_wci_respF_8$enq_1__VAL_2 = { 2'd1, wci_wStatus_8 } ; - assign MUX_wci_respF_8$enq_1__VAL_3 = { 2'd1, x_data__h102164 } ; - assign MUX_wci_respF_8$enq_1__VAL_4 = { 2'd1, x_data__h102170 } ; + assign MUX_wci_respF_8$enq_1__VAL_3 = { 2'd1, x_data__h104535 } ; + assign MUX_wci_respF_8$enq_1__VAL_4 = { 2'd1, x_data__h104541 } ; assign MUX_wci_respF_8$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_8 } ; assign MUX_wci_respF_9$enq_1__VAL_1 = (wci_wciResponse_9$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : wci_wciResponse_9$wget ; assign MUX_wci_respF_9$enq_1__VAL_2 = { 2'd1, wci_wStatus_9 } ; - assign MUX_wci_respF_9$enq_1__VAL_3 = { 2'd1, x_data__h102217 } ; - assign MUX_wci_respF_9$enq_1__VAL_4 = { 2'd1, x_data__h102223 } ; + assign MUX_wci_respF_9$enq_1__VAL_3 = { 2'd1, x_data__h104588 } ; + assign MUX_wci_respF_9$enq_1__VAL_4 = { 2'd1, x_data__h104594 } ; assign MUX_wci_respF_9$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_9 } ; assign MUX_wci_respTimr$write_1__VAL_2 = (wci_wciResponse$wget[33:32] == 2'd0) ? - (wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 ? - x__h11494 : + (wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 ? + x__h11923 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_1$write_1__VAL_2 = (wci_wciResponse_1$wget[33:32] == 2'd0) ? - (wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 ? - x__h15799 : + (wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 ? + x__h16366 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_10$write_1__VAL_2 = (wci_wciResponse_10$wget[33:32] == 2'd0) ? - (wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 ? - x__h54517 : + (wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 ? + x__h56326 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_11$write_1__VAL_2 = (wci_wciResponse_11$wget[33:32] == 2'd0) ? - (wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 ? - x__h58819 : + (wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 ? + x__h60766 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_12$write_1__VAL_2 = (wci_wciResponse_12$wget[33:32] == 2'd0) ? - (wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 ? - x__h63121 : + (wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 ? + x__h65206 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_13$write_1__VAL_2 = (wci_wciResponse_13$wget[33:32] == 2'd0) ? - (wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 ? - x__h67423 : + (wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 ? + x__h69646 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_14$write_1__VAL_2 = (wci_wciResponse_14$wget[33:32] == 2'd0) ? - (wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 ? - x__h71725 : + (wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 ? + x__h74086 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_2$write_1__VAL_2 = (wci_wciResponse_2$wget[33:32] == 2'd0) ? - (wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 ? - x__h20101 : + (wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 ? + x__h20806 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_3$write_1__VAL_2 = (wci_wciResponse_3$wget[33:32] == 2'd0) ? - (wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 ? - x__h24403 : + (wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 ? + x__h25246 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_4$write_1__VAL_2 = (wci_wciResponse_4$wget[33:32] == 2'd0) ? - (wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 ? - x__h28705 : + (wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 ? + x__h29686 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_5$write_1__VAL_2 = (wci_wciResponse_5$wget[33:32] == 2'd0) ? - (wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 ? - x__h33007 : + (wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 ? + x__h34126 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_6$write_1__VAL_2 = (wci_wciResponse_6$wget[33:32] == 2'd0) ? - (wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 ? - x__h37309 : + (wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 ? + x__h38566 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_7$write_1__VAL_2 = (wci_wciResponse_7$wget[33:32] == 2'd0) ? - (wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 ? - x__h41611 : + (wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 ? + x__h43006 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_8$write_1__VAL_2 = (wci_wciResponse_8$wget[33:32] == 2'd0) ? - (wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 ? - x__h45913 : + (wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 ? + x__h47446 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_9$write_1__VAL_2 = (wci_wciResponse_9$wget[33:32] == 2'd0) ? - (wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 ? - x__h50215 : + (wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 ? + x__h51886 : 32'd0) : 32'd0 ; @@ -10614,7 +10622,7 @@ module mkOCCP(pciDevice, assign timeServ_jamFrac_1$wget = 1'd1 ; assign timeServ_jamFrac_1$whas = timeServ_setRefF$dEMPTY_N && !timeServ_ppsOK ; - assign timeServ_jamFracVal_1$wget = x__h3445 ; + assign timeServ_jamFracVal_1$wget = x__h3699 ; assign timeServ_jamFracVal_1$whas = timeServ_jamFrac_1$whas ; assign deviceDNA$wget = { 7'd0, dna_sr } ; assign deviceDNA$whas = dna_cnt == 7'd127 ; @@ -11180,42 +11188,42 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or @@ -11231,11 +11239,11 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or @@ -11247,8 +11255,8 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F or @@ -11261,8 +11269,8 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F or @@ -11271,10 +11279,10 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T or @@ -11292,8 +11300,8 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T or @@ -11310,9 +11318,9 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F or @@ -11324,10 +11332,10 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F or @@ -11341,6 +11349,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F or WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T or + WILL_FIRE_RL_cpDispatch_F_T_T_T or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_T or @@ -11349,8 +11358,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_T or WILL_FIRE_RL_cpDispatch_T_F_F_F_T or WILL_FIRE_RL_cpDispatch_T_F_F_T or - WILL_FIRE_RL_cpDispatch_T_F_T or - WILL_FIRE_RL_cpDispatch_T_T or WILL_FIRE_RL_cpDispatch_F_T_T_T) + WILL_FIRE_RL_cpDispatch_T_F_T or WILL_FIRE_RL_cpDispatch_T_T) case (1'b1) WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -11474,42 +11482,42 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || @@ -11525,11 +11533,11 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || @@ -11541,8 +11549,8 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F || @@ -11555,8 +11563,8 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F || @@ -11565,10 +11573,10 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || @@ -11586,8 +11594,8 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -11604,9 +11612,9 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F || @@ -11618,10 +11626,10 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F || @@ -11635,6 +11643,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F || WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T || + WILL_FIRE_RL_cpDispatch_F_T_T_T || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_F || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_T || @@ -11644,8 +11653,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_T_F_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_F_T || WILL_FIRE_RL_cpDispatch_T_F_T || - WILL_FIRE_RL_cpDispatch_T_T || - WILL_FIRE_RL_cpDispatch_F_T_T_T: + WILL_FIRE_RL_cpDispatch_T_T: dispatched$D_IN = 1'd1; default: dispatched$D_IN = 1'b0 /* unspecified value */ ; endcase @@ -12024,17 +12032,17 @@ module mkOCCP(pciDevice, timeServ_fracSeconds - timeServ_lastSecond ; assign timeServ_delSecond$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5430 && - timeServ_refFromRise_3_ULT_200200000___d5853 ; + !timeServ_refFromRise_3_ULE_199800000___d5433 && + timeServ_refFromRise_3_ULT_200200000___d5848 ; // register timeServ_fracInc - assign timeServ_fracInc$D_IN = timeServ_fracInc + x__h4160 ; + assign timeServ_fracInc$D_IN = timeServ_fracInc + x__h4420 ; assign timeServ_fracInc$EN = timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d70 ; // register timeServ_fracSeconds assign timeServ_fracSeconds$D_IN = - timeServ_jamFrac ? timeServ_jamFracVal : x__h4388 ; + timeServ_jamFrac ? timeServ_jamFracVal : x__h4648 ; assign timeServ_fracSeconds$EN = 1'd1 ; // register timeServ_gpsInSticky @@ -12047,15 +12055,15 @@ module mkOCCP(pciDevice, // register timeServ_jamFracVal assign timeServ_jamFracVal$D_IN = - timeServ_jamFrac_1$whas ? x__h3445 : 50'd0 ; + timeServ_jamFrac_1$whas ? x__h3699 : 50'd0 ; assign timeServ_jamFracVal$EN = 1'd1 ; // register timeServ_lastSecond assign timeServ_lastSecond$D_IN = timeServ_fracSeconds ; assign timeServ_lastSecond$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5430 && - timeServ_refFromRise_3_ULT_200200000___d5853 ; + !timeServ_refFromRise_3_ULE_199800000___d5433 && + timeServ_refFromRise_3_ULT_200200000___d5848 ; // register timeServ_now assign timeServ_now$D_IN = @@ -12108,8 +12116,8 @@ module mkOCCP(pciDevice, // register timeServ_ppsOK assign timeServ_ppsOK$D_IN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5430 && - timeServ_refFromRise_3_ULT_200200000___d5853 || + !timeServ_refFromRise_3_ULE_199800000___d5433 && + timeServ_refFromRise_3_ULT_200200000___d5848 || timeServ_ppsOK && !timeServ_ppsLost ; assign timeServ_ppsOK$EN = 1'd1 ; @@ -12121,16 +12129,16 @@ module mkOCCP(pciDevice, assign timeServ_refFreeSamp$D_IN = timeServ_refFreeCount ; assign timeServ_refFreeSamp$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5430 && - timeServ_refFromRise_3_ULT_200200000___d5853 ; + !timeServ_refFromRise_3_ULE_199800000___d5433 && + timeServ_refFromRise_3_ULT_200200000___d5848 ; // register timeServ_refFreeSpan assign timeServ_refFreeSpan$D_IN = timeServ_refFreeCount - timeServ_refFreeSamp ; assign timeServ_refFreeSpan$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5430 && - timeServ_refFromRise_3_ULT_200200000___d5853 ; + !timeServ_refFromRise_3_ULE_199800000___d5433 && + timeServ_refFromRise_3_ULT_200200000___d5848 ; // register timeServ_refFromRise assign timeServ_refFromRise$D_IN = @@ -12141,7 +12149,7 @@ module mkOCCP(pciDevice, // register timeServ_refPerCount assign timeServ_refPerCount$D_IN = - IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5440 ? + IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d6037 ? 28'd0 : timeServ_refPerCount + 28'd1 ; assign timeServ_refPerCount$EN = 1'd1 ; @@ -12150,10 +12158,10 @@ module mkOCCP(pciDevice, assign timeServ_refSecCount$D_IN = timeServ_setRefF$dEMPTY_N ? timeServ_setRefF$dD_OUT[63:32] : - x__h4453 ; + x__h4714 ; assign timeServ_refSecCount$EN = timeServ_setRefF$dEMPTY_N || - IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5440 ; + IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d6037 ; // register timeServ_rplTimeControl assign timeServ_rplTimeControl$D_IN = cpReq[32:28] ; @@ -12182,7 +12190,7 @@ module mkOCCP(pciDevice, assign wci_busy$D_IN = !MUX_wci_busy$write_1__SEL_1 ; assign wci_busy$EN = WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 || + (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 || wci_wciResponse$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || @@ -12192,7 +12200,7 @@ module mkOCCP(pciDevice, assign wci_busy_1$D_IN = !MUX_wci_busy_1$write_1__SEL_1 ; assign wci_busy_1$EN = WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 || + (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 || wci_wciResponse_1$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || @@ -12202,7 +12210,7 @@ module mkOCCP(pciDevice, assign wci_busy_10$D_IN = !MUX_wci_busy_10$write_1__SEL_1 ; assign wci_busy_10$EN = WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 || + (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 || wci_wciResponse_10$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12212,7 +12220,7 @@ module mkOCCP(pciDevice, assign wci_busy_11$D_IN = !MUX_wci_busy_11$write_1__SEL_1 ; assign wci_busy_11$EN = WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 || + (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 || wci_wciResponse_11$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12222,7 +12230,7 @@ module mkOCCP(pciDevice, assign wci_busy_12$D_IN = !MUX_wci_busy_12$write_1__SEL_1 ; assign wci_busy_12$EN = WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 || + (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 || wci_wciResponse_12$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12232,7 +12240,7 @@ module mkOCCP(pciDevice, assign wci_busy_13$D_IN = !MUX_wci_busy_13$write_1__SEL_1 ; assign wci_busy_13$EN = WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 || + (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 || wci_wciResponse_13$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12242,7 +12250,7 @@ module mkOCCP(pciDevice, assign wci_busy_14$D_IN = !MUX_wci_busy_14$write_1__SEL_1 ; assign wci_busy_14$EN = WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 || + (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 || wci_wciResponse_14$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12252,7 +12260,7 @@ module mkOCCP(pciDevice, assign wci_busy_2$D_IN = !MUX_wci_busy_2$write_1__SEL_1 ; assign wci_busy_2$EN = WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 || + (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 || wci_wciResponse_2$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || @@ -12262,7 +12270,7 @@ module mkOCCP(pciDevice, assign wci_busy_3$D_IN = !MUX_wci_busy_3$write_1__SEL_1 ; assign wci_busy_3$EN = WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 || + (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 || wci_wciResponse_3$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || @@ -12272,7 +12280,7 @@ module mkOCCP(pciDevice, assign wci_busy_4$D_IN = !MUX_wci_busy_4$write_1__SEL_1 ; assign wci_busy_4$EN = WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 || + (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 || wci_wciResponse_4$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || @@ -12282,7 +12290,7 @@ module mkOCCP(pciDevice, assign wci_busy_5$D_IN = !MUX_wci_busy_5$write_1__SEL_1 ; assign wci_busy_5$EN = WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 || + (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 || wci_wciResponse_5$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12292,7 +12300,7 @@ module mkOCCP(pciDevice, assign wci_busy_6$D_IN = !MUX_wci_busy_6$write_1__SEL_1 ; assign wci_busy_6$EN = WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 || + (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 || wci_wciResponse_6$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12302,7 +12310,7 @@ module mkOCCP(pciDevice, assign wci_busy_7$D_IN = !MUX_wci_busy_7$write_1__SEL_1 ; assign wci_busy_7$EN = WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 || + (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 || wci_wciResponse_7$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12312,7 +12320,7 @@ module mkOCCP(pciDevice, assign wci_busy_8$D_IN = !MUX_wci_busy_8$write_1__SEL_1 ; assign wci_busy_8$EN = WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 || + (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 || wci_wciResponse_8$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12322,7 +12330,7 @@ module mkOCCP(pciDevice, assign wci_busy_9$D_IN = !MUX_wci_busy_9$write_1__SEL_1 ; assign wci_busy_9$EN = WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 || + (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 || wci_wciResponse_9$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -14214,7 +14222,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct$D_IN = wci_reqF_c_r ; assign wci_respTimrAct$EN = WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 || + (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 || wci_wciResponse$wget[33:32] != 2'd0) || wci_reqF_c_r ; @@ -14222,7 +14230,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_1$D_IN = wci_reqF_1_c_r ; assign wci_respTimrAct_1$EN = WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 || + (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 || wci_wciResponse_1$wget[33:32] != 2'd0) || wci_reqF_1_c_r ; @@ -14230,7 +14238,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_10$D_IN = wci_reqF_10_c_r ; assign wci_respTimrAct_10$EN = WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 || + (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 || wci_wciResponse_10$wget[33:32] != 2'd0) || wci_reqF_10_c_r ; @@ -14238,7 +14246,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_11$D_IN = wci_reqF_11_c_r ; assign wci_respTimrAct_11$EN = WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 || + (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 || wci_wciResponse_11$wget[33:32] != 2'd0) || wci_reqF_11_c_r ; @@ -14246,7 +14254,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_12$D_IN = wci_reqF_12_c_r ; assign wci_respTimrAct_12$EN = WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 || + (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 || wci_wciResponse_12$wget[33:32] != 2'd0) || wci_reqF_12_c_r ; @@ -14254,7 +14262,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_13$D_IN = wci_reqF_13_c_r ; assign wci_respTimrAct_13$EN = WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 || + (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 || wci_wciResponse_13$wget[33:32] != 2'd0) || wci_reqF_13_c_r ; @@ -14262,7 +14270,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_14$D_IN = wci_reqF_14_c_r ; assign wci_respTimrAct_14$EN = WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 || + (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 || wci_wciResponse_14$wget[33:32] != 2'd0) || wci_reqF_14_c_r ; @@ -14270,7 +14278,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_2$D_IN = wci_reqF_2_c_r ; assign wci_respTimrAct_2$EN = WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 || + (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 || wci_wciResponse_2$wget[33:32] != 2'd0) || wci_reqF_2_c_r ; @@ -14278,7 +14286,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_3$D_IN = wci_reqF_3_c_r ; assign wci_respTimrAct_3$EN = WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 || + (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 || wci_wciResponse_3$wget[33:32] != 2'd0) || wci_reqF_3_c_r ; @@ -14286,7 +14294,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_4$D_IN = wci_reqF_4_c_r ; assign wci_respTimrAct_4$EN = WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 || + (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 || wci_wciResponse_4$wget[33:32] != 2'd0) || wci_reqF_4_c_r ; @@ -14294,7 +14302,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_5$D_IN = wci_reqF_5_c_r ; assign wci_respTimrAct_5$EN = WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 || + (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 || wci_wciResponse_5$wget[33:32] != 2'd0) || wci_reqF_5_c_r ; @@ -14302,7 +14310,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_6$D_IN = wci_reqF_6_c_r ; assign wci_respTimrAct_6$EN = WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 || + (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 || wci_wciResponse_6$wget[33:32] != 2'd0) || wci_reqF_6_c_r ; @@ -14310,7 +14318,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_7$D_IN = wci_reqF_7_c_r ; assign wci_respTimrAct_7$EN = WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 || + (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 || wci_wciResponse_7$wget[33:32] != 2'd0) || wci_reqF_7_c_r ; @@ -14318,7 +14326,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_8$D_IN = wci_reqF_8_c_r ; assign wci_respTimrAct_8$EN = WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 || + (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 || wci_wciResponse_8$wget[33:32] != 2'd0) || wci_reqF_8_c_r ; @@ -14326,7 +14334,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_9$D_IN = wci_reqF_9_c_r ; assign wci_respTimrAct_9$EN = WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 || + (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 || wci_wciResponse_9$wget[33:32] != 2'd0) || wci_reqF_9_c_r ; @@ -15047,13 +15055,13 @@ module mkOCCP(pciDevice, // register wrkAct always@(MUX_wrkAct$write_1__SEL_1 or - _theResult_____1__h74424 or + _theResult_____1__h76795 or MUX_wrkAct$write_1__SEL_2 or - _theResult_____1__h74442 or MUX_wrkAct$write_1__SEL_3) + _theResult_____1__h76813 or MUX_wrkAct$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case - MUX_wrkAct$write_1__SEL_1: wrkAct$D_IN = _theResult_____1__h74424; - MUX_wrkAct$write_1__SEL_2: wrkAct$D_IN = _theResult_____1__h74442; + MUX_wrkAct$write_1__SEL_1: wrkAct$D_IN = _theResult_____1__h76795; + MUX_wrkAct$write_1__SEL_2: wrkAct$D_IN = _theResult_____1__h76813; MUX_wrkAct$write_1__SEL_3: wrkAct$D_IN = 4'd0; default: wrkAct$D_IN = 4'b1010 /* unspecified value */ ; endcase @@ -15589,7 +15597,7 @@ module mkOCCP(pciDevice, end assign wci_respF$ENQ = WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 || + (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 || wci_wciResponse$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T || @@ -15643,7 +15651,7 @@ module mkOCCP(pciDevice, end assign wci_respF_1$ENQ = WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 || + (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 || wci_wciResponse_1$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T || @@ -15698,7 +15706,7 @@ module mkOCCP(pciDevice, end assign wci_respF_10$ENQ = WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 || + (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 || wci_wciResponse_10$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -15753,7 +15761,7 @@ module mkOCCP(pciDevice, end assign wci_respF_11$ENQ = WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 || + (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 || wci_wciResponse_11$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -15808,7 +15816,7 @@ module mkOCCP(pciDevice, end assign wci_respF_12$ENQ = WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 || + (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 || wci_wciResponse_12$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -15863,7 +15871,7 @@ module mkOCCP(pciDevice, end assign wci_respF_13$ENQ = WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 || + (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 || wci_wciResponse_13$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -15918,7 +15926,7 @@ module mkOCCP(pciDevice, end assign wci_respF_14$ENQ = WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 || + (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 || wci_wciResponse_14$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -15973,7 +15981,7 @@ module mkOCCP(pciDevice, end assign wci_respF_2$ENQ = WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 || + (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 || wci_wciResponse_2$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T || @@ -16028,7 +16036,7 @@ module mkOCCP(pciDevice, end assign wci_respF_3$ENQ = WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 || + (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 || wci_wciResponse_3$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16083,7 +16091,7 @@ module mkOCCP(pciDevice, end assign wci_respF_4$ENQ = WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 || + (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 || wci_wciResponse_4$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16138,7 +16146,7 @@ module mkOCCP(pciDevice, end assign wci_respF_5$ENQ = WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 || + (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 || wci_wciResponse_5$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16193,7 +16201,7 @@ module mkOCCP(pciDevice, end assign wci_respF_6$ENQ = WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 || + (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 || wci_wciResponse_6$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16248,7 +16256,7 @@ module mkOCCP(pciDevice, end assign wci_respF_7$ENQ = WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 || + (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 || wci_wciResponse_7$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16303,7 +16311,7 @@ module mkOCCP(pciDevice, end assign wci_respF_8$ENQ = WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 || + (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 || wci_wciResponse_8$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16358,7 +16366,7 @@ module mkOCCP(pciDevice, end assign wci_respF_9$ENQ = WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 || + (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 || wci_wciResponse_9$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16384,276 +16392,276 @@ module mkOCCP(pciDevice, adminResp2F$D_OUT : (adminResp3F$EMPTY_N ? adminResp3F$D_OUT : adminResp4F$D_OUT) ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d3903 = - _theResult_____1__h74442 == 4'd0 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd0 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy && wci_respF$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d3912 = - _theResult_____1__h74442 == 4'd0 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd0 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy && wci_respF$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d3922 = - _theResult_____1__h74442 == 4'd0 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd0 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy && wci_respF$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d3981 = - _theResult_____1__h74442 == 4'd1 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd1 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_1 && wci_respF_1$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d3990 = - _theResult_____1__h74442 == 4'd1 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd1 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_1 && wci_respF_1$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4000 = - _theResult_____1__h74442 == 4'd1 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd1 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_1 && wci_respF_1$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4057 = - _theResult_____1__h74442 == 4'd2 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd2 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_2 && wci_respF_2$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4066 = - _theResult_____1__h74442 == 4'd2 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd2 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_2 && wci_respF_2$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4076 = - _theResult_____1__h74442 == 4'd2 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd2 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_2 && wci_respF_2$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4133 = - _theResult_____1__h74442 == 4'd3 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd3 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_3 && wci_respF_3$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4142 = - _theResult_____1__h74442 == 4'd3 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd3 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_3 && wci_respF_3$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4152 = - _theResult_____1__h74442 == 4'd3 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd3 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_3 && wci_respF_3$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4209 = - _theResult_____1__h74442 == 4'd4 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd4 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_4 && wci_respF_4$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4218 = - _theResult_____1__h74442 == 4'd4 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd4 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_4 && wci_respF_4$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4228 = - _theResult_____1__h74442 == 4'd4 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd4 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_4 && wci_respF_4$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4285 = - _theResult_____1__h74442 == 4'd5 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd5 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_5 && wci_respF_5$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4294 = - _theResult_____1__h74442 == 4'd5 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd5 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_5 && wci_respF_5$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4304 = - _theResult_____1__h74442 == 4'd5 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd5 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_5 && wci_respF_5$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4361 = - _theResult_____1__h74442 == 4'd6 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd6 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_6 && wci_respF_6$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4370 = - _theResult_____1__h74442 == 4'd6 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd6 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_6 && wci_respF_6$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4380 = - _theResult_____1__h74442 == 4'd6 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd6 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_6 && wci_respF_6$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4437 = - _theResult_____1__h74442 == 4'd7 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd7 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_7 && wci_respF_7$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4446 = - _theResult_____1__h74442 == 4'd7 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd7 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_7 && wci_respF_7$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4456 = - _theResult_____1__h74442 == 4'd7 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd7 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_7 && wci_respF_7$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4513 = - _theResult_____1__h74442 == 4'd8 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd8 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_8 && wci_respF_8$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4522 = - _theResult_____1__h74442 == 4'd8 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd8 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_8 && wci_respF_8$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4532 = - _theResult_____1__h74442 == 4'd8 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd8 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_8 && wci_respF_8$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4589 = - _theResult_____1__h74442 == 4'd9 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd9 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_9 && wci_respF_9$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4598 = - _theResult_____1__h74442 == 4'd9 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd9 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_9 && wci_respF_9$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4608 = - _theResult_____1__h74442 == 4'd9 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd9 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_9 && wci_respF_9$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4665 = - _theResult_____1__h74442 == 4'd10 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd10 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_10 && wci_respF_10$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4674 = - _theResult_____1__h74442 == 4'd10 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd10 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_10 && wci_respF_10$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4684 = - _theResult_____1__h74442 == 4'd10 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd10 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_10 && wci_respF_10$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4741 = - _theResult_____1__h74442 == 4'd11 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd11 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_11 && wci_respF_11$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4750 = - _theResult_____1__h74442 == 4'd11 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd11 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_11 && wci_respF_11$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4760 = - _theResult_____1__h74442 == 4'd11 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd11 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_11 && wci_respF_11$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4817 = - _theResult_____1__h74442 == 4'd12 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd12 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_12 && wci_respF_12$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4826 = - _theResult_____1__h74442 == 4'd12 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd12 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_12 && wci_respF_12$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4836 = - _theResult_____1__h74442 == 4'd12 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd12 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_12 && wci_respF_12$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4893 = - _theResult_____1__h74442 == 4'd13 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd13 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_13 && wci_respF_13$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4902 = - _theResult_____1__h74442 == 4'd13 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd13 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_13 && wci_respF_13$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4912 = - _theResult_____1__h74442 == 4'd13 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd13 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_13 && wci_respF_13$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4969 = - _theResult_____1__h74442 == 4'd14 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd14 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h8 && !wci_busy_14 && wci_respF_14$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4978 = - _theResult_____1__h74442 == 4'd14 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd14 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'h9 && !wci_busy_14 && wci_respF_14$FULL_N && !dispatched ; assign IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4988 = - _theResult_____1__h74442 == 4'd14 && cpReq[37:36] != 2'd2 && + _theResult_____1__h76813 == 4'd14 && cpReq[37:36] != 2'd2 && cpReq[9:6] == 4'hA && !wci_busy_14 && wci_respF_14$FULL_N && !dispatched ; - assign IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5440 = + assign IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d6037 = timeServ_ppsOK ? timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD : timeServ_delSec != timeServ_fracSeconds[49:48] ; @@ -16848,25 +16856,25 @@ module mkOCCP(pciDevice, adminResp2F$FULL_N && !dispatched ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_0_852_857_A_ETC___d5044 = - cpReq[64:62] != 3'd0 && _theResult_____1__h74442 != 4'd0 && - _theResult_____1__h74442 != 4'd1 && - _theResult_____1__h74442 != 4'd2 && - _theResult_____1__h74442 != 4'd3 && - _theResult_____1__h74442 != 4'd4 && - _theResult_____1__h74442 != 4'd5 && - _theResult_____1__h74442 != 4'd6 && - _theResult_____1__h74442 != 4'd7 && - _theResult_____1__h74442 != 4'd8 && - _theResult_____1__h74442 != 4'd9 && - _theResult_____1__h74442 != 4'd10 && - _theResult_____1__h74442 != 4'd11 && - _theResult_____1__h74442 != 4'd12 && - _theResult_____1__h74442 != 4'd13 && - _theResult_____1__h74442 != 4'd14 && + cpReq[64:62] != 3'd0 && _theResult_____1__h76813 != 4'd0 && + _theResult_____1__h76813 != 4'd1 && + _theResult_____1__h76813 != 4'd2 && + _theResult_____1__h76813 != 4'd3 && + _theResult_____1__h76813 != 4'd4 && + _theResult_____1__h76813 != 4'd5 && + _theResult_____1__h76813 != 4'd6 && + _theResult_____1__h76813 != 4'd7 && + _theResult_____1__h76813 != 4'd8 && + _theResult_____1__h76813 != 4'd9 && + _theResult_____1__h76813 != 4'd10 && + _theResult_____1__h76813 != 4'd11 && + _theResult_____1__h76813 != 4'd12 && + _theResult_____1__h76813 != 4'd13 && + _theResult_____1__h76813 != 4'd14 && !dispatched ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d3947 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd0 && + _theResult_____1__h76813 == 4'd0 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16875,7 +16883,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d2947 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4023 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd1 && + _theResult_____1__h76813 == 4'd1 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16884,7 +16892,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3009 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4099 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd2 && + _theResult_____1__h76813 == 4'd2 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16893,7 +16901,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3071 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4175 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd3 && + _theResult_____1__h76813 == 4'd3 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16902,7 +16910,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3133 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4251 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd4 && + _theResult_____1__h76813 == 4'd4 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16911,7 +16919,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3195 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4327 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd5 && + _theResult_____1__h76813 == 4'd5 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16920,7 +16928,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3257 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4403 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd6 && + _theResult_____1__h76813 == 4'd6 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16929,7 +16937,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3319 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4479 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd7 && + _theResult_____1__h76813 == 4'd7 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16938,7 +16946,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3381 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4555 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd8 && + _theResult_____1__h76813 == 4'd8 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16947,7 +16955,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3443 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4631 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd9 && + _theResult_____1__h76813 == 4'd9 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16956,7 +16964,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3505 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4707 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd10 && + _theResult_____1__h76813 == 4'd10 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16965,7 +16973,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3567 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4783 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd11 && + _theResult_____1__h76813 == 4'd11 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16974,7 +16982,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3629 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4859 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd12 && + _theResult_____1__h76813 == 4'd12 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16983,7 +16991,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3691 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d4935 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd13 && + _theResult_____1__h76813 == 4'd13 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -16992,7 +17000,7 @@ module mkOCCP(pciDevice, NOT_cpReq_363_BITS_9_TO_6_799_EQ_0xC_825_946_A_ETC___d3753 ; assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d5011 = cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h74442 == 4'd14 && + _theResult_____1__h76813 == 4'd14 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && cpReq[9:6] != 4'h8 && @@ -17127,12 +17135,12 @@ module mkOCCP(pciDevice, _281474976710656_MINUS_timeServ_delSecond__q1[49:28] ; assign _281474976710656_MINUS_timeServ_delSecond__q1 = 50'h1000000000000 - timeServ_delSecond ; - assign _theResult_____1__h74424 = - (cpReq[61:60] == 2'd2) ? wn___1__h75213 : wn__h74423 ; - assign _theResult_____1__h74442 = - (cpReq[37:36] == 2'd2) ? wn___1__h75213 : wn__h74423 ; - assign bAddr__h109903 = { cpReqF$D_OUT[57:36], 2'b0 } ; - assign bAddr__h110451 = { cpReqF$D_OUT[25:4], 2'b0 } ; + assign _theResult_____1__h76795 = + (cpReq[61:60] == 2'd2) ? wn___1__h77584 : wn__h76794 ; + assign _theResult_____1__h76813 = + (cpReq[37:36] == 2'd2) ? wn___1__h77584 : wn__h76794 ; + assign bAddr__h112551 = { cpReqF$D_OUT[57:36], 2'b0 } ; + assign bAddr__h113011 = { cpReqF$D_OUT[25:4], 2'b0 } ; assign cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_OR_cpRe_ETC___d2632 = (cpReq[11:4] == 8'h30 || cpReq[11:4] == 8'h34 || cpReq[11:4] == 8'h38 || @@ -17223,8 +17231,8 @@ module mkOCCP(pciDevice, cpReq[36] && !wci_busy_8 && wci_respF_8$FULL_N && !dispatched ; assign cpReq_363_BIT_36_910_AND_NOT_wci_busy_9_496_45_ETC___d3474 = cpReq[36] && !wci_busy_9 && wci_respF_9$FULL_N && !dispatched ; - assign cpStatus__h73568 = { 28'd0, rogueTLP } ; - assign crr_data__h74230 = + assign cpStatus__h75931 = { 28'd0, rogueTLP } ; + assign crr_data__h76601 = adminRespF$D_OUT[32] ? adminRespF$D_OUT[31:0] : 32'hDEADC0DE ; assign rom_serverAdapter_cnt_29_PLUS_IF_rom_serverAda_ETC___d135 = rom_serverAdapter_cnt + @@ -17234,79 +17242,79 @@ module mkOCCP(pciDevice, (rom_serverAdapter_outData_deqCalled$whas ? 3'd7 : 3'd0) ; assign timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d61 = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - (timeServ_refFromRise_3_ULE_199800000___d5430 || - !timeServ_refFromRise_3_ULT_200200000___d5853) || + (timeServ_refFromRise_3_ULE_199800000___d5433 || + !timeServ_refFromRise_3_ULT_200200000___d5848) || timeServ_refFromRise > 28'd200200000 ; assign timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d70 = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5430 && - timeServ_refFromRise_3_ULT_200200000___d5853 && + !timeServ_refFromRise_3_ULE_199800000___d5433 && + timeServ_refFromRise_3_ULT_200200000___d5848 && timeServ_ppsOK && !timeServ_disableServo$dD_OUT ; - assign timeServ_refFromRise_3_ULE_199800000___d5430 = + assign timeServ_refFromRise_3_ULE_199800000___d5433 = timeServ_refFromRise <= 28'd199800000 ; - assign timeServ_refFromRise_3_ULT_200200000___d5853 = + assign timeServ_refFromRise_3_ULT_200200000___d5848 = timeServ_refFromRise < 28'd200200000 ; - assign toCount__h11335 = 32'd1 << wci_wTimeout ; - assign toCount__h15643 = 32'd1 << wci_wTimeout_1 ; - assign toCount__h19945 = 32'd1 << wci_wTimeout_2 ; - assign toCount__h24247 = 32'd1 << wci_wTimeout_3 ; - assign toCount__h28549 = 32'd1 << wci_wTimeout_4 ; - assign toCount__h32851 = 32'd1 << wci_wTimeout_5 ; - assign toCount__h37153 = 32'd1 << wci_wTimeout_6 ; - assign toCount__h41455 = 32'd1 << wci_wTimeout_7 ; - assign toCount__h45757 = 32'd1 << wci_wTimeout_8 ; - assign toCount__h50059 = 32'd1 << wci_wTimeout_9 ; - assign toCount__h54361 = 32'd1 << wci_wTimeout_10 ; - assign toCount__h58663 = 32'd1 << wci_wTimeout_11 ; - assign toCount__h62965 = 32'd1 << wci_wTimeout_12 ; - assign toCount__h67267 = 32'd1 << wci_wTimeout_13 ; - assign toCount__h71569 = 32'd1 << wci_wTimeout_14 ; - assign wciAddr__h75955 = { wci_pageWindow, cpReq[23:4] } ; - assign wciAddr__h76023 = { wci_pageWindow_1, cpReq[23:4] } ; - assign wciAddr__h76089 = { wci_pageWindow_2, cpReq[23:4] } ; - assign wciAddr__h76155 = { wci_pageWindow_3, cpReq[23:4] } ; - assign wciAddr__h76221 = { wci_pageWindow_4, cpReq[23:4] } ; - assign wciAddr__h76287 = { wci_pageWindow_5, cpReq[23:4] } ; - assign wciAddr__h76353 = { wci_pageWindow_6, cpReq[23:4] } ; - assign wciAddr__h76419 = { wci_pageWindow_7, cpReq[23:4] } ; - assign wciAddr__h76485 = { wci_pageWindow_8, cpReq[23:4] } ; - assign wciAddr__h76551 = { wci_pageWindow_9, cpReq[23:4] } ; - assign wciAddr__h76617 = { wci_pageWindow_10, cpReq[23:4] } ; - assign wciAddr__h76683 = { wci_pageWindow_11, cpReq[23:4] } ; - assign wciAddr__h76749 = { wci_pageWindow_12, cpReq[23:4] } ; - assign wciAddr__h76815 = { wci_pageWindow_13, cpReq[23:4] } ; - assign wciAddr__h76881 = { wci_pageWindow_14, cpReq[23:4] } ; - assign wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 = - wci_respTimr_10 < toCount__h54361 ; - assign wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 = - wci_respTimr_11 < toCount__h58663 ; - assign wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 = - wci_respTimr_12 < toCount__h62965 ; - assign wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 = - wci_respTimr_13 < toCount__h67267 ; - assign wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 = - wci_respTimr_14 < toCount__h71569 ; - assign wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 = - wci_respTimr_1 < toCount__h15643 ; - assign wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 = - wci_respTimr < toCount__h11335 ; - assign wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 = - wci_respTimr_2 < toCount__h19945 ; - assign wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 = - wci_respTimr_3 < toCount__h24247 ; - assign wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 = - wci_respTimr_4 < toCount__h28549 ; - assign wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 = - wci_respTimr_5 < toCount__h32851 ; - assign wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 = - wci_respTimr_6 < toCount__h37153 ; - assign wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 = - wci_respTimr_7 < toCount__h41455 ; - assign wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 = - wci_respTimr_8 < toCount__h45757 ; - assign wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 = - wci_respTimr_9 < toCount__h50059 ; + assign toCount__h11763 = 32'd1 << wci_wTimeout ; + assign toCount__h16209 = 32'd1 << wci_wTimeout_1 ; + assign toCount__h20649 = 32'd1 << wci_wTimeout_2 ; + assign toCount__h25089 = 32'd1 << wci_wTimeout_3 ; + assign toCount__h29529 = 32'd1 << wci_wTimeout_4 ; + assign toCount__h33969 = 32'd1 << wci_wTimeout_5 ; + assign toCount__h38409 = 32'd1 << wci_wTimeout_6 ; + assign toCount__h42849 = 32'd1 << wci_wTimeout_7 ; + assign toCount__h47289 = 32'd1 << wci_wTimeout_8 ; + assign toCount__h51729 = 32'd1 << wci_wTimeout_9 ; + assign toCount__h56169 = 32'd1 << wci_wTimeout_10 ; + assign toCount__h60609 = 32'd1 << wci_wTimeout_11 ; + assign toCount__h65049 = 32'd1 << wci_wTimeout_12 ; + assign toCount__h69489 = 32'd1 << wci_wTimeout_13 ; + assign toCount__h73929 = 32'd1 << wci_wTimeout_14 ; + assign wciAddr__h78326 = { wci_pageWindow, cpReq[23:4] } ; + assign wciAddr__h78394 = { wci_pageWindow_1, cpReq[23:4] } ; + assign wciAddr__h78460 = { wci_pageWindow_2, cpReq[23:4] } ; + assign wciAddr__h78526 = { wci_pageWindow_3, cpReq[23:4] } ; + assign wciAddr__h78592 = { wci_pageWindow_4, cpReq[23:4] } ; + assign wciAddr__h78658 = { wci_pageWindow_5, cpReq[23:4] } ; + assign wciAddr__h78724 = { wci_pageWindow_6, cpReq[23:4] } ; + assign wciAddr__h78790 = { wci_pageWindow_7, cpReq[23:4] } ; + assign wciAddr__h78856 = { wci_pageWindow_8, cpReq[23:4] } ; + assign wciAddr__h78922 = { wci_pageWindow_9, cpReq[23:4] } ; + assign wciAddr__h78988 = { wci_pageWindow_10, cpReq[23:4] } ; + assign wciAddr__h79054 = { wci_pageWindow_11, cpReq[23:4] } ; + assign wciAddr__h79120 = { wci_pageWindow_12, cpReq[23:4] } ; + assign wciAddr__h79186 = { wci_pageWindow_13, cpReq[23:4] } ; + assign wciAddr__h79252 = { wci_pageWindow_14, cpReq[23:4] } ; + assign wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 = + wci_respTimr_10 < toCount__h56169 ; + assign wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 = + wci_respTimr_11 < toCount__h60609 ; + assign wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 = + wci_respTimr_12 < toCount__h65049 ; + assign wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 = + wci_respTimr_13 < toCount__h69489 ; + assign wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 = + wci_respTimr_14 < toCount__h73929 ; + assign wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 = + wci_respTimr_1 < toCount__h16209 ; + assign wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 = + wci_respTimr < toCount__h11763 ; + assign wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 = + wci_respTimr_2 < toCount__h20649 ; + assign wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 = + wci_respTimr_3 < toCount__h25089 ; + assign wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 = + wci_respTimr_4 < toCount__h29529 ; + assign wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 = + wci_respTimr_5 < toCount__h33969 ; + assign wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 = + wci_respTimr_6 < toCount__h38409 ; + assign wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 = + wci_respTimr_7 < toCount__h42849 ; + assign wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 = + wci_respTimr_8 < toCount__h47289 ; + assign wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 = + wci_respTimr_9 < toCount__h51729 ; assign wci_wReset_n_10_616_AND_NOT_wci_busy_10_636_51_ETC___d3515 = wci_wReset_n_10 && !wci_busy_10 && !wci_reqF_10_c_r && !dispatched ; @@ -17344,82 +17352,82 @@ module mkOCCP(pciDevice, wci_wReset_n_9 && !wci_busy_9 && !wci_reqF_9_c_r && !dispatched ; assign wci_wciResponse_10_wget__623_BITS_33_TO_32_624_ETC___d1652 = wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 && (wci_reqPend_10 == 2'd1 || wci_reqPend_10 == 2'd2 || wci_reqPend_10 == 2'd3) ; assign wci_wciResponse_11_wget__763_BITS_33_TO_32_764_ETC___d1792 = wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 && (wci_reqPend_11 == 2'd1 || wci_reqPend_11 == 2'd2 || wci_reqPend_11 == 2'd3) ; assign wci_wciResponse_12_wget__903_BITS_33_TO_32_904_ETC___d1932 = wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 && (wci_reqPend_12 == 2'd1 || wci_reqPend_12 == 2'd2 || wci_reqPend_12 == 2'd3) ; assign wci_wciResponse_13_wget__043_BITS_33_TO_32_044_ETC___d2072 = wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 && (wci_reqPend_13 == 2'd1 || wci_reqPend_13 == 2'd2 || wci_reqPend_13 == 2'd3) ; assign wci_wciResponse_14_wget__183_BITS_33_TO_32_184_ETC___d2212 = wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 && (wci_reqPend_14 == 2'd1 || wci_reqPend_14 == 2'd2 || wci_reqPend_14 == 2'd3) ; assign wci_wciResponse_1_wget__63_BITS_33_TO_32_64_EQ_ETC___d392 = wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 && (wci_reqPend_1 == 2'd1 || wci_reqPend_1 == 2'd2 || wci_reqPend_1 == 2'd3) ; assign wci_wciResponse_2_wget__03_BITS_33_TO_32_04_EQ_ETC___d532 = wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 && (wci_reqPend_2 == 2'd1 || wci_reqPend_2 == 2'd2 || wci_reqPend_2 == 2'd3) ; assign wci_wciResponse_3_wget__43_BITS_33_TO_32_44_EQ_ETC___d672 = wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 && (wci_reqPend_3 == 2'd1 || wci_reqPend_3 == 2'd2 || wci_reqPend_3 == 2'd3) ; assign wci_wciResponse_4_wget__83_BITS_33_TO_32_84_EQ_ETC___d812 = wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 && (wci_reqPend_4 == 2'd1 || wci_reqPend_4 == 2'd2 || wci_reqPend_4 == 2'd3) ; assign wci_wciResponse_5_wget__23_BITS_33_TO_32_24_EQ_ETC___d952 = wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 && (wci_reqPend_5 == 2'd1 || wci_reqPend_5 == 2'd2 || wci_reqPend_5 == 2'd3) ; assign wci_wciResponse_6_wget__063_BITS_33_TO_32_064__ETC___d1092 = wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 && (wci_reqPend_6 == 2'd1 || wci_reqPend_6 == 2'd2 || wci_reqPend_6 == 2'd3) ; assign wci_wciResponse_7_wget__203_BITS_33_TO_32_204__ETC___d1232 = wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 && (wci_reqPend_7 == 2'd1 || wci_reqPend_7 == 2'd2 || wci_reqPend_7 == 2'd3) ; assign wci_wciResponse_8_wget__343_BITS_33_TO_32_344__ETC___d1372 = wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 && (wci_reqPend_8 == 2'd1 || wci_reqPend_8 == 2'd2 || wci_reqPend_8 == 2'd3) ; assign wci_wciResponse_9_wget__483_BITS_33_TO_32_484__ETC___d1512 = wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 && (wci_reqPend_9 == 2'd1 || wci_reqPend_9 == 2'd2 || wci_reqPend_9 == 2'd3) ; assign wci_wciResponse_wget__23_BITS_33_TO_32_24_EQ_0_ETC___d252 = wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 && (wci_reqPend == 2'd1 || wci_reqPend == 2'd2 || wci_reqPend == 2'd3) ; - assign wn___1__h75213 = cpReq[27:24] - 4'd1 ; - assign wn__h74423 = cpReq[23:20] - 4'd1 ; - assign x__h103324 = + assign wn___1__h77584 = cpReq[27:24] - 4'd1 ; + assign wn__h76794 = cpReq[23:20] - 4'd1 ; + assign x__h105695 = { wci_slvPresent_14, wci_slvPresent_13, wci_slvPresent_12, @@ -17435,7 +17443,7 @@ module mkOCCP(pciDevice, wci_slvPresent_2, wci_slvPresent_1, wci_slvPresent } ; - assign x__h103873 = + assign x__h106244 = { wci_wStatus_14[15:0] != 16'd0, wci_wStatus_13[15:0] != 16'd0, wci_wStatus_12[15:0] != 16'd0, @@ -17451,105 +17459,105 @@ module mkOCCP(pciDevice, wci_wStatus_2[15:0] != 16'd0, wci_wStatus_1[15:0] != 16'd0, wci_wStatus[15:0] != 16'd0 } ; - assign x__h11494 = wci_respTimr + 32'd1 ; - assign x__h15799 = wci_respTimr_1 + 32'd1 ; - assign x__h20101 = wci_respTimr_2 + 32'd1 ; - assign x__h24403 = wci_respTimr_3 + 32'd1 ; - assign x__h28705 = wci_respTimr_4 + 32'd1 ; - assign x__h33007 = wci_respTimr_5 + 32'd1 ; - assign x__h3445 = { 2'b0, x_f__h4586 } ; - assign x__h37309 = wci_respTimr_6 + 32'd1 ; - assign x__h4160 = + assign x__h11923 = wci_respTimr + 32'd1 ; + assign x__h16366 = wci_respTimr_1 + 32'd1 ; + assign x__h20806 = wci_respTimr_2 + 32'd1 ; + assign x__h25246 = wci_respTimr_3 + 32'd1 ; + assign x__h29686 = wci_respTimr_4 + 32'd1 ; + assign x__h34126 = wci_respTimr_5 + 32'd1 ; + assign x__h3699 = { 2'b0, x_f__h4847 } ; + assign x__h38566 = wci_respTimr_6 + 32'd1 ; + assign x__h43006 = wci_respTimr_7 + 32'd1 ; + assign x__h4420 = { {28{_281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2[21]}}, _281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2 } ; - assign x__h41611 = wci_respTimr_7 + 32'd1 ; - assign x__h4388 = timeServ_fracSeconds + timeServ_fracInc ; - assign x__h4453 = timeServ_refSecCount + 32'd1 ; - assign x__h45913 = wci_respTimr_8 + 32'd1 ; - assign x__h50215 = wci_respTimr_9 + 32'd1 ; - assign x__h54517 = wci_respTimr_10 + 32'd1 ; - assign x__h58819 = wci_respTimr_11 + 32'd1 ; - assign x__h63121 = wci_respTimr_12 + 32'd1 ; - assign x__h67423 = wci_respTimr_13 + 32'd1 ; - assign x__h71725 = wci_respTimr_14 + 32'd1 ; - assign x__h95536 = { cpReq[8:6], 2'b0 } ; - assign x_addr__h95534 = { 27'd0, x__h95536 } ; - assign x_data__h101740 = { wci_wReset_n, 26'd0, wci_wTimeout } ; - assign x_data__h101746 = + assign x__h4648 = timeServ_fracSeconds + timeServ_fracInc ; + assign x__h4714 = timeServ_refSecCount + 32'd1 ; + assign x__h47446 = wci_respTimr_8 + 32'd1 ; + assign x__h51886 = wci_respTimr_9 + 32'd1 ; + assign x__h56326 = wci_respTimr_10 + 32'd1 ; + assign x__h60766 = wci_respTimr_11 + 32'd1 ; + assign x__h65206 = wci_respTimr_12 + 32'd1 ; + assign x__h69646 = wci_respTimr_13 + 32'd1 ; + assign x__h74086 = wci_respTimr_14 + 32'd1 ; + assign x__h97907 = { cpReq[8:6], 2'b0 } ; + assign x_addr__h97905 = { 27'd0, x__h97907 } ; + assign x_data__h104111 = { wci_wReset_n, 26'd0, wci_wTimeout } ; + assign x_data__h104117 = wci_lastConfigAddr[32] ? wci_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h101793 = { wci_wReset_n_1, 26'd0, wci_wTimeout_1 } ; - assign x_data__h101799 = + assign x_data__h104164 = { wci_wReset_n_1, 26'd0, wci_wTimeout_1 } ; + assign x_data__h104170 = wci_lastConfigAddr_1[32] ? wci_lastConfigAddr_1[31:0] : 32'hFFFFFFFF ; - assign x_data__h101846 = { wci_wReset_n_2, 26'd0, wci_wTimeout_2 } ; - assign x_data__h101852 = + assign x_data__h104217 = { wci_wReset_n_2, 26'd0, wci_wTimeout_2 } ; + assign x_data__h104223 = wci_lastConfigAddr_2[32] ? wci_lastConfigAddr_2[31:0] : 32'hFFFFFFFF ; - assign x_data__h101899 = { wci_wReset_n_3, 26'd0, wci_wTimeout_3 } ; - assign x_data__h101905 = + assign x_data__h104270 = { wci_wReset_n_3, 26'd0, wci_wTimeout_3 } ; + assign x_data__h104276 = wci_lastConfigAddr_3[32] ? wci_lastConfigAddr_3[31:0] : 32'hFFFFFFFF ; - assign x_data__h101952 = { wci_wReset_n_4, 26'd0, wci_wTimeout_4 } ; - assign x_data__h101958 = + assign x_data__h104323 = { wci_wReset_n_4, 26'd0, wci_wTimeout_4 } ; + assign x_data__h104329 = wci_lastConfigAddr_4[32] ? wci_lastConfigAddr_4[31:0] : 32'hFFFFFFFF ; - assign x_data__h102005 = { wci_wReset_n_5, 26'd0, wci_wTimeout_5 } ; - assign x_data__h102011 = + assign x_data__h104376 = { wci_wReset_n_5, 26'd0, wci_wTimeout_5 } ; + assign x_data__h104382 = wci_lastConfigAddr_5[32] ? wci_lastConfigAddr_5[31:0] : 32'hFFFFFFFF ; - assign x_data__h102058 = { wci_wReset_n_6, 26'd0, wci_wTimeout_6 } ; - assign x_data__h102064 = + assign x_data__h104429 = { wci_wReset_n_6, 26'd0, wci_wTimeout_6 } ; + assign x_data__h104435 = wci_lastConfigAddr_6[32] ? wci_lastConfigAddr_6[31:0] : 32'hFFFFFFFF ; - assign x_data__h102111 = { wci_wReset_n_7, 26'd0, wci_wTimeout_7 } ; - assign x_data__h102117 = + assign x_data__h104482 = { wci_wReset_n_7, 26'd0, wci_wTimeout_7 } ; + assign x_data__h104488 = wci_lastConfigAddr_7[32] ? wci_lastConfigAddr_7[31:0] : 32'hFFFFFFFF ; - assign x_data__h102164 = { wci_wReset_n_8, 26'd0, wci_wTimeout_8 } ; - assign x_data__h102170 = + assign x_data__h104535 = { wci_wReset_n_8, 26'd0, wci_wTimeout_8 } ; + assign x_data__h104541 = wci_lastConfigAddr_8[32] ? wci_lastConfigAddr_8[31:0] : 32'hFFFFFFFF ; - assign x_data__h102217 = { wci_wReset_n_9, 26'd0, wci_wTimeout_9 } ; - assign x_data__h102223 = + assign x_data__h104588 = { wci_wReset_n_9, 26'd0, wci_wTimeout_9 } ; + assign x_data__h104594 = wci_lastConfigAddr_9[32] ? wci_lastConfigAddr_9[31:0] : 32'hFFFFFFFF ; - assign x_data__h102270 = { wci_wReset_n_10, 26'd0, wci_wTimeout_10 } ; - assign x_data__h102276 = + assign x_data__h104641 = { wci_wReset_n_10, 26'd0, wci_wTimeout_10 } ; + assign x_data__h104647 = wci_lastConfigAddr_10[32] ? wci_lastConfigAddr_10[31:0] : 32'hFFFFFFFF ; - assign x_data__h102323 = { wci_wReset_n_11, 26'd0, wci_wTimeout_11 } ; - assign x_data__h102329 = + assign x_data__h104694 = { wci_wReset_n_11, 26'd0, wci_wTimeout_11 } ; + assign x_data__h104700 = wci_lastConfigAddr_11[32] ? wci_lastConfigAddr_11[31:0] : 32'hFFFFFFFF ; - assign x_data__h102376 = { wci_wReset_n_12, 26'd0, wci_wTimeout_12 } ; - assign x_data__h102382 = + assign x_data__h104747 = { wci_wReset_n_12, 26'd0, wci_wTimeout_12 } ; + assign x_data__h104753 = wci_lastConfigAddr_12[32] ? wci_lastConfigAddr_12[31:0] : 32'hFFFFFFFF ; - assign x_data__h102429 = { wci_wReset_n_13, 26'd0, wci_wTimeout_13 } ; - assign x_data__h102435 = + assign x_data__h104800 = { wci_wReset_n_13, 26'd0, wci_wTimeout_13 } ; + assign x_data__h104806 = wci_lastConfigAddr_13[32] ? wci_lastConfigAddr_13[31:0] : 32'hFFFFFFFF ; - assign x_data__h102482 = { wci_wReset_n_14, 26'd0, wci_wTimeout_14 } ; - assign x_data__h102488 = + assign x_data__h104853 = { wci_wReset_n_14, 26'd0, wci_wTimeout_14 } ; + assign x_data__h104859 = wci_lastConfigAddr_14[32] ? wci_lastConfigAddr_14[31:0] : 32'hFFFFFFFF ; - assign x_f__h4586 = { timeServ_setRefF$dD_OUT[31:0], 16'h0 } ; + assign x_f__h4847 = { timeServ_setRefF$dD_OUT[31:0], 16'h0 } ; always@(wrkAct or wci_respF_14$D_OUT or wci_respF$D_OUT or @@ -17566,21 +17574,21 @@ module mkOCCP(pciDevice, wci_respF_11$D_OUT or wci_respF_12$D_OUT or wci_respF_13$D_OUT) begin case (wrkAct) - 4'd0: rtnData__h109398 = wci_respF$D_OUT[31:0]; - 4'd1: rtnData__h109398 = wci_respF_1$D_OUT[31:0]; - 4'd2: rtnData__h109398 = wci_respF_2$D_OUT[31:0]; - 4'd3: rtnData__h109398 = wci_respF_3$D_OUT[31:0]; - 4'd4: rtnData__h109398 = wci_respF_4$D_OUT[31:0]; - 4'd5: rtnData__h109398 = wci_respF_5$D_OUT[31:0]; - 4'd6: rtnData__h109398 = wci_respF_6$D_OUT[31:0]; - 4'd7: rtnData__h109398 = wci_respF_7$D_OUT[31:0]; - 4'd8: rtnData__h109398 = wci_respF_8$D_OUT[31:0]; - 4'd9: rtnData__h109398 = wci_respF_9$D_OUT[31:0]; - 4'd10: rtnData__h109398 = wci_respF_10$D_OUT[31:0]; - 4'd11: rtnData__h109398 = wci_respF_11$D_OUT[31:0]; - 4'd12: rtnData__h109398 = wci_respF_12$D_OUT[31:0]; - 4'd13: rtnData__h109398 = wci_respF_13$D_OUT[31:0]; - default: rtnData__h109398 = wci_respF_14$D_OUT[31:0]; + 4'd0: rtnData__h112042 = wci_respF$D_OUT[31:0]; + 4'd1: rtnData__h112042 = wci_respF_1$D_OUT[31:0]; + 4'd2: rtnData__h112042 = wci_respF_2$D_OUT[31:0]; + 4'd3: rtnData__h112042 = wci_respF_3$D_OUT[31:0]; + 4'd4: rtnData__h112042 = wci_respF_4$D_OUT[31:0]; + 4'd5: rtnData__h112042 = wci_respF_5$D_OUT[31:0]; + 4'd6: rtnData__h112042 = wci_respF_6$D_OUT[31:0]; + 4'd7: rtnData__h112042 = wci_respF_7$D_OUT[31:0]; + 4'd8: rtnData__h112042 = wci_respF_8$D_OUT[31:0]; + 4'd9: rtnData__h112042 = wci_respF_9$D_OUT[31:0]; + 4'd10: rtnData__h112042 = wci_respF_10$D_OUT[31:0]; + 4'd11: rtnData__h112042 = wci_respF_11$D_OUT[31:0]; + 4'd12: rtnData__h112042 = wci_respF_12$D_OUT[31:0]; + 4'd13: rtnData__h112042 = wci_respF_13$D_OUT[31:0]; + default: rtnData__h112042 = wci_respF_14$D_OUT[31:0]; endcase end always@(wrkAct or @@ -17601,56 +17609,56 @@ module mkOCCP(pciDevice, begin case (wrkAct) 4'd0: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF$EMPTY_N; 4'd1: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_1$EMPTY_N; 4'd2: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_2$EMPTY_N; 4'd3: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_3$EMPTY_N; 4'd4: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_4$EMPTY_N; 4'd5: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_5$EMPTY_N; 4'd6: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_6$EMPTY_N; 4'd7: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_7$EMPTY_N; 4'd8: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_8$EMPTY_N; 4'd9: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_9$EMPTY_N; 4'd10: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_10$EMPTY_N; 4'd11: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_11$EMPTY_N; 4'd12: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_12$EMPTY_N; 4'd13: - IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wci_respF_13$EMPTY_N; - default: IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6130 = + default: IF_wrkAct_048_EQ_0_049_THEN_wci_respF_i_notEmp_ETC___d6100 = wrkAct != 4'd14 || wci_respF_14$EMPTY_N; endcase end always@(cpReq or - x__h103324 or + x__h105695 or pciDevice or - x__h103873 or - cpStatus__h73568 or scratch20 or scratch24 or cpControl) + x__h106244 or + cpStatus__h75931 or scratch20 or scratch24 or cpControl) begin case (cpReq[11:4]) 8'h0: @@ -17667,16 +17675,16 @@ module mkOCCP(pciDevice, 32'd1347452376; 8'h10: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d6132 = - { 17'd0, x__h103324 }; + { 17'd0, x__h105695 }; 8'h14: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d6132 = { 16'd0, pciDevice }; 8'h18: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d6132 = - { 17'd0, x__h103873 }; + { 17'd0, x__h106244 }; 8'h1C: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d6132 = - cpStatus__h73568; + cpStatus__h75931; 8'h20: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d6132 = scratch20; @@ -17808,7 +17816,7 @@ module mkOCCP(pciDevice, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin cpControl <= `BSV_ASSIGNMENT_DELAY 32'd0; cpReq <= `BSV_ASSIGNMENT_DELAY 65'h02AAAAAAAAAAAAAAA; @@ -18944,7 +18952,7 @@ module mkOCCP(pciDevice, always@(posedge CLK_time_clk) begin - if (!RST_N_time_rst) + if (RST_N_time_rst == `BSV_RESET_VALUE) begin timeServ_delSec <= `BSV_ASSIGNMENT_DELAY 2'd0; timeServ_delSecond <= `BSV_ASSIGNMENT_DELAY 50'h1000000000000; @@ -19442,6185 +19450,6185 @@ module mkOCCP(pciDevice, always@(negedge CLK) begin #0; - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T) begin - v__h77130 = $time; + v__h79501 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h77130); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h79501); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T) begin - v__h77788 = $time; + v__h80159 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h77788); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h80159); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, - cpReq[61:60], - cpReq[27:4], - cpReq[59:28], - cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T) - begin - v__h103101 = $time; - #0; - end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T) - $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T) begin - v__h78433 = $time; + v__h80804 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h78433); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h80804); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T) + begin + v__h105472 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T) + $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", + v__h105472, + _theResult_____1__h76795, + cpReq[61:60], + cpReq[27:4], + cpReq[59:28], + cpReq[3:0]); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T) begin - v__h79078 = $time; + v__h81449 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h79078); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h81449); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T) begin - v__h79723 = $time; + v__h82094 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h79723); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82094); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T) begin - v__h80368 = $time; + v__h82739 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h80368); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82739); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T) begin - v__h81013 = $time; + v__h83384 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h81013); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h83384); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T) begin - v__h81658 = $time; + v__h84029 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h81658); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84029); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T) begin - v__h82303 = $time; + v__h84674 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82303); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84674); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h82948 = $time; + v__h85319 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82948); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h85319); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h85964 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) - $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, - cpReq[61:60], - cpReq[27:4], - cpReq[59:28], - cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h85964); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h83593 = $time; + v__h105472 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h83593); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) + $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", + v__h105472, + _theResult_____1__h76795, + cpReq[61:60], + cpReq[27:4], + cpReq[59:28], + cpReq[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h84238 = $time; + v__h86609 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84238); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h86609); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h84883 = $time; + v__h87254 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84883); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h87254); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h85528 = $time; + v__h87899 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h85528); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h87899); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h86173 = $time; + v__h88544 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h86173); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h88544); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F) begin - v__h94113 = $time; + v__h105472 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94113); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F) + $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", + v__h105472, + _theResult_____1__h76795, + cpReq[61:60], + cpReq[27:4], + cpReq[59:28], + cpReq[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) begin - v__h103101 = $time; + v__h96484 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F) - $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, - cpReq[61:60], - cpReq[27:4], - cpReq[59:28], - cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96484); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F) begin - v__h94185 = $time; + v__h96556 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94185); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96556); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F) begin - v__h94257 = $time; + v__h96628 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94257); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96628); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F) begin - v__h94329 = $time; + v__h96700 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94329); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96700); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h94401 = $time; + v__h96772 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94401); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96772); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h94473 = $time; + v__h96844 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94473); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96844); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) - begin - v__h103154 = $time; - #0; - end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) - $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, - cpReq[37:36], - cpReq[27:4], - cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, + cpReq[37:36], + cpReq[27:4], + cpReq[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + begin + v__h105525 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h94545 = $time; + v__h96916 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94545); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96916); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h94617 = $time; + v__h96988 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94617); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96988); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h97060 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) - $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, - cpReq[37:36], - cpReq[27:4], - cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97060); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h94689 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94689); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", + v__h105525, + _theResult_____1__h76813, + cpReq[37:36], + cpReq[27:4], + cpReq[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) - begin - v__h103154 = $time; - #0; - end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) - $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, - cpReq[37:36], - cpReq[27:4], - cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h94761 = $time; + v__h97132 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94761); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97132); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, + cpReq[37:36], + cpReq[27:4], + cpReq[3:0]); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + begin + v__h105525 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h94833 = $time; + v__h97204 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94833); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97204); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h94905 = $time; + v__h97276 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94905); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97276); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h94977 = $time; + v__h97348 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94977); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97348); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h95049 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95049); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", + v__h105525, + _theResult_____1__h76813, + cpReq[37:36], + cpReq[27:4], + cpReq[3:0]); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h97420 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97420); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, - cpReq[37:36], - cpReq[27:4], - cpReq[3:0]); - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h95121 = $time; + v__h97492 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95121); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97492); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (rom_serverAdapter_s1[1] && !rom_serverAdapter_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T) begin - v__h94113 = $time; + v__h96484 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94113); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96484); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T) begin - v__h94185 = $time; + v__h96556 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94185); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96556); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T) begin - v__h94257 = $time; + v__h96628 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94257); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96628); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T) begin - v__h94329 = $time; + v__h96700 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94329); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96700); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h94401 = $time; + v__h96772 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94401); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96772); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h94473 = $time; + v__h96844 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94473); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96844); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h94545 = $time; + v__h96916 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94545); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96916); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h94617 = $time; + v__h96988 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94617); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96988); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h94689 = $time; + v__h97060 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94689); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97060); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h94761 = $time; + v__h97132 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94761); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97132); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h94833 = $time; + v__h97204 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94833); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97204); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h94905 = $time; + v__h97276 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94905); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97276); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h94977 = $time; + v__h97348 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h94977); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97348); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h95049 = $time; + v__h97420 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95049); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97420); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) begin - v__h103101 = $time; + v__h105472 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h103101, - _theResult_____1__h74424, + v__h105472, + _theResult_____1__h76795, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h95121 = $time; + v__h97492 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95121); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97492); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) begin - v__h103154 = $time; + v__h105525 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h103154, - _theResult_____1__h74442, + v__h105525, + _theResult_____1__h76813, cpReq[37:36], cpReq[27:4], cpReq[3:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 && wci_reqPend == 2'd1) begin - v__h11627 = $time; + v__h12056 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 && wci_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h11627); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h12056); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 && wci_reqPend == 2'd2) begin - v__h11717 = $time; + v__h12146 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 && wci_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h11717); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h12146); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 && wci_reqPend == 2'd3) begin - v__h11806 = $time; + v__h12235 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5849 && wci_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h11806); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h12235); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && wci_reqPend == 2'd1) begin - v__h12030 = $time; + v__h12459 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && wci_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h12030); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h12459); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && wci_reqPend == 2'd2) begin - v__h12120 = $time; + v__h12549 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && wci_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h12120); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h12549); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && wci_reqPend == 2'd3) begin - v__h12209 = $time; + v__h12638 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && wci_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h12209); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h12638); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && wci_reqPend == 2'd1) begin - v__h12438 = $time; + v__h12867 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && wci_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h12438); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h12867); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && wci_reqPend == 2'd2) begin - v__h12528 = $time; + v__h12957 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && wci_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h12528); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h12957); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && wci_reqPend == 2'd3) begin - v__h12617 = $time; + v__h13046 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && wci_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h12617); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h13046); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 && wci_reqPend_1 == 2'd1) begin - v__h15929 = $time; + v__h16496 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 && wci_reqPend_1 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h15929); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h16496); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 && wci_reqPend_1 == 2'd2) begin - v__h16019 = $time; + v__h16586 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 && wci_reqPend_1 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h16019); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h16586); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 && wci_reqPend_1 == 2'd3) begin - v__h16108 = $time; + v__h16675 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5850 && wci_reqPend_1 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h16108); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h16675); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd2 && wci_reqPend_1 == 2'd1) begin - v__h16332 = $time; + v__h16899 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd2 && wci_reqPend_1 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h16332); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h16899); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd2 && wci_reqPend_1 == 2'd2) begin - v__h16422 = $time; + v__h16989 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd2 && wci_reqPend_1 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h16422); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h16989); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd2 && wci_reqPend_1 == 2'd3) begin - v__h16511 = $time; + v__h17078 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd2 && wci_reqPend_1 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h16511); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h17078); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd3 && wci_reqPend_1 == 2'd1) begin - v__h16740 = $time; + v__h17307 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd3 && wci_reqPend_1 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h16740); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h17307); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd3 && wci_reqPend_1 == 2'd2) begin - v__h16830 = $time; + v__h17397 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd3 && wci_reqPend_1 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h16830); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h17397); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd3 && wci_reqPend_1 == 2'd3) begin - v__h16919 = $time; + v__h17486 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd3 && wci_reqPend_1 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h16919); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h17486); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 && wci_reqPend_2 == 2'd1) begin - v__h20231 = $time; + v__h20936 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 && wci_reqPend_2 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h20231); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h20936); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 && wci_reqPend_2 == 2'd2) begin - v__h20321 = $time; + v__h21026 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 && wci_reqPend_2 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h20321); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h21026); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 && wci_reqPend_2 == 2'd3) begin - v__h20410 = $time; + v__h21115 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5453 && wci_reqPend_2 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h20410); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h21115); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd2 && wci_reqPend_2 == 2'd1) begin - v__h20634 = $time; + v__h21339 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd2 && wci_reqPend_2 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h20634); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h21339); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd2 && wci_reqPend_2 == 2'd2) begin - v__h20724 = $time; + v__h21429 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd2 && wci_reqPend_2 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h20724); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h21429); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd2 && wci_reqPend_2 == 2'd3) begin - v__h20813 = $time; + v__h21518 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd2 && wci_reqPend_2 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h20813); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h21518); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd3 && wci_reqPend_2 == 2'd1) begin - v__h21042 = $time; + v__h21747 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd3 && wci_reqPend_2 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h21042); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h21747); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd3 && wci_reqPend_2 == 2'd2) begin - v__h21132 = $time; + v__h21837 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd3 && wci_reqPend_2 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h21132); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h21837); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd3 && wci_reqPend_2 == 2'd3) begin - v__h21221 = $time; + v__h21926 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd3 && wci_reqPend_2 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h21221); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h21926); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 && wci_reqPend_3 == 2'd1) begin - v__h24533 = $time; + v__h25376 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 && wci_reqPend_3 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h24533); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h25376); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 && wci_reqPend_3 == 2'd2) begin - v__h24623 = $time; + v__h25466 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 && wci_reqPend_3 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h24623); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h25466); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 && wci_reqPend_3 == 2'd3) begin - v__h24712 = $time; + v__h25555 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5851 && wci_reqPend_3 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h24712); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h25555); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd2 && wci_reqPend_3 == 2'd1) begin - v__h24936 = $time; + v__h25779 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd2 && wci_reqPend_3 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h24936); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h25779); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd2 && wci_reqPend_3 == 2'd2) begin - v__h25026 = $time; + v__h25869 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd2 && wci_reqPend_3 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h25026); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h25869); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd2 && wci_reqPend_3 == 2'd3) begin - v__h25115 = $time; + v__h25958 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd2 && wci_reqPend_3 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h25115); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h25958); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd3 && wci_reqPend_3 == 2'd1) begin - v__h25344 = $time; + v__h26187 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd3 && wci_reqPend_3 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h25344); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h26187); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd3 && wci_reqPend_3 == 2'd2) begin - v__h25434 = $time; + v__h26277 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd3 && wci_reqPend_3 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h25434); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h26277); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd3 && wci_reqPend_3 == 2'd3) begin - v__h25523 = $time; + v__h26366 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd3 && wci_reqPend_3 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h25523); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h26366); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 && wci_reqPend_4 == 2'd1) begin - v__h28835 = $time; + v__h29816 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 && wci_reqPend_4 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h28835); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h29816); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 && wci_reqPend_4 == 2'd2) begin - v__h28925 = $time; + v__h29906 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 && wci_reqPend_4 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h28925); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h29906); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 && wci_reqPend_4 == 2'd3) begin - v__h29014 = $time; + v__h29995 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5852 && wci_reqPend_4 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h29014); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h29995); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd2 && wci_reqPend_4 == 2'd1) begin - v__h29238 = $time; + v__h30219 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd2 && wci_reqPend_4 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h29238); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h30219); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd2 && wci_reqPend_4 == 2'd2) begin - v__h29328 = $time; + v__h30309 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd2 && wci_reqPend_4 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h29328); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h30309); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd2 && wci_reqPend_4 == 2'd3) begin - v__h29417 = $time; + v__h30398 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd2 && wci_reqPend_4 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h29417); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h30398); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd3 && wci_reqPend_4 == 2'd1) begin - v__h29646 = $time; + v__h30627 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd3 && wci_reqPend_4 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h29646); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h30627); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd3 && wci_reqPend_4 == 2'd2) begin - v__h29736 = $time; + v__h30717 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd3 && wci_reqPend_4 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h29736); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h30717); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd3 && wci_reqPend_4 == 2'd3) begin - v__h29825 = $time; + v__h30806 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd3 && wci_reqPend_4 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h29825); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h30806); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 && wci_reqPend_5 == 2'd1) begin - v__h33137 = $time; + v__h34256 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 && wci_reqPend_5 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h33137); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h34256); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 && wci_reqPend_5 == 2'd2) begin - v__h33227 = $time; + v__h34346 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 && wci_reqPend_5 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h33227); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h34346); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 && wci_reqPend_5 == 2'd3) begin - v__h33316 = $time; + v__h34435 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5853 && wci_reqPend_5 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h33316); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h34435); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd2 && wci_reqPend_5 == 2'd1) begin - v__h33540 = $time; + v__h34659 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd2 && wci_reqPend_5 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h33540); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h34659); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd2 && wci_reqPend_5 == 2'd2) begin - v__h33630 = $time; + v__h34749 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd2 && wci_reqPend_5 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h33630); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h34749); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd2 && wci_reqPend_5 == 2'd3) begin - v__h33719 = $time; + v__h34838 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd2 && wci_reqPend_5 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h33719); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h34838); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd3 && wci_reqPend_5 == 2'd1) begin - v__h33948 = $time; + v__h35067 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd3 && wci_reqPend_5 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h33948); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h35067); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd3 && wci_reqPend_5 == 2'd2) begin - v__h34038 = $time; + v__h35157 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd3 && wci_reqPend_5 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h34038); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h35157); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd3 && wci_reqPend_5 == 2'd3) begin - v__h34127 = $time; + v__h35246 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd3 && wci_reqPend_5 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h34127); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h35246); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 && wci_reqPend_6 == 2'd1) begin - v__h37439 = $time; + v__h38696 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 && wci_reqPend_6 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h37439); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h38696); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 && wci_reqPend_6 == 2'd2) begin - v__h37529 = $time; + v__h38786 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 && wci_reqPend_6 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h37529); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h38786); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 && wci_reqPend_6 == 2'd3) begin - v__h37618 = $time; + v__h38875 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5854 && wci_reqPend_6 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h37618); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h38875); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd2 && wci_reqPend_6 == 2'd1) begin - v__h37842 = $time; + v__h39099 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd2 && wci_reqPend_6 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h37842); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h39099); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd2 && wci_reqPend_6 == 2'd2) begin - v__h37932 = $time; + v__h39189 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd2 && wci_reqPend_6 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h37932); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h39189); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd2 && wci_reqPend_6 == 2'd3) begin - v__h38021 = $time; + v__h39278 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd2 && wci_reqPend_6 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h38021); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h39278); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd3 && wci_reqPend_6 == 2'd1) begin - v__h38250 = $time; + v__h39507 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd3 && wci_reqPend_6 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h38250); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h39507); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd3 && wci_reqPend_6 == 2'd2) begin - v__h38340 = $time; + v__h39597 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd3 && wci_reqPend_6 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h38340); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h39597); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd3 && wci_reqPend_6 == 2'd3) begin - v__h38429 = $time; + v__h39686 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd3 && wci_reqPend_6 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h38429); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h39686); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 && wci_reqPend_7 == 2'd1) begin - v__h41741 = $time; + v__h43136 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 && wci_reqPend_7 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h41741); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h43136); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 && wci_reqPend_7 == 2'd2) begin - v__h41831 = $time; + v__h43226 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 && wci_reqPend_7 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h41831); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h43226); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 && wci_reqPend_7 == 2'd3) begin - v__h41920 = $time; + v__h43315 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5855 && wci_reqPend_7 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h41920); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h43315); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd2 && wci_reqPend_7 == 2'd1) begin - v__h42144 = $time; + v__h43539 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd2 && wci_reqPend_7 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h42144); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h43539); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd2 && wci_reqPend_7 == 2'd2) begin - v__h42234 = $time; + v__h43629 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd2 && wci_reqPend_7 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h42234); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h43629); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd2 && wci_reqPend_7 == 2'd3) begin - v__h42323 = $time; + v__h43718 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd2 && wci_reqPend_7 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h42323); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h43718); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd3 && wci_reqPend_7 == 2'd1) begin - v__h42552 = $time; + v__h43947 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd3 && wci_reqPend_7 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h42552); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h43947); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd3 && wci_reqPend_7 == 2'd2) begin - v__h42642 = $time; + v__h44037 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd3 && wci_reqPend_7 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h42642); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h44037); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd3 && wci_reqPend_7 == 2'd3) begin - v__h42731 = $time; + v__h44126 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd3 && wci_reqPend_7 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h42731); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h44126); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 && wci_reqPend_8 == 2'd1) begin - v__h46043 = $time; + v__h47576 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 && wci_reqPend_8 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h46043); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h47576); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 && wci_reqPend_8 == 2'd2) begin - v__h46133 = $time; + v__h47666 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 && wci_reqPend_8 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h46133); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h47666); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 && wci_reqPend_8 == 2'd3) begin - v__h46222 = $time; + v__h47755 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5856 && wci_reqPend_8 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h46222); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h47755); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd2 && wci_reqPend_8 == 2'd1) begin - v__h46446 = $time; + v__h47979 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd2 && wci_reqPend_8 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h46446); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h47979); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd2 && wci_reqPend_8 == 2'd2) begin - v__h46536 = $time; + v__h48069 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd2 && wci_reqPend_8 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h46536); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h48069); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd2 && wci_reqPend_8 == 2'd3) begin - v__h46625 = $time; + v__h48158 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd2 && wci_reqPend_8 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h46625); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h48158); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd3 && wci_reqPend_8 == 2'd1) begin - v__h46854 = $time; + v__h48387 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd3 && wci_reqPend_8 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h46854); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h48387); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd3 && wci_reqPend_8 == 2'd2) begin - v__h46944 = $time; + v__h48477 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd3 && wci_reqPend_8 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h46944); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h48477); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd3 && wci_reqPend_8 == 2'd3) begin - v__h47033 = $time; + v__h48566 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd3 && wci_reqPend_8 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h47033); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h48566); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 && wci_reqPend_9 == 2'd1) begin - v__h50345 = $time; + v__h52016 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 && wci_reqPend_9 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h50345); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h52016); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 && wci_reqPend_9 == 2'd2) begin - v__h50435 = $time; + v__h52106 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 && wci_reqPend_9 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h50435); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h52106); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 && wci_reqPend_9 == 2'd3) begin - v__h50524 = $time; + v__h52195 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5857 && wci_reqPend_9 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h50524); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h52195); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd2 && wci_reqPend_9 == 2'd1) begin - v__h50748 = $time; + v__h52419 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd2 && wci_reqPend_9 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h50748); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h52419); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd2 && wci_reqPend_9 == 2'd2) begin - v__h50838 = $time; + v__h52509 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd2 && wci_reqPend_9 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h50838); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h52509); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd2 && wci_reqPend_9 == 2'd3) begin - v__h50927 = $time; + v__h52598 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd2 && wci_reqPend_9 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h50927); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h52598); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd3 && wci_reqPend_9 == 2'd1) begin - v__h51156 = $time; + v__h52827 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd3 && wci_reqPend_9 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h51156); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h52827); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd3 && wci_reqPend_9 == 2'd2) begin - v__h51246 = $time; + v__h52917 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd3 && wci_reqPend_9 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h51246); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h52917); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd3 && wci_reqPend_9 == 2'd3) begin - v__h51335 = $time; + v__h53006 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd3 && wci_reqPend_9 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h51335); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h53006); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 && wci_reqPend_10 == 2'd1) begin - v__h54647 = $time; + v__h56456 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 && wci_reqPend_10 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h54647); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h56456); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 && wci_reqPend_10 == 2'd2) begin - v__h54737 = $time; + v__h56546 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 && wci_reqPend_10 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h54737); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h56546); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 && wci_reqPend_10 == 2'd3) begin - v__h54826 = $time; + v__h56635 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5858 && wci_reqPend_10 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h54826); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h56635); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd2 && wci_reqPend_10 == 2'd1) begin - v__h55050 = $time; + v__h56859 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd2 && wci_reqPend_10 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h55050); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h56859); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd2 && wci_reqPend_10 == 2'd2) begin - v__h55140 = $time; + v__h56949 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd2 && wci_reqPend_10 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h55140); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h56949); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd2 && wci_reqPend_10 == 2'd3) begin - v__h55229 = $time; + v__h57038 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd2 && wci_reqPend_10 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h55229); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h57038); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd3 && wci_reqPend_10 == 2'd1) begin - v__h55458 = $time; + v__h57267 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd3 && wci_reqPend_10 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h55458); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h57267); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd3 && wci_reqPend_10 == 2'd2) begin - v__h55548 = $time; + v__h57357 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd3 && wci_reqPend_10 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h55548); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h57357); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd3 && wci_reqPend_10 == 2'd3) begin - v__h55637 = $time; + v__h57446 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd3 && wci_reqPend_10 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h55637); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h57446); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 && wci_reqPend_11 == 2'd1) begin - v__h58949 = $time; + v__h60896 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 && wci_reqPend_11 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h58949); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h60896); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 && wci_reqPend_11 == 2'd2) begin - v__h59039 = $time; + v__h60986 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 && wci_reqPend_11 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h59039); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h60986); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 && wci_reqPend_11 == 2'd3) begin - v__h59128 = $time; + v__h61075 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5859 && wci_reqPend_11 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h59128); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h61075); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd2 && wci_reqPend_11 == 2'd1) begin - v__h59352 = $time; + v__h61299 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd2 && wci_reqPend_11 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h59352); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h61299); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd2 && wci_reqPend_11 == 2'd2) begin - v__h59442 = $time; + v__h61389 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd2 && wci_reqPend_11 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h59442); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h61389); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd2 && wci_reqPend_11 == 2'd3) begin - v__h59531 = $time; + v__h61478 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd2 && wci_reqPend_11 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h59531); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h61478); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd3 && wci_reqPend_11 == 2'd1) begin - v__h59760 = $time; + v__h61707 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd3 && wci_reqPend_11 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h59760); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h61707); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd3 && wci_reqPend_11 == 2'd2) begin - v__h59850 = $time; + v__h61797 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd3 && wci_reqPend_11 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h59850); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h61797); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd3 && wci_reqPend_11 == 2'd3) begin - v__h59939 = $time; + v__h61886 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd3 && wci_reqPend_11 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h59939); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h61886); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 && wci_reqPend_12 == 2'd1) begin - v__h63251 = $time; + v__h65336 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 && wci_reqPend_12 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h63251); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h65336); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 && wci_reqPend_12 == 2'd2) begin - v__h63341 = $time; + v__h65426 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 && wci_reqPend_12 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h63341); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h65426); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 && wci_reqPend_12 == 2'd3) begin - v__h63430 = $time; + v__h65515 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5860 && wci_reqPend_12 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h63430); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h65515); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd2 && wci_reqPend_12 == 2'd1) begin - v__h63654 = $time; + v__h65739 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd2 && wci_reqPend_12 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h63654); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h65739); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd2 && wci_reqPend_12 == 2'd2) begin - v__h63744 = $time; + v__h65829 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd2 && wci_reqPend_12 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h63744); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h65829); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd2 && wci_reqPend_12 == 2'd3) begin - v__h63833 = $time; + v__h65918 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd2 && wci_reqPend_12 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h63833); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h65918); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd3 && wci_reqPend_12 == 2'd1) begin - v__h64062 = $time; + v__h66147 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd3 && wci_reqPend_12 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h64062); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h66147); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd3 && wci_reqPend_12 == 2'd2) begin - v__h64152 = $time; + v__h66237 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd3 && wci_reqPend_12 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h64152); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h66237); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd3 && wci_reqPend_12 == 2'd3) begin - v__h64241 = $time; + v__h66326 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd3 && wci_reqPend_12 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h64241); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h66326); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 && wci_reqPend_13 == 2'd1) begin - v__h67553 = $time; + v__h69776 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 && wci_reqPend_13 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h67553); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h69776); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 && wci_reqPend_13 == 2'd2) begin - v__h67643 = $time; + v__h69866 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 && wci_reqPend_13 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h67643); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h69866); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 && wci_reqPend_13 == 2'd3) begin - v__h67732 = $time; + v__h69955 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5861 && wci_reqPend_13 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h67732); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h69955); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd2 && wci_reqPend_13 == 2'd1) begin - v__h67956 = $time; + v__h70179 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd2 && wci_reqPend_13 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h67956); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h70179); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd2 && wci_reqPend_13 == 2'd2) begin - v__h68046 = $time; + v__h70269 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd2 && wci_reqPend_13 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h68046); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h70269); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd2 && wci_reqPend_13 == 2'd3) begin - v__h68135 = $time; + v__h70358 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd2 && wci_reqPend_13 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h68135); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h70358); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd3 && wci_reqPend_13 == 2'd1) begin - v__h68364 = $time; + v__h70587 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd3 && wci_reqPend_13 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h68364); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h70587); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd3 && wci_reqPend_13 == 2'd2) begin - v__h68454 = $time; + v__h70677 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd3 && wci_reqPend_13 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h68454); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h70677); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd3 && wci_reqPend_13 == 2'd3) begin - v__h68543 = $time; + v__h70766 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd3 && wci_reqPend_13 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h68543); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h70766); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 && wci_reqPend_14 == 2'd1) begin - v__h71855 = $time; + v__h74216 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 && wci_reqPend_14 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h71855); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h74216); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 && wci_reqPend_14 == 2'd2) begin - v__h71945 = $time; + v__h74306 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 && wci_reqPend_14 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h71945); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h74306); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 && wci_reqPend_14 == 2'd3) begin - v__h72034 = $time; + v__h74395 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5862 && wci_reqPend_14 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h72034); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h74395); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd2 && wci_reqPend_14 == 2'd1) begin - v__h72258 = $time; + v__h74619 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd2 && wci_reqPend_14 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h72258); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h74619); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd2 && wci_reqPend_14 == 2'd2) begin - v__h72348 = $time; + v__h74709 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd2 && wci_reqPend_14 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h72348); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h74709); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd2 && wci_reqPend_14 == 2'd3) begin - v__h72437 = $time; + v__h74798 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd2 && wci_reqPend_14 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h72437); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h74798); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd3 && wci_reqPend_14 == 2'd1) begin - v__h72666 = $time; + v__h75027 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd3 && wci_reqPend_14 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h72666); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h75027); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd3 && wci_reqPend_14 == 2'd2) begin - v__h72756 = $time; + v__h75117 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd3 && wci_reqPend_14 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h72756); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h75117); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd3 && wci_reqPend_14 == 2'd3) begin - v__h72845 = $time; + v__h75206 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd3 && wci_reqPend_14 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h72845); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h75206); end // synopsys translate_on endmodule // mkOCCP diff --git a/rtl/mkOCEDP4B.v b/rtl/mkOCEDP4B.v index 952f3928..1389716d 100644 --- a/rtl/mkOCEDP4B.v +++ b/rtl/mkOCEDP4B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:40:30 EDT 2012 +// On Mon Sep 24 15:05:40 EDT 2012 // // // Ports: @@ -54,7 +54,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkOCEDP4B(pciDevice, @@ -1968,8 +1976,8 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory_1$b_put_1__SEL_1, MUX_bram_memory_1$b_put_1__SEL_2, MUX_bram_memory_2$a_put_1__SEL_1, + MUX_bram_memory_2$a_put_1__SEL_2, MUX_bram_memory_2$a_put_1__SEL_3, - MUX_bram_memory_2$a_put_2__SEL_2, MUX_bram_memory_2$b_put_1__SEL_1, MUX_bram_memory_2$b_put_1__SEL_2, MUX_bram_memory_3$a_put_1__SEL_1, @@ -2004,30 +2012,30 @@ module mkOCEDP4B(pciDevice, MUX_wmi_wrFinalize$write_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h109349, - v__h117892, - v__h118046, - v__h15543, - v__h15717, - v__h15861, - v__h77289, - v__h79597, - v__h83920, - v__h86073, - v__h86371, - v__h91705, - v__h91851, - v__h91994, - v__h92126, - v__h94025, - v__h94787; - reg [31 : 0] IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841, - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842, - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843, - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844, - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724, - _theResult____h118030, - rdata__h110466; + reg [63 : 0] v__h109939, + v__h118754, + v__h118910, + v__h15697, + v__h15872, + v__h16016, + v__h77698, + v__h79991, + v__h84290, + v__h86447, + v__h86738, + v__h92069, + v__h92218, + v__h92365, + v__h92500, + v__h94403, + v__h95165; + reg [31 : 0] IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2852, + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2853, + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2854, + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2855, + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2720, + _theResult____h118894, + rdata__h111060; reg [3 : 0] CASE_edp_lastRuleFired_10_1_edp_lastRuleFired__ETC__q5; reg [1 : 0] CASE_edp_inFD_OUT_BITS_19_TO_18_3_0_edp_inFD_ETC__q39, CASE_edp_inFD_OUT_BITS_29_TO_28_3_0_edp_inFD_ETC__q38, @@ -2057,9 +2065,9 @@ module mkOCEDP4B(pciDevice, CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q34, CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q33, CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q36, - lowAddr10__h35545, - x__h35674, - x__h35697; + lowAddr10__h35513, + x__h35642, + x__h35665; reg CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q10, CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q9, CASE_dpControl_BITS_1_TO_0_bml_fabDone_0_bml_f_ETC__q6, @@ -2067,106 +2075,106 @@ module mkOCEDP4B(pciDevice, CASE_edp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q7, CASE_edp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q19, CASE_wmi_p4B_NOT_wmi_p4B_EQ_3_OR_bram_serverAd_ETC__q20, - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809, + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2818, IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839, - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803, + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2819, IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849, - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812, + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2820, IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859, - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810, + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812, IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869, IF_bml_dpControl_wget__213_BITS_1_TO_0_219_EQ__ETC___d2290, IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1076, - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777, + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3215, IF_wmi_p4B_096_EQ_1_099_THEN_bram_serverAdapte_ETC___d2105; wire [127 : 0] IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1201, IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1206, - rdata__h40976; - wire [31 : 0] bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2973, - mesgMeta_opcode__h108747, - nowLS__h82713, - nowMS__h81770, - opcode__h80539, - rdat__h118109, - rdat__h118117, - rdat__h118125, - rdat__h118133, - rdat__h118141, - rdat__h118149, - rdat__h118157, - rdat__h118178, - rdat__h118185, - rdat__h118198, - rdat__h118205, - rdat__h118212, - rdat__h118476, - rdat__h118526, - rdat__h118626, - rdat__h118684, - rdat__h118706, - rdat__h118716, - rdat__h118838, - rdat__h118958, - rdat__h118987, - rdat__h119016, - rdat__h119045, - rdat__h119075, - rdat__h119109, - rdat__h119142, - rdat__h119176, - rdat__h119209, - rdat__h119220, - rdat__h119231, - rresp_data__h35592, - x3__h108707, - x__h78704, - x__h83716, - y__h85926, - y__h86228, - y_avValue__h110302, - y_avValue__h110322, - y_avValue__h110342, - y_avValue__h110362; + rdata__h40953; + wire [31 : 0] bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2979, + mesgMeta_opcode__h109337, + nowLS__h83083, + nowMS__h82140, + opcode__h80909, + rdat__h118973, + rdat__h118981, + rdat__h118989, + rdat__h118997, + rdat__h119005, + rdat__h119013, + rdat__h119021, + rdat__h119042, + rdat__h119049, + rdat__h119062, + rdat__h119069, + rdat__h119076, + rdat__h119340, + rdat__h119390, + rdat__h119490, + rdat__h119548, + rdat__h119570, + rdat__h119580, + rdat__h119702, + rdat__h119822, + rdat__h119851, + rdat__h119880, + rdat__h119909, + rdat__h119939, + rdat__h119973, + rdat__h120006, + rdat__h120040, + rdat__h120073, + rdat__h120084, + rdat__h120095, + rresp_data__h35560, + x3__h109297, + x__h79125, + x__h84086, + y__h86300, + y__h86614, + y_avValue__h110896, + y_avValue__h110916, + y_avValue__h110936, + y_avValue__h110956; wire [16 : 0] edp_mesgLengthRemainPush_PLUS_3__q18, - x__h85845, - y__h85835, - y__h85847; - wire [15 : 0] x__h114823, - x__h115947, - x__h115952, - x__h116059, - x__h116096, - x__h116174, - x__h116179, - x__h116212, - x__h116217; + x__h86219, + y__h86209, + y__h86221; + wire [15 : 0] x__h115651, + x__h116779, + x__h116784, + x__h116891, + x__h116928, + x__h117010, + x__h117015, + x__h117049, + x__h117054; wire [12 : 0] edp_tlpBRAM_readNxtDWAddr_PLUS_1__q15, edp_tlpBRAM_readNxtDWAddr_PLUS_2__q16, edp_tlpBRAM_readNxtDWAddr_PLUS_3__q14, edp_tlpBRAM_writeDWAddr_PLUS_1__q12, edp_tlpBRAM_writeDWAddr_PLUS_2__q13, edp_tlpBRAM_writeDWAddr_PLUS_3__q11, - spanToNextPage__h85809, - thisRequestLength__h85810, - y__h24387, - y__h33157; - wire [11 : 0] byteCount__h35547, - x__h20653, - x__h35665, - x__h35667, - y__h35666, - y__h35668; - wire [9 : 0] IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2731, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2732, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2733, - y__h24458, - y__h33109, - y__h36607, - y__h86177; - wire [7 : 0] rreq_tag__h86003; - wire [6 : 0] lowAddr__h35546; - wire [3 : 0] x__h96121; + spanToNextPage__h86183, + thisRequestLength__h86184, + y__h24591, + y__h33152; + wire [11 : 0] byteCount__h35515, + x__h20838, + x__h35633, + x__h35635, + y__h35634, + y__h35636; + wire [9 : 0] IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2727, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2728, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2729, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730, + y__h24658, + y__h33140, + y__h36575, + y__h86555; + wire [7 : 0] rreq_tag__h86377; + wire [6 : 0] lowAddr__h35514; + wire [3 : 0] x__h96502; wire [2 : 0] bram_serverAdapterA_1_cnt_44_PLUS_IF_bram_serv_ETC___d150, bram_serverAdapterA_2_cnt_62_PLUS_IF_bram_serv_ETC___d268, bram_serverAdapterA_3_cnt_80_PLUS_IF_bram_serv_ETC___d386, @@ -2175,39 +2183,39 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterB_2_cnt_21_PLUS_IF_bram_serv_ETC___d327, bram_serverAdapterB_3_cnt_39_PLUS_IF_bram_serv_ETC___d445, bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91; - wire [1 : 0] ab__h10383, - ab__h11780, - ab__h1600, - ab__h2999, - ab__h4529, - ab__h5926, - ab__h7456, - ab__h8853, - edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2699, - idx__h26173, - idx__h28404, - idx__h29708, - idx__h31012, - idx__h33404, - idx__h33872, - idx__h34245, - idx__h34618; + wire [1 : 0] ab__h10453, + ab__h11857, + ab__h1613, + ab__h3019, + ab__h4561, + ab__h5965, + ab__h7507, + ab__h8911, + edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2692, + idx__h26290, + idx__h28521, + idx__h29825, + idx__h31129, + idx__h33370, + idx__h33838, + idx__h34211, + idx__h34584; wire IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d872, IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1085, IF_wmi_p4B_096_EQ_0_097_THEN_bram_serverAdapte_ETC___d2110, NOT_bml_lclBufDone_237_304_AND_IF_bml_dpContro_ETC___d2317, NOT_edp_outBF_rRdPtr_83_PLUS_1024_283_EQ_edp_o_ETC___d1285, NOT_wmi_wrActive_011_012_OR_NOT_wmi_rdActive_0_ETC___d2021, - bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3163, - bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164, - bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2822, - bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3183, - bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3184, - bram_serverAdapterA_1_cnt_44_SLT_3___d2975, - bram_serverAdapterA_2_cnt_62_SLT_3___d2976, + bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3164, + bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3165, + bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2833, + bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3184, + bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3185, + bram_serverAdapterA_1_cnt_44_SLT_3___d2980, + bram_serverAdapterA_2_cnt_62_SLT_3___d2766, bram_serverAdapterA_2_outDataCore_notEmpty__38_ETC___d1157, - bram_serverAdapterA_3_cnt_80_SLT_3___d2977, - bram_serverAdapterA_cnt_6_SLT_3___d2974, + bram_serverAdapterA_3_cnt_80_SLT_3___d2765, + bram_serverAdapterA_cnt_6_SLT_3___d2772, bram_serverAdapterA_outDataCore_notEmpty_OR_br_ETC___d1159, bram_serverAdapterB_1_cnt_03_SLT_3___d1961, bram_serverAdapterB_1_outData_outData_whas__98_ETC___d1989, @@ -2224,9 +2232,9 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mReqF_first__82_BIT_63_83_OR_IF_ed_ETC___d798, edp_tlpBRAM_rdRespDwRemain_188_ULE_4___d1190, edp_tlpBRAM_readRemainDWLen_010_ULE_4___d1011, - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698, - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695, - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696, + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724, + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694, + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695, hasPush_AND_edp_dpControl_wget__431_BITS_7_TO__ETC___d1451, hasPush_AND_edp_dpControl_wget__431_BITS_7_TO__ETC___d1485, hasPush_AND_edp_dpControl_wget__431_BITS_7_TO__ETC___d1503, @@ -2366,7 +2374,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterA_1_outDataCore(.RST_N(RST_N), + .guarded(32'd1)) bram_serverAdapterA_1_outDataCore(.RST(RST_N), .CLK(CLK), .D_IN(bram_serverAdapterA_1_outDataCore$D_IN), .ENQ(bram_serverAdapterA_1_outDataCore$ENQ), @@ -2380,7 +2388,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterA_2_outDataCore(.RST_N(RST_N), + .guarded(32'd1)) bram_serverAdapterA_2_outDataCore(.RST(RST_N), .CLK(CLK), .D_IN(bram_serverAdapterA_2_outDataCore$D_IN), .ENQ(bram_serverAdapterA_2_outDataCore$ENQ), @@ -2394,7 +2402,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterA_3_outDataCore(.RST_N(RST_N), + .guarded(32'd1)) bram_serverAdapterA_3_outDataCore(.RST(RST_N), .CLK(CLK), .D_IN(bram_serverAdapterA_3_outDataCore$D_IN), .ENQ(bram_serverAdapterA_3_outDataCore$ENQ), @@ -2408,7 +2416,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterA_outDataCore(.RST_N(RST_N), + .guarded(32'd1)) bram_serverAdapterA_outDataCore(.RST(RST_N), .CLK(CLK), .D_IN(bram_serverAdapterA_outDataCore$D_IN), .ENQ(bram_serverAdapterA_outDataCore$ENQ), @@ -2422,7 +2430,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterB_1_outDataCore(.RST_N(RST_N), + .guarded(32'd1)) bram_serverAdapterB_1_outDataCore(.RST(RST_N), .CLK(CLK), .D_IN(bram_serverAdapterB_1_outDataCore$D_IN), .ENQ(bram_serverAdapterB_1_outDataCore$ENQ), @@ -2436,7 +2444,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterB_2_outDataCore(.RST_N(RST_N), + .guarded(32'd1)) bram_serverAdapterB_2_outDataCore(.RST(RST_N), .CLK(CLK), .D_IN(bram_serverAdapterB_2_outDataCore$D_IN), .ENQ(bram_serverAdapterB_2_outDataCore$ENQ), @@ -2450,7 +2458,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterB_3_outDataCore(.RST_N(RST_N), + .guarded(32'd1)) bram_serverAdapterB_3_outDataCore(.RST(RST_N), .CLK(CLK), .D_IN(bram_serverAdapterB_3_outDataCore$D_IN), .ENQ(bram_serverAdapterB_3_outDataCore$ENQ), @@ -2464,7 +2472,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterB_outDataCore(.RST_N(RST_N), + .guarded(32'd1)) bram_serverAdapterB_outDataCore(.RST(RST_N), .CLK(CLK), .D_IN(bram_serverAdapterB_outDataCore$D_IN), .ENQ(bram_serverAdapterB_outDataCore$ENQ), @@ -2475,7 +2483,7 @@ module mkOCEDP4B(pciDevice, .EMPTY_N(bram_serverAdapterB_outDataCore$EMPTY_N)); // submodule edp_inF - FIFO2 #(.width(32'd40), .guarded(32'd1)) edp_inF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) edp_inF(.RST(RST_N), .CLK(CLK), .D_IN(edp_inF$D_IN), .ENQ(edp_inF$ENQ), @@ -2486,7 +2494,7 @@ module mkOCEDP4B(pciDevice, .EMPTY_N(edp_inF$EMPTY_N)); // submodule edp_inProcF - FIFO2 #(.width(32'd40), .guarded(32'd1)) edp_inProcF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) edp_inProcF(.RST(RST_N), .CLK(CLK), .D_IN(edp_inProcF$D_IN), .ENQ(edp_inProcF$ENQ), @@ -2514,7 +2522,7 @@ module mkOCEDP4B(pciDevice, .DOB(edp_outBF_memory$DOB)); // submodule edp_outF - FIFO2 #(.width(32'd40), .guarded(32'd1)) edp_outF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) edp_outF(.RST(RST_N), .CLK(CLK), .D_IN(edp_outF$D_IN), .ENQ(edp_outF$ENQ), @@ -2525,7 +2533,7 @@ module mkOCEDP4B(pciDevice, .EMPTY_N(edp_outF$EMPTY_N)); // submodule edp_outFunl_inF - FIFO2 #(.width(32'd128), .guarded(32'd1)) edp_outFunl_inF(.RST_N(RST_N), + FIFO2 #(.width(32'd128), .guarded(32'd1)) edp_outFunl_inF(.RST(RST_N), .CLK(CLK), .D_IN(edp_outFunl_inF$D_IN), .ENQ(edp_outFunl_inF$ENQ), @@ -2536,7 +2544,7 @@ module mkOCEDP4B(pciDevice, .EMPTY_N(edp_outFunl_inF$EMPTY_N)); // submodule edp_outFunl_outF - FIFO2 #(.width(32'd32), .guarded(32'd1)) edp_outFunl_outF(.RST_N(RST_N), + FIFO2 #(.width(32'd32), .guarded(32'd1)) edp_outFunl_outF(.RST(RST_N), .CLK(CLK), .D_IN(edp_outFunl_outF$D_IN), .ENQ(edp_outFunl_outF$ENQ), @@ -2547,7 +2555,7 @@ module mkOCEDP4B(pciDevice, .EMPTY_N(edp_outFunl_outF$EMPTY_N)); // submodule edp_outTF - FIFO20 #(.guarded(32'd1)) edp_outTF(.RST_N(RST_N), + FIFO20 #(.guarded(32'd1)) edp_outTF(.RST(RST_N), .CLK(CLK), .ENQ(edp_outTF$ENQ), .DEQ(edp_outTF$DEQ), @@ -2556,7 +2564,7 @@ module mkOCEDP4B(pciDevice, .EMPTY_N(edp_outTF$EMPTY_N)); // submodule edp_tailEventF - FIFO2 #(.width(32'd1), .guarded(32'd1)) edp_tailEventF(.RST_N(RST_N), + FIFO2 #(.width(32'd1), .guarded(32'd1)) edp_tailEventF(.RST(RST_N), .CLK(CLK), .D_IN(edp_tailEventF$D_IN), .ENQ(edp_tailEventF$ENQ), @@ -2567,7 +2575,7 @@ module mkOCEDP4B(pciDevice, .EMPTY_N(edp_tailEventF$EMPTY_N)); // submodule edp_tlpBRAM_mReqF - FIFO2 #(.width(32'd130), .guarded(32'd1)) edp_tlpBRAM_mReqF(.RST_N(RST_N), + FIFO2 #(.width(32'd130), .guarded(32'd1)) edp_tlpBRAM_mReqF(.RST(RST_N), .CLK(CLK), .D_IN(edp_tlpBRAM_mReqF$D_IN), .ENQ(edp_tlpBRAM_mReqF$ENQ), @@ -2578,7 +2586,7 @@ module mkOCEDP4B(pciDevice, .EMPTY_N(edp_tlpBRAM_mReqF$EMPTY_N)); // submodule edp_tlpBRAM_mRespF - FIFO2 #(.width(32'd139), .guarded(32'd1)) edp_tlpBRAM_mRespF(.RST_N(RST_N), + FIFO2 #(.width(32'd139), .guarded(32'd1)) edp_tlpBRAM_mRespF(.RST(RST_N), .CLK(CLK), .D_IN(edp_tlpBRAM_mRespF$D_IN), .ENQ(edp_tlpBRAM_mRespF$ENQ), @@ -2589,7 +2597,7 @@ module mkOCEDP4B(pciDevice, .EMPTY_N(edp_tlpBRAM_mRespF$EMPTY_N)); // submodule edp_tlpBRAM_readReq - FIFO2 #(.width(32'd61), .guarded(32'd1)) edp_tlpBRAM_readReq(.RST_N(RST_N), + FIFO2 #(.width(32'd61), .guarded(32'd1)) edp_tlpBRAM_readReq(.RST(RST_N), .CLK(CLK), .D_IN(edp_tlpBRAM_readReq$D_IN), .ENQ(edp_tlpBRAM_readReq$ENQ), @@ -2603,7 +2611,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_reqF(.RST_N(RST_N), + .guarded(32'd1)) wci_reqF(.RST(RST_N), .CLK(CLK), .D_IN(wci_reqF$D_IN), .ENQ(wci_reqF$ENQ), @@ -2617,7 +2625,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd38), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wmi_wmi_dhF(.RST_N(RST_N), + .guarded(32'd1)) wmi_wmi_dhF(.RST(RST_N), .CLK(CLK), .D_IN(wmi_wmi_dhF$D_IN), .ENQ(wmi_wmi_dhF$ENQ), @@ -2631,7 +2639,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wmi_wmi_mFlagF(.RST_N(RST_N), + .guarded(32'd1)) wmi_wmi_mFlagF(.RST(RST_N), .CLK(CLK), .D_IN(wmi_wmi_mFlagF$D_IN), .ENQ(wmi_wmi_mFlagF$ENQ), @@ -2645,7 +2653,7 @@ module mkOCEDP4B(pciDevice, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wmi_wmi_reqF(.RST_N(RST_N), + .guarded(32'd1)) wmi_wmi_reqF(.RST(RST_N), .CLK(CLK), .D_IN(wmi_wmi_reqF$D_IN), .ENQ(wmi_wmi_reqF$ENQ), @@ -2797,7 +2805,7 @@ module mkOCEDP4B(pciDevice, assign WILL_FIRE_RL_edp_tlpBRAM_writeData = edp_tlpBRAM_mReqF$EMPTY_N && (IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839 || - bram_serverAdapterA_cnt_6_SLT_3___d2974) && + bram_serverAdapterA_cnt_6_SLT_3___d2772) && IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d872 && edp_tlpBRAM_mReqF$D_OUT[129:128] == 2'd1 ; @@ -2811,10 +2819,10 @@ module mkOCEDP4B(pciDevice, // rule RL_edp_tlpBRAM_read_NextReq assign WILL_FIRE_RL_edp_tlpBRAM_read_NextReq = - bram_serverAdapterA_cnt_6_SLT_3___d2974 && - bram_serverAdapterA_1_cnt_44_SLT_3___d2975 && - bram_serverAdapterA_2_cnt_62_SLT_3___d2976 && - bram_serverAdapterA_3_cnt_80_SLT_3___d2977 && + bram_serverAdapterA_cnt_6_SLT_3___d2772 && + bram_serverAdapterA_1_cnt_44_SLT_3___d2980 && + bram_serverAdapterA_2_cnt_62_SLT_3___d2766 && + bram_serverAdapterA_3_cnt_80_SLT_3___d2765 && edp_tlpBRAM_mReqF$EMPTY_N && edp_tlpBRAM_readStarted && edp_tlpBRAM_mReqF$D_OUT[129:128] != 2'd0 && @@ -2891,11 +2899,6 @@ module mkOCEDP4B(pciDevice, edp_fhFsm_start_wire$whas && (edp_fhFsm_state_mkFSMstate == 3'd0 || edp_fhFsm_state_mkFSMstate == 3'd3) && - !WILL_FIRE_RL_edp_mhFsm_action_l174c11 && - !WILL_FIRE_RL_edp_mhFsm_action_l173c11 && - !WILL_FIRE_RL_edp_mhFsm_action_l172c11 && - !WILL_FIRE_RL_edp_mhFsm_action_l171c11 && - !WILL_FIRE_RL_edp_mhFsm_action_l170c11 && !WILL_FIRE_RL_edp_dmaXmtTailEvent && !WILL_FIRE_RL_edp_drain_outFunl ; @@ -2908,6 +2911,7 @@ module mkOCEDP4B(pciDevice, assign WILL_FIRE_RL_edp_mhFsm_action_l170c11 = NOT_edp_outBF_rRdPtr_83_PLUS_1024_283_EQ_edp_o_ETC___d1285 && edp_mhFsm_state_mkFSMstate == 4'd1 && + !WILL_FIRE_RL_edp_fhFsm_action_l161c11 && !WILL_FIRE_RL_edp_fhFsm_action_l163c11 && !WILL_FIRE_RL_edp_fhFsm_action_l162c11 && !WILL_FIRE_RL_edp_dmaXmtTailEvent && @@ -2917,6 +2921,7 @@ module mkOCEDP4B(pciDevice, assign WILL_FIRE_RL_edp_mhFsm_action_l171c11 = NOT_edp_outBF_rRdPtr_83_PLUS_1024_283_EQ_edp_o_ETC___d1285 && edp_mhFsm_state_mkFSMstate == 4'd2 && + !WILL_FIRE_RL_edp_fhFsm_action_l161c11 && !WILL_FIRE_RL_edp_fhFsm_action_l163c11 && !WILL_FIRE_RL_edp_fhFsm_action_l162c11 && !WILL_FIRE_RL_edp_dmaXmtTailEvent && @@ -2926,6 +2931,7 @@ module mkOCEDP4B(pciDevice, assign WILL_FIRE_RL_edp_mhFsm_action_l172c11 = NOT_edp_outBF_rRdPtr_83_PLUS_1024_283_EQ_edp_o_ETC___d1285 && edp_mhFsm_state_mkFSMstate == 4'd3 && + !WILL_FIRE_RL_edp_fhFsm_action_l161c11 && !WILL_FIRE_RL_edp_fhFsm_action_l163c11 && !WILL_FIRE_RL_edp_fhFsm_action_l162c11 && !WILL_FIRE_RL_edp_dmaXmtTailEvent && @@ -2935,6 +2941,7 @@ module mkOCEDP4B(pciDevice, assign WILL_FIRE_RL_edp_mhFsm_action_l173c11 = NOT_edp_outBF_rRdPtr_83_PLUS_1024_283_EQ_edp_o_ETC___d1285 && edp_mhFsm_state_mkFSMstate == 4'd4 && + !WILL_FIRE_RL_edp_fhFsm_action_l161c11 && !WILL_FIRE_RL_edp_fhFsm_action_l163c11 && !WILL_FIRE_RL_edp_fhFsm_action_l162c11 && !WILL_FIRE_RL_edp_dmaXmtTailEvent && @@ -2944,6 +2951,7 @@ module mkOCEDP4B(pciDevice, assign WILL_FIRE_RL_edp_mhFsm_action_l174c11 = NOT_edp_outBF_rRdPtr_83_PLUS_1024_283_EQ_edp_o_ETC___d1285 && edp_mhFsm_state_mkFSMstate == 4'd5 && + !WILL_FIRE_RL_edp_fhFsm_action_l161c11 && !WILL_FIRE_RL_edp_fhFsm_action_l163c11 && !WILL_FIRE_RL_edp_fhFsm_action_l162c11 && !WILL_FIRE_RL_edp_dmaXmtTailEvent && @@ -2987,14 +2995,6 @@ module mkOCEDP4B(pciDevice, !WILL_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ; - // rule RL_wmi_doWriteReq - assign CAN_FIRE_RL_wmi_doWriteReq = - wmi_wmi_operateD && wmi_wmi_peerIsReady && wmi_wmi_dhF$EMPTY_N && - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 && - wmi_wrActive ; - assign WILL_FIRE_RL_wmi_doWriteReq = - CAN_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ; - // rule RL_wmi_doWriteFinalize assign WILL_FIRE_RL_wmi_doWriteFinalize = wmi_wmi_operateD_900_AND_wmi_wmi_peerIsReady_9_ETC___d2075 && @@ -3013,7 +3013,7 @@ module mkOCEDP4B(pciDevice, // rule RL_wmi_doReadReq assign WILL_FIRE_RL_wmi_doReadReq = - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 && + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3215 && wmi_rdActive && !WILL_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ; @@ -3063,6 +3063,14 @@ module mkOCEDP4B(pciDevice, CAN_FIRE_RL_wmi_getRequest && !WILL_FIRE_RL_wmi_doReadReq && !WILL_FIRE_RL_wmi_doWriteReq ; + // rule RL_wmi_doWriteReq + assign CAN_FIRE_RL_wmi_doWriteReq = + wmi_wmi_operateD && wmi_wmi_peerIsReady && wmi_wmi_dhF$EMPTY_N && + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3215 && + wmi_wrActive ; + assign WILL_FIRE_RL_wmi_doWriteReq = + CAN_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ; + // rule RL_wmi_wmi_respF_incCtr assign WILL_FIRE_RL_wmi_wmi_respF_incCtr = ((wmi_wmi_respF_c_r == 2'd0) ? @@ -3169,7 +3177,7 @@ module mkOCEDP4B(pciDevice, bml_lclBufStart) ; assign MUX_bml_lclBufsCF$write_1__SEL_1 = wci_cState == 3'd2 && - (bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2822 || + (bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2833 || NOT_bml_lclBufDone_237_304_AND_IF_bml_dpContro_ETC___d2317) ; assign MUX_bml_lclCredit$write_1__SEL_1 = WILL_FIRE_RL_bml_lcredit && @@ -3185,7 +3193,7 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd0 ; assign MUX_bram_memory$a_put_1__SEL_3 = WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 ; + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2818 ; assign MUX_bram_memory$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd0 ; assign MUX_bram_memory$b_put_1__SEL_2 = @@ -3200,7 +3208,7 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd1 ; assign MUX_bram_memory_1$a_put_1__SEL_3 = WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 ; + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2819 ; assign MUX_bram_memory_1$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd1 ; assign MUX_bram_memory_1$b_put_1__SEL_2 = @@ -3209,13 +3217,13 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_edp_tlpBRAM_writeReq && !edp_tlpBRAM_mReqF$D_OUT[63] && edp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd2 ; - assign MUX_bram_memory_2$a_put_1__SEL_3 = - WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 ; - assign MUX_bram_memory_2$a_put_2__SEL_2 = + assign MUX_bram_memory_2$a_put_1__SEL_2 = WILL_FIRE_RL_edp_tlpBRAM_read_FirstReq && !edp_tlpBRAM_mReqF$D_OUT[60] && edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd2 ; + assign MUX_bram_memory_2$a_put_1__SEL_3 = + WILL_FIRE_RL_edp_tlpBRAM_writeData && + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2820 ; assign MUX_bram_memory_2$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd2 ; assign MUX_bram_memory_2$b_put_1__SEL_2 = @@ -3230,7 +3238,7 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd3 ; assign MUX_bram_memory_3$a_put_1__SEL_3 = WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 ; + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 ; assign MUX_bram_memory_3$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd3 ; assign MUX_bram_memory_3$b_put_1__SEL_2 = @@ -3317,79 +3325,79 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd4 && wmi_doneWithMesg ; assign MUX_bml_crdBuf_value$write_1__VAL_3 = - bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3163 ? + bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3164 ? 16'd0 : bml_crdBuf_value + 16'd1 ; assign MUX_bml_fabBuf_value$write_1__VAL_3 = - bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164 ? + bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3165 ? 16'd0 : bml_fabBuf_value + 16'd1 ; assign MUX_bml_fabBufsAvail$write_1__VAL_1 = - (bml_fabAvail && !bml_remStart) ? x__h116174 : x__h116179 ; + (bml_fabAvail && !bml_remStart) ? x__h117010 : x__h117015 ; assign MUX_bml_fabBufsAvail$write_1__VAL_2 = - (dpControl[3:2] == 2'd1) ? x__h114823 : 16'd0 ; + (dpControl[3:2] == 2'd1) ? x__h115651 : 16'd0 ; assign MUX_bml_fabFlowAddr$write_1__VAL_1 = - bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164 ? + bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3165 ? bml_fabFlowBase : - bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2973 ; + bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2979 ; assign MUX_bml_fabFlowAddr$write_1__VAL_3 = - bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3163 ? + bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3164 ? bml_fabFlowBase : - bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2973 ; + bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2979 ; assign MUX_bml_fabMesgAddr$write_1__VAL_1 = - bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164 ? + bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3165 ? bml_fabMesgBase : bml_fabMesgAddr + bml_fabMesgSize ; assign MUX_bml_fabMetaAddr$write_1__VAL_1 = - bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164 ? + bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3165 ? bml_fabMetaBase : bml_fabMetaAddr + bml_fabMetaSize ; assign MUX_bml_lclBuf_value$write_1__VAL_3 = - bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3183 ? + bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3184 ? 16'd0 : bml_lclBuf_value + 16'd1 ; assign MUX_bml_lclBufsAR$write_1__VAL_1 = (IF_bml_dpControl_wget__213_BITS_1_TO_0_219_EQ__ETC___d2290 && !bml_lclBufStart) ? - x__h115947 : - x__h115952 ; + x__h116779 : + x__h116784 ; assign MUX_bml_lclBufsAR$write_1__VAL_2 = (dpControl[3:2] == 2'd1) ? bml_lclNumBufs : 16'd0 ; assign MUX_bml_lclBufsCF$write_1__VAL_1 = - bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2822 ? - x__h116059 : - x__h116096 ; + bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2833 ? + x__h116891 : + x__h116928 ; assign MUX_bml_lclBufsCF$write_1__VAL_2 = (dpControl[3:2] == 2'd1) ? 16'd0 : bml_lclNumBufs ; assign MUX_bml_lclCredit$write_1__VAL_1 = - (bml_lclBufDone && !bml_remStart) ? x__h116212 : x__h116217 ; + (bml_lclBufDone && !bml_remStart) ? x__h117049 : x__h117054 ; assign MUX_bml_lclMesgAddr$write_1__VAL_2 = - bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3183 ? + bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3184 ? bml_mesgBase : bml_lclMesgAddr + bml_mesgSize ; assign MUX_bml_lclMetaAddr$write_1__VAL_2 = - bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3183 ? + bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3184 ? bml_metaBase : bml_lclMetaAddr + bml_metaSize ; assign MUX_bml_remBuf_value$write_1__VAL_3 = - bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3184 ? + bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3185 ? 16'd0 : bml_remBuf_value + 16'd1 ; assign MUX_bml_remMesgAddr$write_1__VAL_2 = - bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3184 ? + bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3185 ? bml_mesgBase : bml_remMesgAddr + bml_mesgSize ; assign MUX_bml_remMetaAddr$write_1__VAL_2 = - bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3184 ? + bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3185 ? bml_metaBase : bml_remMetaAddr + bml_metaSize ; - always@(idx__h26173 or + always@(idx__h26290 or edp_tlpBRAM_writeDWAddr_PLUS_3__q11 or edp_tlpBRAM_writeDWAddr or edp_tlpBRAM_writeDWAddr_PLUS_1__q12 or edp_tlpBRAM_writeDWAddr_PLUS_2__q13) begin - case (idx__h26173) + case (idx__h26290) 2'd0: MUX_bram_memory$a_put_2__VAL_3 = edp_tlpBRAM_writeDWAddr[12:2]; 2'd1: MUX_bram_memory$a_put_2__VAL_3 = @@ -3402,13 +3410,13 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_writeDWAddr_PLUS_3__q11[12:2]; endcase end - always@(idx__h33404 or + always@(idx__h33370 or edp_tlpBRAM_readNxtDWAddr_PLUS_3__q14 or edp_tlpBRAM_readNxtDWAddr or edp_tlpBRAM_readNxtDWAddr_PLUS_1__q15 or edp_tlpBRAM_readNxtDWAddr_PLUS_2__q16) begin - case (idx__h33404) + case (idx__h33370) 2'd0: MUX_bram_memory$a_put_2__VAL_4 = edp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: MUX_bram_memory$a_put_2__VAL_4 = @@ -3427,19 +3435,19 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mReqF$D_OUT[23:16], edp_tlpBRAM_mReqF$D_OUT[31:24] } ; assign MUX_bram_memory$a_put_3__VAL_3 = - { IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841[7:0], - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841[15:8], - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841[23:16], - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841[31:24] } ; + { IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2852[7:0], + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2852[15:8], + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2852[23:16], + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2852[31:24] } ; assign MUX_bram_memory$b_put_2__VAL_1 = wmi_lclMesgAddr[14:4] + { 1'd0, wmi_addr[13:4] } ; - always@(idx__h28404 or + always@(idx__h28521 or edp_tlpBRAM_writeDWAddr_PLUS_3__q11 or edp_tlpBRAM_writeDWAddr or edp_tlpBRAM_writeDWAddr_PLUS_1__q12 or edp_tlpBRAM_writeDWAddr_PLUS_2__q13) begin - case (idx__h28404) + case (idx__h28521) 2'd0: MUX_bram_memory_1$a_put_2__VAL_3 = edp_tlpBRAM_writeDWAddr[12:2]; 2'd1: MUX_bram_memory_1$a_put_2__VAL_3 = @@ -3452,13 +3460,13 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_writeDWAddr_PLUS_3__q11[12:2]; endcase end - always@(idx__h33872 or + always@(idx__h33838 or edp_tlpBRAM_readNxtDWAddr_PLUS_3__q14 or edp_tlpBRAM_readNxtDWAddr or edp_tlpBRAM_readNxtDWAddr_PLUS_1__q15 or edp_tlpBRAM_readNxtDWAddr_PLUS_2__q16) begin - case (idx__h33872) + case (idx__h33838) 2'd0: MUX_bram_memory_1$a_put_2__VAL_4 = edp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: @@ -3473,17 +3481,17 @@ module mkOCEDP4B(pciDevice, endcase end assign MUX_bram_memory_1$a_put_3__VAL_3 = - { IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842[7:0], - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842[15:8], - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842[23:16], - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842[31:24] } ; - always@(idx__h29708 or + { IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2853[7:0], + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2853[15:8], + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2853[23:16], + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2853[31:24] } ; + always@(idx__h29825 or edp_tlpBRAM_writeDWAddr_PLUS_3__q11 or edp_tlpBRAM_writeDWAddr or edp_tlpBRAM_writeDWAddr_PLUS_1__q12 or edp_tlpBRAM_writeDWAddr_PLUS_2__q13) begin - case (idx__h29708) + case (idx__h29825) 2'd0: MUX_bram_memory_2$a_put_2__VAL_3 = edp_tlpBRAM_writeDWAddr[12:2]; 2'd1: MUX_bram_memory_2$a_put_2__VAL_3 = @@ -3496,13 +3504,13 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_writeDWAddr_PLUS_3__q11[12:2]; endcase end - always@(idx__h34245 or + always@(idx__h34211 or edp_tlpBRAM_readNxtDWAddr_PLUS_3__q14 or edp_tlpBRAM_readNxtDWAddr or edp_tlpBRAM_readNxtDWAddr_PLUS_1__q15 or edp_tlpBRAM_readNxtDWAddr_PLUS_2__q16) begin - case (idx__h34245) + case (idx__h34211) 2'd0: MUX_bram_memory_2$a_put_2__VAL_4 = edp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: @@ -3517,17 +3525,17 @@ module mkOCEDP4B(pciDevice, endcase end assign MUX_bram_memory_2$a_put_3__VAL_3 = - { IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843[7:0], - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843[15:8], - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843[23:16], - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843[31:24] } ; - always@(idx__h31012 or + { IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2854[7:0], + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2854[15:8], + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2854[23:16], + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2854[31:24] } ; + always@(idx__h31129 or edp_tlpBRAM_writeDWAddr_PLUS_3__q11 or edp_tlpBRAM_writeDWAddr or edp_tlpBRAM_writeDWAddr_PLUS_1__q12 or edp_tlpBRAM_writeDWAddr_PLUS_2__q13) begin - case (idx__h31012) + case (idx__h31129) 2'd0: MUX_bram_memory_3$a_put_2__VAL_3 = edp_tlpBRAM_writeDWAddr[12:2]; 2'd1: MUX_bram_memory_3$a_put_2__VAL_3 = @@ -3540,13 +3548,13 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_writeDWAddr_PLUS_3__q11[12:2]; endcase end - always@(idx__h34618 or + always@(idx__h34584 or edp_tlpBRAM_readNxtDWAddr_PLUS_3__q14 or edp_tlpBRAM_readNxtDWAddr or edp_tlpBRAM_readNxtDWAddr_PLUS_1__q15 or edp_tlpBRAM_readNxtDWAddr_PLUS_2__q16) begin - case (idx__h34618) + case (idx__h34584) 2'd0: MUX_bram_memory_3$a_put_2__VAL_4 = edp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: @@ -3561,18 +3569,18 @@ module mkOCEDP4B(pciDevice, endcase end assign MUX_bram_memory_3$a_put_3__VAL_3 = - { IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844[7:0], - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844[15:8], - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844[23:16], - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844[31:24] } ; + { IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2855[7:0], + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2855[15:8], + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2855[23:16], + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2855[31:24] } ; assign MUX_edp_doorSeqDwell$write_1__VAL_1 = edp_doorSeqDwell - 4'd1 ; - assign MUX_edp_fabMesgAccu$write_1__VAL_2 = edp_fabMesgAccu + y__h86228 ; + assign MUX_edp_fabMesgAccu$write_1__VAL_2 = edp_fabMesgAccu + y__h86614 ; assign MUX_edp_fabMeta$write_1__VAL_2 = { 1'd1, - x__h83716, - opcode__h80539, - nowMS__h81770, - nowLS__h82713 } ; + x__h84086, + opcode__h80909, + nowMS__h82140, + nowLS__h83083 } ; assign MUX_edp_mesgLengthRemainPush$write_1__VAL_1 = { edp_mesgLengthRemainPush_PLUS_3__q18[16:2], 2'd0 } ; assign MUX_edp_mesgLengthRemainPush$write_1__VAL_2 = @@ -3580,7 +3588,7 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mRespF$D_OUT[23:16], edp_tlpBRAM_mRespF$D_OUT[31:24] } ; assign MUX_edp_mesgLengthRemainPush$write_1__VAL_3 = - edp_mesgLengthRemainPush - y__h85835 ; + edp_mesgLengthRemainPush - y__h86209 ; assign MUX_edp_outBF_wDataIn$wset_1__VAL_1 = { 2'd0, edp_fabMesgAddrMS[15:8], @@ -3653,18 +3661,18 @@ module mkOCEDP4B(pciDevice, 2'd0, edp_outFunl_outF$D_OUT[7:0] } ; assign MUX_edp_outDwRemain$write_1__VAL_1 = - edp_tlpBRAM_mRespF$D_OUT[71:62] - y__h86177 ; + edp_tlpBRAM_mRespF$D_OUT[71:62] - y__h86555 ; assign MUX_edp_outDwRemain$write_1__VAL_2 = edp_outDwRemain - 10'd4 ; assign MUX_edp_outFunl_inF$enq_1__VAL_1 = - { nowLS__h82713, nowMS__h81770, opcode__h80539, edp_lastMetaV } ; + { nowLS__h83083, nowMS__h82140, opcode__h80909, edp_lastMetaV } ; assign MUX_edp_outFunl_inF$enq_1__VAL_2 = - { x__h78704, nowLS__h82713, nowMS__h81770, opcode__h80539 } ; + { x__h79125, nowLS__h83083, nowMS__h82140, opcode__h80909 } ; assign MUX_edp_postSeqDwell$write_1__VAL_1 = (dpControl[1:0] == 2'd2) ? 4'd8 : 4'd4 ; assign MUX_edp_postSeqDwell$write_1__VAL_2 = edp_postSeqDwell - 4'd1 ; assign MUX_edp_remMesgAccu$write_1__VAL_2 = - edp_remMesgAccu + { 3'd0, thisRequestLength__h85810 } ; - assign MUX_edp_srcMesgAccu$write_1__VAL_2 = edp_srcMesgAccu + y__h85926 ; + edp_remMesgAccu + { 3'd0, thisRequestLength__h86184 } ; + assign MUX_edp_srcMesgAccu$write_1__VAL_2 = edp_srcMesgAccu + y__h86300 ; assign MUX_edp_tlpBRAM_mReqF$enq_1__VAL_1 = { 88'h955555555555555553FFF8, edp_remMetaAddr[14:2], @@ -3674,42 +3682,42 @@ module mkOCEDP4B(pciDevice, edp_fabMesgAddrMS != 32'd0, 18'd196600, edp_remMesgAccu[14:2], - thisRequestLength__h85810[11:2], + thisRequestLength__h86184[11:2], 8'd255, - rreq_tag__h86003, + rreq_tag__h86377, 3'h2 } ; assign MUX_edp_tlpBRAM_mRespF$enq_1__VAL_1 = { 48'h2AAAAAAAAAAA, !edp_tlpBRAM_readReq$D_OUT[60], edp_tlpBRAM_readReq$D_OUT[59:42], edp_tlpBRAM_readReq$D_OUT[28:19], - lowAddr__h35546, - byteCount__h35547, + lowAddr__h35514, + byteCount__h35515, edp_tlpBRAM_readReq$D_OUT[10:0], - rresp_data__h35592 } ; + rresp_data__h35560 } ; assign MUX_edp_tlpBRAM_mRespF$enq_1__VAL_2 = { 1'd1, edp_tlpBRAM_readReq$D_OUT[59:58], edp_tlpBRAM_readReq$D_OUT[10:3], - rdata__h40976 } ; + rdata__h40953 } ; assign MUX_edp_tlpBRAM_rdRespDwRemain$write_1__VAL_1 = - edp_tlpBRAM_readReq$D_OUT[28:19] - y__h36607 ; + edp_tlpBRAM_readReq$D_OUT[28:19] - y__h36575 ; assign MUX_edp_tlpBRAM_rdRespDwRemain$write_1__VAL_2 = edp_tlpBRAM_rdRespDwRemain - 10'd4 ; assign MUX_edp_tlpBRAM_readNxtDWAddr$write_1__VAL_1 = - edp_tlpBRAM_mReqF$D_OUT[41:29] + y__h33157 ; + edp_tlpBRAM_mReqF$D_OUT[41:29] + y__h33152 ; assign MUX_edp_tlpBRAM_readNxtDWAddr$write_1__VAL_2 = edp_tlpBRAM_readNxtDWAddr + 13'd4 ; assign MUX_edp_tlpBRAM_readRemainDWLen$write_1__VAL_1 = - edp_tlpBRAM_mReqF$D_OUT[28:19] - y__h33109 ; + edp_tlpBRAM_mReqF$D_OUT[28:19] - y__h33140 ; assign MUX_edp_tlpBRAM_readRemainDWLen$write_1__VAL_2 = edp_tlpBRAM_readRemainDWLen - 10'd4 ; assign MUX_edp_tlpBRAM_writeDWAddr$write_1__VAL_1 = - edp_tlpBRAM_mReqF$D_OUT[62:50] + y__h24387 ; + edp_tlpBRAM_mReqF$D_OUT[62:50] + y__h24591 ; assign MUX_edp_tlpBRAM_writeDWAddr$write_1__VAL_2 = edp_tlpBRAM_writeDWAddr + 13'd4 ; assign MUX_edp_tlpBRAM_writeRemainDWLen$write_1__VAL_1 = - edp_tlpBRAM_mReqF$D_OUT[49:40] - y__h24458 ; + edp_tlpBRAM_mReqF$D_OUT[49:40] - y__h24658 ; assign MUX_edp_tlpBRAM_writeRemainDWLen$write_1__VAL_2 = edp_tlpBRAM_writeRemainDWLen - 10'd4 ; assign MUX_wci_illegalEdge$write_1__VAL_2 = @@ -3745,7 +3753,7 @@ module mkOCEDP4B(pciDevice, assign MUX_wci_respF_x_wire$wset_1__VAL_1 = wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h118030 } ; + { 2'd1, _theResult____h118894 } ; assign MUX_wmi_addr$write_1__VAL_1 = wmi_addr + 14'd4 ; assign MUX_wmi_bufDwell$write_1__VAL_3 = wmi_bufDwell - 2'd1 ; assign MUX_wmi_bytesRemainReq$write_1__VAL_1 = wmi_bytesRemainReq - 14'd4 ; @@ -3756,10 +3764,10 @@ module mkOCEDP4B(pciDevice, assign MUX_wmi_mesgCount$write_1__VAL_1 = wmi_mesgCount + 32'd1 ; assign MUX_wmi_mesgMeta$write_1__VAL_2 = { 1'd1, - y_avValue__h110302, - y_avValue__h110322, - y_avValue__h110342, - y_avValue__h110362 } ; + y_avValue__h110896, + y_avValue__h110916, + y_avValue__h110936, + y_avValue__h110956 } ; assign MUX_wmi_p4B$write_1__VAL_2 = wmi_p4B + 2'd1 ; assign MUX_wmi_wmi_respF_c_r$write_1__VAL_1 = wmi_wmi_respF_c_r + 2'd1 ; assign MUX_wmi_wmi_respF_c_r$write_1__VAL_2 = wmi_wmi_respF_c_r - 2'd1 ; @@ -3767,7 +3775,7 @@ module mkOCEDP4B(pciDevice, (wmi_wmi_respF_c_r == 2'd1) ? MUX_wmi_wmi_respF_q_0$write_1__VAL_2 : wmi_wmi_respF_q_1 ; - assign MUX_wmi_wmi_respF_q_0$write_1__VAL_2 = { 2'd1, rdata__h110466 } ; + assign MUX_wmi_wmi_respF_q_0$write_1__VAL_2 = { 2'd1, rdata__h111060 } ; assign MUX_wmi_wmi_respF_q_1$write_1__VAL_1 = (wmi_wmi_respF_c_r == 2'd2) ? MUX_wmi_wmi_respF_q_0$write_1__VAL_2 : @@ -3794,20 +3802,20 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory$a_put_1__SEL_2 || MUX_bram_memory$a_put_1__SEL_3 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) && - (!ab__h1600[1] || ab__h1600[0]) ; + (!ab__h1613[1] || ab__h1613[0]) ; assign bram_serverAdapterA_cnt_2$wget = 3'd7 ; assign bram_serverAdapterA_cnt_2$whas = bram_serverAdapterA_outData_deqCalled$whas ; assign bram_serverAdapterA_cnt_3$wget = 3'h0 ; assign bram_serverAdapterA_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterA_writeWithResp$wget = ab__h1600 ; + assign bram_serverAdapterA_writeWithResp$wget = ab__h1613 ; assign bram_serverAdapterA_writeWithResp$whas = MUX_bram_memory$a_put_1__SEL_1 || MUX_bram_memory$a_put_1__SEL_2 || MUX_bram_memory$a_put_1__SEL_3 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_serverAdapterA_s1_1$wget = - { 1'd1, !ab__h1600[1] || ab__h1600[0] } ; + { 1'd1, !ab__h1613[1] || ab__h1613[0] } ; assign bram_serverAdapterA_s1_1$whas = bram_serverAdapterA_writeWithResp$whas ; assign bram_serverAdapterB_outData_enqData$wget = bram_memory$DOB ; @@ -3816,7 +3824,7 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterB_outDataCore$FULL_N) && bram_serverAdapterB_s1[1] && bram_serverAdapterB_s1[0] ; - assign bram_serverAdapterB_outData_outData$wget = y_avValue__h110302 ; + assign bram_serverAdapterB_outData_outData$wget = y_avValue__h110896 ; assign bram_serverAdapterB_outData_outData$whas = bram_serverAdapterB_outDataCore$EMPTY_N || !bram_serverAdapterB_outDataCore$EMPTY_N && @@ -3827,20 +3835,20 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory$b_put_1__SEL_2 || WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize) && - (!ab__h2999[1] || ab__h2999[0]) ; + (!ab__h3019[1] || ab__h3019[0]) ; assign bram_serverAdapterB_cnt_2$wget = 3'd7 ; assign bram_serverAdapterB_cnt_2$whas = bram_serverAdapterB_outData_deqCalled$whas ; assign bram_serverAdapterB_cnt_3$wget = 3'h0 ; assign bram_serverAdapterB_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterB_writeWithResp$wget = ab__h2999 ; + assign bram_serverAdapterB_writeWithResp$wget = ab__h3019 ; assign bram_serverAdapterB_writeWithResp$whas = MUX_bram_memory$b_put_1__SEL_1 || MUX_bram_memory$b_put_1__SEL_2 || WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize ; assign bram_serverAdapterB_s1_1$wget = - { 1'd1, !ab__h2999[1] || ab__h2999[0] } ; + { 1'd1, !ab__h3019[1] || ab__h3019[0] } ; assign bram_serverAdapterB_s1_1$whas = bram_serverAdapterB_writeWithResp$whas ; assign bram_serverAdapterA_1_outData_enqData$wget = bram_memory_1$DOA ; @@ -3863,20 +3871,20 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory_1$a_put_1__SEL_2 || MUX_bram_memory_1$a_put_1__SEL_3 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) && - (!ab__h4529[1] || ab__h4529[0]) ; + (!ab__h4561[1] || ab__h4561[0]) ; assign bram_serverAdapterA_1_cnt_2$wget = 3'd7 ; assign bram_serverAdapterA_1_cnt_2$whas = bram_serverAdapterA_1_outData_deqCalled$whas ; assign bram_serverAdapterA_1_cnt_3$wget = 3'h0 ; assign bram_serverAdapterA_1_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterA_1_writeWithResp$wget = ab__h4529 ; + assign bram_serverAdapterA_1_writeWithResp$wget = ab__h4561 ; assign bram_serverAdapterA_1_writeWithResp$whas = MUX_bram_memory_1$a_put_1__SEL_1 || MUX_bram_memory_1$a_put_1__SEL_2 || MUX_bram_memory_1$a_put_1__SEL_3 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_serverAdapterA_1_s1_1$wget = - { 1'd1, !ab__h4529[1] || ab__h4529[0] } ; + { 1'd1, !ab__h4561[1] || ab__h4561[0] } ; assign bram_serverAdapterA_1_s1_1$whas = bram_serverAdapterA_1_writeWithResp$whas ; assign bram_serverAdapterB_1_outData_enqData$wget = bram_memory_1$DOB ; @@ -3885,7 +3893,7 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterB_1_outDataCore$FULL_N) && bram_serverAdapterB_1_s1[1] && bram_serverAdapterB_1_s1[0] ; - assign bram_serverAdapterB_1_outData_outData$wget = y_avValue__h110322 ; + assign bram_serverAdapterB_1_outData_outData$wget = y_avValue__h110916 ; assign bram_serverAdapterB_1_outData_outData$whas = bram_serverAdapterB_1_outDataCore$EMPTY_N || !bram_serverAdapterB_1_outDataCore$EMPTY_N && @@ -3896,20 +3904,20 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory_1$b_put_1__SEL_2 || WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize) && - (!ab__h5926[1] || ab__h5926[0]) ; + (!ab__h5965[1] || ab__h5965[0]) ; assign bram_serverAdapterB_1_cnt_2$wget = 3'd7 ; assign bram_serverAdapterB_1_cnt_2$whas = bram_serverAdapterB_1_outData_deqCalled$whas ; assign bram_serverAdapterB_1_cnt_3$wget = 3'h0 ; assign bram_serverAdapterB_1_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterB_1_writeWithResp$wget = ab__h5926 ; + assign bram_serverAdapterB_1_writeWithResp$wget = ab__h5965 ; assign bram_serverAdapterB_1_writeWithResp$whas = MUX_bram_memory_1$b_put_1__SEL_1 || MUX_bram_memory_1$b_put_1__SEL_2 || WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize ; assign bram_serverAdapterB_1_s1_1$wget = - { 1'd1, !ab__h5926[1] || ab__h5926[0] } ; + { 1'd1, !ab__h5965[1] || ab__h5965[0] } ; assign bram_serverAdapterB_1_s1_1$whas = bram_serverAdapterB_1_writeWithResp$whas ; assign bram_serverAdapterA_2_outData_enqData$wget = bram_memory_2$DOA ; @@ -3929,23 +3937,23 @@ module mkOCEDP4B(pciDevice, assign bram_serverAdapterA_2_cnt_1$wget = 3'd1 ; assign bram_serverAdapterA_2_cnt_1$whas = (MUX_bram_memory_2$a_put_1__SEL_1 || - MUX_bram_memory_2$a_put_2__SEL_2 || + MUX_bram_memory_2$a_put_1__SEL_2 || MUX_bram_memory_2$a_put_1__SEL_3 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) && - (!ab__h7456[1] || ab__h7456[0]) ; + (!ab__h7507[1] || ab__h7507[0]) ; assign bram_serverAdapterA_2_cnt_2$wget = 3'd7 ; assign bram_serverAdapterA_2_cnt_2$whas = bram_serverAdapterA_2_outData_deqCalled$whas ; assign bram_serverAdapterA_2_cnt_3$wget = 3'h0 ; assign bram_serverAdapterA_2_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterA_2_writeWithResp$wget = ab__h7456 ; + assign bram_serverAdapterA_2_writeWithResp$wget = ab__h7507 ; assign bram_serverAdapterA_2_writeWithResp$whas = MUX_bram_memory_2$a_put_1__SEL_1 || - MUX_bram_memory_2$a_put_2__SEL_2 || + MUX_bram_memory_2$a_put_1__SEL_2 || MUX_bram_memory_2$a_put_1__SEL_3 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_serverAdapterA_2_s1_1$wget = - { 1'd1, !ab__h7456[1] || ab__h7456[0] } ; + { 1'd1, !ab__h7507[1] || ab__h7507[0] } ; assign bram_serverAdapterA_2_s1_1$whas = bram_serverAdapterA_2_writeWithResp$whas ; assign bram_serverAdapterB_2_outData_enqData$wget = bram_memory_2$DOB ; @@ -3954,7 +3962,7 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterB_2_outDataCore$FULL_N) && bram_serverAdapterB_2_s1[1] && bram_serverAdapterB_2_s1[0] ; - assign bram_serverAdapterB_2_outData_outData$wget = y_avValue__h110342 ; + assign bram_serverAdapterB_2_outData_outData$wget = y_avValue__h110936 ; assign bram_serverAdapterB_2_outData_outData$whas = bram_serverAdapterB_2_outDataCore$EMPTY_N || !bram_serverAdapterB_2_outDataCore$EMPTY_N && @@ -3965,20 +3973,20 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory_2$b_put_1__SEL_2 || WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize) && - (!ab__h8853[1] || ab__h8853[0]) ; + (!ab__h8911[1] || ab__h8911[0]) ; assign bram_serverAdapterB_2_cnt_2$wget = 3'd7 ; assign bram_serverAdapterB_2_cnt_2$whas = bram_serverAdapterB_2_outData_deqCalled$whas ; assign bram_serverAdapterB_2_cnt_3$wget = 3'h0 ; assign bram_serverAdapterB_2_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterB_2_writeWithResp$wget = ab__h8853 ; + assign bram_serverAdapterB_2_writeWithResp$wget = ab__h8911 ; assign bram_serverAdapterB_2_writeWithResp$whas = MUX_bram_memory_2$b_put_1__SEL_1 || MUX_bram_memory_2$b_put_1__SEL_2 || WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize ; assign bram_serverAdapterB_2_s1_1$wget = - { 1'd1, !ab__h8853[1] || ab__h8853[0] } ; + { 1'd1, !ab__h8911[1] || ab__h8911[0] } ; assign bram_serverAdapterB_2_s1_1$whas = bram_serverAdapterB_2_writeWithResp$whas ; assign bram_serverAdapterA_3_outData_enqData$wget = bram_memory_3$DOA ; @@ -4001,20 +4009,20 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory_3$a_put_1__SEL_2 || MUX_bram_memory_3$a_put_1__SEL_3 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) && - (!ab__h10383[1] || ab__h10383[0]) ; + (!ab__h10453[1] || ab__h10453[0]) ; assign bram_serverAdapterA_3_cnt_2$wget = 3'd7 ; assign bram_serverAdapterA_3_cnt_2$whas = bram_serverAdapterA_3_outData_deqCalled$whas ; assign bram_serverAdapterA_3_cnt_3$wget = 3'h0 ; assign bram_serverAdapterA_3_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterA_3_writeWithResp$wget = ab__h10383 ; + assign bram_serverAdapterA_3_writeWithResp$wget = ab__h10453 ; assign bram_serverAdapterA_3_writeWithResp$whas = MUX_bram_memory_3$a_put_1__SEL_1 || MUX_bram_memory_3$a_put_1__SEL_2 || MUX_bram_memory_3$a_put_1__SEL_3 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_serverAdapterA_3_s1_1$wget = - { 1'd1, !ab__h10383[1] || ab__h10383[0] } ; + { 1'd1, !ab__h10453[1] || ab__h10453[0] } ; assign bram_serverAdapterA_3_s1_1$whas = bram_serverAdapterA_3_writeWithResp$whas ; assign bram_serverAdapterB_3_outData_enqData$wget = bram_memory_3$DOB ; @@ -4023,7 +4031,7 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterB_3_outDataCore$FULL_N) && bram_serverAdapterB_3_s1[1] && bram_serverAdapterB_3_s1[0] ; - assign bram_serverAdapterB_3_outData_outData$wget = y_avValue__h110362 ; + assign bram_serverAdapterB_3_outData_outData$wget = y_avValue__h110956 ; assign bram_serverAdapterB_3_outData_outData$whas = bram_serverAdapterB_3_outDataCore$EMPTY_N || !bram_serverAdapterB_3_outDataCore$EMPTY_N && @@ -4034,20 +4042,20 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory_3$b_put_1__SEL_2 || WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize) && - (!ab__h11780[1] || ab__h11780[0]) ; + (!ab__h11857[1] || ab__h11857[0]) ; assign bram_serverAdapterB_3_cnt_2$wget = 3'd7 ; assign bram_serverAdapterB_3_cnt_2$whas = bram_serverAdapterB_3_outData_deqCalled$whas ; assign bram_serverAdapterB_3_cnt_3$wget = 3'h0 ; assign bram_serverAdapterB_3_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterB_3_writeWithResp$wget = ab__h11780 ; + assign bram_serverAdapterB_3_writeWithResp$wget = ab__h11857 ; assign bram_serverAdapterB_3_writeWithResp$whas = MUX_bram_memory_3$b_put_1__SEL_1 || MUX_bram_memory_3$b_put_1__SEL_2 || WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize ; assign bram_serverAdapterB_3_s1_1$wget = - { 1'd1, !ab__h11780[1] || ab__h11780[0] } ; + { 1'd1, !ab__h11857[1] || ab__h11857[0] } ; assign bram_serverAdapterB_3_s1_1$whas = bram_serverAdapterB_3_writeWithResp$whas ; assign wci_wciReq$wget = @@ -4183,7 +4191,7 @@ module mkOCEDP4B(pciDevice, assign edp_dmaDoneMark_1$wget = 1'd1 ; assign edp_dmaDoneMark_1$whas = WILL_FIRE_RL_edp_dmaTailEventSender ; assign edp_doorBell_1$wget = 1'd1 ; - assign edp_doorBell_1$whas = WILL_FIRE_RL_edp_ingress && x__h96121 != 4'd0 ; + assign edp_doorBell_1$whas = WILL_FIRE_RL_edp_ingress && x__h96502 != 4'd0 ; assign edp_fhFsm_start_wire$wget = 1'd1 ; assign edp_fhFsm_start_wire$whas = WILL_FIRE_RL_edp_fhFsm_fsm_start || @@ -4592,7 +4600,7 @@ module mkOCEDP4B(pciDevice, MUX_bml_lclBufsCF$write_1__VAL_2 ; assign bml_lclBufsCF$EN = wci_cState == 3'd2 && - (bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2822 || + (bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2833 || NOT_bml_lclBufDone_237_304_AND_IF_bml_dpContro_ETC___d2317) || WILL_FIRE_RL_bml_initAccumulators ; @@ -5063,7 +5071,7 @@ module mkOCEDP4B(pciDevice, // register edp_igPtr assign edp_igPtr$D_IN = - (x__h96121 == 4'd0) ? + (x__h96502 == 4'd0) ? ((edp_igPtr == 4'd15) ? edp_igPtr : edp_igPtr + 4'd1) : 4'd0 ; assign edp_igPtr$EN = WILL_FIRE_RL_edp_ingress ; @@ -5073,19 +5081,19 @@ module mkOCEDP4B(pciDevice, assign edp_inIgnorePkt$EN = 1'b0 ; // register edp_lastMetaV - assign edp_lastMetaV$D_IN = x__h78704 ; + assign edp_lastMetaV$D_IN = x__h79125 ; assign edp_lastMetaV$EN = WILL_FIRE_RL_edp_dmaResponseNearMetaHead ; // register edp_lastMetaV_1 - assign edp_lastMetaV_1$D_IN = opcode__h80539 ; + assign edp_lastMetaV_1$D_IN = opcode__h80909 ; assign edp_lastMetaV_1$EN = WILL_FIRE_RL_edp_dmaResponseNearMetaBody ; // register edp_lastMetaV_2 - assign edp_lastMetaV_2$D_IN = nowMS__h81770 ; + assign edp_lastMetaV_2$D_IN = nowMS__h82140 ; assign edp_lastMetaV_2$EN = WILL_FIRE_RL_edp_dmaResponseNearMetaBody ; // register edp_lastMetaV_3 - assign edp_lastMetaV_3$D_IN = nowLS__h82713 ; + assign edp_lastMetaV_3$D_IN = nowLS__h83083 ; assign edp_lastMetaV_3$EN = WILL_FIRE_RL_edp_dmaResponseNearMetaBody ; // register edp_lastRuleFired @@ -5214,14 +5222,14 @@ module mkOCEDP4B(pciDevice, assign edp_outBF_rCache$D_IN = { 1'd1, edp_outBF_rWrPtr, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2732, IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2733, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2731 } ; + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2727, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2728, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2729 } ; assign edp_outBF_rCache$EN = edp_outBF_pwEnqueue$whas ; // register edp_outBF_rRdPtr - assign edp_outBF_rRdPtr$D_IN = x__h20653 ; + assign edp_outBF_rRdPtr$D_IN = x__h20838 ; assign edp_outBF_rRdPtr$EN = edp_outBF_pwDequeue$whas ; // register edp_outBF_rWrPtr @@ -5842,7 +5850,7 @@ module mkOCEDP4B(pciDevice, // register wmi_wmi_sFlagReg assign wmi_wmi_sFlagReg$D_IN = - { y_avValue__h110322[7:0], y_avValue__h110302[23:0] } ; + { y_avValue__h110916[7:0], y_avValue__h110896[23:0] } ; assign wmi_wmi_sFlagReg$EN = WILL_FIRE_RL_wmi_respMetadata ; // register wmi_wmi_statusR @@ -5941,13 +5949,13 @@ module mkOCEDP4B(pciDevice, always@(MUX_bram_memory$b_put_1__SEL_2 or wmi_wmi_dhF$D_OUT or WILL_FIRE_RL_wmi_doWriteFinalize or - x3__h108707 or + x3__h109297 or MUX_bram_memory$b_put_1__SEL_1 or WILL_FIRE_RL_wmi_reqMetadata) begin case (1'b1) // synopsys parallel_case MUX_bram_memory$b_put_1__SEL_2: bram_memory$DIB = wmi_wmi_dhF$D_OUT[35:4]; - WILL_FIRE_RL_wmi_doWriteFinalize: bram_memory$DIB = x3__h108707; + WILL_FIRE_RL_wmi_doWriteFinalize: bram_memory$DIB = x3__h109297; MUX_bram_memory$b_put_1__SEL_1 || WILL_FIRE_RL_wmi_reqMetadata: bram_memory$DIB = 32'd0; default: bram_memory$DIB = 32'hAAAAAAAA /* unspecified value */ ; @@ -5967,7 +5975,7 @@ module mkOCEDP4B(pciDevice, !edp_tlpBRAM_mReqF$D_OUT[60] && edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd0 || WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 || + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2818 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_memory$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd0 || @@ -6033,14 +6041,14 @@ module mkOCEDP4B(pciDevice, always@(MUX_bram_memory_1$b_put_1__SEL_2 or wmi_wmi_dhF$D_OUT or WILL_FIRE_RL_wmi_doWriteFinalize or - mesgMeta_opcode__h108747 or + mesgMeta_opcode__h109337 or MUX_bram_memory_1$b_put_1__SEL_1 or WILL_FIRE_RL_wmi_reqMetadata) begin case (1'b1) // synopsys parallel_case MUX_bram_memory_1$b_put_1__SEL_2: bram_memory_1$DIB = wmi_wmi_dhF$D_OUT[35:4]; WILL_FIRE_RL_wmi_doWriteFinalize: - bram_memory_1$DIB = mesgMeta_opcode__h108747; + bram_memory_1$DIB = mesgMeta_opcode__h109337; MUX_bram_memory_1$b_put_1__SEL_1 || WILL_FIRE_RL_wmi_reqMetadata: bram_memory_1$DIB = 32'd0; default: bram_memory_1$DIB = 32'hAAAAAAAA /* unspecified value */ ; @@ -6060,7 +6068,7 @@ module mkOCEDP4B(pciDevice, !edp_tlpBRAM_mReqF$D_OUT[60] && edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd1 || WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 || + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2819 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_memory_1$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd1 || @@ -6071,7 +6079,7 @@ module mkOCEDP4B(pciDevice, // submodule bram_memory_2 always@(MUX_bram_memory_2$a_put_1__SEL_1 or edp_tlpBRAM_mReqF$D_OUT or - MUX_bram_memory_2$a_put_2__SEL_2 or + MUX_bram_memory_2$a_put_1__SEL_2 or MUX_bram_memory_2$a_put_1__SEL_3 or MUX_bram_memory_2$a_put_2__VAL_3 or WILL_FIRE_RL_edp_tlpBRAM_read_NextReq or @@ -6080,7 +6088,7 @@ module mkOCEDP4B(pciDevice, case (1'b1) // synopsys parallel_case MUX_bram_memory_2$a_put_1__SEL_1: bram_memory_2$ADDRA = edp_tlpBRAM_mReqF$D_OUT[62:52]; - MUX_bram_memory_2$a_put_2__SEL_2: + MUX_bram_memory_2$a_put_1__SEL_2: bram_memory_2$ADDRA = edp_tlpBRAM_mReqF$D_OUT[41:31]; MUX_bram_memory_2$a_put_1__SEL_3: bram_memory_2$ADDRA = MUX_bram_memory_2$a_put_2__VAL_3; @@ -6109,7 +6117,7 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory$a_put_3__VAL_1 or MUX_bram_memory_2$a_put_1__SEL_3 or MUX_bram_memory_2$a_put_3__VAL_3 or - MUX_bram_memory_2$a_put_2__SEL_2 or + MUX_bram_memory_2$a_put_1__SEL_2 or WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) begin case (1'b1) // synopsys parallel_case @@ -6117,7 +6125,7 @@ module mkOCEDP4B(pciDevice, bram_memory_2$DIA = MUX_bram_memory$a_put_3__VAL_1; MUX_bram_memory_2$a_put_1__SEL_3: bram_memory_2$DIA = MUX_bram_memory_2$a_put_3__VAL_3; - MUX_bram_memory_2$a_put_2__SEL_2 || + MUX_bram_memory_2$a_put_1__SEL_2 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq: bram_memory_2$DIA = 32'd0; default: bram_memory_2$DIA = 32'hAAAAAAAA /* unspecified value */ ; @@ -6140,7 +6148,7 @@ module mkOCEDP4B(pciDevice, endcase end assign bram_memory_2$WEA = - !MUX_bram_memory_2$a_put_2__SEL_2 && + !MUX_bram_memory_2$a_put_1__SEL_2 && !WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_memory_2$WEB = !MUX_bram_memory_2$b_put_1__SEL_1 && @@ -6153,7 +6161,7 @@ module mkOCEDP4B(pciDevice, !edp_tlpBRAM_mReqF$D_OUT[60] && edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd2 || WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 || + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2820 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_memory_2$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd2 || @@ -6246,7 +6254,7 @@ module mkOCEDP4B(pciDevice, !edp_tlpBRAM_mReqF$D_OUT[60] && edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd3 || WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 || + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_memory_3$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd3 || @@ -6400,13 +6408,13 @@ module mkOCEDP4B(pciDevice, assign edp_outBF_memory$ADDRA = edp_outBF_rWrPtr[10:0] ; assign edp_outBF_memory$ADDRB = edp_outBF_pwDequeue$whas ? - x__h20653[10:0] : + x__h20838[10:0] : edp_outBF_rRdPtr[10:0] ; assign edp_outBF_memory$DIA = - { IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2732, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2733, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2731 } ; + { IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2727, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2728, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2729 } ; assign edp_outBF_memory$DIB = 40'hAAAAAAAAAA /* unspecified value */ ; assign edp_outBF_memory$WEA = edp_outBF_pwEnqueue$whas ; assign edp_outBF_memory$WEB = 1'd0 ; @@ -6541,12 +6549,12 @@ module mkOCEDP4B(pciDevice, // remaining internal signals assign IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d872 = (IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849 || - bram_serverAdapterA_1_cnt_44_SLT_3___d2975) && + bram_serverAdapterA_1_cnt_44_SLT_3___d2980) && (IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859 || - bram_serverAdapterA_2_cnt_62_SLT_3___d2976) && + bram_serverAdapterA_2_cnt_62_SLT_3___d2766) && (IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2977) ; - assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730 = + bram_serverAdapterA_3_cnt_80_SLT_3___d2765) ; + assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2727 = (!edp_outBF_wDataIn$whas || edp_outBF_wDataIn$wget[29:28] == 2'd0) ? { 2'd0, @@ -6555,7 +6563,16 @@ module mkOCEDP4B(pciDevice, 8'd0 } : { CASE_edp_outBF_wDataInwget_BITS_29_TO_28_3_1__ETC__q30, edp_outBF_wDataIn$wget[27:20] } ; - assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2731 = + assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2728 = + (!edp_outBF_wDataIn$whas || + edp_outBF_wDataIn$wget[19:18] == 2'd0) ? + { 2'd0, + edp_outBF_wDataIn$whas ? + edp_outBF_wDataIn$wget[17:10] : + 8'd0 } : + { CASE_edp_outBF_wDataInwget_BITS_19_TO_18_3_1__ETC__q31, + edp_outBF_wDataIn$wget[17:10] } ; + assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2729 = (!edp_outBF_wDataIn$whas || edp_outBF_wDataIn$wget[9:8] == 2'd0) ? { 2'd0, @@ -6564,7 +6581,7 @@ module mkOCEDP4B(pciDevice, 8'd0 } : { CASE_edp_outBF_wDataInwget_BITS_9_TO_8_3_1_ed_ETC__q32, edp_outBF_wDataIn$wget[7:0] } ; - assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2732 = + assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730 = (!edp_outBF_wDataIn$whas || edp_outBF_wDataIn$wget[39:38] == 2'd0) ? { 2'd0, @@ -6573,20 +6590,11 @@ module mkOCEDP4B(pciDevice, 8'd0 } : { CASE_edp_outBF_wDataInwget_BITS_39_TO_38_3_1__ETC__q29, edp_outBF_wDataIn$wget[37:30] } ; - assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2733 = - (!edp_outBF_wDataIn$whas || - edp_outBF_wDataIn$wget[19:18] == 2'd0) ? - { 2'd0, - edp_outBF_wDataIn$whas ? - edp_outBF_wDataIn$wget[17:10] : - 8'd0 } : - { CASE_edp_outBF_wDataInwget_BITS_19_TO_18_3_1__ETC__q31, - edp_outBF_wDataIn$wget[17:10] } ; assign IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1085 = IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1076 && CASE_edp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q19 ; assign IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1201 = - edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2699[0] ? + edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2692[0] ? { bram_serverAdapterA_3_outData_outData$wget[7:0], bram_serverAdapterA_3_outData_outData$wget[15:8], bram_serverAdapterA_3_outData_outData$wget[23:16], @@ -6620,7 +6628,7 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterA_1_outData_outData$wget[23:16], bram_serverAdapterA_1_outData_outData$wget[31:24] } ; assign IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1206 = - edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2699[0] ? + edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2692[0] ? { bram_serverAdapterA_1_outData_outData$wget[7:0], bram_serverAdapterA_1_outData_outData$wget[15:8], bram_serverAdapterA_1_outData_outData$wget[23:16], @@ -6668,70 +6676,70 @@ module mkOCEDP4B(pciDevice, assign NOT_wmi_wrActive_011_012_OR_NOT_wmi_rdActive_0_ETC___d2021 = (!wmi_wrActive || !wmi_rdActive) && !wmi_wrFinalize && (wmi_mesgBufReady || wmi_mesgBusy) ; - assign ab__h10383 = + assign ab__h10453 = (MUX_bram_memory_3$a_put_1__SEL_2 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) ? 2'd0 : 2'd2 ; - assign ab__h11780 = + assign ab__h11857 = (MUX_bram_memory_3$b_put_1__SEL_1 || WILL_FIRE_RL_wmi_reqMetadata) ? 2'd0 : 2'd2 ; - assign ab__h1600 = + assign ab__h1613 = (MUX_bram_memory$a_put_1__SEL_2 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) ? 2'd0 : 2'd2 ; - assign ab__h2999 = + assign ab__h3019 = (MUX_bram_memory$b_put_1__SEL_1 || WILL_FIRE_RL_wmi_reqMetadata) ? 2'd0 : 2'd2 ; - assign ab__h4529 = + assign ab__h4561 = (MUX_bram_memory_1$a_put_1__SEL_2 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) ? 2'd0 : 2'd2 ; - assign ab__h5926 = + assign ab__h5965 = (MUX_bram_memory_1$b_put_1__SEL_1 || WILL_FIRE_RL_wmi_reqMetadata) ? 2'd0 : 2'd2 ; - assign ab__h7456 = - (MUX_bram_memory_2$a_put_2__SEL_2 || + assign ab__h7507 = + (MUX_bram_memory_2$a_put_1__SEL_2 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) ? 2'd0 : 2'd2 ; - assign ab__h8853 = + assign ab__h8911 = (MUX_bram_memory_2$b_put_1__SEL_1 || WILL_FIRE_RL_wmi_reqMetadata) ? 2'd0 : 2'd2 ; - assign bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3163 = + assign bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3164 = bml_crdBuf_value == bml_crdBuf_modulus ; - assign bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164 = + assign bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3165 = bml_fabBuf_value == bml_fabBuf_modulus ; - assign bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2973 = + assign bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2979 = bml_fabFlowAddr + bml_fabFlowSize ; - assign bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2822 = + assign bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2833 = bml_lclBufDone && CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q9 ; - assign bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3183 = + assign bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3184 = bml_lclBuf_value == bml_lclBuf_modulus ; - assign bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3184 = + assign bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3185 = bml_remBuf_value == bml_remBuf_modulus ; assign bram_serverAdapterA_1_cnt_44_PLUS_IF_bram_serv_ETC___d150 = bram_serverAdapterA_1_cnt + (bram_serverAdapterA_1_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_1_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_1_cnt_44_SLT_3___d2975 = + assign bram_serverAdapterA_1_cnt_44_SLT_3___d2980 = (bram_serverAdapterA_1_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_2_cnt_62_PLUS_IF_bram_serv_ETC___d268 = bram_serverAdapterA_2_cnt + (bram_serverAdapterA_2_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_2_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_2_cnt_62_SLT_3___d2976 = + assign bram_serverAdapterA_2_cnt_62_SLT_3___d2766 = (bram_serverAdapterA_2_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_2_outDataCore_notEmpty__38_ETC___d1157 = (bram_serverAdapterA_2_outDataCore$EMPTY_N || @@ -6747,13 +6755,13 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterA_3_cnt + (bram_serverAdapterA_3_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_3_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_3_cnt_80_SLT_3___d2977 = + assign bram_serverAdapterA_3_cnt_80_SLT_3___d2765 = (bram_serverAdapterA_3_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32 = bram_serverAdapterA_cnt + (bram_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_cnt_6_SLT_3___d2974 = + assign bram_serverAdapterA_cnt_6_SLT_3___d2772 = (bram_serverAdapterA_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_outDataCore_notEmpty_OR_br_ETC___d1159 = (bram_serverAdapterA_outDataCore$EMPTY_N || @@ -6793,7 +6801,7 @@ module mkOCEDP4B(pciDevice, (bram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; assign bram_serverAdapterB_cnt_5_SLT_3___d1960 = (bram_serverAdapterB_cnt ^ 3'h4) < 3'd7 ; - assign byteCount__h35547 = x__h35665 - y__h35666 ; + assign byteCount__h35515 = x__h35633 - y__h35634 ; assign edp_fabMeta_444_BIT_128_445_AND_NOT_edp_fabMet_ETC___d1568 = edp_fabMeta[128] && edp_fabMeta[127:96] != 32'd0 && !edp_tlpRcvBusy && @@ -6831,7 +6839,7 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_readNxtDWAddr + 13'd3 ; assign edp_tlpBRAM_readRemainDWLen_010_ULE_4___d1011 = edp_tlpBRAM_readRemainDWLen <= 10'd4 ; - assign edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2699 = + assign edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2692 = edp_tlpBRAM_readReq$D_OUT[30:29] + (edp_tlpBRAM_readReq$D_OUT[60] ? 2'd0 : 2'd1) ; assign edp_tlpBRAM_writeDWAddr_PLUS_1__q12 = @@ -6840,11 +6848,11 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_writeDWAddr + 13'd2 ; assign edp_tlpBRAM_writeDWAddr_PLUS_3__q11 = edp_tlpBRAM_writeDWAddr + 13'd3 ; - assign edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 = + assign edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724 = edp_tlpBRAM_writeRemainDWLen <= 10'd1 ; - assign edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695 = + assign edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694 = edp_tlpBRAM_writeRemainDWLen <= 10'd2 ; - assign edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 = + assign edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695 = edp_tlpBRAM_writeRemainDWLen <= 10'd3 ; assign hasPush_AND_edp_dpControl_wget__431_BITS_7_TO__ETC___d1451 = hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 && @@ -6889,90 +6897,90 @@ module mkOCEDP4B(pciDevice, !edp_xmtMetaInFlight && edp_xmtMetaOK && edp_postSeqDwell == 4'd0 ; - assign idx__h26173 = 2'd0 - edp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h28404 = 2'd1 - edp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h29708 = 2'd2 - edp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h31012 = 2'd3 - edp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h33404 = 2'd0 - edp_tlpBRAM_readNxtDWAddr[1:0] ; - assign idx__h33872 = 2'd1 - edp_tlpBRAM_readNxtDWAddr[1:0] ; - assign idx__h34245 = 2'd2 - edp_tlpBRAM_readNxtDWAddr[1:0] ; - assign idx__h34618 = 2'd3 - edp_tlpBRAM_readNxtDWAddr[1:0] ; - assign lowAddr__h35546 = - { edp_tlpBRAM_readReq$D_OUT[33:29], lowAddr10__h35545 } ; - assign mesgMeta_opcode__h108747 = + assign idx__h26290 = 2'd0 - edp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h28521 = 2'd1 - edp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h29825 = 2'd2 - edp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h31129 = 2'd3 - edp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h33370 = 2'd0 - edp_tlpBRAM_readNxtDWAddr[1:0] ; + assign idx__h33838 = 2'd1 - edp_tlpBRAM_readNxtDWAddr[1:0] ; + assign idx__h34211 = 2'd2 - edp_tlpBRAM_readNxtDWAddr[1:0] ; + assign idx__h34584 = 2'd3 - edp_tlpBRAM_readNxtDWAddr[1:0] ; + assign lowAddr__h35514 = + { edp_tlpBRAM_readReq$D_OUT[33:29], lowAddr10__h35513 } ; + assign mesgMeta_opcode__h109337 = { 24'h800000, wmi_wmi_mFlagF$D_OUT[31:24] } ; - assign nowLS__h82713 = + assign nowLS__h83083 = { edp_tlpBRAM_mRespF$D_OUT[39:32], edp_tlpBRAM_mRespF$D_OUT[47:40], edp_tlpBRAM_mRespF$D_OUT[55:48], edp_tlpBRAM_mRespF$D_OUT[63:56] } ; - assign nowMS__h81770 = + assign nowMS__h82140 = { edp_tlpBRAM_mRespF$D_OUT[71:64], edp_tlpBRAM_mRespF$D_OUT[79:72], edp_tlpBRAM_mRespF$D_OUT[87:80], edp_tlpBRAM_mRespF$D_OUT[95:88] } ; - assign opcode__h80539 = + assign opcode__h80909 = { edp_tlpBRAM_mRespF$D_OUT[103:96], edp_tlpBRAM_mRespF$D_OUT[111:104], edp_tlpBRAM_mRespF$D_OUT[119:112], edp_tlpBRAM_mRespF$D_OUT[127:120] } ; - assign rdat__h118109 = { 16'd0, bml_lclNumBufs } ; - assign rdat__h118117 = { 16'd0, bml_fabNumBufs } ; - assign rdat__h118125 = { 16'd0, bml_mesgBase } ; - assign rdat__h118133 = { 16'd0, bml_metaBase } ; - assign rdat__h118141 = { 16'd0, bml_mesgSize } ; - assign rdat__h118149 = { 16'd0, bml_metaSize } ; - assign rdat__h118157 = { 16'd0, bml_lclBufsCF } ; - assign rdat__h118178 = + assign rdat__h118973 = { 16'd0, bml_lclNumBufs } ; + assign rdat__h118981 = { 16'd0, bml_fabNumBufs } ; + assign rdat__h118989 = { 16'd0, bml_mesgBase } ; + assign rdat__h118997 = { 16'd0, bml_metaBase } ; + assign rdat__h119005 = { 16'd0, bml_mesgSize } ; + assign rdat__h119013 = { 16'd0, bml_metaSize } ; + assign rdat__h119021 = { 16'd0, bml_lclBufsCF } ; + assign rdat__h119042 = hasDebugLogic ? { bml_lclBufsAR, bml_fabBufsAvail } : 32'd0 ; - assign rdat__h118185 = + assign rdat__h119049 = hasDebugLogic ? { bml_remBuf_value, bml_lclBuf_value } : 32'd0 ; - assign rdat__h118198 = + assign rdat__h119062 = hasDebugLogic ? { bml_lclStarts, bml_lclDones } : 32'd0 ; - assign rdat__h118205 = + assign rdat__h119069 = hasDebugLogic ? { bml_remStarts, bml_remDones } : 32'd0 ; - assign rdat__h118212 = hasDebugLogic ? wmi_thisMesg : 32'd0 ; - assign rdat__h118476 = hasDebugLogic ? wmi_lastMesg : 32'd0 ; - assign rdat__h118526 = + assign rdat__h119076 = hasDebugLogic ? wmi_thisMesg : 32'd0 ; + assign rdat__h119340 = hasDebugLogic ? wmi_lastMesg : 32'd0 ; + assign rdat__h119390 = hasDebugLogic ? { wmi_reqCount, wmi_wrtCount } : 32'd0 ; - assign rdat__h118626 = hasDebugLogic ? 32'hDADEBABE : 32'd0 ; - assign rdat__h118684 = { 24'd0, dpControl } ; - assign rdat__h118706 = hasDebugLogic ? edp_flowDiagCount : 32'd0 ; - assign rdat__h118716 = + assign rdat__h119490 = hasDebugLogic ? 32'hDADEBABE : 32'd0 ; + assign rdat__h119548 = { 24'd0, dpControl } ; + assign rdat__h119570 = hasDebugLogic ? edp_flowDiagCount : 32'd0 ; + assign rdat__h119580 = hasDebugLogic ? { 4'h0, edp_complTimerCount, 12'h0, CASE_edp_lastRuleFired_10_1_edp_lastRuleFired__ETC__q5 } : 32'd0 ; - assign rdat__h118838 = hasDebugLogic ? edp_lastMetaV : 32'd0 ; - assign rdat__h118958 = hasDebugLogic ? edp_lastMetaV_1 : 32'd0 ; - assign rdat__h118987 = hasDebugLogic ? edp_lastMetaV_2 : 32'd0 ; - assign rdat__h119016 = hasDebugLogic ? edp_lastMetaV_3 : 32'd0 ; - assign rdat__h119045 = hasDebugLogic ? 32'hC0DE0111 : 32'd0 ; - assign rdat__h119075 = hasDebugLogic ? dmaStartTime[31:0] : 32'd0 ; - assign rdat__h119109 = hasDebugLogic ? dmaStartTime[63:32] : 32'd0 ; - assign rdat__h119142 = hasDebugLogic ? dmaDoneTime[31:0] : 32'd0 ; - assign rdat__h119176 = hasDebugLogic ? dmaDoneTime[63:32] : 32'd0 ; - assign rdat__h119209 = hasDebugLogic ? edp_dbgBytesTxEnq : 32'd0 ; - assign rdat__h119220 = hasDebugLogic ? edp_dbgBytesTxDeq : 32'd0 ; - assign rdat__h119231 = hasDebugLogic ? edpDebug : 32'd0 ; - assign rdata__h40976 = - edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2699[1] ? + assign rdat__h119702 = hasDebugLogic ? edp_lastMetaV : 32'd0 ; + assign rdat__h119822 = hasDebugLogic ? edp_lastMetaV_1 : 32'd0 ; + assign rdat__h119851 = hasDebugLogic ? edp_lastMetaV_2 : 32'd0 ; + assign rdat__h119880 = hasDebugLogic ? edp_lastMetaV_3 : 32'd0 ; + assign rdat__h119909 = hasDebugLogic ? 32'hC0DE0111 : 32'd0 ; + assign rdat__h119939 = hasDebugLogic ? dmaStartTime[31:0] : 32'd0 ; + assign rdat__h119973 = hasDebugLogic ? dmaStartTime[63:32] : 32'd0 ; + assign rdat__h120006 = hasDebugLogic ? dmaDoneTime[31:0] : 32'd0 ; + assign rdat__h120040 = hasDebugLogic ? dmaDoneTime[63:32] : 32'd0 ; + assign rdat__h120073 = hasDebugLogic ? edp_dbgBytesTxEnq : 32'd0 ; + assign rdat__h120084 = hasDebugLogic ? edp_dbgBytesTxDeq : 32'd0 ; + assign rdat__h120095 = hasDebugLogic ? edpDebug : 32'd0 ; + assign rdata__h40953 = + edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2692[1] ? IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1201 : IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1206 ; - assign rreq_tag__h86003 = - (y__h85835 == edp_mesgLengthRemainPush) ? 8'h01 : 8'h0 ; - assign rresp_data__h35592 = - { IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724[7:0], - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724[15:8], - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724[23:16], - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724[31:24] } ; - assign spanToNextPage__h85809 = 13'd4096 - { 1'd0, edp_srcMesgAccu[11:0] } ; - assign thisRequestLength__h85810 = - (x__h85845[12:0] <= spanToNextPage__h85809) ? - x__h85845[12:0] : - spanToNextPage__h85809 ; + assign rreq_tag__h86377 = + (y__h86209 == edp_mesgLengthRemainPush) ? 8'h01 : 8'h0 ; + assign rresp_data__h35560 = + { IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2720[7:0], + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2720[15:8], + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2720[23:16], + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2720[31:24] } ; + assign spanToNextPage__h86183 = 13'd4096 - { 1'd0, edp_srcMesgAccu[11:0] } ; + assign thisRequestLength__h86184 = + (x__h86219[12:0] <= spanToNextPage__h86183) ? + x__h86219[12:0] : + spanToNextPage__h86183 ; assign wmi_dpControl_whas__947_AND_bram_serverAdapter_ETC___d1993 = (bram_serverAdapterB_outDataCore$EMPTY_N || bram_serverAdapterB_outData_enqData$whas) && @@ -6987,62 +6995,62 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterB_2_cnt_21_SLT_3___d1962 && bram_serverAdapterB_3_cnt_39_SLT_3___d1963 && wmi_wmi_mFlagF$EMPTY_N ; - assign x3__h108707 = { 8'd0, wmi_wmi_mFlagF$D_OUT[23:0] } ; - assign x__h114823 = (dpControl[1:0] == 2'd1) ? bml_fabNumBufs : 16'd0 ; - assign x__h115947 = bml_lclBufsAR + 16'd1 ; - assign x__h115952 = bml_lclBufsAR - 16'd1 ; - assign x__h116059 = bml_lclBufsCF + 16'd1 ; - assign x__h116096 = bml_lclBufsCF - 16'd1 ; - assign x__h116174 = bml_fabBufsAvail + 16'd1 ; - assign x__h116179 = bml_fabBufsAvail - 16'd1 ; - assign x__h116212 = bml_lclCredit + 16'd1 ; - assign x__h116217 = bml_lclCredit - 16'd1 ; - assign x__h20653 = edp_outBF_rRdPtr + 12'd1 ; - assign x__h35665 = x__h35667 - y__h35668 ; - assign x__h35667 = { edp_tlpBRAM_readReq$D_OUT[28:19], 2'b0 } ; - assign x__h78704 = + assign x3__h109297 = { 8'd0, wmi_wmi_mFlagF$D_OUT[23:0] } ; + assign x__h115651 = (dpControl[1:0] == 2'd1) ? bml_fabNumBufs : 16'd0 ; + assign x__h116779 = bml_lclBufsAR + 16'd1 ; + assign x__h116784 = bml_lclBufsAR - 16'd1 ; + assign x__h116891 = bml_lclBufsCF + 16'd1 ; + assign x__h116928 = bml_lclBufsCF - 16'd1 ; + assign x__h117010 = bml_fabBufsAvail + 16'd1 ; + assign x__h117015 = bml_fabBufsAvail - 16'd1 ; + assign x__h117049 = bml_lclCredit + 16'd1 ; + assign x__h117054 = bml_lclCredit - 16'd1 ; + assign x__h20838 = edp_outBF_rRdPtr + 12'd1 ; + assign x__h35633 = x__h35635 - y__h35636 ; + assign x__h35635 = { edp_tlpBRAM_readReq$D_OUT[28:19], 2'b0 } ; + assign x__h79125 = { edp_tlpBRAM_mRespF$D_OUT[7:0], edp_tlpBRAM_mRespF$D_OUT[15:8], edp_tlpBRAM_mRespF$D_OUT[23:16], edp_tlpBRAM_mRespF$D_OUT[31:24] } ; - assign x__h83716 = { 15'd0, edp_mesgLengthRemainPush } ; - assign x__h85845 = - (edp_mesgLengthRemainPush <= y__h85847) ? + assign x__h84086 = { 15'd0, edp_mesgLengthRemainPush } ; + assign x__h86219 = + (edp_mesgLengthRemainPush <= y__h86221) ? edp_mesgLengthRemainPush : - y__h85847 ; - assign x__h96121 = + y__h86221 ; + assign x__h96502 = { edp_inF$D_OUT[39:38] != 2'd0, edp_inF$D_OUT[29:28] != 2'd0, edp_inF$D_OUT[19:18] != 2'd0, edp_inF$D_OUT[9:8] != 2'd0 } ; - assign y__h24387 = edp_tlpBRAM_mReqF$D_OUT[63] ? 13'd0 : 13'd1 ; - assign y__h24458 = edp_tlpBRAM_mReqF$D_OUT[63] ? 10'd0 : 10'd1 ; - assign y__h33109 = edp_tlpBRAM_mReqF$D_OUT[60] ? 10'd0 : 10'd1 ; - assign y__h33157 = edp_tlpBRAM_mReqF$D_OUT[60] ? 13'd0 : 13'd1 ; - assign y__h35666 = + assign y__h24591 = edp_tlpBRAM_mReqF$D_OUT[63] ? 13'd0 : 13'd1 ; + assign y__h24658 = edp_tlpBRAM_mReqF$D_OUT[63] ? 10'd0 : 10'd1 ; + assign y__h33140 = edp_tlpBRAM_mReqF$D_OUT[60] ? 10'd0 : 10'd1 ; + assign y__h33152 = edp_tlpBRAM_mReqF$D_OUT[60] ? 13'd0 : 13'd1 ; + assign y__h35634 = (edp_tlpBRAM_readReq$D_OUT[28:19] == 10'd1) ? 12'd0 : - { 10'd0, x__h35697 } ; - assign y__h35668 = { 10'd0, x__h35674 } ; - assign y__h36607 = edp_tlpBRAM_readReq$D_OUT[60] ? 10'd0 : 10'd1 ; - assign y__h85835 = { 4'd0, thisRequestLength__h85810 } ; - assign y__h85847 = { 4'd0, edp_maxPayloadSize } ; - assign y__h85926 = { 19'd0, thisRequestLength__h85810 } ; - assign y__h86177 = (edp_fabMesgAddrMS == 32'd0) ? 10'd1 : 10'd0 ; - assign y__h86228 = { 20'd0, edp_tlpBRAM_mRespF$D_OUT[71:62], 2'd0 } ; - assign y_avValue__h110302 = + { 10'd0, x__h35665 } ; + assign y__h35636 = { 10'd0, x__h35642 } ; + assign y__h36575 = edp_tlpBRAM_readReq$D_OUT[60] ? 10'd0 : 10'd1 ; + assign y__h86209 = { 4'd0, thisRequestLength__h86184 } ; + assign y__h86221 = { 4'd0, edp_maxPayloadSize } ; + assign y__h86300 = { 19'd0, thisRequestLength__h86184 } ; + assign y__h86555 = (edp_fabMesgAddrMS == 32'd0) ? 10'd1 : 10'd0 ; + assign y__h86614 = { 20'd0, edp_tlpBRAM_mRespF$D_OUT[71:62], 2'd0 } ; + assign y_avValue__h110896 = bram_serverAdapterB_outDataCore$EMPTY_N ? bram_serverAdapterB_outDataCore$D_OUT : bram_memory$DOB ; - assign y_avValue__h110322 = + assign y_avValue__h110916 = bram_serverAdapterB_1_outDataCore$EMPTY_N ? bram_serverAdapterB_1_outDataCore$D_OUT : bram_memory_1$DOB ; - assign y_avValue__h110342 = + assign y_avValue__h110936 = bram_serverAdapterB_2_outDataCore$EMPTY_N ? bram_serverAdapterB_2_outDataCore$D_OUT : bram_memory_2$DOB ; - assign y_avValue__h110362 = + assign y_avValue__h110956 = bram_serverAdapterB_3_outDataCore$EMPTY_N ? bram_serverAdapterB_3_outDataCore$D_OUT : bram_memory_3$DOB ; @@ -7085,19 +7093,19 @@ module mkOCEDP4B(pciDevice, always@(edp_tlpBRAM_readReq$D_OUT) begin case (edp_tlpBRAM_readReq$D_OUT[14:11]) - 4'b1100: x__h35697 = 2'b10; - 4'b1110: x__h35697 = 2'b01; - 4'b1111: x__h35697 = 2'b0; - default: x__h35697 = 2'b11; + 4'b1100: x__h35665 = 2'b10; + 4'b1110: x__h35665 = 2'b01; + 4'b1111: x__h35665 = 2'b0; + default: x__h35665 = 2'b11; endcase end always@(edp_tlpBRAM_readReq$D_OUT) begin case (edp_tlpBRAM_readReq$D_OUT[18:15]) - 4'b1100: x__h35674 = 2'b10; - 4'b1110: x__h35674 = 2'b01; - 4'b1111: x__h35674 = 2'b0; - default: x__h35674 = 2'b11; + 4'b1100: x__h35642 = 2'b10; + 4'b1110: x__h35642 = 2'b01; + 4'b1111: x__h35642 = 2'b0; + default: x__h35642 = 2'b11; endcase end always@(edp_lastRuleFired) @@ -7110,107 +7118,107 @@ module mkOCEDP4B(pciDevice, endcase end always@(wmi_p4B or - y_avValue__h110362 or - y_avValue__h110302 or y_avValue__h110322 or y_avValue__h110342) + y_avValue__h110956 or + y_avValue__h110896 or y_avValue__h110916 or y_avValue__h110936) begin case (wmi_p4B) - 2'd0: rdata__h110466 = y_avValue__h110302; - 2'd1: rdata__h110466 = y_avValue__h110322; - 2'd2: rdata__h110466 = y_avValue__h110342; - 2'd3: rdata__h110466 = y_avValue__h110362; + 2'd0: rdata__h111060 = y_avValue__h110896; + 2'd1: rdata__h111060 = y_avValue__h110916; + 2'd2: rdata__h111060 = y_avValue__h110936; + 2'd3: rdata__h111060 = y_avValue__h110956; endcase end always@(wci_reqF$D_OUT or - rdat__h118109 or - rdat__h118117 or - rdat__h118125 or - rdat__h118133 or - rdat__h118141 or - rdat__h118149 or - rdat__h118157 or - rdat__h118178 or - rdat__h118185 or - rdat__h118198 or - rdat__h118205 or - rdat__h118212 or - rdat__h118476 or - rdat__h118526 or - rdat__h118626 or + rdat__h118973 or + rdat__h118981 or + rdat__h118989 or + rdat__h118997 or + rdat__h119005 or + rdat__h119013 or + rdat__h119021 or + rdat__h119042 or + rdat__h119049 or + rdat__h119062 or + rdat__h119069 or + rdat__h119076 or + rdat__h119340 or + rdat__h119390 or + rdat__h119490 or bml_fabMesgBase or bml_fabMetaBase or bml_fabMesgSize or bml_fabMetaSize or bml_fabFlowBase or bml_fabFlowSize or - rdat__h118684 or - rdat__h118706 or - rdat__h118716 or - rdat__h118838 or - rdat__h118958 or - rdat__h118987 or - rdat__h119016 or - rdat__h119045 or + rdat__h119548 or + rdat__h119570 or + rdat__h119580 or + rdat__h119702 or + rdat__h119822 or + rdat__h119851 or + rdat__h119880 or + rdat__h119909 or bml_fabMesgBaseMS or bml_fabMetaBaseMS or bml_fabFlowBaseMS or - rdat__h119075 or - rdat__h119109 or - rdat__h119142 or - rdat__h119176 or rdat__h119209 or rdat__h119220 or rdat__h119231) + rdat__h119939 or + rdat__h119973 or + rdat__h120006 or + rdat__h120040 or rdat__h120073 or rdat__h120084 or rdat__h120095) begin case (wci_reqF$D_OUT[39:32]) - 8'h0: _theResult____h118030 = rdat__h118109; - 8'h04: _theResult____h118030 = rdat__h118117; - 8'h08: _theResult____h118030 = rdat__h118125; - 8'h0C: _theResult____h118030 = rdat__h118133; - 8'h10: _theResult____h118030 = rdat__h118141; - 8'h14: _theResult____h118030 = rdat__h118149; - 8'h20: _theResult____h118030 = rdat__h118157; - 8'h24: _theResult____h118030 = 32'hF00DFACE; - 8'h28: _theResult____h118030 = rdat__h118178; - 8'h2C: _theResult____h118030 = rdat__h118185; - 8'h30: _theResult____h118030 = rdat__h118198; - 8'h34: _theResult____h118030 = rdat__h118205; - 8'h38: _theResult____h118030 = rdat__h118212; - 8'h3C: _theResult____h118030 = rdat__h118476; - 8'h40: _theResult____h118030 = rdat__h118526; - 8'h44: _theResult____h118030 = 32'd0; - 8'h48: _theResult____h118030 = rdat__h118626; - 8'h4C: _theResult____h118030 = 32'h00008000; - 8'h50: _theResult____h118030 = bml_fabMesgBase; - 8'h54: _theResult____h118030 = bml_fabMetaBase; - 8'h58: _theResult____h118030 = bml_fabMesgSize; - 8'h5C: _theResult____h118030 = bml_fabMetaSize; - 8'h60: _theResult____h118030 = bml_fabFlowBase; - 8'h64: _theResult____h118030 = bml_fabFlowSize; - 8'h68: _theResult____h118030 = rdat__h118684; - 8'h6C: _theResult____h118030 = rdat__h118706; - 8'h70: _theResult____h118030 = rdat__h118716; - 8'h80: _theResult____h118030 = rdat__h118838; - 8'h84: _theResult____h118030 = rdat__h118958; - 8'h88: _theResult____h118030 = rdat__h118987; - 8'h8C: _theResult____h118030 = rdat__h119016; - 8'h90: _theResult____h118030 = rdat__h119045; - 8'h94: _theResult____h118030 = bml_fabMesgBaseMS; - 8'h98: _theResult____h118030 = bml_fabMetaBaseMS; - 8'h9C: _theResult____h118030 = bml_fabFlowBaseMS; - 8'hA0: _theResult____h118030 = rdat__h119075; - 8'hA4: _theResult____h118030 = rdat__h119109; - 8'hA8: _theResult____h118030 = rdat__h119142; - 8'hAC: _theResult____h118030 = rdat__h119176; - 8'hB0: _theResult____h118030 = rdat__h119209; - 8'hB4: _theResult____h118030 = rdat__h119220; - 8'hB8: _theResult____h118030 = rdat__h119231; - default: _theResult____h118030 = 32'd0; + 8'h0: _theResult____h118894 = rdat__h118973; + 8'h04: _theResult____h118894 = rdat__h118981; + 8'h08: _theResult____h118894 = rdat__h118989; + 8'h0C: _theResult____h118894 = rdat__h118997; + 8'h10: _theResult____h118894 = rdat__h119005; + 8'h14: _theResult____h118894 = rdat__h119013; + 8'h20: _theResult____h118894 = rdat__h119021; + 8'h24: _theResult____h118894 = 32'hF00DFACE; + 8'h28: _theResult____h118894 = rdat__h119042; + 8'h2C: _theResult____h118894 = rdat__h119049; + 8'h30: _theResult____h118894 = rdat__h119062; + 8'h34: _theResult____h118894 = rdat__h119069; + 8'h38: _theResult____h118894 = rdat__h119076; + 8'h3C: _theResult____h118894 = rdat__h119340; + 8'h40: _theResult____h118894 = rdat__h119390; + 8'h44: _theResult____h118894 = 32'd0; + 8'h48: _theResult____h118894 = rdat__h119490; + 8'h4C: _theResult____h118894 = 32'h00008000; + 8'h50: _theResult____h118894 = bml_fabMesgBase; + 8'h54: _theResult____h118894 = bml_fabMetaBase; + 8'h58: _theResult____h118894 = bml_fabMesgSize; + 8'h5C: _theResult____h118894 = bml_fabMetaSize; + 8'h60: _theResult____h118894 = bml_fabFlowBase; + 8'h64: _theResult____h118894 = bml_fabFlowSize; + 8'h68: _theResult____h118894 = rdat__h119548; + 8'h6C: _theResult____h118894 = rdat__h119570; + 8'h70: _theResult____h118894 = rdat__h119580; + 8'h80: _theResult____h118894 = rdat__h119702; + 8'h84: _theResult____h118894 = rdat__h119822; + 8'h88: _theResult____h118894 = rdat__h119851; + 8'h8C: _theResult____h118894 = rdat__h119880; + 8'h90: _theResult____h118894 = rdat__h119909; + 8'h94: _theResult____h118894 = bml_fabMesgBaseMS; + 8'h98: _theResult____h118894 = bml_fabMetaBaseMS; + 8'h9C: _theResult____h118894 = bml_fabFlowBaseMS; + 8'hA0: _theResult____h118894 = rdat__h119939; + 8'hA4: _theResult____h118894 = rdat__h119973; + 8'hA8: _theResult____h118894 = rdat__h120006; + 8'hAC: _theResult____h118894 = rdat__h120040; + 8'hB0: _theResult____h118894 = rdat__h120073; + 8'hB4: _theResult____h118894 = rdat__h120084; + 8'hB8: _theResult____h118894 = rdat__h120095; + default: _theResult____h118894 = 32'd0; endcase end always@(edp_tlpBRAM_readReq$D_OUT) begin case (edp_tlpBRAM_readReq$D_OUT[18:15]) - 4'b1000: lowAddr10__h35545 = 2'b11; - 4'b1100: lowAddr10__h35545 = 2'b10; - 4'b1110: lowAddr10__h35545 = 2'b01; - default: lowAddr10__h35545 = 2'b0; + 4'b1000: lowAddr10__h35513 = 2'b11; + 4'b1100: lowAddr10__h35513 = 2'b10; + 4'b1110: lowAddr10__h35513 = 2'b01; + default: lowAddr10__h35513 = 2'b0; endcase end always@(dpControl or bml_fabDone or bml_remDone) @@ -7239,132 +7247,132 @@ module mkOCEDP4B(pciDevice, bml_fabDone; endcase end - always@(idx__h26173 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or + always@(idx__h26290 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694) begin - case (idx__h26173) + case (idx__h26290) 2'd0: IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839 = edp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724; 2'd2: IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694; 2'd3: IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695; endcase end - always@(idx__h28404 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or + always@(idx__h28521 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694) begin - case (idx__h28404) + case (idx__h28521) 2'd0: IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849 = edp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724; 2'd2: IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694; 2'd3: IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695; endcase end - always@(idx__h29708 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or + always@(idx__h29825 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694) begin - case (idx__h29708) + case (idx__h29825) 2'd0: IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859 = edp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724; 2'd2: IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694; 2'd3: IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695; endcase end - always@(idx__h31012 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or + always@(idx__h31129 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694) begin - case (idx__h31012) + case (idx__h31129) 2'd0: IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869 = edp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724; 2'd2: IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694; 2'd3: IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695; endcase end always@(edp_tlpBRAM_mReqF$D_OUT or - bram_serverAdapterA_3_cnt_80_SLT_3___d2977 or - bram_serverAdapterA_cnt_6_SLT_3___d2974 or - bram_serverAdapterA_1_cnt_44_SLT_3___d2975 or - bram_serverAdapterA_2_cnt_62_SLT_3___d2976) + bram_serverAdapterA_3_cnt_80_SLT_3___d2765 or + bram_serverAdapterA_cnt_6_SLT_3___d2772 or + bram_serverAdapterA_1_cnt_44_SLT_3___d2980 or + bram_serverAdapterA_2_cnt_62_SLT_3___d2766) begin case (edp_tlpBRAM_mReqF$D_OUT[51:50]) 2'd0: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q7 = - bram_serverAdapterA_cnt_6_SLT_3___d2974; + bram_serverAdapterA_cnt_6_SLT_3___d2772; 2'd1: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q7 = - bram_serverAdapterA_1_cnt_44_SLT_3___d2975; + bram_serverAdapterA_1_cnt_44_SLT_3___d2980; 2'd2: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q7 = - bram_serverAdapterA_2_cnt_62_SLT_3___d2976; + bram_serverAdapterA_2_cnt_62_SLT_3___d2766; 2'd3: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q7 = edp_tlpBRAM_mReqF$D_OUT[51:50] != 2'd3 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2977; + bram_serverAdapterA_3_cnt_80_SLT_3___d2765; endcase end always@(edp_tlpBRAM_mReqF$D_OUT or - bram_serverAdapterA_3_cnt_80_SLT_3___d2977 or - bram_serverAdapterA_cnt_6_SLT_3___d2974 or - bram_serverAdapterA_1_cnt_44_SLT_3___d2975 or - bram_serverAdapterA_2_cnt_62_SLT_3___d2976) + bram_serverAdapterA_3_cnt_80_SLT_3___d2765 or + bram_serverAdapterA_cnt_6_SLT_3___d2772 or + bram_serverAdapterA_1_cnt_44_SLT_3___d2980 or + bram_serverAdapterA_2_cnt_62_SLT_3___d2766) begin case (edp_tlpBRAM_mReqF$D_OUT[30:29]) 2'd0: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q8 = - bram_serverAdapterA_cnt_6_SLT_3___d2974; + bram_serverAdapterA_cnt_6_SLT_3___d2772; 2'd1: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q8 = - bram_serverAdapterA_1_cnt_44_SLT_3___d2975; + bram_serverAdapterA_1_cnt_44_SLT_3___d2980; 2'd2: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q8 = - bram_serverAdapterA_2_cnt_62_SLT_3___d2976; + bram_serverAdapterA_2_cnt_62_SLT_3___d2766; 2'd3: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q8 = edp_tlpBRAM_mReqF$D_OUT[30:29] != 2'd3 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2977; + bram_serverAdapterA_3_cnt_80_SLT_3___d2765; endcase end always@(wmi_addr or @@ -7375,16 +7383,16 @@ module mkOCEDP4B(pciDevice, begin case (wmi_addr[3:2]) 2'd0: - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 = + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3215 = bram_serverAdapterB_cnt_5_SLT_3___d1960; 2'd1: - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 = + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3215 = bram_serverAdapterB_1_cnt_03_SLT_3___d1961; 2'd2: - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 = + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3215 = bram_serverAdapterB_2_cnt_21_SLT_3___d1962; 2'd3: - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 = + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3215 = wmi_addr[3:2] != 2'd3 || bram_serverAdapterB_3_cnt_39_SLT_3___d1963; endcase @@ -7402,155 +7410,155 @@ module mkOCEDP4B(pciDevice, !bml_fabDone; endcase end - always@(idx__h26173 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or + always@(idx__h26290 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694) begin - case (idx__h26173) + case (idx__h26290) 2'd0: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 = + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2818 = edp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2818 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724; 2'd2: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2818 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694; 2'd3: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2818 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695; endcase end - always@(idx__h28404 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or + always@(idx__h28521 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694) begin - case (idx__h28404) + case (idx__h28521) 2'd0: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 = + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2819 = edp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2819 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724; 2'd2: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2819 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694; 2'd3: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2819 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695; endcase end - always@(idx__h29708 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or + always@(idx__h29825 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694) begin - case (idx__h29708) + case (idx__h29825) 2'd0: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2820 = edp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2820 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724; 2'd2: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2820 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694; 2'd3: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2820 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695; endcase end - always@(idx__h31012 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or + always@(idx__h31129 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694) begin - case (idx__h31012) + case (idx__h31129) 2'd0: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 = + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = edp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2724; 2'd2: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2694; 2'd3: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2695; endcase end - always@(idx__h26173 or edp_tlpBRAM_mReqF$D_OUT) + always@(idx__h26290 or edp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h26173) + case (idx__h26290) 2'd0: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841 = + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2852 = edp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841 = + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2852 = edp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841 = + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2852 = edp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841 = + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2852 = edp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end - always@(idx__h28404 or edp_tlpBRAM_mReqF$D_OUT) + always@(idx__h28521 or edp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h28404) + case (idx__h28521) 2'd0: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842 = + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2853 = edp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842 = + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2853 = edp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842 = + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2853 = edp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842 = + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2853 = edp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end - always@(idx__h29708 or edp_tlpBRAM_mReqF$D_OUT) + always@(idx__h29825 or edp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h29708) + case (idx__h29825) 2'd0: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843 = + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2854 = edp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843 = + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2854 = edp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843 = + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2854 = edp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843 = + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2854 = edp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end - always@(idx__h31012 or edp_tlpBRAM_mReqF$D_OUT) + always@(idx__h31129 or edp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h31012) + case (idx__h31129) 2'd0: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844 = + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2855 = edp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844 = + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2855 = edp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844 = + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2855 = edp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844 = + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2855 = edp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end @@ -7605,16 +7613,16 @@ module mkOCEDP4B(pciDevice, begin case (edp_tlpBRAM_readReq$D_OUT[30:29]) 2'd0: - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724 = + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2720 = bram_serverAdapterA_outData_outData$wget; 2'd1: - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724 = + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2720 = bram_serverAdapterA_1_outData_outData$wget; 2'd2: - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724 = + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2720 = bram_serverAdapterA_2_outData_outData$wget; 2'd3: - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724 = + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2720 = bram_serverAdapterA_3_outData_outData$wget; endcase end @@ -7901,7 +7909,7 @@ module mkOCEDP4B(pciDevice, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin bml_crdBuf_modulus <= `BSV_ASSIGNMENT_DELAY 16'd65535; bml_crdBuf_value <= `BSV_ASSIGNMENT_DELAY 16'd0; @@ -8561,8 +8569,8 @@ module mkOCEDP4B(pciDevice, wmi_wmi_statusR <= `BSV_ASSIGNMENT_DELAY wmi_wmi_statusR$D_IN; end - always@(posedge CLK or negedge RST_N) - if (!RST_N) + always@(posedge CLK or `BSV_RESET_EDGE RST_N) + if (RST_N == `BSV_RESET_VALUE) begin wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wmi_wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -8812,204 +8820,204 @@ module mkOCEDP4B(pciDevice, always@(negedge CLK) begin #0; - if (RST_N) - if (WILL_FIRE_RL_wci_cfrd) - begin - v__h118046 = $time; - #0; - end - if (RST_N) - if (WILL_FIRE_RL_wci_cfrd) - $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h118046, - wci_reqF$D_OUT[63:32], - wci_reqF$D_OUT[67:64], - _theResult____h118030); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (bram_serverAdapterA_s1[1] && !bram_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (bram_serverAdapterB_s1[1] && !bram_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (bram_serverAdapterA_1_s1[1] && !bram_serverAdapterA_1_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (bram_serverAdapterB_1_s1[1] && !bram_serverAdapterB_1_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (bram_serverAdapterA_2_s1[1] && !bram_serverAdapterA_2_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (bram_serverAdapterB_2_s1[1] && !bram_serverAdapterB_2_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (bram_serverAdapterA_3_s1[1] && !bram_serverAdapterA_3_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (bram_serverAdapterB_3_s1[1] && !bram_serverAdapterB_3_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd) + begin + v__h118910 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd) + $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", + v__h118910, + wci_reqF$D_OUT[63:32], + wci_reqF$D_OUT[67:64], + _theResult____h118894); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_start) begin - v__h15543 = $time; + v__h15697 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h15543, + v__h15697, wci_reqF$D_OUT[36:34], wci_cState); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaRequestNearMeta) begin - v__h77289 = $time; + v__h77698 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaRequestNearMeta) $display("[%0d]: %m: dmaRequestNearMeta FPactMesg-Step1/7", - v__h77289); - if (RST_N) + v__h77698); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaPushRequestMesg) begin - v__h86073 = $time; + v__h86447 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaPushRequestMesg) $display("[%0d]: %m: dmaPushRequestMesg FPactMesg-Step3/7", - v__h86073); - if (RST_N) + v__h86447); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaResponseNearMetaHead) begin - v__h79597 = $time; + v__h79991 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaResponseNearMetaHead) $display("[%0d]: %m: dmaResponseNearMetaHead FPactMesg-Step2a/7 mesgLength:%0x", - v__h79597, - x__h78704); - if (RST_N) + v__h79991, + x__h79125); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaPushResponseHeader) begin - v__h86371 = $time; + v__h86738 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaPushResponseHeader) $display("[%0d]: %m: dmaPushResponseHeader FPactMesg-Step4a/7", - v__h86371); - if (RST_N) + v__h86738); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaXmtMetaHead) begin - v__h91851 = $time; + v__h92218 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaXmtMetaHead) - $display("[%0d]: %m: dmaXmtMetaHead FPactMesg-Step5/7", v__h91851); - if (RST_N) + $display("[%0d]: %m: dmaXmtMetaHead FPactMesg-Step5/7", v__h92218); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaPushResponseBody) begin - v__h91705 = $time; + v__h92069 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaPushResponseBody) $display("[%0d]: %m: dmaPushResponseBody FPactMesg-Step4b/7", - v__h91705); - if (RST_N) + v__h92069); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaXmtDoorbell) begin - v__h94025 = $time; + v__h94403 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaXmtDoorbell) - $display("[%0d]: %m: dmaXmtDoorbell FC/FPactFlow-Step1/1", v__h94025); - if (RST_N) + $display("[%0d]: %m: dmaXmtDoorbell FC/FPactFlow-Step1/1", v__h94403); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaXmtTailEvent) begin - v__h92126 = $time; + v__h92500 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaXmtTailEvent) - $display("[%0d]: %m: dmaXmtTailEvent FPactMesg-Step7/7", v__h92126); - if (RST_N) + $display("[%0d]: %m: dmaXmtTailEvent FPactMesg-Step7/7", v__h92500); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaXmtMetaBody) begin - v__h91994 = $time; + v__h92365 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaXmtMetaBody) - $display("[%0d]: %m: dmaXmtMetaBody FPactMesg-Step6/7", v__h91994); - if (RST_N) + $display("[%0d]: %m: dmaXmtMetaBody FPactMesg-Step6/7", v__h92365); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaResponseNearMetaBody) begin - v__h83920 = $time; + v__h84290 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaResponseNearMetaBody) $display("[%0d]: %m: dmaResponseNearMetaBody FPactMesg-Step2b/7 opcode:%0x nowMS:%0x nowLS:%0x", - v__h83920, - opcode__h80539, - nowMS__h81770, - nowLS__h82713); - if (RST_N) + v__h84290, + opcode__h80909, + nowMS__h82140, + nowLS__h83083); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaTailEventSender) begin - v__h94787 = $time; + v__h95165 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_dmaTailEventSender) - $display("[%0d]: %m: dmaTailEventSender - generic", v__h94787); - if (RST_N) + $display("[%0d]: %m: dmaTailEventSender - generic", v__h95165); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_fhFsm_action_l162c11 && WILL_FIRE_RL_edp_fhFsm_action_l163c11) $display("Error: \"bsv/inf/EDPServBC.bsv\", line 162, column 11: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edp_fhFsm_action_l162c11] and\n [RL_edp_fhFsm_action_l163c11] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_fhFsm_action_l161c11 && (WILL_FIRE_RL_edp_fhFsm_action_l162c11 || WILL_FIRE_RL_edp_fhFsm_action_l163c11)) $display("Error: \"bsv/inf/EDPServBC.bsv\", line 161, column 11: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edp_fhFsm_action_l161c11] and\n [RL_edp_fhFsm_action_l162c11, RL_edp_fhFsm_action_l163c11] ) fired in the\n same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_mhFsm_action_l170c11 && (WILL_FIRE_RL_edp_mhFsm_action_l171c11 || WILL_FIRE_RL_edp_mhFsm_action_l172c11 || WILL_FIRE_RL_edp_mhFsm_action_l173c11 || WILL_FIRE_RL_edp_mhFsm_action_l174c11)) $display("Error: \"bsv/inf/EDPServBC.bsv\", line 170, column 11: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edp_mhFsm_action_l170c11] and\n [RL_edp_mhFsm_action_l171c11, RL_edp_mhFsm_action_l172c11,\n RL_edp_mhFsm_action_l173c11, RL_edp_mhFsm_action_l174c11] ) fired in the\n same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_mhFsm_action_l171c11 && (WILL_FIRE_RL_edp_mhFsm_action_l172c11 || WILL_FIRE_RL_edp_mhFsm_action_l173c11 || WILL_FIRE_RL_edp_mhFsm_action_l174c11)) $display("Error: \"bsv/inf/EDPServBC.bsv\", line 171, column 11: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edp_mhFsm_action_l171c11] and\n [RL_edp_mhFsm_action_l172c11, RL_edp_mhFsm_action_l173c11,\n RL_edp_mhFsm_action_l174c11] ) fired in the same clock cycle.\n"); - if (RST_N) - if (WILL_FIRE_RL_edp_mhFsm_action_l173c11 && - WILL_FIRE_RL_edp_mhFsm_action_l174c11) - $display("Error: \"bsv/inf/EDPServBC.bsv\", line 173, column 11: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edp_mhFsm_action_l173c11] and\n [RL_edp_mhFsm_action_l174c11] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_mhFsm_action_l172c11 && (WILL_FIRE_RL_edp_mhFsm_action_l173c11 || WILL_FIRE_RL_edp_mhFsm_action_l174c11)) $display("Error: \"bsv/inf/EDPServBC.bsv\", line 172, column 11: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edp_mhFsm_action_l172c11] and\n [RL_edp_mhFsm_action_l173c11, RL_edp_mhFsm_action_l174c11] ) fired in the\n same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_edp_mhFsm_action_l173c11 && + WILL_FIRE_RL_edp_mhFsm_action_l174c11) + $display("Error: \"bsv/inf/EDPServBC.bsv\", line 173, column 11: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edp_mhFsm_action_l173c11] and\n [RL_edp_mhFsm_action_l174c11] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edp_mhFsm_action_l169c11 && (WILL_FIRE_RL_edp_mhFsm_action_l170c11 || WILL_FIRE_RL_edp_mhFsm_action_l171c11 || @@ -9017,59 +9025,59 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_edp_mhFsm_action_l173c11 || WILL_FIRE_RL_edp_mhFsm_action_l174c11)) $display("Error: \"bsv/inf/EDPServBC.bsv\", line 169, column 11: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edp_mhFsm_action_l169c11] and\n [RL_edp_mhFsm_action_l170c11, RL_edp_mhFsm_action_l171c11,\n RL_edp_mhFsm_action_l172c11, RL_edp_mhFsm_action_l173c11,\n RL_edp_mhFsm_action_l174c11] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmi_doWriteFinalize) begin - v__h109349 = $time; + v__h109939 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmi_doWriteFinalize) $display("[%0d]: %m: doWriteFinalize lclMetaAddr :%0x length:%0x opcode:%0x nowMS:%0x nowLS:%0x ", - v__h109349, + v__h109939, wmi_lclMetaAddr, - x3__h108707, - mesgMeta_opcode__h108747, + x3__h109297, + mesgMeta_opcode__h109337, dmaStartTime$D_IN[63:32], dmaStartTime$D_IN[31:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h117892 = $time; + v__h118754 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h117892, + v__h118754, wci_reqF$D_OUT[63:32], wci_reqF$D_OUT[67:64], wci_reqF$D_OUT[31:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/inf/OCEDP.bsv\", line 76, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) begin - v__h15861 = $time; + v__h16016 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h15861, + v__h16016, wci_cEdge, wci_cState); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) begin - v__h15717 = $time; + v__h15872 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h15717, + v__h15872, wci_cEdge, wci_cState, wci_nState); diff --git a/rtl/mkPWrk_n210.v b/rtl/mkPWrk_n210.v index a3a2c010..2bee9688 100644 --- a/rtl/mkPWrk_n210.v +++ b/rtl/mkPWrk_n210.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:16 EDT 2012 +// On Mon Sep 24 15:03:28 EDT 2012 // // // Ports: @@ -34,7 +34,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkPWrk_n210(RST_N_sys0_rst, @@ -459,41 +467,41 @@ module mkPWrk_n210(RST_N_sys0_rst, MUX_wci_wslv_respF_x_wire$wset_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h19642, v__h19816, v__h19960, v__h24205; + reg [63 : 0] v__h19784, v__h19959, v__h20103, v__h24410; reg [31 : 0] CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1; wire [116 : 0] _130549178157447095380771276656813203__q6, _166153498389916941667817601160445959__q4, _306783360__q2, - wRdData__h1432; + wRdData__h1488; wire [86 : 0] _121583396715528419856163987__q5, _154742503901866210315206599__q3, - wWrData__h1436; - wire [31 : 0] flashStatus__h23194, g_data__h24068; - wire [7 : 0] x__h21741; - wire [2 : 0] a0__h1421, - a1__h1420, - a2__h1419, - a3__h1418, - a4__h1417, - a5__h1416, - a6__h1415, - a7__h1414, - d0__h1430, - d1__h1429, - d2__h1428, - d3__h1427, - d4__h1426, - d5__h1425, - d6__h1424, - d7__h1423, - s0__h1412, - s1__h1411, - s2__h1410, - s3__h1409, - s4__h1408, - s5__h1407, - s6__h1406; - wire _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397, + wWrData__h1492; + wire [31 : 0] flashStatus__h23386, g_data__h24270; + wire [7 : 0] x__h21933; + wire [2 : 0] a0__h1477, + a1__h1476, + a2__h1475, + a3__h1474, + a4__h1473, + a5__h1472, + a6__h1471, + a7__h1470, + d0__h1486, + d1__h1485, + d2__h1484, + d3__h1483, + d4__h1482, + d5__h1481, + d6__h1480, + d7__h1479, + s0__h1468, + s1__h1467, + s2__h1466, + s3__h1465, + s4__h1464, + s5__h1463, + s6__h1462; + wire _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d393, wci_wslv_reqF_i_notEmpty__69_AND_IF_wci_wslv_r_ETC___d350, wci_wslv_reqF_i_notEmpty__69_AND_wci_wslv_reqF_ETC___d329; @@ -524,7 +532,7 @@ module mkPWrk_n210(RST_N_sys0_rst, assign spipad_csn = !flashC_csReg ; // submodule flashC_reqF - FIFO2 #(.width(32'd53), .guarded(32'd1)) flashC_reqF(.RST_N(wciS0_MReset_n), + FIFO2 #(.width(32'd53), .guarded(32'd1)) flashC_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(flashC_reqF$D_IN), .ENQ(flashC_reqF$ENQ), @@ -535,22 +543,21 @@ module mkPWrk_n210(RST_N_sys0_rst, .EMPTY_N()); // submodule flashC_respF - FIFO2 #(.width(32'd32), - .guarded(32'd1)) flashC_respF(.RST_N(wciS0_MReset_n), - .CLK(wciS0_Clk), - .D_IN(flashC_respF$D_IN), - .ENQ(flashC_respF$ENQ), - .DEQ(flashC_respF$DEQ), - .CLR(flashC_respF$CLR), - .D_OUT(flashC_respF$D_OUT), - .FULL_N(), - .EMPTY_N(flashC_respF$EMPTY_N)); + FIFO2 #(.width(32'd32), .guarded(32'd1)) flashC_respF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(flashC_respF$D_IN), + .ENQ(flashC_respF$ENQ), + .DEQ(flashC_respF$DEQ), + .CLR(flashC_respF$CLR), + .D_OUT(flashC_respF$D_OUT), + .FULL_N(), + .EMPTY_N(flashC_respF$EMPTY_N)); // submodule i2cC_fRequest SizedFIFO #(.p1width(32'd24), .p2depth(32'd16), .p3cntr_width(32'd4), - .guarded(32'd1)) i2cC_fRequest(.RST_N(RST_N_sys0_rst), + .guarded(32'd1)) i2cC_fRequest(.RST(RST_N_sys0_rst), .CLK(wciS0_Clk), .D_IN(i2cC_fRequest$D_IN), .ENQ(i2cC_fRequest$ENQ), @@ -564,7 +571,7 @@ module mkPWrk_n210(RST_N_sys0_rst, SizedFIFO #(.p1width(32'd8), .p2depth(32'd16), .p3cntr_width(32'd4), - .guarded(32'd1)) i2cC_fResponse(.RST_N(RST_N_sys0_rst), + .guarded(32'd1)) i2cC_fResponse(.RST(RST_N_sys0_rst), .CLK(wciS0_Clk), .D_IN(i2cC_fResponse$D_IN), .ENQ(i2cC_fResponse$ENQ), @@ -576,7 +583,7 @@ module mkPWrk_n210(RST_N_sys0_rst, // submodule i2cC_rPlayIndex Counter #(.width(32'd10), .init(10'd0)) i2cC_rPlayIndex(.CLK(wciS0_Clk), - .RST_N(RST_N_sys0_rst), + .RST(RST_N_sys0_rst), .DATA_A(i2cC_rPlayIndex$DATA_A), .DATA_B(i2cC_rPlayIndex$DATA_B), .DATA_C(i2cC_rPlayIndex$DATA_C), @@ -589,7 +596,7 @@ module mkPWrk_n210(RST_N_sys0_rst, // submodule i2cC_rPrescaler Counter #(.width(32'd32), .init(32'd416)) i2cC_rPrescaler(.CLK(wciS0_Clk), - .RST_N(RST_N_sys0_rst), + .RST(RST_N_sys0_rst), .DATA_A(i2cC_rPrescaler$DATA_A), .DATA_B(i2cC_rPrescaler$DATA_B), .DATA_C(i2cC_rPrescaler$DATA_C), @@ -616,7 +623,7 @@ module mkPWrk_n210(RST_N_sys0_rst, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -772,9 +779,9 @@ module mkPWrk_n210(RST_N_sys0_rst, assign MUX_i2cC_rSCL$write_1__VAL_2 = _130549178157447095380771276656813203__q6[i2cC_rPlayIndex$Q_OUT[6:0]] ; assign MUX_i2cC_rSDA$write_1__VAL_1 = - wRdData__h1432[i2cC_rPlayIndex$Q_OUT[6:0]] ; + wRdData__h1488[i2cC_rPlayIndex$Q_OUT[6:0]] ; assign MUX_i2cC_rSDA$write_1__VAL_2 = - wWrData__h1436[i2cC_rPlayIndex$Q_OUT[6:0]] ; + wWrData__h1492[i2cC_rPlayIndex$Q_OUT[6:0]] ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && @@ -814,7 +821,7 @@ module mkPWrk_n210(RST_N_sys0_rst, 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, flashC_respF$D_OUT } ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24068 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24270 } ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; @@ -971,49 +978,49 @@ module mkPWrk_n210(RST_N_sys0_rst, assign i2cC_vrReadData$D_IN = i2cC_tSDA$O ; assign i2cC_vrReadData$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d393 ; // register i2cC_vrReadData_1 assign i2cC_vrReadData_1$D_IN = i2cC_vrReadData ; assign i2cC_vrReadData_1$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d393 ; // register i2cC_vrReadData_2 assign i2cC_vrReadData_2$D_IN = i2cC_vrReadData_1 ; assign i2cC_vrReadData_2$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d393 ; // register i2cC_vrReadData_3 assign i2cC_vrReadData_3$D_IN = i2cC_vrReadData_2 ; assign i2cC_vrReadData_3$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d393 ; // register i2cC_vrReadData_4 assign i2cC_vrReadData_4$D_IN = i2cC_vrReadData_3 ; assign i2cC_vrReadData_4$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d393 ; // register i2cC_vrReadData_5 assign i2cC_vrReadData_5$D_IN = i2cC_vrReadData_4 ; assign i2cC_vrReadData_5$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d393 ; // register i2cC_vrReadData_6 assign i2cC_vrReadData_6$D_IN = i2cC_vrReadData_5 ; assign i2cC_vrReadData_6$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d393 ; // register i2cC_vrReadData_7 assign i2cC_vrReadData_7$D_IN = i2cC_vrReadData_6 ; assign i2cC_vrReadData_7$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d393 ; // register macV assign macV$D_IN = { macV[39:0], i2cC_fResponse$D_OUT } ; @@ -1184,7 +1191,7 @@ module mkPWrk_n210(RST_N_sys0_rst, assign flashC_respF$CLR = 1'b0 ; // submodule i2cC_fRequest - assign i2cC_fRequest$D_IN = { 8'd80, x__h21741, 8'd0 } ; + assign i2cC_fRequest$D_IN = { 8'd80, x__h21933, 8'd0 } ; assign i2cC_fRequest$ENQ = i2cC_fRequest$FULL_N && doGetMAC != 8'd0 ; assign i2cC_fRequest$DEQ = MUX_i2cC_rState$write_1__SEL_2 ; assign i2cC_fRequest$CLR = 1'b0 ; @@ -1238,91 +1245,91 @@ module mkPWrk_n210(RST_N_sys0_rst, assign _154742503901866210315206599__q3 = 87'h7FFFFFF1FFFFFE3FFFFFC7 ; assign _166153498389916941667817601160445959__q4 = 117'h1FFFFFFC7FFFFF8FFFFFFE00000007 ; - assign _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 = + assign _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d393 = _306783360__q2[i2cC_rPlayIndex$Q_OUT[6:0]] ; assign _306783360__q2 = 117'd306783360 ; - assign a0__h1421 = {3{i2cC_rAddress[0]}} ; - assign a1__h1420 = {3{i2cC_rAddress[1]}} ; - assign a2__h1419 = {3{i2cC_rAddress[2]}} ; - assign a3__h1418 = {3{i2cC_rAddress[3]}} ; - assign a4__h1417 = {3{i2cC_rAddress[4]}} ; - assign a5__h1416 = {3{i2cC_rAddress[5]}} ; - assign a6__h1415 = {3{i2cC_rAddress[6]}} ; - assign a7__h1414 = {3{i2cC_rAddress[7]}} ; - assign d0__h1430 = {3{i2cC_rWriteData[0]}} ; - assign d1__h1429 = {3{i2cC_rWriteData[1]}} ; - assign d2__h1428 = {3{i2cC_rWriteData[2]}} ; - assign d3__h1427 = {3{i2cC_rWriteData[3]}} ; - assign d4__h1426 = {3{i2cC_rWriteData[4]}} ; - assign d5__h1425 = {3{i2cC_rWriteData[5]}} ; - assign d6__h1424 = {3{i2cC_rWriteData[6]}} ; - assign d7__h1423 = {3{i2cC_rWriteData[7]}} ; - assign flashStatus__h23194 = { 31'd1, flashC_waitReg } ; - assign g_data__h24068 = + assign a0__h1477 = {3{i2cC_rAddress[0]}} ; + assign a1__h1476 = {3{i2cC_rAddress[1]}} ; + assign a2__h1475 = {3{i2cC_rAddress[2]}} ; + assign a3__h1474 = {3{i2cC_rAddress[3]}} ; + assign a4__h1473 = {3{i2cC_rAddress[4]}} ; + assign a5__h1472 = {3{i2cC_rAddress[5]}} ; + assign a6__h1471 = {3{i2cC_rAddress[6]}} ; + assign a7__h1470 = {3{i2cC_rAddress[7]}} ; + assign d0__h1486 = {3{i2cC_rWriteData[0]}} ; + assign d1__h1485 = {3{i2cC_rWriteData[1]}} ; + assign d2__h1484 = {3{i2cC_rWriteData[2]}} ; + assign d3__h1483 = {3{i2cC_rWriteData[3]}} ; + assign d4__h1482 = {3{i2cC_rWriteData[4]}} ; + assign d5__h1481 = {3{i2cC_rWriteData[5]}} ; + assign d6__h1480 = {3{i2cC_rWriteData[6]}} ; + assign d7__h1479 = {3{i2cC_rWriteData[7]}} ; + assign flashStatus__h23386 = { 31'd1, flashC_waitReg } ; + assign g_data__h24270 = wci_wslv_reqF$D_OUT[51] ? 32'd0 : CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 ; - assign s0__h1412 = {3{i2cC_rSlaveAddr[0]}} ; - assign s1__h1411 = {3{i2cC_rSlaveAddr[1]}} ; - assign s2__h1410 = {3{i2cC_rSlaveAddr[2]}} ; - assign s3__h1409 = {3{i2cC_rSlaveAddr[3]}} ; - assign s4__h1408 = {3{i2cC_rSlaveAddr[4]}} ; - assign s5__h1407 = {3{i2cC_rSlaveAddr[5]}} ; - assign s6__h1406 = {3{i2cC_rSlaveAddr[6]}} ; - assign wRdData__h1432 = + assign s0__h1468 = {3{i2cC_rSlaveAddr[0]}} ; + assign s1__h1467 = {3{i2cC_rSlaveAddr[1]}} ; + assign s2__h1466 = {3{i2cC_rSlaveAddr[2]}} ; + assign s3__h1465 = {3{i2cC_rSlaveAddr[3]}} ; + assign s4__h1464 = {3{i2cC_rSlaveAddr[4]}} ; + assign s5__h1463 = {3{i2cC_rSlaveAddr[5]}} ; + assign s6__h1462 = {3{i2cC_rSlaveAddr[6]}} ; + assign wRdData__h1488 = { 3'b100, - s6__h1406, - s5__h1407, - s4__h1408, - s3__h1409, - s2__h1410, - s1__h1411, - s0__h1412, + s6__h1462, + s5__h1463, + s4__h1464, + s3__h1465, + s2__h1466, + s1__h1467, + s0__h1468, 6'd0, - a7__h1414, - a6__h1415, - a5__h1416, - a4__h1417, - a3__h1418, - a2__h1419, - a1__h1420, - a0__h1421, + a7__h1470, + a6__h1471, + a5__h1472, + a4__h1473, + a3__h1474, + a2__h1475, + a1__h1476, + a0__h1477, 6'd6, - s6__h1406, - s5__h1407, - s4__h1408, - s3__h1409, - s2__h1410, - s1__h1411, - s0__h1412, + s6__h1462, + s5__h1463, + s4__h1464, + s3__h1465, + s2__h1466, + s1__h1467, + s0__h1468, 36'hE00000001 } ; - assign wWrData__h1436 = + assign wWrData__h1492 = { 3'b100, - s6__h1406, - s5__h1407, - s4__h1408, - s3__h1409, - s2__h1410, - s1__h1411, - s0__h1412, + s6__h1462, + s5__h1463, + s4__h1464, + s3__h1465, + s2__h1466, + s1__h1467, + s0__h1468, 6'd0, - a7__h1414, - a6__h1415, - a5__h1416, - a4__h1417, - a3__h1418, - a2__h1419, - a1__h1420, - a0__h1421, + a7__h1470, + a6__h1471, + a5__h1472, + a4__h1473, + a3__h1474, + a2__h1475, + a1__h1476, + a0__h1477, 3'b0, - d7__h1423, - d6__h1424, - d5__h1425, - d4__h1426, - d3__h1427, - d2__h1428, - d1__h1429, - d0__h1430, + d7__h1479, + d6__h1480, + d5__h1481, + d4__h1482, + d3__h1483, + d2__h1484, + d1__h1485, + d0__h1486, 6'd1 } ; assign wci_wslv_reqF_i_notEmpty__69_AND_IF_wci_wslv_r_ETC___d350 = wci_wslv_reqF$EMPTY_N && @@ -1334,14 +1341,14 @@ module mkPWrk_n210(RST_N_sys0_rst, ((wci_wslv_reqF$D_OUT[39:32] == 8'h14) ? flashC_reqF$FULL_N : wci_wslv_reqF$D_OUT[39:32] != 8'h18 || flashC_reqF$FULL_N) ; - assign x__h21741 = 8'd8 - doGetMAC ; + assign x__h21933 = 8'd8 - doGetMAC ; always@(wci_wslv_reqF$D_OUT or - flashStatus__h23194 or flashCtrl or aReg or wdReg or rdReg) + flashStatus__h23386 or flashCtrl or aReg or wdReg or rdReg) begin case (wci_wslv_reqF$D_OUT[39:32]) 8'h0: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 = - flashStatus__h23194; + flashStatus__h23386; 8'h04: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 = flashCtrl; 8'h08: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 = aReg; @@ -1355,7 +1362,7 @@ module mkPWrk_n210(RST_N_sys0_rst, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin aReg <= `BSV_ASSIGNMENT_DELAY 32'd0; flashC_clkReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1424,7 +1431,7 @@ module mkPWrk_n210(RST_N_sys0_rst, wci_wslv_sThreadBusy_d$D_IN; if (wdReg$EN) wdReg <= `BSV_ASSIGNMENT_DELAY wdReg$D_IN; end - if (!RST_N_sys0_rst) + if (RST_N_sys0_rst == `BSV_RESET_VALUE) begin doGetMAC <= `BSV_ASSIGNMENT_DELAY 8'd6; i2cC_rOutEn <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -1470,8 +1477,8 @@ module mkPWrk_n210(RST_N_sys0_rst, if (macV$EN) macV <= `BSV_ASSIGNMENT_DELAY macV$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; end @@ -1538,96 +1545,96 @@ module mkPWrk_n210(RST_N_sys0_rst, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h19642 = $time; + v__h19784 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h19642, + v__h19784, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h24205 = $time; + v__h24410 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting flashWorker flashCtrl:%0x", - v__h24205, + v__h24410, flashCtrl); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_advance_response) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_advance_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_advance_response) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_advance_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_advance_response) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_advance_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_advance_response) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_advance_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_advance_response) $display("Error: \"bsv/pwk/PWrk_n210.bsv\", line 60, column 76: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_OrE] and\n [RL_advance_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h19960 = $time; + v__h20103 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h19960, + v__h20103, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h19816 = $time; + v__h19959 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h19816, + v__h19959, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkPktFork.v b/rtl/mkPktFork.v index aed5fa37..0f35e19e 100644 --- a/rtl/mkPktFork.v +++ b/rtl/mkPktFork.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:39:04 EDT 2012 +// On Mon Sep 24 15:04:25 EDT 2012 // // // Ports: @@ -25,7 +25,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkPktFork(pfk, @@ -95,12 +103,12 @@ module mkPktFork(pfk, wire MUX_f0Active$write_1__SEL_1, MUX_f1Active$write_1__SEL_1; // remaining internal signals - reg IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62; - wire [6 : 0] y__h611, y__h836; + reg IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69; + wire [6 : 0] y__h617, y__h842; wire IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33, IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42, fi_RDY_first_AND_IF_IF_pfk_BITS_13_TO_12_5_EQ__ETC___d47, - fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d67; + fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66; // action method iport_put assign RDY_iport_put = fi$FULL_N ; @@ -164,17 +172,17 @@ module mkPktFork(pfk, // inputs to muxes for submodule ports assign MUX_f0Active$write_1__SEL_1 = WILL_FIRE_RL_select && - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 ; + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ; assign MUX_f1Active$write_1__SEL_1 = WILL_FIRE_RL_select && - !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 ; + !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ; // register f0Active assign f0Active$D_IN = MUX_f0Active$write_1__SEL_1 ? !fi$D_OUT[151] : !fi$D_OUT[151] ; assign f0Active$EN = WILL_FIRE_RL_select && - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 || + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 || WILL_FIRE_RL_fo0_advance ; // register f1Active @@ -182,7 +190,7 @@ module mkPktFork(pfk, MUX_f1Active$write_1__SEL_1 ? !fi$D_OUT[151] : !fi$D_OUT[151] ; assign f1Active$EN = WILL_FIRE_RL_select && - !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 || + !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 || WILL_FIRE_RL_fo1_advance ; // submodule fi @@ -199,7 +207,7 @@ module mkPktFork(pfk, assign fo0$DEQ = EN_oport0_get ; assign fo0$ENQ = WILL_FIRE_RL_select && - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 || + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 || WILL_FIRE_RL_fo0_advance ; // submodule fo1 @@ -208,47 +216,47 @@ module mkPktFork(pfk, assign fo1$DEQ = EN_oport1_get ; assign fo1$ENQ = WILL_FIRE_RL_select && - !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 || + !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 || WILL_FIRE_RL_fo1_advance ; // remaining internal signals assign IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33 = (fi$D_OUT[124:120] == 5'b01010) ? fi$D_OUT[50:48] == pfk[2:0] : - fi$D_OUT[150:144] == y__h836 && pfk[3] == fi$D_OUT[47] ; + fi$D_OUT[150:144] == y__h842 && pfk[3] == fi$D_OUT[47] ; assign IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42 = (fi$D_OUT[124:120] == 5'b01010) ? - fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d67 : + fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 : pfk[11:8] == fi$D_OUT[60:57] ; assign fi_RDY_first_AND_IF_IF_pfk_BITS_13_TO_12_5_EQ__ETC___d47 = fi$EMPTY_N && - (IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 ? + (IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ? fo0$FULL_N : fo1$FULL_N) ; - assign fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d67 = + assign fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 = fi$D_OUT[63:56] == pfk[7:0] ; - assign y__h611 = 7'd1 << pfk[2:0] ; - assign y__h836 = 7'd1 << pfk[6:4] ; + assign y__h617 = 7'd1 << pfk[2:0] ; + assign y__h842 = 7'd1 << pfk[6:4] ; always@(pfk or IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42 or fi$D_OUT or - y__h611 or - fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d67 or + y__h617 or + fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 or IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33) begin case (pfk[13:12]) 2'd0: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 = - fi$D_OUT[150:144] == y__h611; + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 = + fi$D_OUT[150:144] == y__h617; 2'd1: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 = - fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d67 && + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 = + fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 && fi$D_OUT[124:120] == 5'b01010; 2'd2: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 = + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 = IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33; 2'd3: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 = + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 = IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42; endcase end @@ -257,7 +265,7 @@ module mkPktFork(pfk, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin f0Active <= `BSV_ASSIGNMENT_DELAY 1'd0; f1Active <= `BSV_ASSIGNMENT_DELAY 1'd0; diff --git a/rtl/mkPktMerge.v b/rtl/mkPktMerge.v index 199f27e9..d3082585 100644 --- a/rtl/mkPktMerge.v +++ b/rtl/mkPktMerge.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:39:04 EDT 2012 +// On Mon Sep 24 15:04:24 EDT 2012 // // // Ports: @@ -24,7 +24,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkPktMerge(CLK, @@ -101,7 +109,7 @@ module mkPktMerge(CLK, MUX_fi1Active$write_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h888; + reg [63 : 0] v__h900; wire fo_RDY_enq_AND_IF_fi0HasPrio_2_THEN_fi0_RDY_de_ETC___d24; // action method iport0_put @@ -147,14 +155,6 @@ module mkPktMerge(CLK, .EMPTY_N(fo$EMPTY_N), .FULL_N(fo$FULL_N)); - // rule RL_arbitrate - assign WILL_FIRE_RL_arbitrate = - fo_RDY_enq_AND_IF_fi0HasPrio_2_THEN_fi0_RDY_de_ETC___d24 && - fi0$EMPTY_N && - fi1$EMPTY_N && - !fi0Active && - !fi1Active ; - // rule RL_fi0_advance assign WILL_FIRE_RL_fi0_advance = fo$FULL_N && fi0$EMPTY_N && !fi1Active && @@ -166,6 +166,14 @@ module mkPktMerge(CLK, !WILL_FIRE_RL_fi0_advance && !WILL_FIRE_RL_arbitrate ; + // rule RL_arbitrate + assign WILL_FIRE_RL_arbitrate = + fo_RDY_enq_AND_IF_fi0HasPrio_2_THEN_fi0_RDY_de_ETC___d24 && + fi0$EMPTY_N && + fi1$EMPTY_N && + !fi0Active && + !fi1Active ; + // inputs to muxes for submodule ports assign MUX_fi0Active$write_1__SEL_1 = WILL_FIRE_RL_arbitrate && fi0HasPrio ; assign MUX_fi1Active$write_1__SEL_1 = @@ -251,7 +259,7 @@ module mkPktMerge(CLK, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin fi0Active <= `BSV_ASSIGNMENT_DELAY 1'd0; fi0HasPrio <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -284,16 +292,16 @@ module mkPktMerge(CLK, always@(negedge CLK) begin #0; - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate) begin - v__h888 = $time; + v__h900 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_arbitrate) $display("[%0d]: %m: Merge from:%d Data:%x", - v__h888, + v__h900, fi0HasPrio, fi0HasPrio ? fi0$D_OUT[127:0] : fi1$D_OUT[127:0]); end diff --git a/rtl/mkQABSMF.v b/rtl/mkQABSMF.v index 71595a7a..6719494d 100644 --- a/rtl/mkQABSMF.v +++ b/rtl/mkQABSMF.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:37:52 EDT 2012 +// On Mon Sep 24 15:02:59 EDT 2012 // // // Ports: @@ -34,7 +34,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkQABSMF(et0, @@ -209,10 +217,10 @@ module mkQABSMF(et0, MUX_merge_fi1Active$write_1__VAL_2; // remaining internal signals - reg [7 : 0] IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728; + reg [7 : 0] IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d738, + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d737, + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d736, + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d739; reg [1 : 0] CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q51, CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q50, CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q49, @@ -257,52 +265,54 @@ module mkQABSMF(et0, CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q46, CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q45, CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q48; - reg CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q13, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q14, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q15, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q16, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q17, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q18, + reg CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q16, + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q17, + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q18, + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q13, + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q14, + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q15, CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q22, CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q23, CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q24, CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q19, CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q20, CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q21; - wire [39 : 0] IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d729; - wire [19 : 0] IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d136; - wire [15 : 0] seen__h10467; - wire [9 : 0] IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d395, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d396, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d397, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d371, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d372, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d373, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d348, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d349, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d350, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d418, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d419, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d420, - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d124, - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d134, + wire [39 : 0] IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d740; + wire [19 : 0] IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d147; + wire [15 : 0] seen__h10505; + wire [9 : 0] IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d406, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d407, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d408, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d382, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d383, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d384, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d359, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d360, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d361, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d429, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d430, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d431, + IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d135, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d145, - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d155; - wire [7 : 0] IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d721, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d722, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d723, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d724; - wire [2 : 0] frk_ptr_08_PLUS_1___d783; - wire [1 : 0] IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d122, - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d132, + IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d156, + IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d166; + wire [7 : 0] IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d732, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d733, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d734, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d735; + wire [2 : 0] frk_ptr_19_PLUS_1___d795; + wire [1 : 0] IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d133, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143, - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d153; - wire IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d898, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d899, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d900, - NOT_frk_stageSent_16_17_OR_frk_srcF_i_notEmpty_ETC___d323, - merge_fo_i_notFull_AND_IF_merge_fi0HasPrio_06__ETC___d108; + IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d154, + IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d164; + wire IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d113, + IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d911, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d704, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d909, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d910, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d912, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_i_notEmp_ETC___d118, + NOT_frk_stageSent_27_28_OR_frk_srcF_i_notEmpty_ETC___d334; // action method server_request_put assign RDY_server_request_put = frk_srcF$FULL_N ; @@ -350,7 +360,7 @@ module mkQABSMF(et0, assign RDY_client1_response_put = merge_fi1$FULL_N ; // submodule frk_d0F - FIFO2 #(.width(32'd40), .guarded(32'd1)) frk_d0F(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) frk_d0F(.RST(RST_N), .CLK(CLK), .D_IN(frk_d0F$D_IN), .ENQ(frk_d0F$ENQ), @@ -361,7 +371,7 @@ module mkQABSMF(et0, .EMPTY_N(frk_d0F$EMPTY_N)); // submodule frk_d1F - FIFO2 #(.width(32'd40), .guarded(32'd1)) frk_d1F(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) frk_d1F(.RST(RST_N), .CLK(CLK), .D_IN(frk_d1F$D_IN), .ENQ(frk_d1F$ENQ), @@ -372,7 +382,7 @@ module mkQABSMF(et0, .EMPTY_N(frk_d1F$EMPTY_N)); // submodule frk_srcF - FIFO2 #(.width(32'd40), .guarded(32'd1)) frk_srcF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) frk_srcF(.RST(RST_N), .CLK(CLK), .D_IN(frk_srcF$D_IN), .ENQ(frk_srcF$ENQ), @@ -383,7 +393,7 @@ module mkQABSMF(et0, .EMPTY_N(frk_srcF$EMPTY_N)); // submodule merge_fi0 - FIFO2 #(.width(32'd40), .guarded(32'd1)) merge_fi0(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) merge_fi0(.RST(RST_N), .CLK(CLK), .D_IN(merge_fi0$D_IN), .ENQ(merge_fi0$ENQ), @@ -394,7 +404,7 @@ module mkQABSMF(et0, .EMPTY_N(merge_fi0$EMPTY_N)); // submodule merge_fi1 - FIFO2 #(.width(32'd40), .guarded(32'd1)) merge_fi1(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) merge_fi1(.RST(RST_N), .CLK(CLK), .D_IN(merge_fi1$D_IN), .ENQ(merge_fi1$ENQ), @@ -405,7 +415,7 @@ module mkQABSMF(et0, .EMPTY_N(merge_fi1$EMPTY_N)); // submodule merge_fo - FIFO2 #(.width(32'd40), .guarded(32'd1)) merge_fo(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) merge_fo(.RST(RST_N), .CLK(CLK), .D_IN(merge_fo$D_IN), .ENQ(merge_fo$ENQ), @@ -415,14 +425,6 @@ module mkQABSMF(et0, .FULL_N(merge_fo$FULL_N), .EMPTY_N(merge_fo$EMPTY_N)); - // rule RL_merge_arbitrate - assign WILL_FIRE_RL_merge_arbitrate = - merge_fo_i_notFull_AND_IF_merge_fi0HasPrio_06__ETC___d108 && - merge_fi0$EMPTY_N && - merge_fi1$EMPTY_N && - !merge_fi0Active && - !merge_fi1Active ; - // rule RL_merge_fi0_advance assign WILL_FIRE_RL_merge_fi0_advance = merge_fi0$EMPTY_N && merge_fo$FULL_N && !merge_fi1Active && @@ -434,6 +436,15 @@ module mkQABSMF(et0, !WILL_FIRE_RL_merge_fi0_advance && !WILL_FIRE_RL_merge_arbitrate ; + // rule RL_merge_arbitrate + assign WILL_FIRE_RL_merge_arbitrate = + merge_fo$FULL_N && + IF_merge_fi0HasPrio_06_THEN_merge_fi0_i_notEmp_ETC___d118 && + merge_fi0$EMPTY_N && + merge_fi1$EMPTY_N && + !merge_fi0Active && + !merge_fi1Active ; + // rule RL_frk_stage assign WILL_FIRE_RL_frk_stage = frk_srcF$EMPTY_N && !frk_staged && !frk_decided ; @@ -444,7 +455,7 @@ module mkQABSMF(et0, // rule RL_frk_egress assign WILL_FIRE_RL_frk_egress = - NOT_frk_stageSent_16_17_OR_frk_srcF_i_notEmpty_ETC___d323 && + NOT_frk_stageSent_27_28_OR_frk_srcF_i_notEmpty_ETC___d334 && frk_staged && frk_decided ; @@ -465,18 +476,18 @@ module mkQABSMF(et0, assign MUX_merge_fi1Active$write_1__SEL_1 = WILL_FIRE_RL_merge_arbitrate && !merge_fi0HasPrio ; assign MUX_frk_ptr$write_1__VAL_1 = - frk_stageSent ? 3'd0 : frk_ptr_08_PLUS_1___d783 ; + frk_stageSent ? 3'd0 : frk_ptr_19_PLUS_1___d795 ; assign MUX_frk_ptr$write_1__VAL_2 = (frk_srcF$D_OUT[9:8] != 2'd0 || frk_srcF$D_OUT[19:18] != 2'd0 || frk_srcF$D_OUT[29:28] != 2'd0 || frk_srcF$D_OUT[39:38] != 2'd0) ? 3'd0 : - frk_ptr_08_PLUS_1___d783 ; + frk_ptr_19_PLUS_1___d795 ; assign MUX_merge_fi0Active$write_1__VAL_1 = - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d900 && - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d899 && - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d898 && - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689 ; + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d912 && + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d910 && + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d909 && + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d704 ; assign MUX_merge_fi0Active$write_1__VAL_2 = merge_fi0$D_OUT[9:8] == 2'd0 && merge_fi0$D_OUT[19:18] == 2'd0 && merge_fi0$D_OUT[29:28] == 2'd0 && @@ -504,15 +515,15 @@ module mkQABSMF(et0, CASE_merge_fi1D_OUT_BITS_9_TO_8_3_0_merge_fi1_ETC__q36, merge_fi1$D_OUT[7:0] } ; assign MUX_merge_fo$enq_1__VAL_3 = - { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d136, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d899 ? + { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d147, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d910 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d723 } : - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d145, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d900 ? + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d734 } : + IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d156, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d912 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d724 } : - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d155 } ; + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d735 } : + IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d166 } ; // register frk_decided assign frk_decided$D_IN = !MUX_frk_decided$write_1__SEL_1 ; @@ -524,7 +535,7 @@ module mkQABSMF(et0, WILL_FIRE_RL_frk_decide ; // register frk_match0 - assign frk_match0$D_IN = et0 == seen__h10467 ; + assign frk_match0$D_IN = et0 == seen__h10505 ; assign frk_match0$EN = WILL_FIRE_RL_frk_decide ; // register frk_ptr @@ -551,7 +562,7 @@ module mkQABSMF(et0, // register frk_sr assign frk_sr$D_IN = - { IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d729, + { IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d740, CASE_frk_sr_BITS_119_TO_118_3_0_frk_sr_BITS_11_ETC__q37, frk_sr[117:110], CASE_frk_sr_BITS_109_TO_108_3_0_frk_sr_BITS_10_ETC__q38, @@ -621,11 +632,11 @@ module mkQABSMF(et0, // submodule frk_d0F assign frk_d0F$D_IN = frk_stageSent ? - IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d729 : - { IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d350, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d373, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d397, - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d420 } ; + IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d740 : + { IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d361, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d384, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d408, + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d431 } ; assign frk_d0F$ENQ = WILL_FIRE_RL_frk_egress && frk_match0 ; assign frk_d0F$DEQ = EN_client0_request_get ; assign frk_d0F$CLR = 1'b0 ; @@ -708,132 +719,132 @@ module mkQABSMF(et0, assign merge_fo$CLR = 1'b0 ; // remaining internal signals - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d395 = + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d406 = { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q19 ? 2'd2 : 2'd3, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 } ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d396 = + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d738 } ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d407 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q20 ? { 2'd1, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 } : - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d395 ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d397 = + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d738 } : + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d406 ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d408 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q21 ? { 2'd0, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 } : - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d396 ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d371 = - { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q13 ? + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d738 } : + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d407 ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d382 = + { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q16 ? 2'd2 : 2'd3, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 } ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d372 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q14 ? + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d737 } ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d383 = + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q17 ? { 2'd1, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 } : - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d371 ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d373 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q15 ? + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d737 } : + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d382 ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d384 = + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q18 ? { 2'd0, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 } : - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d372 ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d348 = - { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q16 ? + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d737 } : + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d383 ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d359 = + { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q13 ? 2'd2 : 2'd3, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 } ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d349 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q17 ? + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d736 } ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d360 = + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q14 ? { 2'd1, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 } : - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d348 ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d350 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q18 ? + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d736 } : + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d359 ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d361 = + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q15 ? { 2'd0, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 } : - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d349 ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d418 = + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d736 } : + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d360 ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d429 = { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q22 ? 2'd2 : 2'd3, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 } ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d419 = + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d739 } ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d430 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q23 ? { 2'd1, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 } : - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d418 ; - assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d420 = + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d739 } : + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d429 ; + assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d431 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q24 ? { 2'd0, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 } : - IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d419 ; - assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d122 = + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d739 } : + IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d430 ; + assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d133 = (merge_fi0HasPrio ? merge_fi0$D_OUT[39:38] == 2'd2 : merge_fi1$D_OUT[39:38] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d124 = + assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d135 = (merge_fi0HasPrio ? merge_fi0$D_OUT[39:38] == 2'd1 : merge_fi1$D_OUT[39:38] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d721 } : - { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d122, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d721 } ; - assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d132 = + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d732 } : + { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d133, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d732 } ; + assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143 = (merge_fi0HasPrio ? merge_fi0$D_OUT[29:28] == 2'd2 : merge_fi1$D_OUT[29:28] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d134 = + assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d145 = (merge_fi0HasPrio ? merge_fi0$D_OUT[29:28] == 2'd1 : merge_fi1$D_OUT[29:28] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d722 } : - { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d132, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d722 } ; - assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d136 = - { IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689 ? + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d733 } : + { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d733 } ; + assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d147 = + { IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d704 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d721 } : - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d124, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d898 ? + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d732 } : + IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d135, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d909 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d722 } : - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d134 } ; - assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143 = + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d733 } : + IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d145 } ; + assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d154 = (merge_fi0HasPrio ? merge_fi0$D_OUT[19:18] == 2'd2 : merge_fi1$D_OUT[19:18] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d145 = + assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d156 = (merge_fi0HasPrio ? merge_fi0$D_OUT[19:18] == 2'd1 : merge_fi1$D_OUT[19:18] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d723 } : - { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d723 } ; - assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d153 = + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d734 } : + { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d154, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d734 } ; + assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d164 = (merge_fi0HasPrio ? merge_fi0$D_OUT[9:8] == 2'd2 : merge_fi1$D_OUT[9:8] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d155 = + assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d166 = (merge_fi0HasPrio ? merge_fi0$D_OUT[9:8] == 2'd1 : merge_fi1$D_OUT[9:8] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d724 } : - { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d153, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d724 } ; - assign IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d729 = + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d735 } : + { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d164, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d735 } ; + assign IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d740 = { CASE_frk_srcFD_OUT_BITS_39_TO_38_3_0_frk_srcF_ETC__q25, frk_srcF$D_OUT[37:30], CASE_frk_srcFD_OUT_BITS_29_TO_28_3_0_frk_srcF_ETC__q26, @@ -842,44 +853,54 @@ module mkQABSMF(et0, frk_srcF$D_OUT[17:10], CASE_frk_srcFD_OUT_BITS_9_TO_8_3_0_frk_srcFD_ETC__q28, frk_srcF$D_OUT[7:0] } ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689 = + assign IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d113 = + merge_fi0HasPrio ? + !merge_fi0$EMPTY_N || merge_fi0$D_OUT[9:8] != 2'd0 : + !merge_fi1$EMPTY_N || merge_fi1$D_OUT[9:8] != 2'd0 ; + assign IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d911 = + IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d113 || + (merge_fi0HasPrio ? merge_fi0$EMPTY_N : merge_fi1$EMPTY_N) ; + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d704 = merge_fi0HasPrio ? merge_fi0$D_OUT[39:38] == 2'd0 : merge_fi1$D_OUT[39:38] == 2'd0 ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d721 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d732 = merge_fi0HasPrio ? merge_fi0$D_OUT[37:30] : merge_fi1$D_OUT[37:30] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d722 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d733 = merge_fi0HasPrio ? merge_fi0$D_OUT[27:20] : merge_fi1$D_OUT[27:20] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d723 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d734 = merge_fi0HasPrio ? merge_fi0$D_OUT[17:10] : merge_fi1$D_OUT[17:10] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d724 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d735 = merge_fi0HasPrio ? merge_fi0$D_OUT[7:0] : merge_fi1$D_OUT[7:0] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d898 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d909 = merge_fi0HasPrio ? merge_fi0$D_OUT[29:28] == 2'd0 : merge_fi1$D_OUT[29:28] == 2'd0 ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d899 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d910 = merge_fi0HasPrio ? merge_fi0$D_OUT[19:18] == 2'd0 : merge_fi1$D_OUT[19:18] == 2'd0 ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d900 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d912 = merge_fi0HasPrio ? merge_fi0$D_OUT[9:8] == 2'd0 : merge_fi1$D_OUT[9:8] == 2'd0 ; - assign NOT_frk_stageSent_16_17_OR_frk_srcF_i_notEmpty_ETC___d323 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_i_notEmp_ETC___d118 = + merge_fi0HasPrio ? + merge_fi0$EMPTY_N && + IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d911 : + merge_fi1$EMPTY_N && + IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d911 ; + assign NOT_frk_stageSent_27_28_OR_frk_srcF_i_notEmpty_ETC___d334 = (!frk_stageSent || frk_srcF$EMPTY_N) && (frk_match0 ? frk_d0F$FULL_N : frk_d1F$FULL_N) ; - assign frk_ptr_08_PLUS_1___d783 = frk_ptr + 3'd1 ; - assign merge_fo_i_notFull_AND_IF_merge_fi0HasPrio_06__ETC___d108 = - merge_fo$FULL_N && - (merge_fi0HasPrio ? merge_fi0$EMPTY_N : merge_fi1$EMPTY_N) ; - assign seen__h10467 = { frk_srcF$D_OUT[7:0], frk_srcF$D_OUT[17:10] } ; + assign frk_ptr_19_PLUS_1___d795 = frk_ptr + 3'd1 ; + assign seen__h10505 = { frk_srcF$D_OUT[7:0], frk_srcF$D_OUT[17:10] } ; always@(frk_d1F$D_OUT) begin case (frk_d1F$D_OUT[39:38]) @@ -992,116 +1013,116 @@ module mkQABSMF(et0, begin case (frk_ptr) 3'd0: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 = - frk_sr[27:20]; + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d736 = + frk_sr[37:30]; 3'd1: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 = - frk_sr[67:60]; - default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 = - frk_sr[107:100]; + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d736 = + frk_sr[77:70]; + default: IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d736 = + frk_sr[117:110]; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q13 = - frk_sr[29:28] == 2'd2; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q13 = + frk_sr[39:38] == 2'd2; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q13 = - frk_sr[69:68] == 2'd2; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q13 = - frk_ptr == 3'd2 && frk_sr[109:108] == 2'd2; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q13 = + frk_sr[79:78] == 2'd2; + default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q13 = + frk_ptr == 3'd2 && frk_sr[119:118] == 2'd2; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q14 = - frk_sr[29:28] == 2'd1; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q14 = + frk_sr[39:38] == 2'd1; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q14 = - frk_sr[69:68] == 2'd1; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q14 = - frk_ptr == 3'd2 && frk_sr[109:108] == 2'd1; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q14 = + frk_sr[79:78] == 2'd1; + default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q14 = + frk_ptr == 3'd2 && frk_sr[119:118] == 2'd1; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q15 = - frk_sr[29:28] == 2'd0; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q15 = + frk_sr[39:38] == 2'd0; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q15 = - frk_sr[69:68] == 2'd0; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q15 = - frk_ptr == 3'd2 && frk_sr[109:108] == 2'd0; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q15 = + frk_sr[79:78] == 2'd0; + default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q15 = + frk_ptr == 3'd2 && frk_sr[119:118] == 2'd0; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 = - frk_sr[37:30]; + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d737 = + frk_sr[27:20]; 3'd1: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 = - frk_sr[77:70]; - default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 = - frk_sr[117:110]; + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d737 = + frk_sr[67:60]; + default: IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d737 = + frk_sr[107:100]; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q16 = - frk_sr[39:38] == 2'd2; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q16 = + frk_sr[29:28] == 2'd2; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q16 = - frk_sr[79:78] == 2'd2; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q16 = - frk_ptr == 3'd2 && frk_sr[119:118] == 2'd2; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q16 = + frk_sr[69:68] == 2'd2; + default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q16 = + frk_ptr == 3'd2 && frk_sr[109:108] == 2'd2; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q17 = - frk_sr[39:38] == 2'd1; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q17 = + frk_sr[29:28] == 2'd1; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q17 = - frk_sr[79:78] == 2'd1; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q17 = - frk_ptr == 3'd2 && frk_sr[119:118] == 2'd1; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q17 = + frk_sr[69:68] == 2'd1; + default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q17 = + frk_ptr == 3'd2 && frk_sr[109:108] == 2'd1; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q18 = - frk_sr[39:38] == 2'd0; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q18 = + frk_sr[29:28] == 2'd0; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q18 = - frk_sr[79:78] == 2'd0; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q18 = - frk_ptr == 3'd2 && frk_sr[119:118] == 2'd0; + CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q18 = + frk_sr[69:68] == 2'd0; + default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q18 = + frk_ptr == 3'd2 && frk_sr[109:108] == 2'd0; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 = + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d738 = frk_sr[17:10]; 3'd1: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 = + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d738 = frk_sr[57:50]; - default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 = + default: IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d738 = frk_sr[97:90]; endcase end @@ -1148,12 +1169,12 @@ module mkQABSMF(et0, begin case (frk_ptr) 3'd0: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 = + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d739 = frk_sr[7:0]; 3'd1: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 = + IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d739 = frk_sr[47:40]; - default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 = + default: IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d739 = frk_sr[87:80]; endcase end @@ -1489,7 +1510,7 @@ module mkQABSMF(et0, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin frk_decided <= `BSV_ASSIGNMENT_DELAY 1'd0; frk_match0 <= `BSV_ASSIGNMENT_DELAY 1'd0; diff --git a/rtl/mkQABSMF3.v b/rtl/mkQABSMF3.v index 4d97b440..76d19c2e 100644 --- a/rtl/mkQABSMF3.v +++ b/rtl/mkQABSMF3.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:37:51 EDT 2012 +// On Mon Sep 24 15:02:57 EDT 2012 // // // Ports: @@ -41,7 +41,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkQABSMF3(et0, @@ -356,14 +364,14 @@ module mkQABSMF3(et0, MUX_merge1_fi1Active$write_1__VAL_2; // remaining internal signals - reg [7 : 0] IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308; + reg [7 : 0] IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1323, + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1324, + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1325, + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1326, + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1327, + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1328, + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1329, + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1330; reg [1 : 0] CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q91, CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q90, CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q89, @@ -468,72 +476,76 @@ module mkQABSMF3(et0, CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q38, CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q39, CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q40; - wire [39 : 0] IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1309, - IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1310; - wire [19 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d136, - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d296; - wire [15 : 0] seen__h16118, seen__h26918; - wire [9 : 0] IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d508, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d509, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d510, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d531, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d532, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d533, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d555, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d556, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d557, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d578, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d579, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d580, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d775, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d776, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d777, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d798, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d799, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d800, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d822, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d823, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d824, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d845, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d846, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d847, - IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d124, - IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d134, + wire [39 : 0] IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d1331, + IF_fork1_srcF_first__17_BITS_39_TO_38_18_EQ_0__ETC___d1332; + wire [19 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d147, + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d318; + wire [15 : 0] seen__h16174, seen__h26999; + wire [9 : 0] IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d530, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d531, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d532, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d553, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d554, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d555, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d577, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d578, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d579, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d600, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d601, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d602, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d797, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d798, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d799, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d820, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d821, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d822, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d844, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d845, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d846, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d867, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d868, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d869, + IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d135, IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145, - IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d155, - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d284, - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d294, - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d305, - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d315; - wire [7 : 0] IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1293, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1294, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1295, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1296, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1297, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1298, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1299, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1300; - wire [2 : 0] fork0_ptr_68_PLUS_1___d1411, fork1_ptr_35_PLUS_1___d1412; - wire [1 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d122, - IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d132, + IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d156, + IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d166, + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d306, + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d316, + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d327, + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d337; + wire [7 : 0] IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1315, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1316, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1317, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1318, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1319, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1320, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1321, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1322; + wire [2 : 0] fork0_ptr_90_PLUS_1___d1433, fork1_ptr_57_PLUS_1___d1434; + wire [1 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d133, IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143, - IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d153, - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d282, - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d292, - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d303, - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d313; - wire IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1626, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1627, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1628, + IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d154, + IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d164, + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d304, + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d314, + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d325, + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d335; + wire IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d113, + IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d1650, IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1630, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1631, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1632, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1649, - NOT_fork0_stageSent_76_77_OR_fork0_srcF_i_notE_ETC___d483, - NOT_fork1_stageSent_43_44_OR_fork1_srcF_i_notE_ETC___d750, - merge0_fo_i_notFull_AND_IF_merge0_fi0HasPrio_0_ETC___d108, - merge1_fo_i_notFull__62_AND_IF_merge1_fi0HasPr_ETC___d268; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1649, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1651, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1672, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_i_notE_ETC___d118, + IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d1654, + IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d284, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1652, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1653, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1655, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1673, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_i_notE_ETC___d289, + NOT_fork0_stageSent_98_99_OR_fork0_srcF_i_notE_ETC___d505, + NOT_fork1_stageSent_65_66_OR_fork1_srcF_i_notE_ETC___d772; // action method server_request_put assign RDY_server_request_put = fork0_srcF$FULL_N ; @@ -596,7 +608,7 @@ module mkQABSMF3(et0, assign RDY_client2_response_put = merge1_fi1$FULL_N ; // submodule fork0_d0F - FIFO2 #(.width(32'd40), .guarded(32'd1)) fork0_d0F(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) fork0_d0F(.RST(RST_N), .CLK(CLK), .D_IN(fork0_d0F$D_IN), .ENQ(fork0_d0F$ENQ), @@ -607,7 +619,7 @@ module mkQABSMF3(et0, .EMPTY_N(fork0_d0F$EMPTY_N)); // submodule fork0_d1F - FIFO2 #(.width(32'd40), .guarded(32'd1)) fork0_d1F(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) fork0_d1F(.RST(RST_N), .CLK(CLK), .D_IN(fork0_d1F$D_IN), .ENQ(fork0_d1F$ENQ), @@ -618,7 +630,7 @@ module mkQABSMF3(et0, .EMPTY_N(fork0_d1F$EMPTY_N)); // submodule fork0_srcF - FIFO2 #(.width(32'd40), .guarded(32'd1)) fork0_srcF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) fork0_srcF(.RST(RST_N), .CLK(CLK), .D_IN(fork0_srcF$D_IN), .ENQ(fork0_srcF$ENQ), @@ -629,7 +641,7 @@ module mkQABSMF3(et0, .EMPTY_N(fork0_srcF$EMPTY_N)); // submodule fork1_d0F - FIFO2 #(.width(32'd40), .guarded(32'd1)) fork1_d0F(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) fork1_d0F(.RST(RST_N), .CLK(CLK), .D_IN(fork1_d0F$D_IN), .ENQ(fork1_d0F$ENQ), @@ -640,7 +652,7 @@ module mkQABSMF3(et0, .EMPTY_N(fork1_d0F$EMPTY_N)); // submodule fork1_d1F - FIFO2 #(.width(32'd40), .guarded(32'd1)) fork1_d1F(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) fork1_d1F(.RST(RST_N), .CLK(CLK), .D_IN(fork1_d1F$D_IN), .ENQ(fork1_d1F$ENQ), @@ -651,7 +663,7 @@ module mkQABSMF3(et0, .EMPTY_N(fork1_d1F$EMPTY_N)); // submodule fork1_srcF - FIFO2 #(.width(32'd40), .guarded(32'd1)) fork1_srcF(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) fork1_srcF(.RST(RST_N), .CLK(CLK), .D_IN(fork1_srcF$D_IN), .ENQ(fork1_srcF$ENQ), @@ -662,7 +674,7 @@ module mkQABSMF3(et0, .EMPTY_N(fork1_srcF$EMPTY_N)); // submodule merge0_fi0 - FIFO2 #(.width(32'd40), .guarded(32'd1)) merge0_fi0(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) merge0_fi0(.RST(RST_N), .CLK(CLK), .D_IN(merge0_fi0$D_IN), .ENQ(merge0_fi0$ENQ), @@ -673,7 +685,7 @@ module mkQABSMF3(et0, .EMPTY_N(merge0_fi0$EMPTY_N)); // submodule merge0_fi1 - FIFO2 #(.width(32'd40), .guarded(32'd1)) merge0_fi1(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) merge0_fi1(.RST(RST_N), .CLK(CLK), .D_IN(merge0_fi1$D_IN), .ENQ(merge0_fi1$ENQ), @@ -684,7 +696,7 @@ module mkQABSMF3(et0, .EMPTY_N(merge0_fi1$EMPTY_N)); // submodule merge0_fo - FIFO2 #(.width(32'd40), .guarded(32'd1)) merge0_fo(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) merge0_fo(.RST(RST_N), .CLK(CLK), .D_IN(merge0_fo$D_IN), .ENQ(merge0_fo$ENQ), @@ -695,7 +707,7 @@ module mkQABSMF3(et0, .EMPTY_N(merge0_fo$EMPTY_N)); // submodule merge1_fi0 - FIFO2 #(.width(32'd40), .guarded(32'd1)) merge1_fi0(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) merge1_fi0(.RST(RST_N), .CLK(CLK), .D_IN(merge1_fi0$D_IN), .ENQ(merge1_fi0$ENQ), @@ -706,7 +718,7 @@ module mkQABSMF3(et0, .EMPTY_N(merge1_fi0$EMPTY_N)); // submodule merge1_fi1 - FIFO2 #(.width(32'd40), .guarded(32'd1)) merge1_fi1(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) merge1_fi1(.RST(RST_N), .CLK(CLK), .D_IN(merge1_fi1$D_IN), .ENQ(merge1_fi1$ENQ), @@ -717,7 +729,7 @@ module mkQABSMF3(et0, .EMPTY_N(merge1_fi1$EMPTY_N)); // submodule merge1_fo - FIFO2 #(.width(32'd40), .guarded(32'd1)) merge1_fo(.RST_N(RST_N), + FIFO2 #(.width(32'd40), .guarded(32'd1)) merge1_fo(.RST(RST_N), .CLK(CLK), .D_IN(merge1_fo$D_IN), .ENQ(merge1_fo$ENQ), @@ -727,22 +739,6 @@ module mkQABSMF3(et0, .FULL_N(merge1_fo$FULL_N), .EMPTY_N(merge1_fo$EMPTY_N)); - // rule RL_merge0_arbitrate - assign WILL_FIRE_RL_merge0_arbitrate = - merge0_fo_i_notFull_AND_IF_merge0_fi0HasPrio_0_ETC___d108 && - merge0_fi0$EMPTY_N && - merge0_fi1$EMPTY_N && - !merge0_fi0Active && - !merge0_fi1Active ; - - // rule RL_merge1_arbitrate - assign WILL_FIRE_RL_merge1_arbitrate = - merge1_fo_i_notFull__62_AND_IF_merge1_fi0HasPr_ETC___d268 && - merge1_fi0$EMPTY_N && - merge1_fi1$EMPTY_N && - !merge1_fi0Active && - !merge1_fi1Active ; - // rule RL_merge0_fi0_advance assign WILL_FIRE_RL_merge0_fi0_advance = merge0_fi0$EMPTY_N && merge0_fo$FULL_N && !merge0_fi1Active && @@ -754,6 +750,15 @@ module mkQABSMF3(et0, !WILL_FIRE_RL_merge0_fi0_advance && !WILL_FIRE_RL_merge0_arbitrate ; + // rule RL_merge0_arbitrate + assign WILL_FIRE_RL_merge0_arbitrate = + merge0_fo$FULL_N && + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_i_notE_ETC___d118 && + merge0_fi0$EMPTY_N && + merge0_fi1$EMPTY_N && + !merge0_fi0Active && + !merge0_fi1Active ; + // rule RL_merge1_fi0_advance assign WILL_FIRE_RL_merge1_fi0_advance = merge1_fi0$EMPTY_N && merge1_fo$FULL_N && !merge1_fi1Active && @@ -765,6 +770,15 @@ module mkQABSMF3(et0, !WILL_FIRE_RL_merge1_fi0_advance && !WILL_FIRE_RL_merge1_arbitrate ; + // rule RL_merge1_arbitrate + assign WILL_FIRE_RL_merge1_arbitrate = + merge1_fo$FULL_N && + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_i_notE_ETC___d289 && + merge1_fi0$EMPTY_N && + merge1_fi1$EMPTY_N && + !merge1_fi0Active && + !merge1_fi1Active ; + // rule RL_fork0_stage assign WILL_FIRE_RL_fork0_stage = fork0_srcF$EMPTY_N && !fork0_staged && !fork0_decided ; @@ -775,7 +789,7 @@ module mkQABSMF3(et0, // rule RL_fork0_egress assign WILL_FIRE_RL_fork0_egress = - NOT_fork0_stageSent_76_77_OR_fork0_srcF_i_notE_ETC___d483 && + NOT_fork0_stageSent_98_99_OR_fork0_srcF_i_notE_ETC___d505 && fork0_staged && fork0_decided ; @@ -789,7 +803,7 @@ module mkQABSMF3(et0, // rule RL_fork1_egress assign WILL_FIRE_RL_fork1_egress = - NOT_fork1_stageSent_43_44_OR_fork1_srcF_i_notE_ETC___d750 && + NOT_fork1_stageSent_65_66_OR_fork1_srcF_i_notE_ETC___d772 && fork1_staged && fork1_decided ; @@ -829,28 +843,28 @@ module mkQABSMF3(et0, assign MUX_merge1_fi1Active$write_1__SEL_1 = WILL_FIRE_RL_merge1_arbitrate && !merge1_fi0HasPrio ; assign MUX_fork0_ptr$write_1__VAL_1 = - fork0_stageSent ? 3'd0 : fork0_ptr_68_PLUS_1___d1411 ; + fork0_stageSent ? 3'd0 : fork0_ptr_90_PLUS_1___d1433 ; assign MUX_fork0_ptr$write_1__VAL_2 = (fork0_srcF$D_OUT[9:8] != 2'd0 || fork0_srcF$D_OUT[19:18] != 2'd0 || fork0_srcF$D_OUT[29:28] != 2'd0 || fork0_srcF$D_OUT[39:38] != 2'd0) ? 3'd0 : - fork0_ptr_68_PLUS_1___d1411 ; + fork0_ptr_90_PLUS_1___d1433 ; assign MUX_fork1_ptr$write_1__VAL_1 = - fork1_stageSent ? 3'd0 : fork1_ptr_35_PLUS_1___d1412 ; + fork1_stageSent ? 3'd0 : fork1_ptr_57_PLUS_1___d1434 ; assign MUX_fork1_ptr$write_1__VAL_2 = (fork1_srcF$D_OUT[9:8] != 2'd0 || fork1_srcF$D_OUT[19:18] != 2'd0 || fork1_srcF$D_OUT[29:28] != 2'd0 || fork1_srcF$D_OUT[39:38] != 2'd0) ? 3'd0 : - fork1_ptr_35_PLUS_1___d1412 ; + fork1_ptr_57_PLUS_1___d1434 ; assign MUX_merge0_fi0Active$write_1__VAL_1 = - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1628 && - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1627 && - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1626 && - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648 ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1651 && + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1649 && + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648 && + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1672 ; assign MUX_merge0_fi0Active$write_1__VAL_2 = merge0_fi0$D_OUT[9:8] == 2'd0 && merge0_fi0$D_OUT[19:18] == 2'd0 && @@ -880,20 +894,20 @@ module mkQABSMF3(et0, CASE_merge0_fi1D_OUT_BITS_9_TO_8_3_0_merge0_f_ETC__q56, merge0_fi1$D_OUT[7:0] } ; assign MUX_merge0_fo$enq_1__VAL_3 = - { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d136, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1627 ? + { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d147, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1649 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1295 } : - IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1628 ? + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1317 } : + IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d156, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1651 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1296 } : - IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d155 } ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1318 } : + IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d166 } ; assign MUX_merge1_fi0Active$write_1__VAL_1 = - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1632 && - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1631 && - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1630 && - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1649 ; + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1655 && + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1653 && + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1652 && + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1673 ; assign MUX_merge1_fi0Active$write_1__VAL_2 = merge1_fi0$D_OUT[9:8] == 2'd0 && merge1_fi0$D_OUT[19:18] == 2'd0 && @@ -923,15 +937,15 @@ module mkQABSMF3(et0, CASE_merge1_fi1D_OUT_BITS_9_TO_8_3_0_merge1_f_ETC__q64, merge1_fi1$D_OUT[7:0] } ; assign MUX_merge1_fo$enq_1__VAL_3 = - { IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d296, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1631 ? + { IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d318, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1653 ? { 2'd0, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1299 } : - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d305, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1632 ? + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1321 } : + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d327, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1655 ? { 2'd0, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1300 } : - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d315 } ; + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1322 } : + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d337 } ; // register fork0_decided assign fork0_decided$D_IN = !MUX_fork0_decided$write_1__SEL_1 ; @@ -944,7 +958,7 @@ module mkQABSMF3(et0, WILL_FIRE_RL_fork0_decide ; // register fork0_match0 - assign fork0_match0$D_IN = et0 == seen__h16118 ; + assign fork0_match0$D_IN = et0 == seen__h16174 ; assign fork0_match0$EN = WILL_FIRE_RL_fork0_decide ; // register fork0_ptr @@ -973,7 +987,7 @@ module mkQABSMF3(et0, // register fork0_sr assign fork0_sr$D_IN = - { IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1309, + { IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d1331, CASE_fork0_sr_BITS_119_TO_118_3_0_fork0_sr_BIT_ETC__q65, fork0_sr[117:110], CASE_fork0_sr_BITS_109_TO_108_3_0_fork0_sr_BIT_ETC__q66, @@ -1018,7 +1032,7 @@ module mkQABSMF3(et0, WILL_FIRE_RL_fork1_decide ; // register fork1_match0 - assign fork1_match0$D_IN = did == seen__h26918 ; + assign fork1_match0$D_IN = did == seen__h26999 ; assign fork1_match0$EN = WILL_FIRE_RL_fork1_decide ; // register fork1_ptr @@ -1047,7 +1061,7 @@ module mkQABSMF3(et0, // register fork1_sr assign fork1_sr$D_IN = - { IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1310, + { IF_fork1_srcF_first__17_BITS_39_TO_38_18_EQ_0__ETC___d1332, CASE_fork1_sr_BITS_119_TO_118_3_0_fork1_sr_BIT_ETC__q77, fork1_sr[117:110], CASE_fork1_sr_BITS_109_TO_108_3_0_fork1_sr_BIT_ETC__q78, @@ -1156,11 +1170,11 @@ module mkQABSMF3(et0, // submodule fork0_d0F assign fork0_d0F$D_IN = fork0_stageSent ? - IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1309 : - { IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d510, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d533, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d557, - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d580 } ; + IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d1331 : + { IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d532, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d555, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d579, + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d602 } ; assign fork0_d0F$ENQ = WILL_FIRE_RL_fork0_egress && fork0_match0 ; assign fork0_d0F$DEQ = EN_client0_request_get ; assign fork0_d0F$CLR = 1'b0 ; @@ -1190,11 +1204,11 @@ module mkQABSMF3(et0, // submodule fork1_d0F assign fork1_d0F$D_IN = fork1_stageSent ? - IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1310 : - { IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d777, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d800, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d824, - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d847 } ; + IF_fork1_srcF_first__17_BITS_39_TO_38_18_EQ_0__ETC___d1332 : + { IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d799, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d822, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d846, + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d869 } ; assign fork1_d0F$ENQ = WILL_FIRE_RL_fork1_egress && fork1_match0 ; assign fork1_d0F$DEQ = EN_client1_request_get ; assign fork1_d0F$CLR = 1'b0 ; @@ -1334,257 +1348,257 @@ module mkQABSMF3(et0, assign merge1_fo$CLR = 1'b0 ; // remaining internal signals - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d508 = + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d530 = { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q17 ? 2'd2 : 2'd3, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 } ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d509 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1323 } ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d531 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q18 ? { 2'd1, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 } : - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d508 ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d510 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1323 } : + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d530 ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d532 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q19 ? { 2'd0, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 } : - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d509 ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d531 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1323 } : + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d531 ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d553 = { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q20 ? 2'd2 : 2'd3, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 } ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d532 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1324 } ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d554 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q21 ? { 2'd1, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 } : - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d531 ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d533 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1324 } : + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d553 ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d555 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q22 ? { 2'd0, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 } : - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d532 ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d555 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1324 } : + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d554 ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d577 = { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q23 ? 2'd2 : 2'd3, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 } ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d556 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1325 } ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d578 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q24 ? { 2'd1, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 } : - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d555 ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d557 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1325 } : + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d577 ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d579 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q25 ? { 2'd0, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 } : - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d556 ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d578 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1325 } : + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d578 ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d600 = { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q26 ? 2'd2 : 2'd3, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 } ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d579 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1326 } ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d601 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q27 ? { 2'd1, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 } : - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d578 ; - assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d580 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1326 } : + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d600 ; + assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d602 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q28 ? { 2'd0, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 } : - IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d579 ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d775 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1326 } : + IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d601 ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d797 = { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q29 ? 2'd2 : 2'd3, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 } ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d776 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1327 } ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d798 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q30 ? { 2'd1, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 } : - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d775 ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d777 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1327 } : + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d797 ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d799 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q31 ? { 2'd0, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 } : - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d776 ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d798 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1327 } : + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d798 ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d820 = { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q32 ? 2'd2 : 2'd3, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 } ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d799 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1328 } ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d821 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q33 ? { 2'd1, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 } : - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d798 ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d800 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1328 } : + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d820 ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d822 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q34 ? { 2'd0, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 } : - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d799 ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d822 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1328 } : + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d821 ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d844 = { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q35 ? 2'd2 : 2'd3, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 } ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d823 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1329 } ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d845 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q36 ? { 2'd1, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 } : - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d822 ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d824 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1329 } : + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d844 ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d846 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q37 ? { 2'd0, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 } : - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d823 ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d845 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1329 } : + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d845 ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d867 = { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q38 ? 2'd2 : 2'd3, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 } ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d846 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1330 } ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d868 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q39 ? { 2'd1, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 } : - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d845 ; - assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d847 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1330 } : + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d867 ; + assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d869 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q40 ? { 2'd0, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 } : - IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d846 ; - assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d122 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1330 } : + IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d868 ; + assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d133 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[39:38] == 2'd2 : merge0_fi1$D_OUT[39:38] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d124 = + assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d135 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[39:38] == 2'd1 : merge0_fi1$D_OUT[39:38] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1293 } : - { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d122, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1293 } ; - assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d132 = + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1315 } : + { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d133, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1315 } ; + assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[29:28] == 2'd2 : merge0_fi1$D_OUT[29:28] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d134 = + assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[29:28] == 2'd1 : merge0_fi1$D_OUT[29:28] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1294 } : - { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d132, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1294 } ; - assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d136 = - { IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648 ? + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1316 } : + { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1316 } ; + assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d147 = + { IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1672 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1293 } : - IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d124, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1626 ? + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1315 } : + IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d135, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1294 } : - IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d134 } ; - assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143 = + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1316 } : + IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145 } ; + assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d154 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[19:18] == 2'd2 : merge0_fi1$D_OUT[19:18] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145 = + assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d156 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[19:18] == 2'd1 : merge0_fi1$D_OUT[19:18] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1295 } : - { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1295 } ; - assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d153 = + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1317 } : + { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d154, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1317 } ; + assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d164 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[9:8] == 2'd2 : merge0_fi1$D_OUT[9:8] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d155 = + assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d166 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[9:8] == 2'd1 : merge0_fi1$D_OUT[9:8] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1296 } : - { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d153, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1296 } ; - assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d282 = + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1318 } : + { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d164, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1318 } ; + assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d304 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[39:38] == 2'd2 : merge1_fi1$D_OUT[39:38] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d284 = + assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d306 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[39:38] == 2'd1 : merge1_fi1$D_OUT[39:38] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1297 } : - { IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d282, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1297 } ; - assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d292 = + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1319 } : + { IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d304, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1319 } ; + assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d314 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[29:28] == 2'd2 : merge1_fi1$D_OUT[29:28] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d294 = + assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d316 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[29:28] == 2'd1 : merge1_fi1$D_OUT[29:28] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1298 } : - { IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d292, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1298 } ; - assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d296 = - { IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1649 ? + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1320 } : + { IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d314, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1320 } ; + assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d318 = + { IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1673 ? { 2'd0, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1297 } : - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d284, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1630 ? + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1319 } : + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d306, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1652 ? { 2'd0, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1298 } : - IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d294 } ; - assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d303 = + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1320 } : + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d316 } ; + assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d325 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[19:18] == 2'd2 : merge1_fi1$D_OUT[19:18] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d305 = + assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d327 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[19:18] == 2'd1 : merge1_fi1$D_OUT[19:18] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1299 } : - { IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d303, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1299 } ; - assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d313 = + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1321 } : + { IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d325, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1321 } ; + assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d335 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[9:8] == 2'd2 : merge1_fi1$D_OUT[9:8] == 2'd2) ? 2'd2 : 2'd3 ; - assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d315 = + assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d337 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[9:8] == 2'd1 : merge1_fi1$D_OUT[9:8] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1300 } : - { IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d313, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1300 } ; - assign IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1309 = + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1322 } : + { IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d335, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1322 } ; + assign IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d1331 = { CASE_fork0_srcFD_OUT_BITS_39_TO_38_3_0_fork0__ETC__q41, fork0_srcF$D_OUT[37:30], CASE_fork0_srcFD_OUT_BITS_29_TO_28_3_0_fork0__ETC__q42, @@ -1593,7 +1607,7 @@ module mkQABSMF3(et0, fork0_srcF$D_OUT[17:10], CASE_fork0_srcFD_OUT_BITS_9_TO_8_3_0_fork0_sr_ETC__q44, fork0_srcF$D_OUT[7:0] } ; - assign IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1310 = + assign IF_fork1_srcF_first__17_BITS_39_TO_38_18_EQ_0__ETC___d1332 = { CASE_fork1_srcFD_OUT_BITS_39_TO_38_3_0_fork1__ETC__q45, fork1_srcF$D_OUT[37:30], CASE_fork1_srcFD_OUT_BITS_29_TO_28_3_0_fork1__ETC__q46, @@ -1602,86 +1616,106 @@ module mkQABSMF3(et0, fork1_srcF$D_OUT[17:10], CASE_fork1_srcFD_OUT_BITS_9_TO_8_3_0_fork1_sr_ETC__q48, fork1_srcF$D_OUT[7:0] } ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1293 = + assign IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d113 = + merge0_fi0HasPrio ? + !merge0_fi0$EMPTY_N || merge0_fi0$D_OUT[9:8] != 2'd0 : + !merge0_fi1$EMPTY_N || merge0_fi1$D_OUT[9:8] != 2'd0 ; + assign IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d1650 = + IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d113 || + (merge0_fi0HasPrio ? merge0_fi0$EMPTY_N : merge0_fi1$EMPTY_N) ; + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1315 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[37:30] : merge0_fi1$D_OUT[37:30] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1294 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1316 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[27:20] : merge0_fi1$D_OUT[27:20] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1295 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1317 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[17:10] : merge0_fi1$D_OUT[17:10] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1296 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1318 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[7:0] : merge0_fi1$D_OUT[7:0] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1626 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[29:28] == 2'd0 : merge0_fi1$D_OUT[29:28] == 2'd0 ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1627 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1649 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[19:18] == 2'd0 : merge0_fi1$D_OUT[19:18] == 2'd0 ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1628 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1651 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[9:8] == 2'd0 : merge0_fi1$D_OUT[9:8] == 2'd0 ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1672 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[39:38] == 2'd0 : merge0_fi1$D_OUT[39:38] == 2'd0 ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1297 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_i_notE_ETC___d118 = + merge0_fi0HasPrio ? + merge0_fi0$EMPTY_N && + IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d1650 : + merge0_fi1$EMPTY_N && + IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d1650 ; + assign IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d1654 = + IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d284 || + (merge1_fi0HasPrio ? merge1_fi0$EMPTY_N : merge1_fi1$EMPTY_N) ; + assign IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d284 = + merge1_fi0HasPrio ? + !merge1_fi0$EMPTY_N || merge1_fi0$D_OUT[9:8] != 2'd0 : + !merge1_fi1$EMPTY_N || merge1_fi1$D_OUT[9:8] != 2'd0 ; + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1319 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[37:30] : merge1_fi1$D_OUT[37:30] ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1298 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1320 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[27:20] : merge1_fi1$D_OUT[27:20] ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1299 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1321 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[17:10] : merge1_fi1$D_OUT[17:10] ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1300 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1322 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[7:0] : merge1_fi1$D_OUT[7:0] ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1630 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1652 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[29:28] == 2'd0 : merge1_fi1$D_OUT[29:28] == 2'd0 ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1631 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1653 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[19:18] == 2'd0 : merge1_fi1$D_OUT[19:18] == 2'd0 ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1632 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1655 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[9:8] == 2'd0 : merge1_fi1$D_OUT[9:8] == 2'd0 ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1649 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1673 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[39:38] == 2'd0 : merge1_fi1$D_OUT[39:38] == 2'd0 ; - assign NOT_fork0_stageSent_76_77_OR_fork0_srcF_i_notE_ETC___d483 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_i_notE_ETC___d289 = + merge1_fi0HasPrio ? + merge1_fi0$EMPTY_N && + IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d1654 : + merge1_fi1$EMPTY_N && + IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d1654 ; + assign NOT_fork0_stageSent_98_99_OR_fork0_srcF_i_notE_ETC___d505 = (!fork0_stageSent || fork0_srcF$EMPTY_N) && (fork0_match0 ? fork0_d0F$FULL_N : fork0_d1F$FULL_N) ; - assign NOT_fork1_stageSent_43_44_OR_fork1_srcF_i_notE_ETC___d750 = + assign NOT_fork1_stageSent_65_66_OR_fork1_srcF_i_notE_ETC___d772 = (!fork1_stageSent || fork1_srcF$EMPTY_N) && (fork1_match0 ? fork1_d0F$FULL_N : fork1_d1F$FULL_N) ; - assign fork0_ptr_68_PLUS_1___d1411 = fork0_ptr + 3'd1 ; - assign fork1_ptr_35_PLUS_1___d1412 = fork1_ptr + 3'd1 ; - assign merge0_fo_i_notFull_AND_IF_merge0_fi0HasPrio_0_ETC___d108 = - merge0_fo$FULL_N && - (merge0_fi0HasPrio ? merge0_fi0$EMPTY_N : merge0_fi1$EMPTY_N) ; - assign merge1_fo_i_notFull__62_AND_IF_merge1_fi0HasPr_ETC___d268 = - merge1_fo$FULL_N && - (merge1_fi0HasPrio ? merge1_fi0$EMPTY_N : merge1_fi1$EMPTY_N) ; - assign seen__h16118 = { fork0_srcF$D_OUT[7:0], fork0_srcF$D_OUT[17:10] } ; - assign seen__h26918 = { fork1_srcF$D_OUT[27:20], fork1_srcF$D_OUT[37:30] } ; + assign fork0_ptr_90_PLUS_1___d1433 = fork0_ptr + 3'd1 ; + assign fork1_ptr_57_PLUS_1___d1434 = fork1_ptr + 3'd1 ; + assign seen__h16174 = { fork0_srcF$D_OUT[7:0], fork0_srcF$D_OUT[17:10] } ; + assign seen__h26999 = { fork1_srcF$D_OUT[27:20], fork1_srcF$D_OUT[37:30] } ; always@(fork1_d1F$D_OUT) begin case (fork1_d1F$D_OUT[39:38]) @@ -1830,12 +1864,12 @@ module mkQABSMF3(et0, begin case (fork0_ptr) 3'd0: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1323 = fork0_sr[37:30]; 3'd1: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1323 = fork0_sr[77:70]; - default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 = + default: IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1323 = fork0_sr[117:110]; endcase end @@ -1882,12 +1916,12 @@ module mkQABSMF3(et0, begin case (fork0_ptr) 3'd0: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1324 = fork0_sr[27:20]; 3'd1: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1324 = fork0_sr[67:60]; - default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 = + default: IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1324 = fork0_sr[107:100]; endcase end @@ -1934,12 +1968,12 @@ module mkQABSMF3(et0, begin case (fork0_ptr) 3'd0: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1325 = fork0_sr[17:10]; 3'd1: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1325 = fork0_sr[57:50]; - default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 = + default: IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1325 = fork0_sr[97:90]; endcase end @@ -1986,12 +2020,12 @@ module mkQABSMF3(et0, begin case (fork0_ptr) 3'd0: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1326 = fork0_sr[7:0]; 3'd1: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 = + IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1326 = fork0_sr[47:40]; - default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 = + default: IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1326 = fork0_sr[87:80]; endcase end @@ -2038,12 +2072,12 @@ module mkQABSMF3(et0, begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1327 = fork1_sr[37:30]; 3'd1: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1327 = fork1_sr[77:70]; - default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 = + default: IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1327 = fork1_sr[117:110]; endcase end @@ -2090,12 +2124,12 @@ module mkQABSMF3(et0, begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1328 = fork1_sr[27:20]; 3'd1: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1328 = fork1_sr[67:60]; - default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 = + default: IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1328 = fork1_sr[107:100]; endcase end @@ -2142,12 +2176,12 @@ module mkQABSMF3(et0, begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1329 = fork1_sr[17:10]; 3'd1: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1329 = fork1_sr[57:50]; - default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 = + default: IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1329 = fork1_sr[97:90]; endcase end @@ -2194,12 +2228,12 @@ module mkQABSMF3(et0, begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1330 = fork1_sr[7:0]; 3'd1: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 = + IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1330 = fork1_sr[47:40]; - default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 = + default: IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1330 = fork1_sr[87:80]; endcase end @@ -2823,7 +2857,7 @@ module mkQABSMF3(et0, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin fork0_decided <= `BSV_ASSIGNMENT_DELAY 1'd0; fork0_match0 <= `BSV_ASSIGNMENT_DELAY 1'd0; diff --git a/rtl/mkQBGMAC.v b/rtl/mkQBGMAC.v index 1e7e6cda..748f4803 100644 --- a/rtl/mkQBGMAC.v +++ b/rtl/mkQBGMAC.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:37:58 EDT 2012 +// On Mon Sep 24 15:03:06 EDT 2012 // // // Ports: @@ -48,7 +48,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkQBGMAC(CLK_rxClk, @@ -302,7 +310,7 @@ module mkQBGMAC(CLK_rxClk, wire WILL_FIRE_RL_rxfun_unfunnel; // remaining internal signals - reg [7 : 0] IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d375; + reg [7 : 0] IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d373; reg [1 : 0] CASE_gmacrx_get_BITS_9_TO_8_3_0_gmacrx_get_B_ETC__q16, CASE_rxFdD_OUT_BITS_19_TO_18_3_0_rxFdD_OUT_B_ETC__q3, CASE_rxFdD_OUT_BITS_29_TO_28_3_0_rxFdD_OUT_B_ETC__q2, @@ -331,9 +339,9 @@ module mkQBGMAC(CLK_rxClk, IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454; wire [9 : 0] IF_IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__ETC___d126, IF_IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__ETC___d127, - IF_rxfun_inF_first__1_BITS_9_TO_8_2_EQ_0_3_OR__ETC___d376, - IF_rxfun_sr_8_BITS_19_TO_18_9_EQ_0_0_OR_rxfun__ETC___d378, - IF_rxfun_sr_8_BITS_9_TO_8_0_EQ_0_1_OR_rxfun_sr_ETC___d377; + IF_rxfun_inF_first__1_BITS_9_TO_8_2_EQ_0_3_OR__ETC___d374, + IF_rxfun_sr_8_BITS_19_TO_18_9_EQ_0_0_OR_rxfun__ETC___d376, + IF_rxfun_sr_8_BITS_9_TO_8_0_EQ_0_1_OR_rxfun_sr_ETC___d375; // oscillator and gates for output clock CLK_gmii_tx_tx_clk assign CLK_gmii_tx_tx_clk = gmac$CLK_gmii_tx_tx_clk ; @@ -427,7 +435,7 @@ module mkQBGMAC(CLK_rxClk, // submodule ovfBit SyncBit #(.init(1'd0)) ovfBit(.sCLK(CLK_txClk), .dCLK(CLK), - .sRST_N(RST_N_gmRst), + .sRST(RST_N_gmRst), .sD_IN(ovfBit$sD_IN), .sEN(ovfBit$sEN), .dD_OUT()); @@ -437,7 +445,7 @@ module mkQBGMAC(CLK_rxClk, .depth(32'd8), .indxWidth(32'd3)) rxF(.sCLK(CLK_txClk), .dCLK(CLK), - .sRST_N(RST_N_gmRst), + .sRST(RST_N_gmRst), .sD_IN(rxF$sD_IN), .sENQ(rxF$sENQ), .dDEQ(rxF$dDEQ), @@ -448,13 +456,13 @@ module mkQBGMAC(CLK_rxClk, // submodule rxOper SyncBit #(.init(1'd0)) rxOper(.sCLK(CLK), .dCLK(CLK_txClk), - .sRST_N(RST_N), + .sRST(RST_N), .sD_IN(rxOper$sD_IN), .sEN(rxOper$sEN), .dD_OUT(rxOper$dD_OUT)); // submodule rxfun_inF - FIFO2 #(.width(32'd10), .guarded(32'd1)) rxfun_inF(.RST_N(RST_N_gmRst), + FIFO2 #(.width(32'd10), .guarded(32'd1)) rxfun_inF(.RST(RST_N_gmRst), .CLK(CLK_txClk), .D_IN(rxfun_inF$D_IN), .ENQ(rxfun_inF$ENQ), @@ -465,7 +473,7 @@ module mkQBGMAC(CLK_rxClk, .EMPTY_N(rxfun_inF$EMPTY_N)); // submodule rxfun_outF - FIFO2 #(.width(32'd40), .guarded(32'd1)) rxfun_outF(.RST_N(RST_N_gmRst), + FIFO2 #(.width(32'd40), .guarded(32'd1)) rxfun_outF(.RST(RST_N_gmRst), .CLK(CLK_txClk), .D_IN(rxfun_outF$D_IN), .ENQ(rxfun_outF$ENQ), @@ -480,7 +488,7 @@ module mkQBGMAC(CLK_rxClk, .depth(32'd8), .indxWidth(32'd3)) txF(.sCLK(CLK), .dCLK(CLK_txClk), - .sRST_N(RST_N), + .sRST(RST_N), .sD_IN(txF$sD_IN), .sENQ(txF$sENQ), .dDEQ(txF$dDEQ), @@ -491,13 +499,13 @@ module mkQBGMAC(CLK_rxClk, // submodule txOper SyncBit #(.init(1'd0)) txOper(.sCLK(CLK), .dCLK(CLK_txClk), - .sRST_N(RST_N), + .sRST(RST_N), .sD_IN(txOper$sD_IN), .sEN(txOper$sEN), .dD_OUT(txOper$dD_OUT)); // submodule txfun_inF - FIFO2 #(.width(32'd40), .guarded(32'd1)) txfun_inF(.RST_N(RST_N_gmRst), + FIFO2 #(.width(32'd40), .guarded(32'd1)) txfun_inF(.RST(RST_N_gmRst), .CLK(CLK_txClk), .D_IN(txfun_inF$D_IN), .ENQ(txfun_inF$ENQ), @@ -508,7 +516,7 @@ module mkQBGMAC(CLK_rxClk, .EMPTY_N(txfun_inF$EMPTY_N)); // submodule txfun_outF - FIFO2 #(.width(32'd10), .guarded(32'd1)) txfun_outF(.RST_N(RST_N_gmRst), + FIFO2 #(.width(32'd10), .guarded(32'd1)) txfun_outF(.RST(RST_N_gmRst), .CLK(CLK_txClk), .D_IN(txfun_outF$D_IN), .ENQ(txfun_outF$ENQ), @@ -521,7 +529,7 @@ module mkQBGMAC(CLK_rxClk, // submodule unfBit SyncBit #(.init(1'd0)) unfBit(.sCLK(CLK_txClk), .dCLK(CLK), - .sRST_N(RST_N_gmRst), + .sRST(RST_N_gmRst), .sD_IN(unfBit$sD_IN), .sEN(unfBit$sEN), .dD_OUT()); @@ -549,9 +557,9 @@ module mkQBGMAC(CLK_rxClk, // register rxfun_sr assign rxfun_sr$D_IN = - { IF_rxfun_sr_8_BITS_19_TO_18_9_EQ_0_0_OR_rxfun__ETC___d378, - IF_rxfun_sr_8_BITS_9_TO_8_0_EQ_0_1_OR_rxfun_sr_ETC___d377, - IF_rxfun_inF_first__1_BITS_9_TO_8_2_EQ_0_3_OR__ETC___d376 } ; + { IF_rxfun_sr_8_BITS_19_TO_18_9_EQ_0_0_OR_rxfun__ETC___d376, + IF_rxfun_sr_8_BITS_9_TO_8_0_EQ_0_1_OR_rxfun_sr_ETC___d375, + IF_rxfun_inF_first__1_BITS_9_TO_8_2_EQ_0_3_OR__ETC___d374 } ; assign rxfun_sr$EN = WILL_FIRE_RL_rxfun_unfunnel ; // register txOperD @@ -611,9 +619,9 @@ module mkQBGMAC(CLK_rxClk, // submodule rxfun_outF assign rxfun_outF$D_IN = - { IF_rxfun_inF_first__1_BITS_9_TO_8_2_EQ_0_3_OR__ETC___d376, - IF_rxfun_sr_8_BITS_9_TO_8_0_EQ_0_1_OR_rxfun_sr_ETC___d377, - IF_rxfun_sr_8_BITS_19_TO_18_9_EQ_0_0_OR_rxfun__ETC___d378, + { IF_rxfun_inF_first__1_BITS_9_TO_8_2_EQ_0_3_OR__ETC___d374, + IF_rxfun_sr_8_BITS_9_TO_8_0_EQ_0_1_OR_rxfun_sr_ETC___d375, + IF_rxfun_sr_8_BITS_19_TO_18_9_EQ_0_0_OR_rxfun__ETC___d376, CASE_rxfun_sr_BITS_29_TO_28_3_0_rxfun_sr_BITS__ETC__q15, rxfun_sr[27:20] } ; assign rxfun_outF$ENQ = @@ -660,7 +668,7 @@ module mkQBGMAC(CLK_rxClk, assign txfun_outF$D_IN = CASE_txfun_ptr_txfun_ptr_EQ_3_AND_txfun_inFD__ETC__q25 ? { 2'd0, - IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d375 } : + IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d373 } : IF_IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__ETC___d127 ; assign txfun_outF$ENQ = txfun_inF$EMPTY_N && txfun_outF$FULL_N ; assign txfun_outF$DEQ = gmac$RDY_tx_put && txfun_outF$EMPTY_N ; @@ -675,19 +683,19 @@ module mkQBGMAC(CLK_rxClk, { CASE_txfun_ptr_txfun_ptr_EQ_3_AND_txfun_inFD__ETC__q8 ? 2'd2 : 2'd3, - IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d375 } ; + IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d373 } ; assign IF_IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__ETC___d127 = CASE_txfun_ptr_txfun_ptr_EQ_3_AND_txfun_inFD__ETC__q9 ? { 2'd1, - IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d375 } : + IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d373 } : IF_IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__ETC___d126 ; - assign IF_rxfun_inF_first__1_BITS_9_TO_8_2_EQ_0_3_OR__ETC___d376 = + assign IF_rxfun_inF_first__1_BITS_9_TO_8_2_EQ_0_3_OR__ETC___d374 = { CASE_rxfun_inFD_OUT_BITS_9_TO_8_3_0_rxfun_inF_ETC__q7, rxfun_inF$D_OUT[7:0] } ; - assign IF_rxfun_sr_8_BITS_19_TO_18_9_EQ_0_0_OR_rxfun__ETC___d378 = + assign IF_rxfun_sr_8_BITS_19_TO_18_9_EQ_0_0_OR_rxfun__ETC___d376 = { CASE_rxfun_sr_BITS_19_TO_18_3_0_rxfun_sr_BITS__ETC__q6, rxfun_sr[17:10] } ; - assign IF_rxfun_sr_8_BITS_9_TO_8_0_EQ_0_1_OR_rxfun_sr_ETC___d377 = + assign IF_rxfun_sr_8_BITS_9_TO_8_0_EQ_0_1_OR_rxfun_sr_ETC___d375 = { CASE_rxfun_sr_BITS_9_TO_8_3_0_rxfun_sr_BITS_9__ETC__q5, rxfun_sr[7:0] } ; always@(rxF$dD_OUT) @@ -774,16 +782,16 @@ module mkQBGMAC(CLK_rxClk, begin case (txfun_ptr) 2'd0: - IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d375 = + IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d373 = txfun_inF$D_OUT[7:0]; 2'd1: - IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d375 = + IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d373 = txfun_inF$D_OUT[17:10]; 2'd2: - IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d375 = + IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d373 = txfun_inF$D_OUT[27:20]; 2'd3: - IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d375 = + IF_txfun_ptr_0_EQ_0_1_THEN_txfun_inF_first__2__ETC___d373 = txfun_inF$D_OUT[37:30]; endcase end @@ -978,7 +986,7 @@ module mkQBGMAC(CLK_rxClk, always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin rxOperD <= `BSV_ASSIGNMENT_DELAY 1'd0; txOperD <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -992,7 +1000,7 @@ module mkQBGMAC(CLK_rxClk, always@(posedge CLK_txClk) begin - if (!RST_N_gmRst) + if (RST_N_gmRst == `BSV_RESET_VALUE) begin rxfun_ptr <= `BSV_ASSIGNMENT_DELAY 2'd0; txfun_ptr <= `BSV_ASSIGNMENT_DELAY 2'd0; diff --git a/rtl/mkSMAdapter16B.v b/rtl/mkSMAdapter16B.v index 203d6bf8..8796814b 100644 --- a/rtl/mkSMAdapter16B.v +++ b/rtl/mkSMAdapter16B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:28 EDT 2012 +// On Mon Sep 24 15:03:43 EDT 2012 // // // Ports: @@ -64,7 +64,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkSMAdapter16B(wciS0_Clk, @@ -990,83 +998,83 @@ module mkSMAdapter16B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h18191, - v__h21903, - v__h21962, - v__h23796, - v__h23979, - v__h24175, - v__h24833, - v__h3651, - v__h3825, - v__h3969; - reg [31 : 0] g_data__h24345; - wire [163 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d919; - wire [31 : 0] rdat__h24388, - rdat__h24394, - rdat__h24400, - rdat__h24413, - rdat__h24436, - rdat__h24536, - rdat__h24550, - rdat__h24558, - rdat__h24564, - rdat__h24578, - rdat__h24586, - rdat__h24592, - rdat__h24598, - rdat__h24604, - rdat__h24610, - rdat__h24620, - value__h6580, - x__h18791; - wire [23 : 0] b__h17902, - mesgMetaF_length__h22484, - residue__h17765, - x__h18022; - wire [15 : 0] sendData_byteEn__h18734, - wsiBurstLength__h18650, - x__h24440, - x_length__h23376; - wire [13 : 0] b__h18275, mlB__h22317, mlInc__h22316; - wire [11 : 0] b__h15090, sendData_burstLength__h18732, x__h16444; - wire [7 : 0] mesgMetaF_opcode__h22483; - wire [4 : 0] x__h22523, - x__h22535, - x__h22547, - x__h22559, - x__h22571, - x__h22583, - x__h22595, - x__h22607, - x__h22619, - x__h22631, - x__h22643, - x__h22655, - x__h22667, - x__h22679, - x__h22691, - y__h22524, - y__h22536, - y__h22548, - y__h22560, - y__h22572, - y__h22584, - y__h22596, - y__h22608, - y__h22620, - y__h22632, - y__h22644, - y__h22656, - y__h22668, - y__h22680, - y__h22692; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d916; + reg [63 : 0] v__h18699, + v__h22418, + v__h22477, + v__h24317, + v__h24500, + v__h24696, + v__h25358, + v__h3729, + v__h3904, + v__h4048; + reg [31 : 0] g_data__h24868; + wire [163 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d930; + wire [31 : 0] rdat__h24911, + rdat__h24917, + rdat__h24923, + rdat__h24936, + rdat__h24959, + rdat__h25059, + rdat__h25073, + rdat__h25081, + rdat__h25087, + rdat__h25101, + rdat__h25109, + rdat__h25115, + rdat__h25121, + rdat__h25127, + rdat__h25133, + rdat__h25143, + value__h6702, + x__h19302; + wire [23 : 0] b__h18410, + mesgMetaF_length__h22999, + residue__h18273, + x__h18530; + wire [15 : 0] sendData_byteEn__h19245, + wsiBurstLength__h19161, + x__h24963, + x_length__h23891; + wire [13 : 0] b__h18783, mlB__h22832, mlInc__h22831; + wire [11 : 0] b__h15473, sendData_burstLength__h19243, x__h16878; + wire [7 : 0] mesgMetaF_opcode__h22998; + wire [4 : 0] x__h23038, + x__h23050, + x__h23062, + x__h23074, + x__h23086, + x__h23098, + x__h23110, + x__h23122, + x__h23134, + x__h23146, + x__h23158, + x__h23170, + x__h23182, + x__h23194, + x__h23206, + y__h23039, + y__h23051, + y__h23063, + y__h23075, + y__h23087, + y__h23099, + y__h23111, + y__h23123, + y__h23135, + y__h23147, + y__h23159, + y__h23171, + y__h23183, + y__h23195, + y__h23207; + wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d918; wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542, wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670, - x__h18446, - x__h24614; + x__h18954, + x__h25137; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1151,7 +1159,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ; // submodule mesgTokenF - FIFO10 #(.guarded(32'd1)) mesgTokenF(.RST_N(wciS0_MReset_n), + FIFO10 #(.guarded(32'd1)) mesgTokenF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .ENQ(mesgTokenF$ENQ), .DEQ(mesgTokenF$DEQ), @@ -1180,7 +1188,7 @@ module mkSMAdapter16B(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -1191,7 +1199,7 @@ module mkSMAdapter16B(wciS0_Clk, .EMPTY_N(wci_wslv_reqF$EMPTY_N)); // submodule wmi_respF - FIFO2 #(.width(32'd130), .guarded(32'd1)) wmi_respF(.RST_N(wciS0_MReset_n), + FIFO2 #(.width(32'd130), .guarded(32'd1)) wmi_respF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wmi_respF$D_IN), .ENQ(wmi_respF$ENQ), @@ -1205,7 +1213,7 @@ module mkSMAdapter16B(wciS0_Clk, SizedFIFO #(.p1width(32'd169), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wsiS_reqFifo$D_IN), .ENQ(wsiS_reqFifo$ENQ), @@ -1232,6 +1240,40 @@ module mkSMAdapter16B(wciS0_Clk, smaCtrl[3:0] == 4'h9) && mesgPreRequest ; + // rule RL_wci_wslv_ctl_op_start + assign WILL_FIRE_RL_wci_wslv_ctl_op_start = + wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd2 && + wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_wmi_reqF_deq + assign WILL_FIRE_RL_wmi_reqF_deq = + wmi_operateD && wmi_peerIsReady && !wmi_sThreadBusy_d ; + + // rule RL_wsiM_reqFifo_deq + assign WILL_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + + // rule RL_wsipass_doMessagePush + assign WILL_FIRE_RL_wsipass_doMessagePush = + wsiS_reqFifo$EMPTY_N && + (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && + wci_wslv_cState == 3'd2 && + smaCtrl[3:0] == 4'h0 ; + // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && @@ -1248,13 +1290,6 @@ module mkSMAdapter16B(wciS0_Clk, !wmi_sDataThreadBusy_d && unrollCnt == 16'd0 ; - // rule RL_wsipass_doMessagePush - assign WILL_FIRE_RL_wsipass_doMessagePush = - wsiS_reqFifo$EMPTY_N && - (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && - wci_wslv_cState == 3'd2 && - smaCtrl[3:0] == 4'h0 ; - // rule RL_wmrd_mesgBodyResponse assign WILL_FIRE_RL_wmrd_mesgBodyResponse = wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && @@ -1297,29 +1332,6 @@ module mkSMAdapter16B(wciS0_Clk, !doAbort && endOfMessage ; - // rule RL_wci_wslv_ctl_op_start - assign WILL_FIRE_RL_wci_wslv_ctl_op_start = - wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && - !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - - // rule RL_wci_ctrl_EiI - assign WILL_FIRE_RL_wci_ctrl_EiI = - wci_wslv_wci_ctrl_pw$whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF$D_OUT[36:34] == 3'd0 ; - - // rule RL_wci_ctrl_OrE - assign WILL_FIRE_RL_wci_ctrl_OrE = - wci_wslv_wci_ctrl_pw$whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd2 && - wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; - - // rule RL_wmi_reqF_deq - assign WILL_FIRE_RL_wmi_reqF_deq = - wmi_operateD && wmi_peerIsReady && !wmi_sThreadBusy_d ; - // rule RL_wmi_reqF_incCtr assign WILL_FIRE_RL_wmi_reqF_incCtr = ((wmi_reqF_c_r == 2'd0) ? @@ -1383,10 +1395,6 @@ module mkSMAdapter16B(wciS0_Clk, wmi_dhF_dequeueing$whas && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - // rule RL_wsiM_reqFifo_deq - assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; - // rule RL_wmrd_mesgResptoWsi assign WILL_FIRE_RL_wmrd_mesgResptoWsi = wsiM_reqFifo_c_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && @@ -1499,7 +1507,7 @@ module mkSMAdapter16B(wciS0_Clk, assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ; assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 ; + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 ; assign MUX_wmi_reqF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ; assign MUX_wmi_reqF_q_1$write_1__SEL_2 = @@ -1518,23 +1526,23 @@ module mkSMAdapter16B(wciS0_Clk, !WILL_FIRE_RL_wmwt_messageFinalize ; assign MUX_fabRespCredit_value$write_1__VAL_2 = fabRespCredit_value + - (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15090 : 12'd0) + + (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15473 : 12'd0) + (WILL_FIRE_RL_wmrd_mesgResptoWsi ? 12'd1 : 12'd0) ; assign MUX_fabWordsRemain$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17902[13:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h18410[13:0] ; assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; assign MUX_mesgCount$write_1__VAL_1 = mesgCount + 32'd1 ; assign MUX_mesgLengthSoFar$write_1__VAL_1 = - mesgLengthSoFar + mlInc__h22316 ; + mesgLengthSoFar + mlInc__h22831 ; assign MUX_mesgReqAddr$write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[9:0], 4'd0 } ; assign MUX_opcode$write_1__VAL_3 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ; assign MUX_thisMesg$write_1__VAL_1 = - { mesgCount[7:0], mesgMetaF_opcode__h22483, x_length__h23376 } ; + { mesgCount[7:0], mesgMetaF_opcode__h22998, x_length__h23891 } ; assign MUX_thisMesg$write_1__VAL_2 = { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; assign MUX_unrollCnt$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h17902[15:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h18410[15:0] ; assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && @@ -1570,7 +1578,7 @@ module mkSMAdapter16B(wciS0_Clk, 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24345 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24868 } ; assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r + 2'd1 ; assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ; assign MUX_wmi_dhF_q_0$write_1__VAL_1 = @@ -1584,11 +1592,11 @@ module mkSMAdapter16B(wciS0_Clk, assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ; assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ; assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd1) ? value__h6580 : wmi_mFlagF_q_1 ; + (wmi_mFlagF_c_r == 2'd1) ? value__h6702 : wmi_mFlagF_q_1 ; assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd2) ? value__h6580 : 32'd0 ; + (wmi_mFlagF_c_r == 2'd2) ? value__h6702 : 32'd0 ; assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 = - { mesgMetaF_opcode__h22483, mesgMetaF_length__h22484 } ; + { mesgMetaF_opcode__h22998, mesgMetaF_length__h22999 } ; assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r + 2'd1 ; assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r - 2'd1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_1 = @@ -1604,7 +1612,7 @@ module mkSMAdapter16B(wciS0_Clk, MUX_wmi_reqF_q_0$write_1__VAL_2 : 32'd0 ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_1 = - { 4'd5, x__h18446, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; + { 4'd5, x__h18954, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_2 = { 4'd3, wsiS_reqFifo$D_OUT[165], 1'b0, mesgLengthSoFar, 12'd1 } ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; @@ -1661,7 +1669,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_reqF_x_wire$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - assign wmi_mFlagF_x_wire$wget = value__h6580 ; + assign wmi_mFlagF_x_wire$wget = value__h6702 ; assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ; assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_2 ; assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; @@ -1697,7 +1705,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; assign wsiS_sThreadBusy_dw$whas = wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; - assign fabRespCredit_acc_v1$wget = b__h15090 ; + assign fabRespCredit_acc_v1$wget = b__h15473 ; assign fabRespCredit_acc_v1$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign fabRespCredit_acc_v2$wget = 12'd1 ; assign fabRespCredit_acc_v2$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; @@ -1707,9 +1715,9 @@ module mkSMAdapter16B(wciS0_Clk, { 3'd1, unrollCnt == 16'd1, !smaCtrl[5], - sendData_burstLength__h18732, + sendData_burstLength__h19243, wmi_respF$D_OUT[127:0], - sendData_byteEn__h18734, + sendData_byteEn__h19245, thisMesg[23:16] } ; assign respF_wDataIn$whas = respF_pwEnqueue$whas ; assign respF_wDataOut$wget = MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; @@ -1753,7 +1761,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_reqF_dequeueing$whas = WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'd0 ; assign wmi_mFlagF_enqueueing$whas = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 || + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[165] ; assign wmi_mFlagF_dequeueing$whas = @@ -1822,7 +1830,7 @@ module mkSMAdapter16B(wciS0_Clk, // register fabWordsCurReq assign fabWordsCurReq$D_IN = - (fabWordsRemain <= b__h18275) ? fabWordsRemain : b__h18275 ; + (fabWordsRemain <= b__h18783) ? fabWordsRemain : b__h18783 ; assign fabWordsCurReq$EN = MUX_mesgReqOK$write_1__SEL_3 ; // register fabWordsRemain @@ -1929,14 +1937,14 @@ module mkSMAdapter16B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d916, + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d918, respF_pwEnqueue$whas && respF_wDataIn$wget[165], respF_pwEnqueue$whas && respF_wDataIn$wget[164], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d919 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d930 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr - assign respF_rRdPtr$D_IN = x__h16444 ; + assign respF_rRdPtr$D_IN = x__h16878 ; assign respF_rRdPtr$EN = WILL_FIRE_RL_wmrd_mesgResptoWsi ; // register respF_rWrPtr @@ -2186,12 +2194,12 @@ module mkSMAdapter16B(wciS0_Clk, always@(WILL_FIRE_RL_wmi_mFlagF_both or MUX_wmi_mFlagF_q_0$write_1__VAL_1 or MUX_wmi_mFlagF_q_0$write_1__SEL_2 or - value__h6580 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_mFlagF_both: wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_1; - MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6580; + MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6702; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1; default: wmi_mFlagF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -2205,12 +2213,12 @@ module mkSMAdapter16B(wciS0_Clk, always@(WILL_FIRE_RL_wmi_mFlagF_both or MUX_wmi_mFlagF_q_1$write_1__VAL_1 or MUX_wmi_mFlagF_q_1$write_1__SEL_2 or - value__h6580 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_mFlagF_both: wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_1; - MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6580; + MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6702; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0; default: wmi_mFlagF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -2532,13 +2540,13 @@ module mkSMAdapter16B(wciS0_Clk, assign respF_memory$ADDRA = respF_rWrPtr[10:0] ; assign respF_memory$ADDRB = WILL_FIRE_RL_wmrd_mesgResptoWsi ? - x__h16444[10:0] : + x__h16878[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d916, + { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d918, respF_pwEnqueue$whas && respF_wDataIn$wget[165], respF_pwEnqueue$whas && respF_wDataIn$wget[164], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d919 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d930 } ; assign respF_memory$DIB = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; @@ -2567,70 +2575,70 @@ module mkSMAdapter16B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d916 = + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d918 = respF_pwEnqueue$whas ? respF_wDataIn$wget[168:166] : 3'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d919 = + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d930 = respF_pwEnqueue$whas ? respF_wDataIn$wget[163:0] : 164'd0 ; assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && - (!x__h18446 || wmi_mFlagF_c_r != 2'd2) ; - assign b__h15090 = -fabWordsCurReq[11:0] ; - assign b__h17902 = x__h18022 + residue__h17765 ; - assign b__h18275 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; - assign mesgMetaF_length__h22484 = + (!x__h18954 || wmi_mFlagF_c_r != 2'd2) ; + assign b__h15473 = -fabWordsCurReq[11:0] ; + assign b__h18410 = x__h18530 + residue__h18273 ; + assign b__h18783 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; + assign mesgMetaF_length__h22999 = (wsiS_reqFifo$D_OUT[165] && wsiS_reqFifo$D_OUT[23:8] == 16'd0 && mesgLengthSoFar == 14'd0) ? 24'd0 : - { 10'd0, mlB__h22317 } ; - assign mesgMetaF_opcode__h22483 = opcode[8] ? opcode[7:0] : 8'd0 ; - assign mlB__h22317 = MUX_mesgLengthSoFar$write_1__VAL_1 ; - assign mlInc__h22316 = + { 10'd0, mlB__h22832 } ; + assign mesgMetaF_opcode__h22998 = opcode[8] ? opcode[7:0] : 8'd0 ; + assign mlB__h22832 = MUX_mesgLengthSoFar$write_1__VAL_1 ; + assign mlInc__h22831 = wsiS_reqFifo$D_OUT[165] ? - { 9'd0, x__h22523 + y__h22524 } : + { 9'd0, x__h23038 + y__h23039 } : 14'd16 ; - assign rdat__h24388 = hasDebugLogic ? mesgCount : 32'd0 ; - assign rdat__h24394 = hasDebugLogic ? abortCount : 32'd0 ; - assign rdat__h24400 = hasDebugLogic ? thisMesg : 32'd0 ; - assign rdat__h24413 = hasDebugLogic ? lastMesg : 32'd0 ; - assign rdat__h24436 = hasDebugLogic ? { 16'd0, x__h24440 } : 32'd0 ; - assign rdat__h24536 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h24550 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h24558 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h24564 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h24578 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h24586 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h24592 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; - assign rdat__h24598 = hasDebugLogic ? wmwtPushCount : 32'd0 ; - assign rdat__h24604 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; - assign rdat__h24610 = hasDebugLogic ? { 31'd0, x__h24614 } : 32'd0 ; - assign rdat__h24620 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; - assign residue__h17765 = + assign rdat__h24911 = hasDebugLogic ? mesgCount : 32'd0 ; + assign rdat__h24917 = hasDebugLogic ? abortCount : 32'd0 ; + assign rdat__h24923 = hasDebugLogic ? thisMesg : 32'd0 ; + assign rdat__h24936 = hasDebugLogic ? lastMesg : 32'd0 ; + assign rdat__h24959 = hasDebugLogic ? { 16'd0, x__h24963 } : 32'd0 ; + assign rdat__h25059 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h25073 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h25081 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h25087 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h25101 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h25109 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h25115 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; + assign rdat__h25121 = hasDebugLogic ? wmwtPushCount : 32'd0 ; + assign rdat__h25127 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; + assign rdat__h25133 = hasDebugLogic ? { 31'd0, x__h25137 } : 32'd0 ; + assign rdat__h25143 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; + assign residue__h18273 = ({ 2'd0, wmi_sFlagReg[3:0] } == 6'd0) ? 24'd0 : 24'd1 ; - assign sendData_burstLength__h18732 = + assign sendData_burstLength__h19243 = (thisMesg[15:0] == 16'd0 || smaCtrl[5] && unrollCnt == 16'd1) ? 12'd1 : - (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h18650[11:0]) ; - assign sendData_byteEn__h18734 = + (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h19161[11:0]) ; + assign sendData_byteEn__h19245 = (thisMesg[15:0] == 16'd0) ? thisMesg[15:0] : - ((unrollCnt == 16'd1) ? x__h18791[15:0] : 16'd65535) ; - assign value__h6580 = + ((unrollCnt == 16'd1) ? x__h19302[15:0] : 16'd65535) ; + assign value__h6702 = MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 ? 32'hAAAAAAAA /* unspecified value */ : MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 ; assign wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 = wmi_respF$EMPTY_N && (smaCtrl[4] || respF_rRdPtr + 12'd1024 != respF_rWrPtr) ; - assign wsiBurstLength__h18650 = + assign wsiBurstLength__h19161 = smaCtrl[5] ? 16'd2 : { 4'd0, thisMesg[15:4] } ; assign wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670 = wsiS_reqFifo$EMPTY_N && (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_c_r != 2'd2) && (!wsiS_reqFifo$D_OUT[165] || wmi_mFlagF_c_r != 2'd2) ; - assign x__h16444 = respF_rRdPtr + 12'd1 ; - assign x__h18022 = { 4'd0, wmi_sFlagReg[23:4] } ; - assign x__h18446 = fabWordsRemain == fabWordsCurReq ; - assign x__h18791 = + assign x__h16878 = respF_rRdPtr + 12'd1 ; + assign x__h18530 = { 4'd0, wmi_sFlagReg[23:4] } ; + assign x__h18954 = fabWordsRemain == fabWordsCurReq ; + assign x__h19302 = ({ 2'd0, thisMesg[3:0] } == 6'd0) ? 32'hFFFFFFFF : (({ 2'd0, thisMesg[3:0] } <= 6'd1) ? @@ -2737,74 +2745,74 @@ module mkSMAdapter16B(wciS0_Clk, 6'd31) ? 32'h7FFFFFFF : 32'hFFFFFFFF))))))))))))))))))))))))))))))) ; - assign x__h22523 = x__h22535 + y__h22536 ; - assign x__h22535 = x__h22547 + y__h22548 ; - assign x__h22547 = x__h22559 + y__h22560 ; - assign x__h22559 = x__h22571 + y__h22572 ; - assign x__h22571 = x__h22583 + y__h22584 ; - assign x__h22583 = x__h22595 + y__h22596 ; - assign x__h22595 = x__h22607 + y__h22608 ; - assign x__h22607 = x__h22619 + y__h22620 ; - assign x__h22619 = x__h22631 + y__h22632 ; - assign x__h22631 = x__h22643 + y__h22644 ; - assign x__h22643 = x__h22655 + y__h22656 ; - assign x__h22655 = x__h22667 + y__h22668 ; - assign x__h22667 = x__h22679 + y__h22680 ; - assign x__h22679 = x__h22691 + y__h22692 ; - assign x__h22691 = { 4'd0, wsiS_reqFifo$D_OUT[23] } ; - assign x__h24440 = { wsiS_statusR, wsiM_statusR } ; - assign x__h24614 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; - assign x_length__h23376 = { 2'd0, mlB__h22317 } ; - assign y__h22524 = { 4'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h22536 = { 4'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h22548 = { 4'd0, wsiS_reqFifo$D_OUT[10] } ; - assign y__h22560 = { 4'd0, wsiS_reqFifo$D_OUT[11] } ; - assign y__h22572 = { 4'd0, wsiS_reqFifo$D_OUT[12] } ; - assign y__h22584 = { 4'd0, wsiS_reqFifo$D_OUT[13] } ; - assign y__h22596 = { 4'd0, wsiS_reqFifo$D_OUT[14] } ; - assign y__h22608 = { 4'd0, wsiS_reqFifo$D_OUT[15] } ; - assign y__h22620 = { 4'd0, wsiS_reqFifo$D_OUT[16] } ; - assign y__h22632 = { 4'd0, wsiS_reqFifo$D_OUT[17] } ; - assign y__h22644 = { 4'd0, wsiS_reqFifo$D_OUT[18] } ; - assign y__h22656 = { 4'd0, wsiS_reqFifo$D_OUT[19] } ; - assign y__h22668 = { 4'd0, wsiS_reqFifo$D_OUT[20] } ; - assign y__h22680 = { 4'd0, wsiS_reqFifo$D_OUT[21] } ; - assign y__h22692 = { 4'd0, wsiS_reqFifo$D_OUT[22] } ; + assign x__h23038 = x__h23050 + y__h23051 ; + assign x__h23050 = x__h23062 + y__h23063 ; + assign x__h23062 = x__h23074 + y__h23075 ; + assign x__h23074 = x__h23086 + y__h23087 ; + assign x__h23086 = x__h23098 + y__h23099 ; + assign x__h23098 = x__h23110 + y__h23111 ; + assign x__h23110 = x__h23122 + y__h23123 ; + assign x__h23122 = x__h23134 + y__h23135 ; + assign x__h23134 = x__h23146 + y__h23147 ; + assign x__h23146 = x__h23158 + y__h23159 ; + assign x__h23158 = x__h23170 + y__h23171 ; + assign x__h23170 = x__h23182 + y__h23183 ; + assign x__h23182 = x__h23194 + y__h23195 ; + assign x__h23194 = x__h23206 + y__h23207 ; + assign x__h23206 = { 4'd0, wsiS_reqFifo$D_OUT[23] } ; + assign x__h24963 = { wsiS_statusR, wsiM_statusR } ; + assign x__h25137 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; + assign x_length__h23891 = { 2'd0, mlB__h22832 } ; + assign y__h23039 = { 4'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h23051 = { 4'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h23063 = { 4'd0, wsiS_reqFifo$D_OUT[10] } ; + assign y__h23075 = { 4'd0, wsiS_reqFifo$D_OUT[11] } ; + assign y__h23087 = { 4'd0, wsiS_reqFifo$D_OUT[12] } ; + assign y__h23099 = { 4'd0, wsiS_reqFifo$D_OUT[13] } ; + assign y__h23111 = { 4'd0, wsiS_reqFifo$D_OUT[14] } ; + assign y__h23123 = { 4'd0, wsiS_reqFifo$D_OUT[15] } ; + assign y__h23135 = { 4'd0, wsiS_reqFifo$D_OUT[16] } ; + assign y__h23147 = { 4'd0, wsiS_reqFifo$D_OUT[17] } ; + assign y__h23159 = { 4'd0, wsiS_reqFifo$D_OUT[18] } ; + assign y__h23171 = { 4'd0, wsiS_reqFifo$D_OUT[19] } ; + assign y__h23183 = { 4'd0, wsiS_reqFifo$D_OUT[20] } ; + assign y__h23195 = { 4'd0, wsiS_reqFifo$D_OUT[21] } ; + assign y__h23207 = { 4'd0, wsiS_reqFifo$D_OUT[22] } ; always@(wci_wslv_reqF$D_OUT or smaCtrl or - rdat__h24388 or - rdat__h24394 or - rdat__h24400 or - rdat__h24413 or - rdat__h24436 or - rdat__h24536 or - rdat__h24550 or - rdat__h24558 or - rdat__h24564 or - rdat__h24578 or - rdat__h24586 or - rdat__h24592 or - rdat__h24598 or rdat__h24604 or rdat__h24610 or rdat__h24620) + rdat__h24911 or + rdat__h24917 or + rdat__h24923 or + rdat__h24936 or + rdat__h24959 or + rdat__h25059 or + rdat__h25073 or + rdat__h25081 or + rdat__h25087 or + rdat__h25101 or + rdat__h25109 or + rdat__h25115 or + rdat__h25121 or rdat__h25127 or rdat__h25133 or rdat__h25143) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h24345 = smaCtrl; - 8'h04: g_data__h24345 = rdat__h24388; - 8'h08: g_data__h24345 = rdat__h24394; - 8'h10: g_data__h24345 = rdat__h24400; - 8'h14: g_data__h24345 = rdat__h24413; - 8'h18: g_data__h24345 = rdat__h24436; - 8'h20: g_data__h24345 = rdat__h24536; - 8'h24: g_data__h24345 = rdat__h24550; - 8'h28: g_data__h24345 = rdat__h24558; - 8'h2C: g_data__h24345 = rdat__h24564; - 8'h30: g_data__h24345 = rdat__h24578; - 8'h34: g_data__h24345 = rdat__h24586; - 8'h38: g_data__h24345 = rdat__h24592; - 8'h3C: g_data__h24345 = rdat__h24598; - 8'h40: g_data__h24345 = rdat__h24604; - 8'h44: g_data__h24345 = rdat__h24610; - 8'h48: g_data__h24345 = rdat__h24620; - default: g_data__h24345 = 32'd0; + 8'h0: g_data__h24868 = smaCtrl; + 8'h04: g_data__h24868 = rdat__h24911; + 8'h08: g_data__h24868 = rdat__h24917; + 8'h10: g_data__h24868 = rdat__h24923; + 8'h14: g_data__h24868 = rdat__h24936; + 8'h18: g_data__h24868 = rdat__h24959; + 8'h20: g_data__h24868 = rdat__h25059; + 8'h24: g_data__h24868 = rdat__h25073; + 8'h28: g_data__h24868 = rdat__h25081; + 8'h2C: g_data__h24868 = rdat__h25087; + 8'h30: g_data__h24868 = rdat__h25101; + 8'h34: g_data__h24868 = rdat__h25109; + 8'h38: g_data__h24868 = rdat__h25115; + 8'h3C: g_data__h24868 = rdat__h25121; + 8'h40: g_data__h24868 = rdat__h25127; + 8'h44: g_data__h24868 = rdat__h25133; + 8'h48: g_data__h24868 = rdat__h25143; + default: g_data__h24868 = 32'd0; endcase end @@ -2812,7 +2820,7 @@ module mkSMAdapter16B(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin abortCount <= `BSV_ASSIGNMENT_DELAY 32'd0; doAbort <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -3063,8 +3071,8 @@ module mkSMAdapter16B(wciS0_Clk, wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -3189,152 +3197,152 @@ module mkSMAdapter16B(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_start) + begin + v__h3729 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3729, + wci_wslv_reqF$D_OUT[36:34], + wci_wslv_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmrd_mesgBegin) begin - v__h18191 = $time; + v__h18699 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmrd_mesgBegin) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", - v__h18191, + v__h18699, mesgCount, wmi_sFlagReg[23:0], wmi_sFlagReg[31:24]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[164]) begin - v__h21903 = $time; + v__h22418 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[164]) $display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x", - v__h21903, + v__h22418, mesgCount, wsiS_reqFifo$D_OUT[163:152], wsiS_reqFifo$D_OUT[7:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[164]) begin - v__h21962 = $time; + v__h22477 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[164]) $display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x", - v__h21962, + v__h22477, mesgCount); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) begin - v__h23796 = $time; + v__h24317 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) - $display("[%0d]: %m: wmwt_doAbort", v__h23796); - if (wciS0_MReset_n) + $display("[%0d]: %m: wmwt_doAbort", v__h24317); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) begin - v__h23979 = $time; + v__h24500 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) $display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x", - v__h23979, + v__h24500, mesgCount, thisMesg[15:0]); - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_wslv_ctl_op_start) - begin - v__h3651 = $time; - #0; - end - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_wslv_ctl_op_start) - $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3651, - wci_wslv_reqF$D_OUT[36:34], - wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h24175 = $time; + v__h24696 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h24175, + v__h24696, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h24833 = $time; + v__h25358 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x", - v__h24833, + v__h25358, smaCtrl); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3969 = $time; + v__h4048 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3969, + v__h4048, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3825 = $time; + v__h3904 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3825, + v__h3904, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkSMAdapter32B.v b/rtl/mkSMAdapter32B.v index 2b328181..0f211141 100644 --- a/rtl/mkSMAdapter32B.v +++ b/rtl/mkSMAdapter32B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:30 EDT 2012 +// On Mon Sep 24 15:03:45 EDT 2012 // // // Ports: @@ -64,7 +64,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkSMAdapter32B(wciS0_Clk, @@ -989,112 +997,112 @@ module mkSMAdapter32B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h18191, - v__h21903, - v__h21962, - v__h24452, - v__h24635, - v__h24831, - v__h25489, - v__h3651, - v__h3825, - v__h3969; - reg [31 : 0] g_data__h25001; - wire [307 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d963; - wire [31 : 0] rdat__h25044, - rdat__h25050, - rdat__h25056, - rdat__h25069, - rdat__h25092, - rdat__h25192, - rdat__h25206, - rdat__h25214, - rdat__h25220, - rdat__h25234, - rdat__h25242, - rdat__h25248, - rdat__h25254, - rdat__h25260, - rdat__h25266, - rdat__h25276, - sendData_byteEn__h18734, - value__h6580; - wire [23 : 0] b__h17902, - mesgMetaF_length__h22484, - residue__h17765, - x__h18022; - wire [15 : 0] wsiBurstLength__h18650, x__h25096, x_length__h24032; - wire [13 : 0] b__h18275, mlB__h22317, mlInc__h22316; - wire [11 : 0] b__h15090, sendData_burstLength__h18732, x__h16444; - wire [7 : 0] mesgMetaF_opcode__h22483; - wire [5 : 0] x__h22523, - x__h22535, - x__h22547, - x__h22559, - x__h22571, - x__h22583, - x__h22595, - x__h22607, - x__h22619, - x__h22631, - x__h22643, - x__h22655, - x__h22667, - x__h22679, - x__h22691, - x__h22703, - x__h22715, - x__h22727, - x__h22739, - x__h22751, - x__h22763, - x__h22775, - x__h22787, - x__h22799, - x__h22811, - x__h22823, - x__h22835, - x__h22847, - x__h22859, - x__h22871, - x__h22883, - y__h22524, - y__h22536, - y__h22548, - y__h22560, - y__h22572, - y__h22584, - y__h22596, - y__h22608, - y__h22620, - y__h22632, - y__h22644, - y__h22656, - y__h22668, - y__h22680, - y__h22692, - y__h22704, - y__h22716, - y__h22728, - y__h22740, - y__h22752, - y__h22764, - y__h22776, - y__h22788, - y__h22800, - y__h22812, - y__h22824, - y__h22836, - y__h22848, - y__h22860, - y__h22872, - y__h22884; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964; + reg [63 : 0] v__h18699, + v__h22418, + v__h22477, + v__h24973, + v__h25156, + v__h25352, + v__h26014, + v__h3729, + v__h3904, + v__h4048; + reg [31 : 0] g_data__h25524; + wire [307 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964; + wire [31 : 0] rdat__h25567, + rdat__h25573, + rdat__h25579, + rdat__h25592, + rdat__h25615, + rdat__h25715, + rdat__h25729, + rdat__h25737, + rdat__h25743, + rdat__h25757, + rdat__h25765, + rdat__h25771, + rdat__h25777, + rdat__h25783, + rdat__h25789, + rdat__h25799, + sendData_byteEn__h19245, + value__h6702; + wire [23 : 0] b__h18410, + mesgMetaF_length__h22999, + residue__h18273, + x__h18530; + wire [15 : 0] wsiBurstLength__h19161, x__h25619, x_length__h24547; + wire [13 : 0] b__h18783, mlB__h22832, mlInc__h22831; + wire [11 : 0] b__h15473, sendData_burstLength__h19243, x__h16878; + wire [7 : 0] mesgMetaF_opcode__h22998; + wire [5 : 0] x__h23038, + x__h23050, + x__h23062, + x__h23074, + x__h23086, + x__h23098, + x__h23110, + x__h23122, + x__h23134, + x__h23146, + x__h23158, + x__h23170, + x__h23182, + x__h23194, + x__h23206, + x__h23218, + x__h23230, + x__h23242, + x__h23254, + x__h23266, + x__h23278, + x__h23290, + x__h23302, + x__h23314, + x__h23326, + x__h23338, + x__h23350, + x__h23362, + x__h23374, + x__h23386, + x__h23398, + y__h23039, + y__h23051, + y__h23063, + y__h23075, + y__h23087, + y__h23099, + y__h23111, + y__h23123, + y__h23135, + y__h23147, + y__h23159, + y__h23171, + y__h23183, + y__h23195, + y__h23207, + y__h23219, + y__h23231, + y__h23243, + y__h23255, + y__h23267, + y__h23279, + y__h23291, + y__h23303, + y__h23315, + y__h23327, + y__h23339, + y__h23351, + y__h23363, + y__h23375, + y__h23387, + y__h23399; + wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965; wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542, wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669, - x__h18446, - x__h25270; + x__h18954, + x__h25793; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1179,7 +1187,7 @@ module mkSMAdapter32B(wciS0_Clk, assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ; // submodule mesgTokenF - FIFO10 #(.guarded(32'd1)) mesgTokenF(.RST_N(wciS0_MReset_n), + FIFO10 #(.guarded(32'd1)) mesgTokenF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .ENQ(mesgTokenF$ENQ), .DEQ(mesgTokenF$DEQ), @@ -1208,7 +1216,7 @@ module mkSMAdapter32B(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -1219,7 +1227,7 @@ module mkSMAdapter32B(wciS0_Clk, .EMPTY_N(wci_wslv_reqF$EMPTY_N)); // submodule wmi_respF - FIFO2 #(.width(32'd258), .guarded(32'd1)) wmi_respF(.RST_N(wciS0_MReset_n), + FIFO2 #(.width(32'd258), .guarded(32'd1)) wmi_respF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wmi_respF$D_IN), .ENQ(wmi_respF$ENQ), @@ -1233,7 +1241,7 @@ module mkSMAdapter32B(wciS0_Clk, SizedFIFO #(.p1width(32'd313), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wsiS_reqFifo$D_IN), .ENQ(wsiS_reqFifo$ENQ), @@ -1260,6 +1268,40 @@ module mkSMAdapter32B(wciS0_Clk, smaCtrl[3:0] == 4'h9) && mesgPreRequest ; + // rule RL_wci_wslv_ctl_op_start + assign WILL_FIRE_RL_wci_wslv_ctl_op_start = + wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd2 && + wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_wmi_reqF_deq + assign WILL_FIRE_RL_wmi_reqF_deq = + wmi_operateD && wmi_peerIsReady && !wmi_sThreadBusy_d ; + + // rule RL_wsiM_reqFifo_deq + assign WILL_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + + // rule RL_wsipass_doMessagePush + assign WILL_FIRE_RL_wsipass_doMessagePush = + wsiS_reqFifo$EMPTY_N && + (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && + wci_wslv_cState == 3'd2 && + smaCtrl[3:0] == 4'h0 ; + // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && @@ -1276,13 +1318,6 @@ module mkSMAdapter32B(wciS0_Clk, !wmi_sDataThreadBusy_d && unrollCnt == 16'd0 ; - // rule RL_wsipass_doMessagePush - assign WILL_FIRE_RL_wsipass_doMessagePush = - wsiS_reqFifo$EMPTY_N && - (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && - wci_wslv_cState == 3'd2 && - smaCtrl[3:0] == 4'h0 ; - // rule RL_wmrd_mesgBodyResponse assign WILL_FIRE_RL_wmrd_mesgBodyResponse = wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && @@ -1325,29 +1360,6 @@ module mkSMAdapter32B(wciS0_Clk, !doAbort && endOfMessage ; - // rule RL_wci_wslv_ctl_op_start - assign WILL_FIRE_RL_wci_wslv_ctl_op_start = - wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && - !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - - // rule RL_wci_ctrl_EiI - assign WILL_FIRE_RL_wci_ctrl_EiI = - wci_wslv_wci_ctrl_pw$whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF$D_OUT[36:34] == 3'd0 ; - - // rule RL_wci_ctrl_OrE - assign WILL_FIRE_RL_wci_ctrl_OrE = - wci_wslv_wci_ctrl_pw$whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd2 && - wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; - - // rule RL_wmi_reqF_deq - assign WILL_FIRE_RL_wmi_reqF_deq = - wmi_operateD && wmi_peerIsReady && !wmi_sThreadBusy_d ; - // rule RL_wmi_reqF_incCtr assign WILL_FIRE_RL_wmi_reqF_incCtr = ((wmi_reqF_c_r == 2'd0) ? @@ -1411,10 +1423,6 @@ module mkSMAdapter32B(wciS0_Clk, wmi_dhF_dequeueing$whas && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - // rule RL_wsiM_reqFifo_deq - assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; - // rule RL_wmrd_mesgResptoWsi assign WILL_FIRE_RL_wmrd_mesgResptoWsi = wsiM_reqFifo_c_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && @@ -1527,7 +1535,7 @@ module mkSMAdapter32B(wciS0_Clk, assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ; assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 ; + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 ; assign MUX_wmi_reqF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ; assign MUX_wmi_reqF_q_1$write_1__SEL_2 = @@ -1546,23 +1554,23 @@ module mkSMAdapter32B(wciS0_Clk, !WILL_FIRE_RL_wmwt_messageFinalize ; assign MUX_fabRespCredit_value$write_1__VAL_2 = fabRespCredit_value + - (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15090 : 12'd0) + + (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15473 : 12'd0) + (WILL_FIRE_RL_wmrd_mesgResptoWsi ? 12'd1 : 12'd0) ; assign MUX_fabWordsRemain$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17902[13:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h18410[13:0] ; assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; assign MUX_mesgCount$write_1__VAL_1 = mesgCount + 32'd1 ; assign MUX_mesgLengthSoFar$write_1__VAL_1 = - mesgLengthSoFar + mlInc__h22316 ; + mesgLengthSoFar + mlInc__h22831 ; assign MUX_mesgReqAddr$write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[8:0], 5'd0 } ; assign MUX_opcode$write_1__VAL_3 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ; assign MUX_thisMesg$write_1__VAL_1 = - { mesgCount[7:0], mesgMetaF_opcode__h22483, x_length__h24032 } ; + { mesgCount[7:0], mesgMetaF_opcode__h22998, x_length__h24547 } ; assign MUX_thisMesg$write_1__VAL_2 = { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; assign MUX_unrollCnt$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h17902[15:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h18410[15:0] ; assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && @@ -1598,7 +1606,7 @@ module mkSMAdapter32B(wciS0_Clk, 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h25001 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h25524 } ; assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r + 2'd1 ; assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ; assign MUX_wmi_dhF_q_0$write_1__VAL_1 = @@ -1612,11 +1620,11 @@ module mkSMAdapter32B(wciS0_Clk, assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ; assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ; assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd1) ? value__h6580 : wmi_mFlagF_q_1 ; + (wmi_mFlagF_c_r == 2'd1) ? value__h6702 : wmi_mFlagF_q_1 ; assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd2) ? value__h6580 : 32'd0 ; + (wmi_mFlagF_c_r == 2'd2) ? value__h6702 : 32'd0 ; assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 = - { mesgMetaF_opcode__h22483, mesgMetaF_length__h22484 } ; + { mesgMetaF_opcode__h22998, mesgMetaF_length__h22999 } ; assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r + 2'd1 ; assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r - 2'd1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_1 = @@ -1632,7 +1640,7 @@ module mkSMAdapter32B(wciS0_Clk, MUX_wmi_reqF_q_0$write_1__VAL_2 : 32'd0 ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_1 = - { 4'd5, x__h18446, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; + { 4'd5, x__h18954, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_2 = { 4'd3, wsiS_reqFifo$D_OUT[309], 1'b0, mesgLengthSoFar, 12'd1 } ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; @@ -1689,7 +1697,7 @@ module mkSMAdapter32B(wciS0_Clk, assign wmi_reqF_x_wire$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - assign wmi_mFlagF_x_wire$wget = value__h6580 ; + assign wmi_mFlagF_x_wire$wget = value__h6702 ; assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ; assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_2 ; assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; @@ -1725,7 +1733,7 @@ module mkSMAdapter32B(wciS0_Clk, assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; assign wsiS_sThreadBusy_dw$whas = wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; - assign fabRespCredit_acc_v1$wget = b__h15090 ; + assign fabRespCredit_acc_v1$wget = b__h15473 ; assign fabRespCredit_acc_v1$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign fabRespCredit_acc_v2$wget = 12'd1 ; assign fabRespCredit_acc_v2$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; @@ -1735,9 +1743,9 @@ module mkSMAdapter32B(wciS0_Clk, { 3'd1, unrollCnt == 16'd1, !smaCtrl[5], - sendData_burstLength__h18732, + sendData_burstLength__h19243, wmi_respF$D_OUT[255:0], - sendData_byteEn__h18734, + sendData_byteEn__h19245, thisMesg[23:16] } ; assign respF_wDataIn$whas = respF_pwEnqueue$whas ; assign respF_wDataOut$wget = MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; @@ -1781,7 +1789,7 @@ module mkSMAdapter32B(wciS0_Clk, assign wmi_reqF_dequeueing$whas = WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'd0 ; assign wmi_mFlagF_enqueueing$whas = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 || + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[309] ; assign wmi_mFlagF_dequeueing$whas = @@ -1850,7 +1858,7 @@ module mkSMAdapter32B(wciS0_Clk, // register fabWordsCurReq assign fabWordsCurReq$D_IN = - (fabWordsRemain <= b__h18275) ? fabWordsRemain : b__h18275 ; + (fabWordsRemain <= b__h18783) ? fabWordsRemain : b__h18783 ; assign fabWordsCurReq$EN = MUX_mesgReqOK$write_1__SEL_3 ; // register fabWordsRemain @@ -1957,14 +1965,14 @@ module mkSMAdapter32B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964, + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965, respF_pwEnqueue$whas && respF_wDataIn$wget[309], respF_pwEnqueue$whas && respF_wDataIn$wget[308], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d963 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr - assign respF_rRdPtr$D_IN = x__h16444 ; + assign respF_rRdPtr$D_IN = x__h16878 ; assign respF_rRdPtr$EN = WILL_FIRE_RL_wmrd_mesgResptoWsi ; // register respF_rWrPtr @@ -2214,12 +2222,12 @@ module mkSMAdapter32B(wciS0_Clk, always@(WILL_FIRE_RL_wmi_mFlagF_both or MUX_wmi_mFlagF_q_0$write_1__VAL_1 or MUX_wmi_mFlagF_q_0$write_1__SEL_2 or - value__h6580 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_mFlagF_both: wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_1; - MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6580; + MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6702; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1; default: wmi_mFlagF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -2233,12 +2241,12 @@ module mkSMAdapter32B(wciS0_Clk, always@(WILL_FIRE_RL_wmi_mFlagF_both or MUX_wmi_mFlagF_q_1$write_1__VAL_1 or MUX_wmi_mFlagF_q_1$write_1__SEL_2 or - value__h6580 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_mFlagF_both: wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_1; - MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6580; + MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6702; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0; default: wmi_mFlagF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -2560,13 +2568,13 @@ module mkSMAdapter32B(wciS0_Clk, assign respF_memory$ADDRA = respF_rWrPtr[10:0] ; assign respF_memory$ADDRB = WILL_FIRE_RL_wmrd_mesgResptoWsi ? - x__h16444[10:0] : + x__h16878[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964, + { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965, respF_pwEnqueue$whas && respF_wDataIn$wget[309], respF_pwEnqueue$whas && respF_wDataIn$wget[308], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d963 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964 } ; assign respF_memory$DIB = 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; @@ -2595,50 +2603,50 @@ module mkSMAdapter32B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d963 = - respF_pwEnqueue$whas ? respF_wDataIn$wget[307:0] : 308'd0 ; assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964 = + respF_pwEnqueue$whas ? respF_wDataIn$wget[307:0] : 308'd0 ; + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965 = respF_pwEnqueue$whas ? respF_wDataIn$wget[312:310] : 3'd0 ; assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && - (!x__h18446 || wmi_mFlagF_c_r != 2'd2) ; - assign b__h15090 = -fabWordsCurReq[11:0] ; - assign b__h17902 = x__h18022 + residue__h17765 ; - assign b__h18275 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; - assign mesgMetaF_length__h22484 = + (!x__h18954 || wmi_mFlagF_c_r != 2'd2) ; + assign b__h15473 = -fabWordsCurReq[11:0] ; + assign b__h18410 = x__h18530 + residue__h18273 ; + assign b__h18783 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; + assign mesgMetaF_length__h22999 = (wsiS_reqFifo$D_OUT[309] && wsiS_reqFifo$D_OUT[39:8] == 32'd0 && mesgLengthSoFar == 14'd0) ? 24'd0 : - { 10'd0, mlB__h22317 } ; - assign mesgMetaF_opcode__h22483 = opcode[8] ? opcode[7:0] : 8'd0 ; - assign mlB__h22317 = MUX_mesgLengthSoFar$write_1__VAL_1 ; - assign mlInc__h22316 = + { 10'd0, mlB__h22832 } ; + assign mesgMetaF_opcode__h22998 = opcode[8] ? opcode[7:0] : 8'd0 ; + assign mlB__h22832 = MUX_mesgLengthSoFar$write_1__VAL_1 ; + assign mlInc__h22831 = wsiS_reqFifo$D_OUT[309] ? - { 8'd0, x__h22523 + y__h22524 } : + { 8'd0, x__h23038 + y__h23039 } : 14'd32 ; - assign rdat__h25044 = hasDebugLogic ? mesgCount : 32'd0 ; - assign rdat__h25050 = hasDebugLogic ? abortCount : 32'd0 ; - assign rdat__h25056 = hasDebugLogic ? thisMesg : 32'd0 ; - assign rdat__h25069 = hasDebugLogic ? lastMesg : 32'd0 ; - assign rdat__h25092 = hasDebugLogic ? { 16'd0, x__h25096 } : 32'd0 ; - assign rdat__h25192 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h25206 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h25214 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h25220 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h25234 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h25242 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h25248 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; - assign rdat__h25254 = hasDebugLogic ? wmwtPushCount : 32'd0 ; - assign rdat__h25260 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; - assign rdat__h25266 = hasDebugLogic ? { 31'd0, x__h25270 } : 32'd0 ; - assign rdat__h25276 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; - assign residue__h17765 = + assign rdat__h25567 = hasDebugLogic ? mesgCount : 32'd0 ; + assign rdat__h25573 = hasDebugLogic ? abortCount : 32'd0 ; + assign rdat__h25579 = hasDebugLogic ? thisMesg : 32'd0 ; + assign rdat__h25592 = hasDebugLogic ? lastMesg : 32'd0 ; + assign rdat__h25615 = hasDebugLogic ? { 16'd0, x__h25619 } : 32'd0 ; + assign rdat__h25715 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h25729 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h25737 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h25743 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h25757 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h25765 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h25771 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; + assign rdat__h25777 = hasDebugLogic ? wmwtPushCount : 32'd0 ; + assign rdat__h25783 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; + assign rdat__h25789 = hasDebugLogic ? { 31'd0, x__h25793 } : 32'd0 ; + assign rdat__h25799 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; + assign residue__h18273 = ({ 1'd0, wmi_sFlagReg[4:0] } == 6'd0) ? 24'd0 : 24'd1 ; - assign sendData_burstLength__h18732 = + assign sendData_burstLength__h19243 = (thisMesg[15:0] == 16'd0 || smaCtrl[5] && unrollCnt == 16'd1) ? 12'd1 : - (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h18650[11:0]) ; - assign sendData_byteEn__h18734 = + (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h19161[11:0]) ; + assign sendData_byteEn__h19245 = (thisMesg[15:0] == 16'd0) ? 32'd0 : ((unrollCnt == 16'd1) ? @@ -2752,122 +2760,122 @@ module mkSMAdapter32B(wciS0_Clk, 32'h7FFFFFFF : 32'hFFFFFFFF)))))))))))))))))))))))))))))))) : 32'hFFFFFFFF) ; - assign value__h6580 = + assign value__h6702 = MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 ? 32'hAAAAAAAA /* unspecified value */ : MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 ; assign wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 = wmi_respF$EMPTY_N && (smaCtrl[4] || respF_rRdPtr + 12'd1024 != respF_rWrPtr) ; - assign wsiBurstLength__h18650 = + assign wsiBurstLength__h19161 = smaCtrl[5] ? 16'd2 : { 5'd0, thisMesg[15:5] } ; assign wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669 = wsiS_reqFifo$EMPTY_N && (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_c_r != 2'd2) && (!wsiS_reqFifo$D_OUT[309] || wmi_mFlagF_c_r != 2'd2) ; - assign x__h16444 = respF_rRdPtr + 12'd1 ; - assign x__h18022 = { 5'd0, wmi_sFlagReg[23:5] } ; - assign x__h18446 = fabWordsRemain == fabWordsCurReq ; - assign x__h22523 = x__h22535 + y__h22536 ; - assign x__h22535 = x__h22547 + y__h22548 ; - assign x__h22547 = x__h22559 + y__h22560 ; - assign x__h22559 = x__h22571 + y__h22572 ; - assign x__h22571 = x__h22583 + y__h22584 ; - assign x__h22583 = x__h22595 + y__h22596 ; - assign x__h22595 = x__h22607 + y__h22608 ; - assign x__h22607 = x__h22619 + y__h22620 ; - assign x__h22619 = x__h22631 + y__h22632 ; - assign x__h22631 = x__h22643 + y__h22644 ; - assign x__h22643 = x__h22655 + y__h22656 ; - assign x__h22655 = x__h22667 + y__h22668 ; - assign x__h22667 = x__h22679 + y__h22680 ; - assign x__h22679 = x__h22691 + y__h22692 ; - assign x__h22691 = x__h22703 + y__h22704 ; - assign x__h22703 = x__h22715 + y__h22716 ; - assign x__h22715 = x__h22727 + y__h22728 ; - assign x__h22727 = x__h22739 + y__h22740 ; - assign x__h22739 = x__h22751 + y__h22752 ; - assign x__h22751 = x__h22763 + y__h22764 ; - assign x__h22763 = x__h22775 + y__h22776 ; - assign x__h22775 = x__h22787 + y__h22788 ; - assign x__h22787 = x__h22799 + y__h22800 ; - assign x__h22799 = x__h22811 + y__h22812 ; - assign x__h22811 = x__h22823 + y__h22824 ; - assign x__h22823 = x__h22835 + y__h22836 ; - assign x__h22835 = x__h22847 + y__h22848 ; - assign x__h22847 = x__h22859 + y__h22860 ; - assign x__h22859 = x__h22871 + y__h22872 ; - assign x__h22871 = x__h22883 + y__h22884 ; - assign x__h22883 = { 5'd0, wsiS_reqFifo$D_OUT[39] } ; - assign x__h25096 = { wsiS_statusR, wsiM_statusR } ; - assign x__h25270 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; - assign x_length__h24032 = { 2'd0, mlB__h22317 } ; - assign y__h22524 = { 5'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h22536 = { 5'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h22548 = { 5'd0, wsiS_reqFifo$D_OUT[10] } ; - assign y__h22560 = { 5'd0, wsiS_reqFifo$D_OUT[11] } ; - assign y__h22572 = { 5'd0, wsiS_reqFifo$D_OUT[12] } ; - assign y__h22584 = { 5'd0, wsiS_reqFifo$D_OUT[13] } ; - assign y__h22596 = { 5'd0, wsiS_reqFifo$D_OUT[14] } ; - assign y__h22608 = { 5'd0, wsiS_reqFifo$D_OUT[15] } ; - assign y__h22620 = { 5'd0, wsiS_reqFifo$D_OUT[16] } ; - assign y__h22632 = { 5'd0, wsiS_reqFifo$D_OUT[17] } ; - assign y__h22644 = { 5'd0, wsiS_reqFifo$D_OUT[18] } ; - assign y__h22656 = { 5'd0, wsiS_reqFifo$D_OUT[19] } ; - assign y__h22668 = { 5'd0, wsiS_reqFifo$D_OUT[20] } ; - assign y__h22680 = { 5'd0, wsiS_reqFifo$D_OUT[21] } ; - assign y__h22692 = { 5'd0, wsiS_reqFifo$D_OUT[22] } ; - assign y__h22704 = { 5'd0, wsiS_reqFifo$D_OUT[23] } ; - assign y__h22716 = { 5'd0, wsiS_reqFifo$D_OUT[24] } ; - assign y__h22728 = { 5'd0, wsiS_reqFifo$D_OUT[25] } ; - assign y__h22740 = { 5'd0, wsiS_reqFifo$D_OUT[26] } ; - assign y__h22752 = { 5'd0, wsiS_reqFifo$D_OUT[27] } ; - assign y__h22764 = { 5'd0, wsiS_reqFifo$D_OUT[28] } ; - assign y__h22776 = { 5'd0, wsiS_reqFifo$D_OUT[29] } ; - assign y__h22788 = { 5'd0, wsiS_reqFifo$D_OUT[30] } ; - assign y__h22800 = { 5'd0, wsiS_reqFifo$D_OUT[31] } ; - assign y__h22812 = { 5'd0, wsiS_reqFifo$D_OUT[32] } ; - assign y__h22824 = { 5'd0, wsiS_reqFifo$D_OUT[33] } ; - assign y__h22836 = { 5'd0, wsiS_reqFifo$D_OUT[34] } ; - assign y__h22848 = { 5'd0, wsiS_reqFifo$D_OUT[35] } ; - assign y__h22860 = { 5'd0, wsiS_reqFifo$D_OUT[36] } ; - assign y__h22872 = { 5'd0, wsiS_reqFifo$D_OUT[37] } ; - assign y__h22884 = { 5'd0, wsiS_reqFifo$D_OUT[38] } ; + assign x__h16878 = respF_rRdPtr + 12'd1 ; + assign x__h18530 = { 5'd0, wmi_sFlagReg[23:5] } ; + assign x__h18954 = fabWordsRemain == fabWordsCurReq ; + assign x__h23038 = x__h23050 + y__h23051 ; + assign x__h23050 = x__h23062 + y__h23063 ; + assign x__h23062 = x__h23074 + y__h23075 ; + assign x__h23074 = x__h23086 + y__h23087 ; + assign x__h23086 = x__h23098 + y__h23099 ; + assign x__h23098 = x__h23110 + y__h23111 ; + assign x__h23110 = x__h23122 + y__h23123 ; + assign x__h23122 = x__h23134 + y__h23135 ; + assign x__h23134 = x__h23146 + y__h23147 ; + assign x__h23146 = x__h23158 + y__h23159 ; + assign x__h23158 = x__h23170 + y__h23171 ; + assign x__h23170 = x__h23182 + y__h23183 ; + assign x__h23182 = x__h23194 + y__h23195 ; + assign x__h23194 = x__h23206 + y__h23207 ; + assign x__h23206 = x__h23218 + y__h23219 ; + assign x__h23218 = x__h23230 + y__h23231 ; + assign x__h23230 = x__h23242 + y__h23243 ; + assign x__h23242 = x__h23254 + y__h23255 ; + assign x__h23254 = x__h23266 + y__h23267 ; + assign x__h23266 = x__h23278 + y__h23279 ; + assign x__h23278 = x__h23290 + y__h23291 ; + assign x__h23290 = x__h23302 + y__h23303 ; + assign x__h23302 = x__h23314 + y__h23315 ; + assign x__h23314 = x__h23326 + y__h23327 ; + assign x__h23326 = x__h23338 + y__h23339 ; + assign x__h23338 = x__h23350 + y__h23351 ; + assign x__h23350 = x__h23362 + y__h23363 ; + assign x__h23362 = x__h23374 + y__h23375 ; + assign x__h23374 = x__h23386 + y__h23387 ; + assign x__h23386 = x__h23398 + y__h23399 ; + assign x__h23398 = { 5'd0, wsiS_reqFifo$D_OUT[39] } ; + assign x__h25619 = { wsiS_statusR, wsiM_statusR } ; + assign x__h25793 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; + assign x_length__h24547 = { 2'd0, mlB__h22832 } ; + assign y__h23039 = { 5'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h23051 = { 5'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h23063 = { 5'd0, wsiS_reqFifo$D_OUT[10] } ; + assign y__h23075 = { 5'd0, wsiS_reqFifo$D_OUT[11] } ; + assign y__h23087 = { 5'd0, wsiS_reqFifo$D_OUT[12] } ; + assign y__h23099 = { 5'd0, wsiS_reqFifo$D_OUT[13] } ; + assign y__h23111 = { 5'd0, wsiS_reqFifo$D_OUT[14] } ; + assign y__h23123 = { 5'd0, wsiS_reqFifo$D_OUT[15] } ; + assign y__h23135 = { 5'd0, wsiS_reqFifo$D_OUT[16] } ; + assign y__h23147 = { 5'd0, wsiS_reqFifo$D_OUT[17] } ; + assign y__h23159 = { 5'd0, wsiS_reqFifo$D_OUT[18] } ; + assign y__h23171 = { 5'd0, wsiS_reqFifo$D_OUT[19] } ; + assign y__h23183 = { 5'd0, wsiS_reqFifo$D_OUT[20] } ; + assign y__h23195 = { 5'd0, wsiS_reqFifo$D_OUT[21] } ; + assign y__h23207 = { 5'd0, wsiS_reqFifo$D_OUT[22] } ; + assign y__h23219 = { 5'd0, wsiS_reqFifo$D_OUT[23] } ; + assign y__h23231 = { 5'd0, wsiS_reqFifo$D_OUT[24] } ; + assign y__h23243 = { 5'd0, wsiS_reqFifo$D_OUT[25] } ; + assign y__h23255 = { 5'd0, wsiS_reqFifo$D_OUT[26] } ; + assign y__h23267 = { 5'd0, wsiS_reqFifo$D_OUT[27] } ; + assign y__h23279 = { 5'd0, wsiS_reqFifo$D_OUT[28] } ; + assign y__h23291 = { 5'd0, wsiS_reqFifo$D_OUT[29] } ; + assign y__h23303 = { 5'd0, wsiS_reqFifo$D_OUT[30] } ; + assign y__h23315 = { 5'd0, wsiS_reqFifo$D_OUT[31] } ; + assign y__h23327 = { 5'd0, wsiS_reqFifo$D_OUT[32] } ; + assign y__h23339 = { 5'd0, wsiS_reqFifo$D_OUT[33] } ; + assign y__h23351 = { 5'd0, wsiS_reqFifo$D_OUT[34] } ; + assign y__h23363 = { 5'd0, wsiS_reqFifo$D_OUT[35] } ; + assign y__h23375 = { 5'd0, wsiS_reqFifo$D_OUT[36] } ; + assign y__h23387 = { 5'd0, wsiS_reqFifo$D_OUT[37] } ; + assign y__h23399 = { 5'd0, wsiS_reqFifo$D_OUT[38] } ; always@(wci_wslv_reqF$D_OUT or smaCtrl or - rdat__h25044 or - rdat__h25050 or - rdat__h25056 or - rdat__h25069 or - rdat__h25092 or - rdat__h25192 or - rdat__h25206 or - rdat__h25214 or - rdat__h25220 or - rdat__h25234 or - rdat__h25242 or - rdat__h25248 or - rdat__h25254 or rdat__h25260 or rdat__h25266 or rdat__h25276) + rdat__h25567 or + rdat__h25573 or + rdat__h25579 or + rdat__h25592 or + rdat__h25615 or + rdat__h25715 or + rdat__h25729 or + rdat__h25737 or + rdat__h25743 or + rdat__h25757 or + rdat__h25765 or + rdat__h25771 or + rdat__h25777 or rdat__h25783 or rdat__h25789 or rdat__h25799) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h25001 = smaCtrl; - 8'h04: g_data__h25001 = rdat__h25044; - 8'h08: g_data__h25001 = rdat__h25050; - 8'h10: g_data__h25001 = rdat__h25056; - 8'h14: g_data__h25001 = rdat__h25069; - 8'h18: g_data__h25001 = rdat__h25092; - 8'h20: g_data__h25001 = rdat__h25192; - 8'h24: g_data__h25001 = rdat__h25206; - 8'h28: g_data__h25001 = rdat__h25214; - 8'h2C: g_data__h25001 = rdat__h25220; - 8'h30: g_data__h25001 = rdat__h25234; - 8'h34: g_data__h25001 = rdat__h25242; - 8'h38: g_data__h25001 = rdat__h25248; - 8'h3C: g_data__h25001 = rdat__h25254; - 8'h40: g_data__h25001 = rdat__h25260; - 8'h44: g_data__h25001 = rdat__h25266; - 8'h48: g_data__h25001 = rdat__h25276; - default: g_data__h25001 = 32'd0; + 8'h0: g_data__h25524 = smaCtrl; + 8'h04: g_data__h25524 = rdat__h25567; + 8'h08: g_data__h25524 = rdat__h25573; + 8'h10: g_data__h25524 = rdat__h25579; + 8'h14: g_data__h25524 = rdat__h25592; + 8'h18: g_data__h25524 = rdat__h25615; + 8'h20: g_data__h25524 = rdat__h25715; + 8'h24: g_data__h25524 = rdat__h25729; + 8'h28: g_data__h25524 = rdat__h25737; + 8'h2C: g_data__h25524 = rdat__h25743; + 8'h30: g_data__h25524 = rdat__h25757; + 8'h34: g_data__h25524 = rdat__h25765; + 8'h38: g_data__h25524 = rdat__h25771; + 8'h3C: g_data__h25524 = rdat__h25777; + 8'h40: g_data__h25524 = rdat__h25783; + 8'h44: g_data__h25524 = rdat__h25789; + 8'h48: g_data__h25524 = rdat__h25799; + default: g_data__h25524 = 32'd0; endcase end @@ -2875,7 +2883,7 @@ module mkSMAdapter32B(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin abortCount <= `BSV_ASSIGNMENT_DELAY 32'd0; doAbort <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -3126,8 +3134,8 @@ module mkSMAdapter32B(wciS0_Clk, wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -3259,152 +3267,152 @@ module mkSMAdapter32B(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_start) + begin + v__h3729 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3729, + wci_wslv_reqF$D_OUT[36:34], + wci_wslv_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmrd_mesgBegin) begin - v__h18191 = $time; + v__h18699 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmrd_mesgBegin) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", - v__h18191, + v__h18699, mesgCount, wmi_sFlagReg[23:0], wmi_sFlagReg[31:24]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[308]) begin - v__h21903 = $time; + v__h22418 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[308]) $display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x", - v__h21903, + v__h22418, mesgCount, wsiS_reqFifo$D_OUT[307:296], wsiS_reqFifo$D_OUT[7:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[308]) begin - v__h21962 = $time; + v__h22477 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[308]) $display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x", - v__h21962, + v__h22477, mesgCount); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) begin - v__h24452 = $time; + v__h24973 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) - $display("[%0d]: %m: wmwt_doAbort", v__h24452); - if (wciS0_MReset_n) + $display("[%0d]: %m: wmwt_doAbort", v__h24973); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) begin - v__h24635 = $time; + v__h25156 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) $display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x", - v__h24635, + v__h25156, mesgCount, thisMesg[15:0]); - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_wslv_ctl_op_start) - begin - v__h3651 = $time; - #0; - end - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_wslv_ctl_op_start) - $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3651, - wci_wslv_reqF$D_OUT[36:34], - wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h24831 = $time; + v__h25352 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h24831, + v__h25352, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h25489 = $time; + v__h26014 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x", - v__h25489, + v__h26014, smaCtrl); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3969 = $time; + v__h4048 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3969, + v__h4048, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3825 = $time; + v__h3904 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3825, + v__h3904, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkSMAdapter4B.v b/rtl/mkSMAdapter4B.v index b1745576..64d6c747 100644 --- a/rtl/mkSMAdapter4B.v +++ b/rtl/mkSMAdapter4B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:23 EDT 2012 +// On Mon Sep 24 15:03:37 EDT 2012 // // // Ports: @@ -64,7 +64,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkSMAdapter4B(wciS0_Clk, @@ -987,57 +995,57 @@ module mkSMAdapter4B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h18191, - v__h22600, - v__h22659, - v__h24001, - v__h24184, - v__h24380, - v__h25038, - v__h3651, - v__h3825, - v__h3969; - reg [31 : 0] g_data__h24550; - wire [55 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881; - wire [31 : 0] rdat__h24593, - rdat__h24599, - rdat__h24605, - rdat__h24618, - rdat__h24641, - rdat__h24741, - rdat__h24755, - rdat__h24763, - rdat__h24769, - rdat__h24783, - rdat__h24791, - rdat__h24797, - rdat__h24803, - rdat__h24809, - rdat__h24815, - rdat__h24825, - value__h6580, - x__h18791; - wire [23 : 0] b__h17902, - mesgMetaF_length__h23181, - residue__h17765, - x__h18022; - wire [15 : 0] wsiBurstLength__h18650, x__h24645, x_length__h23581; - wire [13 : 0] b__h18275, mlB__h23014, mlInc__h23013; - wire [11 : 0] b__h15090, sendData_burstLength__h18732, x__h16444; - wire [7 : 0] mesgMetaF_opcode__h23180; - wire [3 : 0] sendData_byteEn__h18734; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889, - x__h23220, - x__h23232, - x__h23244, - y__h23221, - y__h23233, - y__h23245; + reg [63 : 0] v__h18699, + v__h23115, + v__h23174, + v__h24522, + v__h24705, + v__h24901, + v__h25563, + v__h3729, + v__h3904, + v__h4048; + reg [31 : 0] g_data__h25073; + wire [55 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d878; + wire [31 : 0] rdat__h25116, + rdat__h25122, + rdat__h25128, + rdat__h25141, + rdat__h25164, + rdat__h25264, + rdat__h25278, + rdat__h25286, + rdat__h25292, + rdat__h25306, + rdat__h25314, + rdat__h25320, + rdat__h25326, + rdat__h25332, + rdat__h25338, + rdat__h25348, + value__h6702, + x__h19302; + wire [23 : 0] b__h18410, + mesgMetaF_length__h23696, + residue__h18273, + x__h18530; + wire [15 : 0] wsiBurstLength__h19161, x__h25168, x_length__h24096; + wire [13 : 0] b__h18783, mlB__h23529, mlInc__h23528; + wire [11 : 0] b__h15473, sendData_burstLength__h19243, x__h16878; + wire [7 : 0] mesgMetaF_opcode__h23695; + wire [3 : 0] sendData_byteEn__h19245; + wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881, + x__h23735, + x__h23747, + x__h23759, + y__h23736, + y__h23748, + y__h23760; wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541, wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669, - x__h18446, - x__h24819; + x__h18954, + x__h25342; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1121,7 +1129,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ; // submodule mesgTokenF - FIFO10 #(.guarded(32'd1)) mesgTokenF(.RST_N(wciS0_MReset_n), + FIFO10 #(.guarded(32'd1)) mesgTokenF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .ENQ(mesgTokenF$ENQ), .DEQ(mesgTokenF$DEQ), @@ -1150,7 +1158,7 @@ module mkSMAdapter4B(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -1161,7 +1169,7 @@ module mkSMAdapter4B(wciS0_Clk, .EMPTY_N(wci_wslv_reqF$EMPTY_N)); // submodule wmi_respF - FIFO2 #(.width(32'd34), .guarded(32'd1)) wmi_respF(.RST_N(wciS0_MReset_n), + FIFO2 #(.width(32'd34), .guarded(32'd1)) wmi_respF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wmi_respF$D_IN), .ENQ(wmi_respF$ENQ), @@ -1175,7 +1183,7 @@ module mkSMAdapter4B(wciS0_Clk, SizedFIFO #(.p1width(32'd61), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wsiS_reqFifo$D_IN), .ENQ(wsiS_reqFifo$ENQ), @@ -1202,6 +1210,40 @@ module mkSMAdapter4B(wciS0_Clk, smaCtrl[3:0] == 4'h9) && mesgPreRequest ; + // rule RL_wci_wslv_ctl_op_start + assign WILL_FIRE_RL_wci_wslv_ctl_op_start = + wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd2 && + wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_wmi_reqF_deq + assign WILL_FIRE_RL_wmi_reqF_deq = + wmi_operateD && wmi_peerIsReady && !wmi_sThreadBusy_d ; + + // rule RL_wsiM_reqFifo_deq + assign WILL_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + + // rule RL_wsipass_doMessagePush + assign WILL_FIRE_RL_wsipass_doMessagePush = + wsiS_reqFifo$EMPTY_N && + (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && + wci_wslv_cState == 3'd2 && + smaCtrl[3:0] == 4'h0 ; + // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && @@ -1218,13 +1260,6 @@ module mkSMAdapter4B(wciS0_Clk, !wmi_sDataThreadBusy_d && unrollCnt == 16'd0 ; - // rule RL_wsipass_doMessagePush - assign WILL_FIRE_RL_wsipass_doMessagePush = - wsiS_reqFifo$EMPTY_N && - (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && - wci_wslv_cState == 3'd2 && - smaCtrl[3:0] == 4'h0 ; - // rule RL_wmrd_mesgBodyResponse assign WILL_FIRE_RL_wmrd_mesgBodyResponse = wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541 && @@ -1267,29 +1302,6 @@ module mkSMAdapter4B(wciS0_Clk, !doAbort && endOfMessage ; - // rule RL_wci_wslv_ctl_op_start - assign WILL_FIRE_RL_wci_wslv_ctl_op_start = - wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && - !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - - // rule RL_wci_ctrl_EiI - assign WILL_FIRE_RL_wci_ctrl_EiI = - wci_wslv_wci_ctrl_pw$whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF$D_OUT[36:34] == 3'd0 ; - - // rule RL_wci_ctrl_OrE - assign WILL_FIRE_RL_wci_ctrl_OrE = - wci_wslv_wci_ctrl_pw$whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd2 && - wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; - - // rule RL_wmi_reqF_deq - assign WILL_FIRE_RL_wmi_reqF_deq = - wmi_operateD && wmi_peerIsReady && !wmi_sThreadBusy_d ; - // rule RL_wmi_reqF_incCtr assign WILL_FIRE_RL_wmi_reqF_incCtr = ((wmi_reqF_c_r == 2'd0) ? @@ -1353,10 +1365,6 @@ module mkSMAdapter4B(wciS0_Clk, wmi_dhF_dequeueing$whas && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - // rule RL_wsiM_reqFifo_deq - assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; - // rule RL_wmrd_mesgResptoWsi assign WILL_FIRE_RL_wmrd_mesgResptoWsi = wsiM_reqFifo_c_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && @@ -1469,7 +1477,7 @@ module mkSMAdapter4B(wciS0_Clk, assign MUX_wmi_mFlagF_q_1$write_1__SEL_1 = WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ; assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 ; + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 ; assign MUX_wmi_reqF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ; assign MUX_wmi_reqF_q_1$write_1__SEL_2 = @@ -1488,21 +1496,21 @@ module mkSMAdapter4B(wciS0_Clk, !WILL_FIRE_RL_wmwt_messageFinalize ; assign MUX_fabRespCredit_value$write_1__VAL_2 = fabRespCredit_value + - (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15090 : 12'd0) + + (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15473 : 12'd0) + (WILL_FIRE_RL_wmrd_mesgResptoWsi ? 12'd1 : 12'd0) ; assign MUX_fabWordsRemain$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17902[13:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h18410[13:0] ; assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; assign MUX_mesgCount$write_1__VAL_2 = mesgCount + 32'd1 ; assign MUX_mesgReqAddr$write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[11:0], 2'd0 } ; assign MUX_opcode$write_1__VAL_3 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ; assign MUX_thisMesg$write_1__VAL_1 = - { mesgCount[7:0], mesgMetaF_opcode__h23180, x_length__h23581 } ; + { mesgCount[7:0], mesgMetaF_opcode__h23695, x_length__h24096 } ; assign MUX_thisMesg$write_1__VAL_2 = { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; assign MUX_unrollCnt$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h17902[15:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h18410[15:0] ; assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && @@ -1538,7 +1546,7 @@ module mkSMAdapter4B(wciS0_Clk, 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24550 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h25073 } ; assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r + 2'd1 ; assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ; assign MUX_wmi_dhF_q_0$write_1__VAL_1 = @@ -1552,11 +1560,11 @@ module mkSMAdapter4B(wciS0_Clk, assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ; assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ; assign MUX_wmi_mFlagF_q_0$write_1__VAL_2 = - (wmi_mFlagF_c_r == 2'd1) ? value__h6580 : wmi_mFlagF_q_1 ; + (wmi_mFlagF_c_r == 2'd1) ? value__h6702 : wmi_mFlagF_q_1 ; assign MUX_wmi_mFlagF_q_1$write_1__VAL_2 = - (wmi_mFlagF_c_r == 2'd2) ? value__h6580 : 32'd0 ; + (wmi_mFlagF_c_r == 2'd2) ? value__h6702 : 32'd0 ; assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 = - { mesgMetaF_opcode__h23180, mesgMetaF_length__h23181 } ; + { mesgMetaF_opcode__h23695, mesgMetaF_length__h23696 } ; assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r + 2'd1 ; assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r - 2'd1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_1 = @@ -1572,7 +1580,7 @@ module mkSMAdapter4B(wciS0_Clk, MUX_wmi_reqF_q_0$write_1__VAL_2 : 32'd0 ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_1 = - { 4'd5, x__h18446, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; + { 4'd5, x__h18954, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_2 = { 4'd3, wsiS_reqFifo$D_OUT[57], 1'b0, mesgLengthSoFar, 12'd1 } ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; @@ -1629,7 +1637,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wmi_reqF_x_wire$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - assign wmi_mFlagF_x_wire$wget = value__h6580 ; + assign wmi_mFlagF_x_wire$wget = value__h6702 ; assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ; assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_1 ; assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; @@ -1665,7 +1673,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; assign wsiS_sThreadBusy_dw$whas = wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; - assign fabRespCredit_acc_v1$wget = b__h15090 ; + assign fabRespCredit_acc_v1$wget = b__h15473 ; assign fabRespCredit_acc_v1$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign fabRespCredit_acc_v2$wget = 12'd1 ; assign fabRespCredit_acc_v2$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; @@ -1675,9 +1683,9 @@ module mkSMAdapter4B(wciS0_Clk, { 3'd1, unrollCnt == 16'd1, !smaCtrl[5], - sendData_burstLength__h18732, + sendData_burstLength__h19243, wmi_respF$D_OUT[31:0], - sendData_byteEn__h18734, + sendData_byteEn__h19245, thisMesg[23:16] } ; assign respF_wDataIn$whas = respF_pwEnqueue$whas ; assign respF_wDataOut$wget = MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; @@ -1721,7 +1729,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wmi_reqF_dequeueing$whas = WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'd0 ; assign wmi_mFlagF_enqueueing$whas = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 || + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[57] ; assign wmi_mFlagF_dequeueing$whas = @@ -1790,7 +1798,7 @@ module mkSMAdapter4B(wciS0_Clk, // register fabWordsCurReq assign fabWordsCurReq$D_IN = - (fabWordsRemain <= b__h18275) ? fabWordsRemain : b__h18275 ; + (fabWordsRemain <= b__h18783) ? fabWordsRemain : b__h18783 ; assign fabWordsCurReq$EN = MUX_mesgReqOK$write_1__SEL_3 ; // register fabWordsRemain @@ -1840,7 +1848,7 @@ module mkSMAdapter4B(wciS0_Clk, // register mesgLengthSoFar assign mesgLengthSoFar$D_IN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ? - mlB__h23014 : + mlB__h23529 : 14'd0 ; assign mesgLengthSoFar$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || @@ -1897,14 +1905,14 @@ module mkSMAdapter4B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889, + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881, respF_pwEnqueue$whas && respF_wDataIn$wget[57], respF_pwEnqueue$whas && respF_wDataIn$wget[56], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d878 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr - assign respF_rRdPtr$D_IN = x__h16444 ; + assign respF_rRdPtr$D_IN = x__h16878 ; assign respF_rRdPtr$EN = WILL_FIRE_RL_wmrd_mesgResptoWsi ; // register respF_rWrPtr @@ -2150,13 +2158,13 @@ module mkSMAdapter4B(wciS0_Clk, // register wmi_mFlagF_q_0 always@(MUX_wmi_mFlagF_q_0$write_1__SEL_1 or - value__h6580 or + value__h6702 or WILL_FIRE_RL_wmi_mFlagF_both or MUX_wmi_mFlagF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) begin case (1'b1) // synopsys parallel_case - MUX_wmi_mFlagF_q_0$write_1__SEL_1: wmi_mFlagF_q_0$D_IN = value__h6580; + MUX_wmi_mFlagF_q_0$write_1__SEL_1: wmi_mFlagF_q_0$D_IN = value__h6702; WILL_FIRE_RL_wmi_mFlagF_both: wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_2; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1; @@ -2170,12 +2178,12 @@ module mkSMAdapter4B(wciS0_Clk, // register wmi_mFlagF_q_1 always@(MUX_wmi_mFlagF_q_1$write_1__SEL_1 or - value__h6580 or + value__h6702 or WILL_FIRE_RL_wmi_mFlagF_both or MUX_wmi_mFlagF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmi_mFlagF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wmi_mFlagF_q_1$write_1__SEL_1: wmi_mFlagF_q_1$D_IN = value__h6580; + MUX_wmi_mFlagF_q_1$write_1__SEL_1: wmi_mFlagF_q_1$D_IN = value__h6702; WILL_FIRE_RL_wmi_mFlagF_both: wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_2; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0; @@ -2498,13 +2506,13 @@ module mkSMAdapter4B(wciS0_Clk, assign respF_memory$ADDRA = respF_rWrPtr[10:0] ; assign respF_memory$ADDRB = WILL_FIRE_RL_wmrd_mesgResptoWsi ? - x__h16444[10:0] : + x__h16878[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889, + { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881, respF_pwEnqueue$whas && respF_wDataIn$wget[57], respF_pwEnqueue$whas && respF_wDataIn$wget[56], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d878 } ; assign respF_memory$DIB = 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; assign respF_memory$WEB = 1'd0 ; @@ -2532,70 +2540,70 @@ module mkSMAdapter4B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 = + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d878 = respF_pwEnqueue$whas ? respF_wDataIn$wget[55:0] : 56'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889 = + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 = respF_pwEnqueue$whas ? respF_wDataIn$wget[60:58] : 3'd0 ; assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && - (!x__h18446 || wmi_mFlagF_c_r != 2'd2) ; - assign b__h15090 = -fabWordsCurReq[11:0] ; - assign b__h17902 = x__h18022 + residue__h17765 ; - assign b__h18275 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; - assign mesgMetaF_length__h23181 = + (!x__h18954 || wmi_mFlagF_c_r != 2'd2) ; + assign b__h15473 = -fabWordsCurReq[11:0] ; + assign b__h18410 = x__h18530 + residue__h18273 ; + assign b__h18783 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; + assign mesgMetaF_length__h23696 = (wsiS_reqFifo$D_OUT[57] && wsiS_reqFifo$D_OUT[11:8] == 4'd0 && mesgLengthSoFar == 14'd0) ? 24'd0 : - { 10'd0, mlB__h23014 } ; - assign mesgMetaF_opcode__h23180 = opcode[8] ? opcode[7:0] : 8'd0 ; - assign mlB__h23014 = mesgLengthSoFar + mlInc__h23013 ; - assign mlInc__h23013 = + { 10'd0, mlB__h23529 } ; + assign mesgMetaF_opcode__h23695 = opcode[8] ? opcode[7:0] : 8'd0 ; + assign mlB__h23529 = mesgLengthSoFar + mlInc__h23528 ; + assign mlInc__h23528 = wsiS_reqFifo$D_OUT[57] ? - { 11'd0, x__h23220 + y__h23221 } : + { 11'd0, x__h23735 + y__h23736 } : 14'd4 ; - assign rdat__h24593 = hasDebugLogic ? mesgCount : 32'd0 ; - assign rdat__h24599 = hasDebugLogic ? abortCount : 32'd0 ; - assign rdat__h24605 = hasDebugLogic ? thisMesg : 32'd0 ; - assign rdat__h24618 = hasDebugLogic ? lastMesg : 32'd0 ; - assign rdat__h24641 = hasDebugLogic ? { 16'd0, x__h24645 } : 32'd0 ; - assign rdat__h24741 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h24755 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h24763 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h24769 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h24783 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h24791 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h24797 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; - assign rdat__h24803 = hasDebugLogic ? wmwtPushCount : 32'd0 ; - assign rdat__h24809 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; - assign rdat__h24815 = hasDebugLogic ? { 31'd0, x__h24819 } : 32'd0 ; - assign rdat__h24825 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; - assign residue__h17765 = + assign rdat__h25116 = hasDebugLogic ? mesgCount : 32'd0 ; + assign rdat__h25122 = hasDebugLogic ? abortCount : 32'd0 ; + assign rdat__h25128 = hasDebugLogic ? thisMesg : 32'd0 ; + assign rdat__h25141 = hasDebugLogic ? lastMesg : 32'd0 ; + assign rdat__h25164 = hasDebugLogic ? { 16'd0, x__h25168 } : 32'd0 ; + assign rdat__h25264 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h25278 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h25286 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h25292 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h25306 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h25314 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h25320 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; + assign rdat__h25326 = hasDebugLogic ? wmwtPushCount : 32'd0 ; + assign rdat__h25332 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; + assign rdat__h25338 = hasDebugLogic ? { 31'd0, x__h25342 } : 32'd0 ; + assign rdat__h25348 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; + assign residue__h18273 = ({ 4'd0, wmi_sFlagReg[1:0] } == 6'd0) ? 24'd0 : 24'd1 ; - assign sendData_burstLength__h18732 = + assign sendData_burstLength__h19243 = (thisMesg[15:0] == 16'd0 || smaCtrl[5] && unrollCnt == 16'd1) ? 12'd1 : - (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h18650[11:0]) ; - assign sendData_byteEn__h18734 = + (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h19161[11:0]) ; + assign sendData_byteEn__h19245 = (thisMesg[15:0] == 16'd0) ? 4'd0 : - ((unrollCnt == 16'd1) ? x__h18791[3:0] : 4'd15) ; - assign value__h6580 = + ((unrollCnt == 16'd1) ? x__h19302[3:0] : 4'd15) ; + assign value__h6702 = MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 ? 32'hAAAAAAAA /* unspecified value */ : MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 ; assign wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541 = wmi_respF$EMPTY_N && (smaCtrl[4] || respF_rRdPtr + 12'd1024 != respF_rWrPtr) ; - assign wsiBurstLength__h18650 = + assign wsiBurstLength__h19161 = smaCtrl[5] ? 16'd2 : { 2'd0, thisMesg[15:2] } ; assign wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669 = wsiS_reqFifo$EMPTY_N && (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_c_r != 2'd2) && (!wsiS_reqFifo$D_OUT[57] || wmi_mFlagF_c_r != 2'd2) ; - assign x__h16444 = respF_rRdPtr + 12'd1 ; - assign x__h18022 = { 2'd0, wmi_sFlagReg[23:2] } ; - assign x__h18446 = fabWordsRemain == fabWordsCurReq ; - assign x__h18791 = + assign x__h16878 = respF_rRdPtr + 12'd1 ; + assign x__h18530 = { 2'd0, wmi_sFlagReg[23:2] } ; + assign x__h18954 = fabWordsRemain == fabWordsCurReq ; + assign x__h19302 = ({ 4'd0, thisMesg[1:0] } == 6'd0) ? 32'hFFFFFFFF : (({ 4'd0, thisMesg[1:0] } <= 6'd1) ? @@ -2702,50 +2710,50 @@ module mkSMAdapter4B(wciS0_Clk, 6'd31) ? 32'h7FFFFFFF : 32'hFFFFFFFF))))))))))))))))))))))))))))))) ; - assign x__h23220 = x__h23232 + y__h23233 ; - assign x__h23232 = x__h23244 + y__h23245 ; - assign x__h23244 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; - assign x__h24645 = { wsiS_statusR, wsiM_statusR } ; - assign x__h24819 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; - assign x_length__h23581 = { 2'd0, mlB__h23014 } ; - assign y__h23221 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h23233 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h23245 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; + assign x__h23735 = x__h23747 + y__h23748 ; + assign x__h23747 = x__h23759 + y__h23760 ; + assign x__h23759 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; + assign x__h25168 = { wsiS_statusR, wsiM_statusR } ; + assign x__h25342 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; + assign x_length__h24096 = { 2'd0, mlB__h23529 } ; + assign y__h23736 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h23748 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h23760 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; always@(wci_wslv_reqF$D_OUT or smaCtrl or - rdat__h24593 or - rdat__h24599 or - rdat__h24605 or - rdat__h24618 or - rdat__h24641 or - rdat__h24741 or - rdat__h24755 or - rdat__h24763 or - rdat__h24769 or - rdat__h24783 or - rdat__h24791 or - rdat__h24797 or - rdat__h24803 or rdat__h24809 or rdat__h24815 or rdat__h24825) + rdat__h25116 or + rdat__h25122 or + rdat__h25128 or + rdat__h25141 or + rdat__h25164 or + rdat__h25264 or + rdat__h25278 or + rdat__h25286 or + rdat__h25292 or + rdat__h25306 or + rdat__h25314 or + rdat__h25320 or + rdat__h25326 or rdat__h25332 or rdat__h25338 or rdat__h25348) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h24550 = smaCtrl; - 8'h04: g_data__h24550 = rdat__h24593; - 8'h08: g_data__h24550 = rdat__h24599; - 8'h10: g_data__h24550 = rdat__h24605; - 8'h14: g_data__h24550 = rdat__h24618; - 8'h18: g_data__h24550 = rdat__h24641; - 8'h20: g_data__h24550 = rdat__h24741; - 8'h24: g_data__h24550 = rdat__h24755; - 8'h28: g_data__h24550 = rdat__h24763; - 8'h2C: g_data__h24550 = rdat__h24769; - 8'h30: g_data__h24550 = rdat__h24783; - 8'h34: g_data__h24550 = rdat__h24791; - 8'h38: g_data__h24550 = rdat__h24797; - 8'h3C: g_data__h24550 = rdat__h24803; - 8'h40: g_data__h24550 = rdat__h24809; - 8'h44: g_data__h24550 = rdat__h24815; - 8'h48: g_data__h24550 = rdat__h24825; - default: g_data__h24550 = 32'd0; + 8'h0: g_data__h25073 = smaCtrl; + 8'h04: g_data__h25073 = rdat__h25116; + 8'h08: g_data__h25073 = rdat__h25122; + 8'h10: g_data__h25073 = rdat__h25128; + 8'h14: g_data__h25073 = rdat__h25141; + 8'h18: g_data__h25073 = rdat__h25164; + 8'h20: g_data__h25073 = rdat__h25264; + 8'h24: g_data__h25073 = rdat__h25278; + 8'h28: g_data__h25073 = rdat__h25286; + 8'h2C: g_data__h25073 = rdat__h25292; + 8'h30: g_data__h25073 = rdat__h25306; + 8'h34: g_data__h25073 = rdat__h25314; + 8'h38: g_data__h25073 = rdat__h25320; + 8'h3C: g_data__h25073 = rdat__h25326; + 8'h40: g_data__h25073 = rdat__h25332; + 8'h44: g_data__h25073 = rdat__h25338; + 8'h48: g_data__h25073 = rdat__h25348; + default: g_data__h25073 = 32'd0; endcase end @@ -2753,7 +2761,7 @@ module mkSMAdapter4B(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin abortCount <= `BSV_ASSIGNMENT_DELAY 32'd0; doAbort <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -3001,8 +3009,8 @@ module mkSMAdapter4B(wciS0_Clk, wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -3127,152 +3135,152 @@ module mkSMAdapter4B(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_start) + begin + v__h3729 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3729, + wci_wslv_reqF$D_OUT[36:34], + wci_wslv_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmrd_mesgBegin) begin - v__h18191 = $time; + v__h18699 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmrd_mesgBegin) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", - v__h18191, + v__h18699, mesgCount, wmi_sFlagReg[23:0], wmi_sFlagReg[31:24]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56]) begin - v__h22600 = $time; + v__h23115 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56]) $display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x", - v__h22600, + v__h23115, mesgCount, wsiS_reqFifo$D_OUT[55:44], wsiS_reqFifo$D_OUT[7:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56]) begin - v__h22659 = $time; + v__h23174 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56]) $display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x", - v__h22659, + v__h23174, mesgCount); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) begin - v__h24001 = $time; + v__h24522 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) - $display("[%0d]: %m: wmwt_doAbort", v__h24001); - if (wciS0_MReset_n) + $display("[%0d]: %m: wmwt_doAbort", v__h24522); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) begin - v__h24184 = $time; + v__h24705 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) $display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x", - v__h24184, + v__h24705, mesgCount, thisMesg[15:0]); - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_wslv_ctl_op_start) - begin - v__h3651 = $time; - #0; - end - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_wslv_ctl_op_start) - $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3651, - wci_wslv_reqF$D_OUT[36:34], - wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h24380 = $time; + v__h24901 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h24380, + v__h24901, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h25038 = $time; + v__h25563 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x", - v__h25038, + v__h25563, smaCtrl); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3969 = $time; + v__h4048 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3969, + v__h4048, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3825 = $time; + v__h3904 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3825, + v__h3904, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkSMAdapter8B.v b/rtl/mkSMAdapter8B.v index fe3f43e8..00b3b377 100644 --- a/rtl/mkSMAdapter8B.v +++ b/rtl/mkSMAdapter8B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:25 EDT 2012 +// On Mon Sep 24 15:03:40 EDT 2012 // // // Ports: @@ -64,7 +64,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkSMAdapter8B(wciS0_Clk, @@ -988,64 +996,64 @@ module mkSMAdapter8B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h18191, - v__h21903, - v__h21962, - v__h23468, - v__h23651, - v__h23847, - v__h24505, - v__h3651, - v__h3825, - v__h3969; - reg [31 : 0] g_data__h24017; - wire [91 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894; - wire [31 : 0] rdat__h24060, - rdat__h24066, - rdat__h24072, - rdat__h24085, - rdat__h24108, - rdat__h24208, - rdat__h24222, - rdat__h24230, - rdat__h24236, - rdat__h24250, - rdat__h24258, - rdat__h24264, - rdat__h24270, - rdat__h24276, - rdat__h24282, - rdat__h24292, - value__h6580, - x__h18791; - wire [23 : 0] b__h17902, - mesgMetaF_length__h22484, - residue__h17765, - x__h18022; - wire [15 : 0] wsiBurstLength__h18650, x__h24112, x_length__h23048; - wire [13 : 0] b__h18275, mlB__h22317, mlInc__h22316; - wire [11 : 0] b__h15090, sendData_burstLength__h18732, x__h16444; - wire [7 : 0] mesgMetaF_opcode__h22483, sendData_byteEn__h18734; - wire [3 : 0] x__h22523, - x__h22535, - x__h22547, - x__h22559, - x__h22571, - x__h22583, - x__h22595, - y__h22524, - y__h22536, - y__h22548, - y__h22560, - y__h22572, - y__h22584, - y__h22596; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893; + reg [63 : 0] v__h18699, + v__h22418, + v__h22477, + v__h23989, + v__h24172, + v__h24368, + v__h25030, + v__h3729, + v__h3904, + v__h4048; + reg [31 : 0] g_data__h24540; + wire [91 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893; + wire [31 : 0] rdat__h24583, + rdat__h24589, + rdat__h24595, + rdat__h24608, + rdat__h24631, + rdat__h24731, + rdat__h24745, + rdat__h24753, + rdat__h24759, + rdat__h24773, + rdat__h24781, + rdat__h24787, + rdat__h24793, + rdat__h24799, + rdat__h24805, + rdat__h24815, + value__h6702, + x__h19302; + wire [23 : 0] b__h18410, + mesgMetaF_length__h22999, + residue__h18273, + x__h18530; + wire [15 : 0] wsiBurstLength__h19161, x__h24635, x_length__h23563; + wire [13 : 0] b__h18783, mlB__h22832, mlInc__h22831; + wire [11 : 0] b__h15473, sendData_burstLength__h19243, x__h16878; + wire [7 : 0] mesgMetaF_opcode__h22998, sendData_byteEn__h19245; + wire [3 : 0] x__h23038, + x__h23050, + x__h23062, + x__h23074, + x__h23086, + x__h23098, + x__h23110, + y__h23039, + y__h23051, + y__h23063, + y__h23075, + y__h23087, + y__h23099, + y__h23111; + wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d901; wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542, wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670, - x__h18446, - x__h24286; + x__h18954, + x__h24809; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1129,7 +1137,7 @@ module mkSMAdapter8B(wciS0_Clk, assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ; // submodule mesgTokenF - FIFO10 #(.guarded(32'd1)) mesgTokenF(.RST_N(wciS0_MReset_n), + FIFO10 #(.guarded(32'd1)) mesgTokenF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .ENQ(mesgTokenF$ENQ), .DEQ(mesgTokenF$DEQ), @@ -1158,7 +1166,7 @@ module mkSMAdapter8B(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -1169,7 +1177,7 @@ module mkSMAdapter8B(wciS0_Clk, .EMPTY_N(wci_wslv_reqF$EMPTY_N)); // submodule wmi_respF - FIFO2 #(.width(32'd66), .guarded(32'd1)) wmi_respF(.RST_N(wciS0_MReset_n), + FIFO2 #(.width(32'd66), .guarded(32'd1)) wmi_respF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wmi_respF$D_IN), .ENQ(wmi_respF$ENQ), @@ -1183,7 +1191,7 @@ module mkSMAdapter8B(wciS0_Clk, SizedFIFO #(.p1width(32'd97), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wsiS_reqFifo$D_IN), .ENQ(wsiS_reqFifo$ENQ), @@ -1210,6 +1218,40 @@ module mkSMAdapter8B(wciS0_Clk, smaCtrl[3:0] == 4'h9) && mesgPreRequest ; + // rule RL_wci_wslv_ctl_op_start + assign WILL_FIRE_RL_wci_wslv_ctl_op_start = + wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd2 && + wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_wmi_reqF_deq + assign WILL_FIRE_RL_wmi_reqF_deq = + wmi_operateD && wmi_peerIsReady && !wmi_sThreadBusy_d ; + + // rule RL_wsiM_reqFifo_deq + assign WILL_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + + // rule RL_wsipass_doMessagePush + assign WILL_FIRE_RL_wsipass_doMessagePush = + wsiS_reqFifo$EMPTY_N && + (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && + wci_wslv_cState == 3'd2 && + smaCtrl[3:0] == 4'h0 ; + // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && @@ -1226,13 +1268,6 @@ module mkSMAdapter8B(wciS0_Clk, !wmi_sDataThreadBusy_d && unrollCnt == 16'd0 ; - // rule RL_wsipass_doMessagePush - assign WILL_FIRE_RL_wsipass_doMessagePush = - wsiS_reqFifo$EMPTY_N && - (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && - wci_wslv_cState == 3'd2 && - smaCtrl[3:0] == 4'h0 ; - // rule RL_wmrd_mesgBodyResponse assign WILL_FIRE_RL_wmrd_mesgBodyResponse = wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && @@ -1275,29 +1310,6 @@ module mkSMAdapter8B(wciS0_Clk, !doAbort && endOfMessage ; - // rule RL_wci_wslv_ctl_op_start - assign WILL_FIRE_RL_wci_wslv_ctl_op_start = - wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && - !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - - // rule RL_wci_ctrl_EiI - assign WILL_FIRE_RL_wci_ctrl_EiI = - wci_wslv_wci_ctrl_pw$whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd0 && - wci_wslv_reqF$D_OUT[36:34] == 3'd0 ; - - // rule RL_wci_ctrl_OrE - assign WILL_FIRE_RL_wci_ctrl_OrE = - wci_wslv_wci_ctrl_pw$whas && - WILL_FIRE_RL_wci_wslv_ctl_op_start && - wci_wslv_cState == 3'd2 && - wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; - - // rule RL_wmi_reqF_deq - assign WILL_FIRE_RL_wmi_reqF_deq = - wmi_operateD && wmi_peerIsReady && !wmi_sThreadBusy_d ; - // rule RL_wmi_reqF_incCtr assign WILL_FIRE_RL_wmi_reqF_incCtr = ((wmi_reqF_c_r == 2'd0) ? @@ -1361,10 +1373,6 @@ module mkSMAdapter8B(wciS0_Clk, wmi_dhF_dequeueing$whas && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - // rule RL_wsiM_reqFifo_deq - assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; - // rule RL_wmrd_mesgResptoWsi assign WILL_FIRE_RL_wmrd_mesgResptoWsi = wsiM_reqFifo_c_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && @@ -1477,7 +1485,7 @@ module mkSMAdapter8B(wciS0_Clk, assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ; assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 ; + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 ; assign MUX_wmi_reqF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ; assign MUX_wmi_reqF_q_1$write_1__SEL_2 = @@ -1496,23 +1504,23 @@ module mkSMAdapter8B(wciS0_Clk, !WILL_FIRE_RL_wmwt_messageFinalize ; assign MUX_fabRespCredit_value$write_1__VAL_2 = fabRespCredit_value + - (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15090 : 12'd0) + + (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15473 : 12'd0) + (WILL_FIRE_RL_wmrd_mesgResptoWsi ? 12'd1 : 12'd0) ; assign MUX_fabWordsRemain$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17902[13:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h18410[13:0] ; assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; assign MUX_mesgCount$write_1__VAL_1 = mesgCount + 32'd1 ; assign MUX_mesgLengthSoFar$write_1__VAL_1 = - mesgLengthSoFar + mlInc__h22316 ; + mesgLengthSoFar + mlInc__h22831 ; assign MUX_mesgReqAddr$write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[10:0], 3'd0 } ; assign MUX_opcode$write_1__VAL_3 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ; assign MUX_thisMesg$write_1__VAL_1 = - { mesgCount[7:0], mesgMetaF_opcode__h22483, x_length__h23048 } ; + { mesgCount[7:0], mesgMetaF_opcode__h22998, x_length__h23563 } ; assign MUX_thisMesg$write_1__VAL_2 = { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; assign MUX_unrollCnt$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h17902[15:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h18410[15:0] ; assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && @@ -1548,7 +1556,7 @@ module mkSMAdapter8B(wciS0_Clk, 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24017 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24540 } ; assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r + 2'd1 ; assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ; assign MUX_wmi_dhF_q_0$write_1__VAL_1 = @@ -1562,11 +1570,11 @@ module mkSMAdapter8B(wciS0_Clk, assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ; assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ; assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd1) ? value__h6580 : wmi_mFlagF_q_1 ; + (wmi_mFlagF_c_r == 2'd1) ? value__h6702 : wmi_mFlagF_q_1 ; assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd2) ? value__h6580 : 32'd0 ; + (wmi_mFlagF_c_r == 2'd2) ? value__h6702 : 32'd0 ; assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 = - { mesgMetaF_opcode__h22483, mesgMetaF_length__h22484 } ; + { mesgMetaF_opcode__h22998, mesgMetaF_length__h22999 } ; assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r + 2'd1 ; assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r - 2'd1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_1 = @@ -1582,7 +1590,7 @@ module mkSMAdapter8B(wciS0_Clk, MUX_wmi_reqF_q_0$write_1__VAL_2 : 32'd0 ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_1 = - { 4'd5, x__h18446, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; + { 4'd5, x__h18954, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_2 = { 4'd3, wsiS_reqFifo$D_OUT[93], 1'b0, mesgLengthSoFar, 12'd1 } ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; @@ -1639,7 +1647,7 @@ module mkSMAdapter8B(wciS0_Clk, assign wmi_reqF_x_wire$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - assign wmi_mFlagF_x_wire$wget = value__h6580 ; + assign wmi_mFlagF_x_wire$wget = value__h6702 ; assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ; assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_2 ; assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; @@ -1675,7 +1683,7 @@ module mkSMAdapter8B(wciS0_Clk, assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; assign wsiS_sThreadBusy_dw$whas = wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; - assign fabRespCredit_acc_v1$wget = b__h15090 ; + assign fabRespCredit_acc_v1$wget = b__h15473 ; assign fabRespCredit_acc_v1$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign fabRespCredit_acc_v2$wget = 12'd1 ; assign fabRespCredit_acc_v2$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; @@ -1685,9 +1693,9 @@ module mkSMAdapter8B(wciS0_Clk, { 3'd1, unrollCnt == 16'd1, !smaCtrl[5], - sendData_burstLength__h18732, + sendData_burstLength__h19243, wmi_respF$D_OUT[63:0], - sendData_byteEn__h18734, + sendData_byteEn__h19245, thisMesg[23:16] } ; assign respF_wDataIn$whas = respF_pwEnqueue$whas ; assign respF_wDataOut$wget = MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; @@ -1731,7 +1739,7 @@ module mkSMAdapter8B(wciS0_Clk, assign wmi_reqF_dequeueing$whas = WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'd0 ; assign wmi_mFlagF_enqueueing$whas = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 || + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[93] ; assign wmi_mFlagF_dequeueing$whas = @@ -1800,7 +1808,7 @@ module mkSMAdapter8B(wciS0_Clk, // register fabWordsCurReq assign fabWordsCurReq$D_IN = - (fabWordsRemain <= b__h18275) ? fabWordsRemain : b__h18275 ; + (fabWordsRemain <= b__h18783) ? fabWordsRemain : b__h18783 ; assign fabWordsCurReq$EN = MUX_mesgReqOK$write_1__SEL_3 ; // register fabWordsRemain @@ -1907,14 +1915,14 @@ module mkSMAdapter8B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893, + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d901, respF_pwEnqueue$whas && respF_wDataIn$wget[93], respF_pwEnqueue$whas && respF_wDataIn$wget[92], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr - assign respF_rRdPtr$D_IN = x__h16444 ; + assign respF_rRdPtr$D_IN = x__h16878 ; assign respF_rRdPtr$EN = WILL_FIRE_RL_wmrd_mesgResptoWsi ; // register respF_rWrPtr @@ -2164,12 +2172,12 @@ module mkSMAdapter8B(wciS0_Clk, always@(WILL_FIRE_RL_wmi_mFlagF_both or MUX_wmi_mFlagF_q_0$write_1__VAL_1 or MUX_wmi_mFlagF_q_0$write_1__SEL_2 or - value__h6580 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_mFlagF_both: wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_1; - MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6580; + MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6702; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1; default: wmi_mFlagF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -2183,12 +2191,12 @@ module mkSMAdapter8B(wciS0_Clk, always@(WILL_FIRE_RL_wmi_mFlagF_both or MUX_wmi_mFlagF_q_1$write_1__VAL_1 or MUX_wmi_mFlagF_q_1$write_1__SEL_2 or - value__h6580 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_mFlagF_both: wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_1; - MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6580; + MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6702; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0; default: wmi_mFlagF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -2509,13 +2517,13 @@ module mkSMAdapter8B(wciS0_Clk, assign respF_memory$ADDRA = respF_rWrPtr[10:0] ; assign respF_memory$ADDRB = WILL_FIRE_RL_wmrd_mesgResptoWsi ? - x__h16444[10:0] : + x__h16878[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893, + { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d901, respF_pwEnqueue$whas && respF_wDataIn$wget[93], respF_pwEnqueue$whas && respF_wDataIn$wget[92], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893 } ; assign respF_memory$DIB = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; @@ -2545,69 +2553,69 @@ module mkSMAdapter8B(wciS0_Clk, // remaining internal signals assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893 = - respF_pwEnqueue$whas ? respF_wDataIn$wget[96:94] : 3'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894 = respF_pwEnqueue$whas ? respF_wDataIn$wget[91:0] : 92'd0 ; + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d901 = + respF_pwEnqueue$whas ? respF_wDataIn$wget[96:94] : 3'd0 ; assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && - (!x__h18446 || wmi_mFlagF_c_r != 2'd2) ; - assign b__h15090 = -fabWordsCurReq[11:0] ; - assign b__h17902 = x__h18022 + residue__h17765 ; - assign b__h18275 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; - assign mesgMetaF_length__h22484 = + (!x__h18954 || wmi_mFlagF_c_r != 2'd2) ; + assign b__h15473 = -fabWordsCurReq[11:0] ; + assign b__h18410 = x__h18530 + residue__h18273 ; + assign b__h18783 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; + assign mesgMetaF_length__h22999 = (wsiS_reqFifo$D_OUT[93] && wsiS_reqFifo$D_OUT[15:8] == 8'd0 && mesgLengthSoFar == 14'd0) ? 24'd0 : - { 10'd0, mlB__h22317 } ; - assign mesgMetaF_opcode__h22483 = opcode[8] ? opcode[7:0] : 8'd0 ; - assign mlB__h22317 = MUX_mesgLengthSoFar$write_1__VAL_1 ; - assign mlInc__h22316 = + { 10'd0, mlB__h22832 } ; + assign mesgMetaF_opcode__h22998 = opcode[8] ? opcode[7:0] : 8'd0 ; + assign mlB__h22832 = MUX_mesgLengthSoFar$write_1__VAL_1 ; + assign mlInc__h22831 = wsiS_reqFifo$D_OUT[93] ? - { 10'd0, x__h22523 + y__h22524 } : + { 10'd0, x__h23038 + y__h23039 } : 14'd8 ; - assign rdat__h24060 = hasDebugLogic ? mesgCount : 32'd0 ; - assign rdat__h24066 = hasDebugLogic ? abortCount : 32'd0 ; - assign rdat__h24072 = hasDebugLogic ? thisMesg : 32'd0 ; - assign rdat__h24085 = hasDebugLogic ? lastMesg : 32'd0 ; - assign rdat__h24108 = hasDebugLogic ? { 16'd0, x__h24112 } : 32'd0 ; - assign rdat__h24208 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h24222 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h24230 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h24236 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h24250 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h24258 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h24264 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; - assign rdat__h24270 = hasDebugLogic ? wmwtPushCount : 32'd0 ; - assign rdat__h24276 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; - assign rdat__h24282 = hasDebugLogic ? { 31'd0, x__h24286 } : 32'd0 ; - assign rdat__h24292 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; - assign residue__h17765 = + assign rdat__h24583 = hasDebugLogic ? mesgCount : 32'd0 ; + assign rdat__h24589 = hasDebugLogic ? abortCount : 32'd0 ; + assign rdat__h24595 = hasDebugLogic ? thisMesg : 32'd0 ; + assign rdat__h24608 = hasDebugLogic ? lastMesg : 32'd0 ; + assign rdat__h24631 = hasDebugLogic ? { 16'd0, x__h24635 } : 32'd0 ; + assign rdat__h24731 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h24745 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h24753 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h24759 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h24773 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h24781 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h24787 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; + assign rdat__h24793 = hasDebugLogic ? wmwtPushCount : 32'd0 ; + assign rdat__h24799 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; + assign rdat__h24805 = hasDebugLogic ? { 31'd0, x__h24809 } : 32'd0 ; + assign rdat__h24815 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; + assign residue__h18273 = ({ 3'd0, wmi_sFlagReg[2:0] } == 6'd0) ? 24'd0 : 24'd1 ; - assign sendData_burstLength__h18732 = + assign sendData_burstLength__h19243 = (thisMesg[15:0] == 16'd0 || smaCtrl[5] && unrollCnt == 16'd1) ? 12'd1 : - (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h18650[11:0]) ; - assign sendData_byteEn__h18734 = + (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h19161[11:0]) ; + assign sendData_byteEn__h19245 = (thisMesg[15:0] == 16'd0) ? 8'd0 : - ((unrollCnt == 16'd1) ? x__h18791[7:0] : 8'd255) ; - assign value__h6580 = + ((unrollCnt == 16'd1) ? x__h19302[7:0] : 8'd255) ; + assign value__h6702 = MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 ? 32'hAAAAAAAA /* unspecified value */ : MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 ; assign wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 = wmi_respF$EMPTY_N && (smaCtrl[4] || respF_rRdPtr + 12'd1024 != respF_rWrPtr) ; - assign wsiBurstLength__h18650 = + assign wsiBurstLength__h19161 = smaCtrl[5] ? 16'd2 : { 3'd0, thisMesg[15:3] } ; assign wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670 = wsiS_reqFifo$EMPTY_N && (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_c_r != 2'd2) && (!wsiS_reqFifo$D_OUT[93] || wmi_mFlagF_c_r != 2'd2) ; - assign x__h16444 = respF_rRdPtr + 12'd1 ; - assign x__h18022 = { 3'd0, wmi_sFlagReg[23:3] } ; - assign x__h18446 = fabWordsRemain == fabWordsCurReq ; - assign x__h18791 = + assign x__h16878 = respF_rRdPtr + 12'd1 ; + assign x__h18530 = { 3'd0, wmi_sFlagReg[23:3] } ; + assign x__h18954 = fabWordsRemain == fabWordsCurReq ; + assign x__h19302 = ({ 3'd0, thisMesg[2:0] } == 6'd0) ? 32'hFFFFFFFF : (({ 3'd0, thisMesg[2:0] } <= 6'd1) ? @@ -2714,58 +2722,58 @@ module mkSMAdapter8B(wciS0_Clk, 6'd31) ? 32'h7FFFFFFF : 32'hFFFFFFFF))))))))))))))))))))))))))))))) ; - assign x__h22523 = x__h22535 + y__h22536 ; - assign x__h22535 = x__h22547 + y__h22548 ; - assign x__h22547 = x__h22559 + y__h22560 ; - assign x__h22559 = x__h22571 + y__h22572 ; - assign x__h22571 = x__h22583 + y__h22584 ; - assign x__h22583 = x__h22595 + y__h22596 ; - assign x__h22595 = { 3'd0, wsiS_reqFifo$D_OUT[15] } ; - assign x__h24112 = { wsiS_statusR, wsiM_statusR } ; - assign x__h24286 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; - assign x_length__h23048 = { 2'd0, mlB__h22317 } ; - assign y__h22524 = { 3'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h22536 = { 3'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h22548 = { 3'd0, wsiS_reqFifo$D_OUT[10] } ; - assign y__h22560 = { 3'd0, wsiS_reqFifo$D_OUT[11] } ; - assign y__h22572 = { 3'd0, wsiS_reqFifo$D_OUT[12] } ; - assign y__h22584 = { 3'd0, wsiS_reqFifo$D_OUT[13] } ; - assign y__h22596 = { 3'd0, wsiS_reqFifo$D_OUT[14] } ; + assign x__h23038 = x__h23050 + y__h23051 ; + assign x__h23050 = x__h23062 + y__h23063 ; + assign x__h23062 = x__h23074 + y__h23075 ; + assign x__h23074 = x__h23086 + y__h23087 ; + assign x__h23086 = x__h23098 + y__h23099 ; + assign x__h23098 = x__h23110 + y__h23111 ; + assign x__h23110 = { 3'd0, wsiS_reqFifo$D_OUT[15] } ; + assign x__h24635 = { wsiS_statusR, wsiM_statusR } ; + assign x__h24809 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; + assign x_length__h23563 = { 2'd0, mlB__h22832 } ; + assign y__h23039 = { 3'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h23051 = { 3'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h23063 = { 3'd0, wsiS_reqFifo$D_OUT[10] } ; + assign y__h23075 = { 3'd0, wsiS_reqFifo$D_OUT[11] } ; + assign y__h23087 = { 3'd0, wsiS_reqFifo$D_OUT[12] } ; + assign y__h23099 = { 3'd0, wsiS_reqFifo$D_OUT[13] } ; + assign y__h23111 = { 3'd0, wsiS_reqFifo$D_OUT[14] } ; always@(wci_wslv_reqF$D_OUT or smaCtrl or - rdat__h24060 or - rdat__h24066 or - rdat__h24072 or - rdat__h24085 or - rdat__h24108 or - rdat__h24208 or - rdat__h24222 or - rdat__h24230 or - rdat__h24236 or - rdat__h24250 or - rdat__h24258 or - rdat__h24264 or - rdat__h24270 or rdat__h24276 or rdat__h24282 or rdat__h24292) + rdat__h24583 or + rdat__h24589 or + rdat__h24595 or + rdat__h24608 or + rdat__h24631 or + rdat__h24731 or + rdat__h24745 or + rdat__h24753 or + rdat__h24759 or + rdat__h24773 or + rdat__h24781 or + rdat__h24787 or + rdat__h24793 or rdat__h24799 or rdat__h24805 or rdat__h24815) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h24017 = smaCtrl; - 8'h04: g_data__h24017 = rdat__h24060; - 8'h08: g_data__h24017 = rdat__h24066; - 8'h10: g_data__h24017 = rdat__h24072; - 8'h14: g_data__h24017 = rdat__h24085; - 8'h18: g_data__h24017 = rdat__h24108; - 8'h20: g_data__h24017 = rdat__h24208; - 8'h24: g_data__h24017 = rdat__h24222; - 8'h28: g_data__h24017 = rdat__h24230; - 8'h2C: g_data__h24017 = rdat__h24236; - 8'h30: g_data__h24017 = rdat__h24250; - 8'h34: g_data__h24017 = rdat__h24258; - 8'h38: g_data__h24017 = rdat__h24264; - 8'h3C: g_data__h24017 = rdat__h24270; - 8'h40: g_data__h24017 = rdat__h24276; - 8'h44: g_data__h24017 = rdat__h24282; - 8'h48: g_data__h24017 = rdat__h24292; - default: g_data__h24017 = 32'd0; + 8'h0: g_data__h24540 = smaCtrl; + 8'h04: g_data__h24540 = rdat__h24583; + 8'h08: g_data__h24540 = rdat__h24589; + 8'h10: g_data__h24540 = rdat__h24595; + 8'h14: g_data__h24540 = rdat__h24608; + 8'h18: g_data__h24540 = rdat__h24631; + 8'h20: g_data__h24540 = rdat__h24731; + 8'h24: g_data__h24540 = rdat__h24745; + 8'h28: g_data__h24540 = rdat__h24753; + 8'h2C: g_data__h24540 = rdat__h24759; + 8'h30: g_data__h24540 = rdat__h24773; + 8'h34: g_data__h24540 = rdat__h24781; + 8'h38: g_data__h24540 = rdat__h24787; + 8'h3C: g_data__h24540 = rdat__h24793; + 8'h40: g_data__h24540 = rdat__h24799; + 8'h44: g_data__h24540 = rdat__h24805; + 8'h48: g_data__h24540 = rdat__h24815; + default: g_data__h24540 = 32'd0; endcase end @@ -2773,7 +2781,7 @@ module mkSMAdapter8B(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin abortCount <= `BSV_ASSIGNMENT_DELAY 32'd0; doAbort <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -3024,8 +3032,8 @@ module mkSMAdapter8B(wciS0_Clk, wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -3150,152 +3158,152 @@ module mkSMAdapter8B(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_start) + begin + v__h3729 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3729, + wci_wslv_reqF$D_OUT[36:34], + wci_wslv_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmrd_mesgBegin) begin - v__h18191 = $time; + v__h18699 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmrd_mesgBegin) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", - v__h18191, + v__h18699, mesgCount, wmi_sFlagReg[23:0], wmi_sFlagReg[31:24]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[92]) begin - v__h21903 = $time; + v__h22418 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[92]) $display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x", - v__h21903, + v__h22418, mesgCount, wsiS_reqFifo$D_OUT[91:80], wsiS_reqFifo$D_OUT[7:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[92]) begin - v__h21962 = $time; + v__h22477 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[92]) $display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x", - v__h21962, + v__h22477, mesgCount); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) begin - v__h23468 = $time; + v__h23989 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) - $display("[%0d]: %m: wmwt_doAbort", v__h23468); - if (wciS0_MReset_n) + $display("[%0d]: %m: wmwt_doAbort", v__h23989); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) begin - v__h23651 = $time; + v__h24172 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) $display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x", - v__h23651, + v__h24172, mesgCount, thisMesg[15:0]); - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_wslv_ctl_op_start) - begin - v__h3651 = $time; - #0; - end - if (wciS0_MReset_n) - if (WILL_FIRE_RL_wci_wslv_ctl_op_start) - $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3651, - wci_wslv_reqF$D_OUT[36:34], - wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h23847 = $time; + v__h24368 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h23847, + v__h24368, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h24505 = $time; + v__h25030 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x", - v__h24505, + v__h25030, smaCtrl); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3969 = $time; + v__h4048 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3969, + v__h4048, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3825 = $time; + v__h3904 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3825, + v__h3904, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkTLPCM.v b/rtl/mkTLPCM.v index 026384e9..6ab19ed5 100644 --- a/rtl/mkTLPCM.v +++ b/rtl/mkTLPCM.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:39:04 EDT 2012 +// On Mon Sep 24 15:04:25 EDT 2012 // // // Ports: @@ -34,7 +34,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkTLPCM(pfk, @@ -127,7 +135,7 @@ module mkTLPCM(pfk, // remaining internal signals reg [1 : 0] CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1; - wire [13 : 0] IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d11; + wire [13 : 0] x__h110; // actionvalue method c_request_get assign c_request_get = pktMerge$oport_get ; @@ -151,7 +159,7 @@ module mkTLPCM(pfk, assign RDY_s1_response_get = pktFork$RDY_oport1_get ; // submodule pktFork - mkPktFork pktFork(.pfk(IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d11), + mkPktFork pktFork(.pfk(x__h110), .CLK(CLK), .RST_N(RST_N), .iport_put(pktFork$iport_put), @@ -191,7 +199,7 @@ module mkTLPCM(pfk, assign pktMerge$EN_oport_get = EN_c_request_get ; // remaining internal signals - assign IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d11 = + assign x__h110 = { CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1, pfk[11:0] } ; always@(pfk) diff --git a/rtl/mkTLPClientNode.v b/rtl/mkTLPClientNode.v index 82fb434f..532f7ca6 100644 --- a/rtl/mkTLPClientNode.v +++ b/rtl/mkTLPClientNode.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:39:04 EDT 2012 +// On Mon Sep 24 15:04:25 EDT 2012 // // // Ports: @@ -28,7 +28,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkTLPClientNode(pfk, @@ -98,7 +106,7 @@ module mkTLPClientNode(pfk, // remaining internal signals reg [1 : 0] CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1; - wire [13 : 0] IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d15; + wire [13 : 0] x__h110; // action method s_request_put assign RDY_s_request_put = pktMerge$RDY_iport0_put ; @@ -115,7 +123,7 @@ module mkTLPClientNode(pfk, assign RDY_g_get = pktMerge$RDY_oport_get ; // submodule pktFork - mkPktFork pktFork(.pfk(IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d15), + mkPktFork pktFork(.pfk(x__h110), .CLK(CLK), .RST_N(RST_N), .iport_put(pktFork$iport_put), @@ -157,7 +165,7 @@ module mkTLPClientNode(pfk, assign pktMerge$EN_oport_get = EN_g_get ; // remaining internal signals - assign IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d15 = + assign x__h110 = { CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1, pfk[11:0] } ; always@(pfk) diff --git a/rtl/mkTLPSM.v b/rtl/mkTLPSM.v index 6f1b18bc..71451111 100644 --- a/rtl/mkTLPSM.v +++ b/rtl/mkTLPSM.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:39:04 EDT 2012 +// On Mon Sep 24 15:04:25 EDT 2012 // // // Ports: @@ -34,7 +34,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkTLPSM(pfk, @@ -127,7 +135,7 @@ module mkTLPSM(pfk, // remaining internal signals reg [1 : 0] CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1; - wire [13 : 0] IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d11; + wire [13 : 0] x__h110; // action method s_request_put assign RDY_s_request_put = pktFork$RDY_iport_put ; @@ -151,7 +159,7 @@ module mkTLPSM(pfk, assign RDY_c1_response_put = pktMerge$RDY_iport1_put ; // submodule pktFork - mkPktFork pktFork(.pfk(IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d11), + mkPktFork pktFork(.pfk(x__h110), .CLK(CLK), .RST_N(RST_N), .iport_put(pktFork$iport_put), @@ -191,7 +199,7 @@ module mkTLPSM(pfk, assign pktMerge$EN_oport_get = EN_s_response_get ; // remaining internal signals - assign IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d11 = + assign x__h110 = { CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1, pfk[11:0] } ; always@(pfk) diff --git a/rtl/mkTLPServerNode.v b/rtl/mkTLPServerNode.v index 44f9473b..c6bb3f56 100644 --- a/rtl/mkTLPServerNode.v +++ b/rtl/mkTLPServerNode.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:39:04 EDT 2012 +// On Mon Sep 24 15:04:25 EDT 2012 // // // Ports: @@ -28,7 +28,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkTLPServerNode(pfk, @@ -98,7 +106,7 @@ module mkTLPServerNode(pfk, // remaining internal signals reg [1 : 0] CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1; - wire [13 : 0] IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d15; + wire [13 : 0] x__h110; // actionvalue method c_request_get assign c_request_get = pktFork$oport0_get ; @@ -115,7 +123,7 @@ module mkTLPServerNode(pfk, assign RDY_g_get = pktMerge$RDY_oport_get ; // submodule pktFork - mkPktFork pktFork(.pfk(IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d15), + mkPktFork pktFork(.pfk(x__h110), .CLK(CLK), .RST_N(RST_N), .iport_put(pktFork$iport_put), @@ -157,7 +165,7 @@ module mkTLPServerNode(pfk, assign pktMerge$EN_oport_get = EN_g_get ; // remaining internal signals - assign IF_pfk_BITS_13_TO_12_EQ_0_OR_pfk_BITS_13_TO_12_ETC___d15 = + assign x__h110 = { CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1, pfk[11:0] } ; always@(pfk) diff --git a/rtl/mkTimeClient.v b/rtl/mkTimeClient.v index d2fca9fc..bf25381e 100644 --- a/rtl/mkTimeClient.v +++ b/rtl/mkTimeClient.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:37 EDT 2012 +// On Mon Sep 24 15:03:53 EDT 2012 // // // Ports: @@ -25,7 +25,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkTimeClient(CLK_sys0_clk, @@ -100,7 +108,7 @@ module mkTimeClient(CLK_sys0_clk, // submodule now SyncRegister #(.width(32'd64), .init(64'd0)) now(.sCLK(CLK_sys0_clk), .dCLK(CLK_wti_clk), - .sRST_N(RST_N_sys0_rst), + .sRST(RST_N_sys0_rst), .sD_IN(now$sD_IN), .sEN(now$sEN), .dD_OUT(now$dD_OUT), @@ -131,7 +139,7 @@ module mkTimeClient(CLK_sys0_clk, always@(posedge CLK_wti_clk) begin - if (!RST_N_wti_rst) + if (RST_N_wti_rst == `BSV_RESET_VALUE) begin wti_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0; wti_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; diff --git a/rtl/mkWSICaptureWorker4B.v b/rtl/mkWSICaptureWorker4B.v index 30553680..23aac7d2 100644 --- a/rtl/mkWSICaptureWorker4B.v +++ b/rtl/mkWSICaptureWorker4B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:42 EDT 2012 +// On Mon Sep 24 15:03:58 EDT 2012 // // // Ports: @@ -39,7 +39,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkWSICaptureWorker4B(wciS0_Clk, @@ -875,49 +883,49 @@ module mkWSICaptureWorker4B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h25170, - v__h26216, - v__h26499, - v__h26702, - v__h3640, - v__h3814, - v__h3958; + reg [63 : 0] v__h25452, + v__h26500, + v__h26795, + v__h27000, + v__h3718, + v__h3893, + v__h4037; reg [31 : 0] IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951, - v__h26683; + v__h26981; reg CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q2, IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918, - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_80_EQ__ETC___d993, - IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d997; + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994, + IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d998; wire [63 : 0] wtiS_nowReq_BITS_63_TO_0__q1; - wire [31 : 0] g_data__h27773, - rdat___1__h26780, - rdat___1__h26864, - rdat___1__h26919, - rdat___1__h26933, - rdat___1__h26941, - v__h25297, - y_avValue__h25924, - y_avValue__h25968, - y_avValue__h26008, - y_avValue__h26048, - y_avValue__h26088; - wire [13 : 0] mlB__h23066, mlInc__h23065; + wire [31 : 0] g_data__h28071, + rdat___1__h27078, + rdat___1__h27162, + rdat___1__h27217, + rdat___1__h27231, + rdat___1__h27239, + v__h25581, + y_avValue__h26208, + y_avValue__h26252, + y_avValue__h26292, + y_avValue__h26332, + y_avValue__h26372; + wire [13 : 0] mlB__h23348, mlInc__h23347; wire [2 : 0] dataBram_serverAdapterB_cnt_21_PLUS_IF_dataBra_ETC___d327, metaBram_serverAdapterB_1_cnt_57_PLUS_IF_metaB_ETC___d563, metaBram_serverAdapterB_2_cnt_75_PLUS_IF_metaB_ETC___d681, metaBram_serverAdapterB_3_cnt_93_PLUS_IF_metaB_ETC___d799, metaBram_serverAdapterB_cnt_39_PLUS_IF_metaBra_ETC___d445, - x__h23114, - x__h23126, - x__h23138, - y__h23115, - y__h23127, - y__h23139; + x__h23396, + x__h23408, + x__h23420, + y__h23397, + y__h23409, + y__h23421; wire IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d927, NOT_controlReg_30_BIT_0_31_32_OR_controlReg_30_ETC___d856, controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878, - dataCount_37_ULT_1024___d1204, - metaCount_34_ULT_1024___d1203, + dataCount_37_ULT_1024___d1164, + metaCount_34_ULT_1024___d1096, splaF_i_notEmpty__96_AND_IF_splaF_first__97_BI_ETC___d929; // value method wciS0_sResp @@ -967,7 +975,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) dataBram_serverAdapterA_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) dataBram_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(dataBram_serverAdapterA_outDataCore$D_IN), .ENQ(dataBram_serverAdapterA_outDataCore$ENQ), @@ -981,7 +989,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) dataBram_serverAdapterB_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) dataBram_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(dataBram_serverAdapterB_outDataCore$D_IN), .ENQ(dataBram_serverAdapterB_outDataCore$ENQ), @@ -1063,7 +1071,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_1_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterA_1_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterA_1_outDataCore$D_IN), .ENQ(metaBram_serverAdapterA_1_outDataCore$ENQ), @@ -1077,7 +1085,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_2_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterA_2_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterA_2_outDataCore$D_IN), .ENQ(metaBram_serverAdapterA_2_outDataCore$ENQ), @@ -1091,7 +1099,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_3_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterA_3_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterA_3_outDataCore$D_IN), .ENQ(metaBram_serverAdapterA_3_outDataCore$ENQ), @@ -1105,7 +1113,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterA_outDataCore$D_IN), .ENQ(metaBram_serverAdapterA_outDataCore$ENQ), @@ -1119,7 +1127,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_1_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterB_1_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterB_1_outDataCore$D_IN), .ENQ(metaBram_serverAdapterB_1_outDataCore$ENQ), @@ -1133,7 +1141,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_2_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterB_2_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterB_2_outDataCore$D_IN), .ENQ(metaBram_serverAdapterB_2_outDataCore$ENQ), @@ -1147,7 +1155,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_3_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterB_3_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterB_3_outDataCore$D_IN), .ENQ(metaBram_serverAdapterB_3_outDataCore$ENQ), @@ -1161,7 +1169,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterB_outDataCore$D_IN), .ENQ(metaBram_serverAdapterB_outDataCore$ENQ), @@ -1172,7 +1180,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, .EMPTY_N(metaBram_serverAdapterB_outDataCore$EMPTY_N)); // submodule splaF - FIFO2 #(.width(32'd3), .guarded(32'd1)) splaF(.RST_N(wciS0_MReset_n), + FIFO2 #(.width(32'd3), .guarded(32'd1)) splaF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(splaF$D_IN), .ENQ(splaF$ENQ), @@ -1186,7 +1194,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -1200,7 +1208,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd61), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wsiS_reqFifo$D_IN), .ENQ(wsiS_reqFifo$ENQ), @@ -1232,7 +1240,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, // rule RL_wci_cfrd assign CAN_FIRE_RL_wci_cfrd = wci_wslv_reqF$EMPTY_N && - IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d997 && + IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d998 && (wci_wslv_reqF$D_OUT[63:52] == 12'h800 || wci_wslv_reqF$D_OUT[63:52] == 12'h400 || wci_wslv_respF_c_r != 2'd2) && @@ -1432,10 +1440,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, (wci_wslv_respF_c_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h27773 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h28071 } ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = { 2'd1, v__h25297 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = { 2'd1, v__h25581 } ; // inlined wires assign wci_wslv_wciReq$wget = @@ -1494,8 +1502,8 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign nowW$whas = 1'd1 ; assign statusReg_w$wget = { 6'd40, - !metaCount_34_ULT_1024___d1203, - !dataCount_37_ULT_1024___d1204, + !metaCount_34_ULT_1024___d1096, + !dataCount_37_ULT_1024___d1164, 24'd2361866 } ; assign statusReg_w$whas = 1'd1 ; assign dataBram_serverAdapterA_outData_enqData$wget = dataBram_memory$DOA ; @@ -1900,7 +1908,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign isFirst$EN = 1'b0 ; // register mesgLengthSoFar - assign mesgLengthSoFar$D_IN = wsiS_reqFifo$D_OUT[57] ? 14'd0 : mlB__h23066 ; + assign mesgLengthSoFar$D_IN = wsiS_reqFifo$D_OUT[57] ? 14'd0 : mlB__h23348 ; assign mesgLengthSoFar$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; // register metaBram_serverAdapterA_1_cnt @@ -2282,7 +2290,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, // submodule metaBram_memory assign metaBram_memory$ADDRA = metaCount[9:0] ; assign metaBram_memory$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; - assign metaBram_memory$DIA = { 18'd0, mlB__h23066 } ; + assign metaBram_memory$DIA = { 18'd0, mlB__h23348 } ; assign metaBram_memory$DIB = 32'd0 ; assign metaBram_memory$WEA = 1'd1 ; assign metaBram_memory$WEB = 1'd0 ; @@ -2439,8 +2447,8 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign NOT_controlReg_30_BIT_0_31_32_OR_controlReg_30_ETC___d856 = !controlReg[0] || controlReg[1] && - (!metaCount_34_ULT_1024___d1203 || - !dataCount_37_ULT_1024___d1204) || + (!metaCount_34_ULT_1024___d1096 || + !dataCount_37_ULT_1024___d1164) || (dataBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 && (!wsiS_reqFifo$D_OUT[57] || (metaBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 && @@ -2450,17 +2458,17 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 = controlReg[0] && (!controlReg[1] || - metaCount_34_ULT_1024___d1203 && - dataCount_37_ULT_1024___d1204) ; + metaCount_34_ULT_1024___d1096 && + dataCount_37_ULT_1024___d1164) ; assign dataBram_serverAdapterB_cnt_21_PLUS_IF_dataBra_ETC___d327 = dataBram_serverAdapterB_cnt + (WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways ? 3'd1 : 3'd0) + (dataBram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign dataCount_37_ULT_1024___d1204 = dataCount < 32'd1024 ; - assign g_data__h27773 = - (wci_wslv_reqF$D_OUT[63:52] == 12'h0) ? v__h26683 : 32'd0 ; + assign dataCount_37_ULT_1024___d1164 = dataCount < 32'd1024 ; + assign g_data__h28071 = + (wci_wslv_reqF$D_OUT[63:52] == 12'h0) ? v__h26981 : 32'd0 ; assign metaBram_serverAdapterB_1_cnt_57_PLUS_IF_metaB_ETC___d563 = metaBram_serverAdapterB_1_cnt + (WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways ? @@ -2491,19 +2499,19 @@ module mkWSICaptureWorker4B(wciS0_Clk, 3'd1 : 3'd0) + (metaBram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign metaCount_34_ULT_1024___d1203 = metaCount < 32'd1024 ; - assign mlB__h23066 = mesgLengthSoFar + mlInc__h23065 ; - assign mlInc__h23065 = + assign metaCount_34_ULT_1024___d1096 = metaCount < 32'd1024 ; + assign mlB__h23348 = mesgLengthSoFar + mlInc__h23347 ; + assign mlInc__h23347 = wsiS_reqFifo$D_OUT[57] ? - { 11'd0, x__h23114 + y__h23115 } : + { 11'd0, x__h23396 + y__h23397 } : 14'd4 ; - assign rdat___1__h26780 = statusReg_w$wget ; - assign rdat___1__h26864 = hasDebugLogic ? { 24'd0, wsiS_statusR } : 32'd0 ; - assign rdat___1__h26919 = + assign rdat___1__h27078 = statusReg_w$wget ; + assign rdat___1__h27162 = hasDebugLogic ? { 24'd0, wsiS_statusR } : 32'd0 ; + assign rdat___1__h27217 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat___1__h26933 = + assign rdat___1__h27231 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat___1__h26941 = + assign rdat___1__h27239 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; assign splaF_i_notEmpty__96_AND_IF_splaF_first__97_BI_ETC___d929 = splaF$EMPTY_N && @@ -2514,22 +2522,22 @@ module mkWSICaptureWorker4B(wciS0_Clk, (splaF$D_OUT[1:0] != 2'd0 || dataBram_serverAdapterB_outData_outData$whas) : IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d927) ; - assign v__h25297 = + assign v__h25581 = splaF$D_OUT[2] ? - y_avValue__h25924 : + y_avValue__h26208 : IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 ; assign wtiS_nowReq_BITS_63_TO_0__q1 = wtiS_nowReq[63:0] ; - assign x__h23114 = x__h23126 + y__h23127 ; - assign x__h23126 = x__h23138 + y__h23139 ; - assign x__h23138 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; - assign y__h23115 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h23127 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h23139 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; - assign y_avValue__h25924 = dataBram_serverAdapterB_outData_outData$wget ; - assign y_avValue__h25968 = metaBram_serverAdapterB_outData_outData$wget ; - assign y_avValue__h26008 = metaBram_serverAdapterB_1_outData_outData$wget ; - assign y_avValue__h26048 = metaBram_serverAdapterB_2_outData_outData$wget ; - assign y_avValue__h26088 = metaBram_serverAdapterB_3_outData_outData$wget ; + assign x__h23396 = x__h23408 + y__h23409 ; + assign x__h23408 = x__h23420 + y__h23421 ; + assign x__h23420 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; + assign y__h23397 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h23409 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h23421 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; + assign y_avValue__h26208 = dataBram_serverAdapterB_outData_outData$wget ; + assign y_avValue__h26252 = metaBram_serverAdapterB_outData_outData$wget ; + assign y_avValue__h26292 = metaBram_serverAdapterB_1_outData_outData$wget ; + assign y_avValue__h26332 = metaBram_serverAdapterB_2_outData_outData$wget ; + assign y_avValue__h26372 = metaBram_serverAdapterB_3_outData_outData$wget ; always@(splaF$D_OUT or metaBram_serverAdapterB_3_outDataCore$EMPTY_N or metaBram_serverAdapterB_3_outData_enqData$whas or @@ -2589,73 +2597,73 @@ module mkWSICaptureWorker4B(wciS0_Clk, begin case (wci_wslv_reqF$D_OUT[35:34]) 2'd0: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_80_EQ__ETC___d993 = + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994 = (metaBram_serverAdapterB_cnt ^ 3'h4) < 3'd7; 2'd1: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_80_EQ__ETC___d993 = + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994 = (metaBram_serverAdapterB_1_cnt ^ 3'h4) < 3'd7; 2'd2: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_80_EQ__ETC___d993 = + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994 = (metaBram_serverAdapterB_2_cnt ^ 3'h4) < 3'd7; 2'd3: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_80_EQ__ETC___d993 = + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994 = wci_wslv_reqF$D_OUT[35:34] != 2'd3 || (metaBram_serverAdapterB_3_cnt ^ 3'h4) < 3'd7; endcase end always@(wci_wslv_reqF$D_OUT or splaF$FULL_N or - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_80_EQ__ETC___d993 or + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994 or dataBram_serverAdapterB_cnt) begin case (wci_wslv_reqF$D_OUT[63:52]) - 12'h0: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d997 = 1'b1; + 12'h0: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d998 = 1'b1; 12'h800: - IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d997 = + IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d998 = (dataBram_serverAdapterB_cnt ^ 3'h4) < 3'd7 && splaF$FULL_N; - default: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d997 = + default: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d998 = wci_wslv_reqF$D_OUT[63:52] != 12'h400 || splaF$FULL_N && - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_80_EQ__ETC___d993; + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994; endcase end always@(splaF$D_OUT or - y_avValue__h26088 or - y_avValue__h25968 or y_avValue__h26008 or y_avValue__h26048) + y_avValue__h26372 or + y_avValue__h26252 or y_avValue__h26292 or y_avValue__h26332) begin case (splaF$D_OUT[1:0]) 2'd0: IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 = - y_avValue__h25968; + y_avValue__h26252; 2'd1: IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 = - y_avValue__h26008; + y_avValue__h26292; 2'd2: IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 = - y_avValue__h26048; + y_avValue__h26332; 2'd3: IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 = - y_avValue__h26088; + y_avValue__h26372; endcase end always@(wci_wslv_reqF$D_OUT or controlReg or metaCount or dataCount or - rdat___1__h26780 or - rdat___1__h26864 or - rdat___1__h26919 or rdat___1__h26933 or rdat___1__h26941) + rdat___1__h27078 or + rdat___1__h27162 or + rdat___1__h27217 or rdat___1__h27231 or rdat___1__h27239) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: v__h26683 = controlReg; - 8'h04: v__h26683 = metaCount; - 8'h08: v__h26683 = dataCount; - 8'h0C: v__h26683 = rdat___1__h26780; - 8'h10: v__h26683 = rdat___1__h26864; - 8'h14: v__h26683 = rdat___1__h26919; - 8'h18: v__h26683 = rdat___1__h26933; - 8'h1C: v__h26683 = rdat___1__h26941; - default: v__h26683 = 32'd0; + 8'h0: v__h26981 = controlReg; + 8'h04: v__h26981 = metaCount; + 8'h08: v__h26981 = dataCount; + 8'h0C: v__h26981 = rdat___1__h27078; + 8'h10: v__h26981 = rdat___1__h27162; + 8'h14: v__h26981 = rdat___1__h27217; + 8'h18: v__h26981 = rdat___1__h27231; + 8'h1C: v__h26981 = rdat___1__h27239; + default: v__h26981 = 32'd0; endcase end @@ -2663,7 +2671,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin dataBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; dataBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; @@ -2847,8 +2855,8 @@ module mkWSICaptureWorker4B(wciS0_Clk, wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -2938,180 +2946,180 @@ module mkWSICaptureWorker4B(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3640 = $time; + v__h3718 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3640, + v__h3718, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h0) begin - v__h26702 = $time; + v__h27000 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h0) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h26702, + v__h27000, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - v__h26683); - if (wciS0_MReset_n) + v__h26981); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 && wsiS_reqFifo$D_OUT[57]) begin - v__h25170 = $time; + v__h25452 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 && wsiS_reqFifo$D_OUT[57]) $display("[%0d]: %m: doMessageAccept DWM metaCount:%0x WSI opcode:%0x length:%0x", - v__h25170, + v__h25452, metaCount, wsiS_reqFifo$D_OUT[7:0], - mlB__h23066); - if (wciS0_MReset_n) + mlB__h23348); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h26499 = $time; + v__h26795 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h26499, + v__h26795, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3958 = $time; + v__h4037 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3958, + v__h4037, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3814 = $time; + v__h3893 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3814, + v__h3893, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (dataBram_serverAdapterA_s1[1] && !dataBram_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (dataBram_serverAdapterB_s1[1] && !dataBram_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterA_s1[1] && !metaBram_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterB_s1[1] && !metaBram_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterA_1_s1[1] && !metaBram_serverAdapterA_1_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterB_1_s1[1] && !metaBram_serverAdapterB_1_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterA_2_s1[1] && !metaBram_serverAdapterA_2_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterB_2_s1[1] && !metaBram_serverAdapterB_2_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterA_3_s1[1] && !metaBram_serverAdapterA_3_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterB_3_s1[1] && !metaBram_serverAdapterB_3_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) begin - v__h26216 = $time; + v__h26500 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) - $display("[%0d]: %m: WCI SPLIT READ Data:%0x", v__h26216, v__h25297); - if (wciS0_MReset_n) + $display("[%0d]: %m: WCI SPLIT READ Data:%0x", v__h26500, v__h25581); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && MUX_controlReg$write_1__SEL_2) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && MUX_controlReg$write_1__SEL_2) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_controlReg$write_1__SEL_2 && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_controlReg$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_controlReg$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_OrE && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 76: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_OrE] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); diff --git a/rtl/mkWSIPatternWorker4B.v b/rtl/mkWSIPatternWorker4B.v index a912ba65..0c4355a8 100644 --- a/rtl/mkWSIPatternWorker4B.v +++ b/rtl/mkWSIPatternWorker4B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:35 EDT 2012 +// On Mon Sep 24 15:03:50 EDT 2012 // // // Ports: @@ -35,7 +35,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkWSIPatternWorker4B(wciS0_Clk, @@ -906,37 +914,36 @@ module mkWSIPatternWorker4B(wciS0_Clk, MUX_wsiM_reqFifo_q_1$write_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h29373, - v__h30469, - v__h30959, - v__h31946, - v__h3647, - v__h3821, - v__h3965; + reg [63 : 0] v__h29716, + v__h30815, + v__h31317, + v__h32313, + v__h3725, + v__h3900, + v__h4044; reg [31 : 0] IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066, - v__h31927; + v__h32294; reg CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1, IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1033, - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205, - IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1132; - wire [31 : 0] b__h25071, - g_data__h32953, - rdat___1__h32113, - rdat___1__h32168, - rdat___1__h32182, - rdat___1__h32190, - residue__h25060, - v__h24454, - v__h29551, - x__h25087, - x__h26045, - y_avValue__h30177, - y_avValue__h30221, - y_avValue__h30261, - y_avValue__h30301, - y_avValue__h30341; - wire [11 : 0] x_burstLength__h25879; - wire [3 : 0] x_byteEn__h25881; + IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1138; + wire [31 : 0] b__h25414, + g_data__h33320, + rdat___1__h32480, + rdat___1__h32535, + rdat___1__h32549, + rdat___1__h32557, + residue__h25403, + v__h24797, + v__h29897, + x__h25430, + x__h26388, + y_avValue__h30523, + y_avValue__h30567, + y_avValue__h30607, + y_avValue__h30647, + y_avValue__h30687; + wire [11 : 0] x_burstLength__h26222; + wire [3 : 0] x_byteEn__h26224; wire [2 : 0] dataBram_serverAdapterA_cnt_74_PLUS_IF_dataBra_ETC___d280, dataBram_serverAdapterB_cnt_33_PLUS_IF_dataBra_ETC___d339, metaBram_serverAdapterA_1_cnt_10_PLUS_IF_metaB_ETC___d516, @@ -947,9 +954,12 @@ module mkWSIPatternWorker4B(wciS0_Clk, metaBram_serverAdapterB_2_cnt_87_PLUS_IF_metaB_ETC___d693, metaBram_serverAdapterB_3_cnt_05_PLUS_IF_metaB_ETC___d811, metaBram_serverAdapterB_cnt_51_PLUS_IF_metaBra_ETC___d457; - wire [1 : 0] ab__h11456, ab__h14555, ab__h17482, ab__h20409, ab__h23336; + wire [1 : 0] ab__h11724, ab__h14842, ab__h17788, ab__h20734, ab__h23680; wire IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1042, - dataBram_serverAdapterB_cnt_33_SLT_3___d1314, + IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1092, + IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1093, + IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1420, + dataBram_serverAdapterB_cnt_33_SLT_3___d1322, doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d913, doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d923, metaBram_serverAdapterA_1_outData_outData_whas_ETC___d871, @@ -1015,7 +1025,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) dataBram_serverAdapterA_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) dataBram_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(dataBram_serverAdapterA_outDataCore$D_IN), .ENQ(dataBram_serverAdapterA_outDataCore$ENQ), @@ -1029,7 +1039,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) dataBram_serverAdapterB_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) dataBram_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(dataBram_serverAdapterB_outDataCore$D_IN), .ENQ(dataBram_serverAdapterB_outDataCore$ENQ), @@ -1040,7 +1050,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, .EMPTY_N(dataBram_serverAdapterB_outDataCore$EMPTY_N)); // submodule loopReqInFlightF - FIFO10 #(.guarded(32'd1)) loopReqInFlightF(.RST_N(wciS0_MReset_n), + FIFO10 #(.guarded(32'd1)) loopReqInFlightF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .ENQ(loopReqInFlightF$ENQ), .DEQ(loopReqInFlightF$DEQ), @@ -1120,7 +1130,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_1_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterA_1_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterA_1_outDataCore$D_IN), .ENQ(metaBram_serverAdapterA_1_outDataCore$ENQ), @@ -1134,7 +1144,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_2_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterA_2_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterA_2_outDataCore$D_IN), .ENQ(metaBram_serverAdapterA_2_outDataCore$ENQ), @@ -1148,7 +1158,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_3_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterA_3_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterA_3_outDataCore$D_IN), .ENQ(metaBram_serverAdapterA_3_outDataCore$ENQ), @@ -1162,7 +1172,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterA_outDataCore$D_IN), .ENQ(metaBram_serverAdapterA_outDataCore$ENQ), @@ -1176,7 +1186,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_1_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterB_1_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterB_1_outDataCore$D_IN), .ENQ(metaBram_serverAdapterB_1_outDataCore$ENQ), @@ -1190,7 +1200,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_2_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterB_2_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterB_2_outDataCore$D_IN), .ENQ(metaBram_serverAdapterB_2_outDataCore$ENQ), @@ -1204,7 +1214,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_3_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterB_3_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterB_3_outDataCore$D_IN), .ENQ(metaBram_serverAdapterB_3_outDataCore$ENQ), @@ -1218,7 +1228,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_outDataCore(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) metaBram_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(metaBram_serverAdapterB_outDataCore$D_IN), .ENQ(metaBram_serverAdapterB_outDataCore$ENQ), @@ -1229,7 +1239,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, .EMPTY_N(metaBram_serverAdapterB_outDataCore$EMPTY_N)); // submodule metaReqInFlightF - FIFO10 #(.guarded(32'd1)) metaReqInFlightF(.RST_N(wciS0_MReset_n), + FIFO10 #(.guarded(32'd1)) metaReqInFlightF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .ENQ(metaReqInFlightF$ENQ), .DEQ(metaReqInFlightF$DEQ), @@ -1238,7 +1248,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, .EMPTY_N(metaReqInFlightF$EMPTY_N)); // submodule splaF - FIFO2 #(.width(32'd3), .guarded(32'd1)) splaF(.RST_N(wciS0_MReset_n), + FIFO2 #(.width(32'd3), .guarded(32'd1)) splaF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(splaF$D_IN), .ENQ(splaF$ENQ), @@ -1252,7 +1262,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) wci_wslv_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(wci_wslv_reqF$D_IN), .ENQ(wci_wslv_reqF$ENQ), @@ -1284,7 +1294,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, // rule RL_wci_cfrd assign CAN_FIRE_RL_wci_cfrd = wci_wslv_reqF$EMPTY_N && - IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1132 && + IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1138 && (wci_wslv_reqF$D_OUT[63:52] == 12'h800 || wci_wslv_reqF$D_OUT[63:52] == 12'h400 || wci_wslv_respF_c_r != 2'd2) && @@ -1345,9 +1355,9 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign CAN_FIRE_RL_wci_cfwr = wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && ((wci_wslv_reqF$D_OUT[63:52] == 12'h800) ? - dataBram_serverAdapterB_cnt_33_SLT_3___d1314 : + dataBram_serverAdapterB_cnt_33_SLT_3___d1322 : wci_wslv_reqF$D_OUT[63:52] != 12'h400 || - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205) && + IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1420) && wci_wslv_wci_cfwr_pw$whas ; assign WILL_FIRE_RL_wci_cfwr = CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_wslv_ctl_op_start && @@ -1544,7 +1554,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, 16'd0 : metaPtr_value + 16'd1 ; assign MUX_unrollCnt$write_1__VAL_1 = - (v__h24454 == 32'd0) ? 16'd1 : b__h25071[15:0] ; + (v__h24797 == 32'd0) ? 16'd1 : b__h25414[15:0] ; assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && @@ -1583,10 +1593,10 @@ module mkWSIPatternWorker4B(wciS0_Clk, (wci_wslv_respF_c_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h32953 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h33320 } ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = { 2'd1, v__h29551 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = { 2'd1, v__h29897 } ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = @@ -1597,9 +1607,9 @@ module mkWSIPatternWorker4B(wciS0_Clk, { 3'd1, unrollCnt == 16'd1, 1'd0, - x_burstLength__h25879, + x_burstLength__h26222, dataBram_serverAdapterA_outData_outData$wget, - x_byteEn__h25881, + x_byteEn__h26224, thisOpcode[7:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = (wsiM_reqFifo_c_r == 2'd2) ? @@ -1681,7 +1691,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, dataBram_serverAdapterB_outDataCore$FULL_N) && dataBram_serverAdapterB_s1[1] && dataBram_serverAdapterB_s1[0] ; - assign dataBram_serverAdapterB_outData_outData$wget = y_avValue__h30177 ; + assign dataBram_serverAdapterB_outData_outData$wget = y_avValue__h30523 ; assign dataBram_serverAdapterB_outData_outData$whas = dataBram_serverAdapterB_outDataCore$EMPTY_N || !dataBram_serverAdapterB_outDataCore$EMPTY_N && @@ -1690,18 +1700,18 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign dataBram_serverAdapterB_cnt_1$whas = (MUX_dataBram_memory$b_put_1__SEL_1 || MUX_dataBram_memory$b_put_1__SEL_2) && - (!ab__h11456[1] || ab__h11456[0]) ; + (!ab__h11724[1] || ab__h11724[0]) ; assign dataBram_serverAdapterB_cnt_2$wget = 3'd7 ; assign dataBram_serverAdapterB_cnt_2$whas = dataBram_serverAdapterB_outData_deqCalled$whas ; assign dataBram_serverAdapterB_cnt_3$wget = 3'h0 ; assign dataBram_serverAdapterB_cnt_3$whas = 1'b0 ; - assign dataBram_serverAdapterB_writeWithResp$wget = ab__h11456 ; + assign dataBram_serverAdapterB_writeWithResp$wget = ab__h11724 ; assign dataBram_serverAdapterB_writeWithResp$whas = MUX_dataBram_memory$b_put_1__SEL_1 || MUX_dataBram_memory$b_put_1__SEL_2 ; assign dataBram_serverAdapterB_s1_1$wget = - { 1'd1, !ab__h11456[1] || ab__h11456[0] } ; + { 1'd1, !ab__h11724[1] || ab__h11724[0] } ; assign dataBram_serverAdapterB_s1_1$whas = dataBram_serverAdapterB_writeWithResp$whas ; assign metaBram_serverAdapterA_outData_enqData$wget = metaBram_memory$DOA ; @@ -1710,7 +1720,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, metaBram_serverAdapterA_outDataCore$FULL_N) && metaBram_serverAdapterA_s1[1] && metaBram_serverAdapterA_s1[0] ; - assign metaBram_serverAdapterA_outData_outData$wget = v__h24454 ; + assign metaBram_serverAdapterA_outData_outData$wget = v__h24797 ; assign metaBram_serverAdapterA_outData_outData$whas = metaBram_serverAdapterA_outDataCore$EMPTY_N || !metaBram_serverAdapterA_outDataCore$EMPTY_N && @@ -1734,7 +1744,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, metaBram_serverAdapterB_outDataCore$FULL_N) && metaBram_serverAdapterB_s1[1] && metaBram_serverAdapterB_s1[0] ; - assign metaBram_serverAdapterB_outData_outData$wget = y_avValue__h30221 ; + assign metaBram_serverAdapterB_outData_outData$wget = y_avValue__h30567 ; assign metaBram_serverAdapterB_outData_outData$whas = metaBram_serverAdapterB_outDataCore$EMPTY_N || !metaBram_serverAdapterB_outDataCore$EMPTY_N && @@ -1743,18 +1753,18 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign metaBram_serverAdapterB_cnt_1$whas = (MUX_metaBram_memory$b_put_1__SEL_1 || MUX_metaBram_memory$b_put_1__SEL_2) && - (!ab__h14555[1] || ab__h14555[0]) ; + (!ab__h14842[1] || ab__h14842[0]) ; assign metaBram_serverAdapterB_cnt_2$wget = 3'd7 ; assign metaBram_serverAdapterB_cnt_2$whas = metaBram_serverAdapterB_outData_deqCalled$whas ; assign metaBram_serverAdapterB_cnt_3$wget = 3'h0 ; assign metaBram_serverAdapterB_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterB_writeWithResp$wget = ab__h14555 ; + assign metaBram_serverAdapterB_writeWithResp$wget = ab__h14842 ; assign metaBram_serverAdapterB_writeWithResp$whas = MUX_metaBram_memory$b_put_1__SEL_1 || MUX_metaBram_memory$b_put_1__SEL_2 ; assign metaBram_serverAdapterB_s1_1$wget = - { 1'd1, !ab__h14555[1] || ab__h14555[0] } ; + { 1'd1, !ab__h14842[1] || ab__h14842[0] } ; assign metaBram_serverAdapterB_s1_1$whas = metaBram_serverAdapterB_writeWithResp$whas ; assign metaBram_serverAdapterA_1_outData_enqData$wget = @@ -1792,7 +1802,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, metaBram_serverAdapterB_1_outDataCore$FULL_N) && metaBram_serverAdapterB_1_s1[1] && metaBram_serverAdapterB_1_s1[0] ; - assign metaBram_serverAdapterB_1_outData_outData$wget = y_avValue__h30261 ; + assign metaBram_serverAdapterB_1_outData_outData$wget = y_avValue__h30607 ; assign metaBram_serverAdapterB_1_outData_outData$whas = metaBram_serverAdapterB_1_outDataCore$EMPTY_N || !metaBram_serverAdapterB_1_outDataCore$EMPTY_N && @@ -1801,17 +1811,17 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign metaBram_serverAdapterB_1_cnt_1$whas = (MUX_metaBram_memory_1$b_put_1__SEL_1 || MUX_metaBram_memory_1$b_put_1__SEL_2) && - (!ab__h17482[1] || ab__h17482[0]) ; + (!ab__h17788[1] || ab__h17788[0]) ; assign metaBram_serverAdapterB_1_cnt_2$wget = 3'd7 ; assign metaBram_serverAdapterB_1_cnt_2$whas = metaBram_serverAdapterB_1_outData_deqCalled$whas ; assign metaBram_serverAdapterB_1_cnt_3$wget = 3'h0 ; assign metaBram_serverAdapterB_1_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterB_1_writeWithResp$wget = ab__h17482 ; + assign metaBram_serverAdapterB_1_writeWithResp$wget = ab__h17788 ; assign metaBram_serverAdapterB_1_writeWithResp$whas = metaBram_serverAdapterB_1_s1_1$whas ; assign metaBram_serverAdapterB_1_s1_1$wget = - { 1'd1, !ab__h17482[1] || ab__h17482[0] } ; + { 1'd1, !ab__h17788[1] || ab__h17788[0] } ; assign metaBram_serverAdapterB_1_s1_1$whas = MUX_metaBram_memory_1$b_put_1__SEL_1 || MUX_metaBram_memory_1$b_put_1__SEL_2 ; @@ -1850,7 +1860,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, metaBram_serverAdapterB_2_outDataCore$FULL_N) && metaBram_serverAdapterB_2_s1[1] && metaBram_serverAdapterB_2_s1[0] ; - assign metaBram_serverAdapterB_2_outData_outData$wget = y_avValue__h30301 ; + assign metaBram_serverAdapterB_2_outData_outData$wget = y_avValue__h30647 ; assign metaBram_serverAdapterB_2_outData_outData$whas = metaBram_serverAdapterB_2_outDataCore$EMPTY_N || !metaBram_serverAdapterB_2_outDataCore$EMPTY_N && @@ -1859,18 +1869,18 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign metaBram_serverAdapterB_2_cnt_1$whas = (MUX_metaBram_memory_2$b_put_1__SEL_1 || MUX_metaBram_memory_2$b_put_1__SEL_2) && - (!ab__h20409[1] || ab__h20409[0]) ; + (!ab__h20734[1] || ab__h20734[0]) ; assign metaBram_serverAdapterB_2_cnt_2$wget = 3'd7 ; assign metaBram_serverAdapterB_2_cnt_2$whas = metaBram_serverAdapterB_2_outData_deqCalled$whas ; assign metaBram_serverAdapterB_2_cnt_3$wget = 3'h0 ; assign metaBram_serverAdapterB_2_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterB_2_writeWithResp$wget = ab__h20409 ; + assign metaBram_serverAdapterB_2_writeWithResp$wget = ab__h20734 ; assign metaBram_serverAdapterB_2_writeWithResp$whas = MUX_metaBram_memory_2$b_put_1__SEL_1 || MUX_metaBram_memory_2$b_put_1__SEL_2 ; assign metaBram_serverAdapterB_2_s1_1$wget = - { 1'd1, !ab__h20409[1] || ab__h20409[0] } ; + { 1'd1, !ab__h20734[1] || ab__h20734[0] } ; assign metaBram_serverAdapterB_2_s1_1$whas = metaBram_serverAdapterB_2_writeWithResp$whas ; assign metaBram_serverAdapterA_3_outData_enqData$wget = @@ -1908,7 +1918,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, metaBram_serverAdapterB_3_outDataCore$FULL_N) && metaBram_serverAdapterB_3_s1[1] && metaBram_serverAdapterB_3_s1[0] ; - assign metaBram_serverAdapterB_3_outData_outData$wget = y_avValue__h30341 ; + assign metaBram_serverAdapterB_3_outData_outData$wget = y_avValue__h30687 ; assign metaBram_serverAdapterB_3_outData_outData$whas = metaBram_serverAdapterB_3_outDataCore$EMPTY_N || !metaBram_serverAdapterB_3_outDataCore$EMPTY_N && @@ -1917,18 +1927,18 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign metaBram_serverAdapterB_3_cnt_1$whas = (MUX_metaBram_memory_3$b_put_1__SEL_1 || MUX_metaBram_memory_3$b_put_1__SEL_2) && - (!ab__h23336[1] || ab__h23336[0]) ; + (!ab__h23680[1] || ab__h23680[0]) ; assign metaBram_serverAdapterB_3_cnt_2$wget = 3'd7 ; assign metaBram_serverAdapterB_3_cnt_2$whas = metaBram_serverAdapterB_3_outData_deqCalled$whas ; assign metaBram_serverAdapterB_3_cnt_3$wget = 3'h0 ; assign metaBram_serverAdapterB_3_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterB_3_writeWithResp$wget = ab__h23336 ; + assign metaBram_serverAdapterB_3_writeWithResp$wget = ab__h23680 ; assign metaBram_serverAdapterB_3_writeWithResp$whas = MUX_metaBram_memory_3$b_put_1__SEL_1 || MUX_metaBram_memory_3$b_put_1__SEL_2 ; assign metaBram_serverAdapterB_3_s1_1$wget = - { 1'd1, !ab__h23336[1] || ab__h23336[0] } ; + { 1'd1, !ab__h23680[1] || ab__h23680[0] } ; assign metaBram_serverAdapterB_3_s1_1$whas = metaBram_serverAdapterB_3_writeWithResp$whas ; assign wci_wslv_reqF_r_enq$whas = wci_wslv_wciReq$wget[71:69] != 3'd0 ; @@ -1994,7 +2004,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, // register bytesRemain assign bytesRemain$D_IN = MUX_unrollCnt$write_1__SEL_1 ? - v__h24454 : + v__h24797 : MUX_bytesRemain$write_1__VAL_2 ; assign bytesRemain$EN = MUX_unrollCnt$write_1__SEL_1 || @@ -2065,7 +2075,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways ; // register doZLM - assign doZLM$D_IN = MUX_unrollCnt$write_1__SEL_1 && v__h24454 == 32'd0 ; + assign doZLM$D_IN = MUX_unrollCnt$write_1__SEL_1 && v__h24797 == 32'd0 ; assign doZLM$EN = wsiM_reqFifo_enqueueing$whas && doZLM || MUX_unrollCnt$write_1__SEL_1 ; @@ -2243,7 +2253,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 ; // register thisLength - assign thisLength$D_IN = v__h24454 ; + assign thisLength$D_IN = v__h24797 ; assign thisLength$EN = MUX_unrollCnt$write_1__SEL_1 ; // register thisOpcode @@ -2778,12 +2788,25 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1042 = IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1033 && CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 ; - assign ab__h11456 = MUX_dataBram_memory$b_put_1__SEL_1 ? 2'd0 : 2'd2 ; - assign ab__h14555 = MUX_metaBram_memory$b_put_1__SEL_1 ? 2'd0 : 2'd2 ; - assign ab__h17482 = MUX_metaBram_memory_1$b_put_1__SEL_1 ? 2'd0 : 2'd2 ; - assign ab__h20409 = MUX_metaBram_memory_2$b_put_1__SEL_1 ? 2'd0 : 2'd2 ; - assign ab__h23336 = MUX_metaBram_memory_3$b_put_1__SEL_1 ? 2'd0 : 2'd2 ; - assign b__h25071 = x__h25087 + residue__h25060 ; + assign IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1092 = + (wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[35:34] == 2'd2) ? + (metaBram_serverAdapterB_2_cnt ^ 3'h4) < 3'd7 : + !wci_wslv_reqF$EMPTY_N || wci_wslv_reqF$D_OUT[35:34] != 2'd3 || + (metaBram_serverAdapterB_3_cnt ^ 3'h4) < 3'd7 ; + assign IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1093 = + (wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[35:34] == 2'd1) ? + (metaBram_serverAdapterB_1_cnt ^ 3'h4) < 3'd7 : + IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1092 ; + assign IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1420 = + (wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[35:34] == 2'd0) ? + (metaBram_serverAdapterB_cnt ^ 3'h4) < 3'd7 : + IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1093 ; + assign ab__h11724 = MUX_dataBram_memory$b_put_1__SEL_1 ? 2'd0 : 2'd2 ; + assign ab__h14842 = MUX_metaBram_memory$b_put_1__SEL_1 ? 2'd0 : 2'd2 ; + assign ab__h17788 = MUX_metaBram_memory_1$b_put_1__SEL_1 ? 2'd0 : 2'd2 ; + assign ab__h20734 = MUX_metaBram_memory_2$b_put_1__SEL_1 ? 2'd0 : 2'd2 ; + assign ab__h23680 = MUX_metaBram_memory_3$b_put_1__SEL_1 ? 2'd0 : 2'd2 ; + assign b__h25414 = x__h25430 + residue__h25403 ; assign dataBram_serverAdapterA_cnt_74_PLUS_IF_dataBra_ETC___d280 = dataBram_serverAdapterA_cnt + (WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways ? @@ -2794,7 +2817,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, dataBram_serverAdapterB_cnt + (dataBram_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) + (dataBram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign dataBram_serverAdapterB_cnt_33_SLT_3___d1314 = + assign dataBram_serverAdapterB_cnt_33_SLT_3___d1322 = (dataBram_serverAdapterB_cnt ^ 3'h4) < 3'd7 ; assign doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d913 = doZLM || @@ -2805,8 +2828,8 @@ module mkWSIPatternWorker4B(wciS0_Clk, doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d913 && (thisLength != 32'd0 && unrollCnt != 16'd1 || loopReqInFlightF$EMPTY_N) ; - assign g_data__h32953 = - (wci_wslv_reqF$D_OUT[63:52] == 12'h0) ? v__h31927 : 32'd0 ; + assign g_data__h33320 = + (wci_wslv_reqF$D_OUT[63:52] == 12'h0) ? v__h32294 : 32'd0 ; assign metaBram_serverAdapterA_1_cnt_10_PLUS_IF_metaB_ETC___d516 = metaBram_serverAdapterA_1_cnt + (WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ? @@ -2869,15 +2892,15 @@ module mkWSIPatternWorker4B(wciS0_Clk, (metaBram_serverAdapterA_1_outDataCore$EMPTY_N || metaBram_serverAdapterA_1_outData_enqData$whas) && metaBram_serverAdapterA_1_outData_outData_whas_ETC___d871 ; - assign rdat___1__h32113 = hasDebugLogic ? { 24'd0, wsiM_statusR } : 32'd0 ; - assign rdat___1__h32168 = + assign rdat___1__h32480 = hasDebugLogic ? { 24'd0, wsiM_statusR } : 32'd0 ; + assign rdat___1__h32535 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat___1__h32182 = + assign rdat___1__h32549 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat___1__h32190 = + assign rdat___1__h32557 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign residue__h25060 = - ({ 4'd0, v__h24454[1:0] } == 6'd0) ? 32'd0 : 32'd1 ; + assign residue__h25403 = + ({ 4'd0, v__h24797[1:0] } == 6'd0) ? 32'd0 : 32'd1 ; assign splaF_i_notEmpty__011_AND_IF_splaF_first__012__ETC___d1044 = splaF$EMPTY_N && (splaF$D_OUT[2] ? @@ -2887,16 +2910,16 @@ module mkWSIPatternWorker4B(wciS0_Clk, (splaF$D_OUT[1:0] != 2'd0 || dataBram_serverAdapterB_outData_outData$whas) : IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1042) ; - assign v__h24454 = + assign v__h24797 = metaBram_serverAdapterA_outDataCore$EMPTY_N ? metaBram_serverAdapterA_outDataCore$D_OUT : metaBram_memory$DOA ; - assign v__h29551 = + assign v__h29897 = splaF$D_OUT[2] ? - y_avValue__h30177 : + y_avValue__h30523 : IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066 ; - assign x__h25087 = { 2'd0, v__h24454[31:2] } ; - assign x__h26045 = + assign x__h25430 = { 2'd0, v__h24797[31:2] } ; + assign x__h26388 = ({ 4'd0, thisLength[1:0] } == 6'd0) ? 32'hFFFFFFFF : (({ 4'd0, thisLength[1:0] } <= 6'd1) ? @@ -3003,29 +3026,29 @@ module mkWSIPatternWorker4B(wciS0_Clk, 6'd31) ? 32'h7FFFFFFF : 32'hFFFFFFFF))))))))))))))))))))))))))))))) ; - assign x_burstLength__h25879 = + assign x_burstLength__h26222 = (thisLength == 32'd0 || unrollCnt == 16'd1) ? 12'd1 : 12'd4095 ; - assign x_byteEn__h25881 = + assign x_byteEn__h26224 = (thisLength == 32'd0) ? 4'd0 : - ((unrollCnt == 16'd1) ? x__h26045[3:0] : 4'd15) ; - assign y_avValue__h30177 = + ((unrollCnt == 16'd1) ? x__h26388[3:0] : 4'd15) ; + assign y_avValue__h30523 = dataBram_serverAdapterB_outDataCore$EMPTY_N ? dataBram_serverAdapterB_outDataCore$D_OUT : dataBram_memory$DOB ; - assign y_avValue__h30221 = + assign y_avValue__h30567 = metaBram_serverAdapterB_outDataCore$EMPTY_N ? metaBram_serverAdapterB_outDataCore$D_OUT : metaBram_memory$DOB ; - assign y_avValue__h30261 = + assign y_avValue__h30607 = metaBram_serverAdapterB_1_outDataCore$EMPTY_N ? metaBram_serverAdapterB_1_outDataCore$D_OUT : metaBram_memory_1$DOB ; - assign y_avValue__h30301 = + assign y_avValue__h30647 = metaBram_serverAdapterB_2_outDataCore$EMPTY_N ? metaBram_serverAdapterB_2_outDataCore$D_OUT : metaBram_memory_2$DOB ; - assign y_avValue__h30341 = + assign y_avValue__h30687 = metaBram_serverAdapterB_3_outDataCore$EMPTY_N ? metaBram_serverAdapterB_3_outDataCore$D_OUT : metaBram_memory_3$DOB ; @@ -3034,77 +3057,56 @@ module mkWSIPatternWorker4B(wciS0_Clk, mesgCount or dataCount or mesgRemain or - rdat___1__h32113 or - rdat___1__h32168 or rdat___1__h32182 or rdat___1__h32190) + rdat___1__h32480 or + rdat___1__h32535 or rdat___1__h32549 or rdat___1__h32557) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: v__h31927 = controlReg; - 8'h08: v__h31927 = mesgCount; - 8'h0C: v__h31927 = dataCount; - 8'h10: v__h31927 = mesgRemain; - 8'h1C: v__h31927 = 32'hA0240A0A; - 8'h20: v__h31927 = rdat___1__h32113; - 8'h24: v__h31927 = rdat___1__h32168; - 8'h28: v__h31927 = rdat___1__h32182; - 8'h2C: v__h31927 = rdat___1__h32190; - default: v__h31927 = 32'd0; + 8'h0: v__h32294 = controlReg; + 8'h08: v__h32294 = mesgCount; + 8'h0C: v__h32294 = dataCount; + 8'h10: v__h32294 = mesgRemain; + 8'h1C: v__h32294 = 32'hA0240A0A; + 8'h20: v__h32294 = rdat___1__h32480; + 8'h24: v__h32294 = rdat___1__h32535; + 8'h28: v__h32294 = rdat___1__h32549; + 8'h2C: v__h32294 = rdat___1__h32557; + default: v__h32294 = 32'd0; endcase end always@(splaF$D_OUT or - y_avValue__h30341 or - y_avValue__h30221 or y_avValue__h30261 or y_avValue__h30301) + y_avValue__h30687 or + y_avValue__h30567 or y_avValue__h30607 or y_avValue__h30647) begin case (splaF$D_OUT[1:0]) 2'd0: IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066 = - y_avValue__h30221; + y_avValue__h30567; 2'd1: IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066 = - y_avValue__h30261; + y_avValue__h30607; 2'd2: IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066 = - y_avValue__h30301; + y_avValue__h30647; 2'd3: IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066 = - y_avValue__h30341; - endcase - end - always@(wci_wslv_reqF$D_OUT or - metaBram_serverAdapterB_3_cnt or - metaBram_serverAdapterB_cnt or - metaBram_serverAdapterB_1_cnt or metaBram_serverAdapterB_2_cnt) - begin - case (wci_wslv_reqF$D_OUT[35:34]) - 2'd0: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205 = - (metaBram_serverAdapterB_cnt ^ 3'h4) < 3'd7; - 2'd1: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205 = - (metaBram_serverAdapterB_1_cnt ^ 3'h4) < 3'd7; - 2'd2: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205 = - (metaBram_serverAdapterB_2_cnt ^ 3'h4) < 3'd7; - 2'd3: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205 = - wci_wslv_reqF$D_OUT[35:34] != 2'd3 || - (metaBram_serverAdapterB_3_cnt ^ 3'h4) < 3'd7; + y_avValue__h30687; endcase end always@(wci_wslv_reqF$D_OUT or splaF$FULL_N or - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205 or - dataBram_serverAdapterB_cnt_33_SLT_3___d1314) + IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1420 or + dataBram_serverAdapterB_cnt_33_SLT_3___d1322) begin case (wci_wslv_reqF$D_OUT[63:52]) 12'h0: - IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1132 = 1'b1; + IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1138 = 1'b1; 12'h800: - IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1132 = - dataBram_serverAdapterB_cnt_33_SLT_3___d1314 && splaF$FULL_N; - default: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1132 = + IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1138 = + dataBram_serverAdapterB_cnt_33_SLT_3___d1322 && splaF$FULL_N; + default: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1138 = wci_wslv_reqF$D_OUT[63:52] != 12'h400 || splaF$FULL_N && - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205; + IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1420; endcase end always@(splaF$D_OUT or @@ -3164,7 +3166,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin bytesRemain <= `BSV_ASSIGNMENT_DELAY 32'd0; dataBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; @@ -3369,8 +3371,8 @@ module mkWSIPatternWorker4B(wciS0_Clk, wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -3464,176 +3466,176 @@ module mkWSIPatternWorker4B(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3647 = $time; + v__h3725 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3647, + v__h3725, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h0) begin - v__h31946 = $time; + v__h32313 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h0) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h31946, + v__h32313, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - v__h31927); - if (wciS0_MReset_n) + v__h32294); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (dataBram_serverAdapterA_s1[1] && !dataBram_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (wsiM_reqFifo_enqueueing$whas && unrollCnt == 16'd1) begin - v__h29373 = $time; + v__h29716 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (wsiM_reqFifo_enqueueing$whas && unrollCnt == 16'd1) $display("[%0d]: %m: wsi_source: End of WSI Producer Egress: mesgCount:%0x thisOpcode:%0x thisLength:%0x", - v__h29373, + v__h29716, mesgCount, thisOpcode, thisLength); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (dataBram_serverAdapterB_s1[1] && !dataBram_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterA_s1[1] && !metaBram_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterB_s1[1] && !metaBram_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterA_1_s1[1] && !metaBram_serverAdapterA_1_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterB_1_s1[1] && !metaBram_serverAdapterB_1_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterA_2_s1[1] && !metaBram_serverAdapterA_2_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterB_2_s1[1] && !metaBram_serverAdapterB_2_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterA_3_s1[1] && !metaBram_serverAdapterA_3_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0) begin - v__h30959 = $time; + v__h31317 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h30959, + v__h31317, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h3965 = $time; + v__h4044 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3965, + v__h4044, wci_wslv_cEdge, wci_wslv_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3821 = $time; + v__h3900 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3821, + v__h3900, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (metaBram_serverAdapterB_3_s1[1] && !metaBram_serverAdapterB_3_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) begin - v__h30469 = $time; + v__h30815 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) - $display("[%0d]: %m: WCI SPLIT READ Data:%0x", v__h30469, v__h29551); - if (wciS0_MReset_n) + $display("[%0d]: %m: WCI SPLIT READ Data:%0x", v__h30815, v__h29897); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && MUX_controlReg$write_1__SEL_2) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && MUX_controlReg$write_1__SEL_2) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_controlReg$write_1__SEL_2 && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_controlReg$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_controlReg$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_OrE && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 76: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_OrE] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); diff --git a/rtl/mkWciInitiator.v b/rtl/mkWciInitiator.v index fbfa99c7..0186d90b 100644 --- a/rtl/mkWciInitiator.v +++ b/rtl/mkWciInitiator.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:09 EDT 2012 +// On Mon Sep 24 15:03:20 EDT 2012 // // // Ports: @@ -26,7 +26,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkWciInitiator(CLK, @@ -255,7 +263,7 @@ module mkWciInitiator(CLK, wire started$D_IN, started$EN; // ports of submodule initiator_mReset - wire initiator_mReset$ASSERT_IN, initiator_mReset$OUT_RST_N; + wire initiator_mReset$ASSERT_IN, initiator_mReset$OUT_RST; // ports of submodule initiator_respF reg [33 : 0] initiator_respF$D_IN; @@ -309,24 +317,24 @@ module mkWciInitiator(CLK, MUX_initiator_respF$enq_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h22225, - v__h23010, - v__h23299, - v__h23791, - v__h24092, - v__h24592, - v__h25369, - v__h26168, - v__h2732, - v__h2822, - v__h2911, - v__h3144, - v__h3234, - v__h3323, - v__h3561, - v__h3651, - v__h3740; - wire [31 : 0] toCount__h2428, x__h25066, x__h2590; + reg [63 : 0] v__h22397, + v__h23185, + v__h23475, + v__h23971, + v__h24273, + v__h24777, + v__h25559, + v__h26363, + v__h2868, + v__h2958, + v__h3047, + v__h3280, + v__h3370, + v__h3459, + v__h3697, + v__h3787, + v__h3876; + wire [31 : 0] toCount__h2563, x__h25252, x__h2726; wire [26 : 0] IF_initiator_lastControlOp_22_BIT_3_23_THEN_in_ETC___d137; wire NOT_initiator_busy_5_79_AND_IF_initiator_wRese_ETC___d192, _dand1initiator_busy$EN_write, @@ -334,10 +342,10 @@ module mkWciInitiator(CLK, _dor1initiator_lastConfigAddr$EN_write, _dor1initiator_lastConfigBE$EN_write, initFsm_abort_whas__45_AND_initFsm_abort_wget__ETC___d231, - initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258; + initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286; // output resets - assign RST_N_wciM0 = initiator_mReset$OUT_RST_N ; + assign RST_N_wciM0 = initiator_mReset$OUT_RST ; // value method wciM0_mCmd assign wciM0_MCmd = @@ -363,14 +371,14 @@ module mkWciInitiator(CLK, // submodule initiator_mReset MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) initiator_mReset(.CLK(CLK), - .RST_N(RST_N), + .RST(RST_N), .DST_CLK(CLK), .ASSERT_IN(initiator_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST_N(initiator_mReset$OUT_RST_N)); + .OUT_RST(initiator_mReset$OUT_RST)); // submodule initiator_respF - FIFO1 #(.width(32'd34), .guarded(32'd1)) initiator_respF(.RST_N(RST_N), + FIFO1 #(.width(32'd34), .guarded(32'd1)) initiator_respF(.RST(RST_N), .CLK(CLK), .D_IN(initiator_respF$D_IN), .ENQ(initiator_respF$ENQ), @@ -443,7 +451,7 @@ module mkWciInitiator(CLK, // rule RL_initiator_wrkBusy assign WILL_FIRE_RL_initiator_wrkBusy = ((initiator_wciResponse$wget[33:32] == 2'd0) ? - initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 || + initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 || initiator_respF$FULL_N : initiator_respF$FULL_N) && initiator_busy ; @@ -479,7 +487,7 @@ module mkWciInitiator(CLK, MUX_initiator_busy$write_1__PSEL_1 && initiator_wReset_n ; assign MUX_initiator_busy$write_1__SEL_2 = WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 || initiator_wciResponse$wget[33:32] != 2'd0) ; assign MUX_initiator_lastControlOp$write_1__SEL_1 = WILL_FIRE_RL_initFsm_action_l1107c14 && initiator_wReset_n ; @@ -530,17 +538,17 @@ module mkWciInitiator(CLK, MUX_initiator_reqF_q_0$write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_initiator_reqF_x_wire$wset_1__VAL_1 = - { 8'd63, x__h25066, 32'h80000042 } ; + { 8'd63, x__h25252, 32'h80000042 } ; assign MUX_initiator_reqF_x_wire$wset_1__VAL_2 = - { 8'd95, x__h25066, 32'h80000000 } ; + { 8'd95, x__h25252, 32'h80000000 } ; assign MUX_initiator_respF$enq_1__VAL_2 = (initiator_wciResponse$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : initiator_wciResponse$wget ; assign MUX_initiator_respTimr$write_1__VAL_2 = (initiator_wciResponse$wget[33:32] == 2'd0) ? - (initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 ? - x__h2590 : + (initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 ? + x__h2726 : 32'd0) : 32'd0 ; @@ -675,7 +683,7 @@ module mkWciInitiator(CLK, assign initiator_busy$EN = _dand1initiator_busy$EN_write || WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 || initiator_wciResponse$wget[33:32] != 2'd0) ; // register initiator_lastConfigAddr @@ -813,7 +821,7 @@ module mkWciInitiator(CLK, assign initiator_reqTO$EN = WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 && (initiator_reqPend == 2'd1 || initiator_reqPend == 2'd2 || initiator_reqPend == 2'd3) ; @@ -829,7 +837,7 @@ module mkWciInitiator(CLK, assign initiator_respTimrAct$D_IN = initiator_reqF_c_r ; assign initiator_respTimrAct$EN = WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 || initiator_wciResponse$wget[33:32] != 2'd0) || initiator_reqF_c_r ; @@ -893,7 +901,7 @@ module mkWciInitiator(CLK, assign initiator_respF$ENQ = _dand1initiator_respF$EN_enq || WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 || initiator_wciResponse$wget[33:32] != 2'd0) || WILL_FIRE_RL_initFsm_action_l1105c14 ; assign initiator_respF$DEQ = @@ -946,17 +954,17 @@ module mkWciInitiator(CLK, (initFsm_state_mkFSMstate == 4'd0 || initFsm_state_mkFSMstate == 4'd11) && (!initFsm_start_reg_1 || initFsm_state_fired) ; - assign initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 = - initiator_respTimr < toCount__h2428 ; - assign toCount__h2428 = 32'd1 << initiator_wTimeout ; - assign x__h25066 = { initiator_pageWindow, 20'h0 } ; - assign x__h2590 = initiator_respTimr + 32'd1 ; + assign initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 = + initiator_respTimr < toCount__h2563 ; + assign toCount__h2563 = 32'd1 << initiator_wTimeout ; + assign x__h25252 = { initiator_pageWindow, 20'h0 } ; + assign x__h2726 = initiator_respTimr + 32'd1 ; // handling of inlined registers always@(posedge CLK) begin - if (!RST_N) + if (RST_N == `BSV_RESET_VALUE) begin initFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; initFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1106,80 +1114,80 @@ module mkWciInitiator(CLK, always@(negedge CLK) begin #0; - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1106c5) begin - v__h23010 = $time; + v__h23185 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1106c5) $display("[%0d]: %m: WCI Initiator received response %0x", - v__h23010, + v__h23185, initiator_respF$D_OUT[31:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1107c14) begin - v__h23299 = $time; + v__h23475 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1107c14) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h23299); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h23475); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1108c5) begin - v__h23791 = $time; + v__h23971 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1108c5) $display("[%0d]: %m: WCI Initiator received response %0x", - v__h23791, + v__h23971, initiator_respF$D_OUT[31:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1109c14) begin - v__h24092 = $time; + v__h24273 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1109c14) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h24092); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h24273); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1110c5) begin - v__h24592 = $time; + v__h24777 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1110c5) $display("[%0d]: %m: WCI Initiator received response %0x", - v__h24592, + v__h24777, initiator_respF$D_OUT[31:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1112c5) begin - v__h25369 = $time; + v__h25559 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1112c5) $display("[%0d]: %m: WCI Initiator received response %0x", - v__h25369, + v__h25559, initiator_respF$D_OUT[31:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1114c5) begin - v__h26168 = $time; + v__h26363 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1114c5) $display("[%0d]: %m: WCI Initiator received response %0x", - v__h26168, + v__h26363, initiator_respF$D_OUT[31:0]); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1105c14 && (WILL_FIRE_RL_initFsm_action_l1106c5 || WILL_FIRE_RL_initFsm_action_l1107c14 || @@ -1191,7 +1199,7 @@ module mkWciInitiator(CLK, WILL_FIRE_RL_initFsm_action_l1113c14 || WILL_FIRE_RL_initFsm_action_l1114c5)) $display("Error: \"bsv/wip/OCWci.bsv\", line 1105, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1105c14] and\n [RL_initFsm_action_l1106c5, RL_initFsm_action_l1107c14,\n RL_initFsm_action_l1108c5, RL_initFsm_action_l1109c14,\n RL_initFsm_action_l1110c5, RL_initFsm_action_l1111c14,\n RL_initFsm_action_l1112c5, RL_initFsm_action_l1113c14,\n RL_initFsm_action_l1114c5] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1106c5 && (WILL_FIRE_RL_initFsm_action_l1107c14 || WILL_FIRE_RL_initFsm_action_l1108c5 || @@ -1202,7 +1210,7 @@ module mkWciInitiator(CLK, WILL_FIRE_RL_initFsm_action_l1113c14 || WILL_FIRE_RL_initFsm_action_l1114c5)) $display("Error: \"bsv/wip/OCWci.bsv\", line 1106, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1106c5] and\n [RL_initFsm_action_l1107c14, RL_initFsm_action_l1108c5,\n RL_initFsm_action_l1109c14, RL_initFsm_action_l1110c5,\n RL_initFsm_action_l1111c14, RL_initFsm_action_l1112c5,\n RL_initFsm_action_l1113c14, RL_initFsm_action_l1114c5] ) fired in the same\n clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1107c14 && (WILL_FIRE_RL_initFsm_action_l1108c5 || WILL_FIRE_RL_initFsm_action_l1109c14 || @@ -1212,7 +1220,7 @@ module mkWciInitiator(CLK, WILL_FIRE_RL_initFsm_action_l1113c14 || WILL_FIRE_RL_initFsm_action_l1114c5)) $display("Error: \"bsv/wip/OCWci.bsv\", line 1107, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1107c14] and\n [RL_initFsm_action_l1108c5, RL_initFsm_action_l1109c14,\n RL_initFsm_action_l1110c5, RL_initFsm_action_l1111c14,\n RL_initFsm_action_l1112c5, RL_initFsm_action_l1113c14,\n RL_initFsm_action_l1114c5] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1108c5 && (WILL_FIRE_RL_initFsm_action_l1109c14 || WILL_FIRE_RL_initFsm_action_l1110c5 || @@ -1221,7 +1229,7 @@ module mkWciInitiator(CLK, WILL_FIRE_RL_initFsm_action_l1113c14 || WILL_FIRE_RL_initFsm_action_l1114c5)) $display("Error: \"bsv/wip/OCWci.bsv\", line 1108, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1108c5] and\n [RL_initFsm_action_l1109c14, RL_initFsm_action_l1110c5,\n RL_initFsm_action_l1111c14, RL_initFsm_action_l1112c5,\n RL_initFsm_action_l1113c14, RL_initFsm_action_l1114c5] ) fired in the same\n clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1109c14 && (WILL_FIRE_RL_initFsm_action_l1110c5 || WILL_FIRE_RL_initFsm_action_l1111c14 || @@ -1229,39 +1237,39 @@ module mkWciInitiator(CLK, WILL_FIRE_RL_initFsm_action_l1113c14 || WILL_FIRE_RL_initFsm_action_l1114c5)) $display("Error: \"bsv/wip/OCWci.bsv\", line 1109, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1109c14] and\n [RL_initFsm_action_l1110c5, RL_initFsm_action_l1111c14,\n RL_initFsm_action_l1112c5, RL_initFsm_action_l1113c14,\n RL_initFsm_action_l1114c5] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1110c5 && (WILL_FIRE_RL_initFsm_action_l1111c14 || WILL_FIRE_RL_initFsm_action_l1112c5 || WILL_FIRE_RL_initFsm_action_l1113c14 || WILL_FIRE_RL_initFsm_action_l1114c5)) $display("Error: \"bsv/wip/OCWci.bsv\", line 1110, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1110c5] and\n [RL_initFsm_action_l1111c14, RL_initFsm_action_l1112c5,\n RL_initFsm_action_l1113c14, RL_initFsm_action_l1114c5] ) fired in the same\n clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1112c5 && (WILL_FIRE_RL_initFsm_action_l1113c14 || WILL_FIRE_RL_initFsm_action_l1114c5)) $display("Error: \"bsv/wip/OCWci.bsv\", line 1112, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1112c5] and\n [RL_initFsm_action_l1113c14, RL_initFsm_action_l1114c5] ) fired in the same\n clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1111c14 && (WILL_FIRE_RL_initFsm_action_l1112c5 || WILL_FIRE_RL_initFsm_action_l1113c14 || WILL_FIRE_RL_initFsm_action_l1114c5)) $display("Error: \"bsv/wip/OCWci.bsv\", line 1111, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1111c14] and\n [RL_initFsm_action_l1112c5, RL_initFsm_action_l1113c14,\n RL_initFsm_action_l1114c5] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1113c14 && WILL_FIRE_RL_initFsm_action_l1114c5) $display("Error: \"bsv/wip/OCWci.bsv\", line 1113, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1113c14] and\n [RL_initFsm_action_l1114c5] ) fired in the same clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1104c5) begin - v__h22225 = $time; + v__h22397 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1104c5) $display("[%0d]: %m: WCI Initiator Taking Worker out of Reset...", - v__h22225); - if (RST_N) + v__h22397); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1104c5 && (WILL_FIRE_RL_initFsm_action_l1105c14 || WILL_FIRE_RL_initFsm_action_l1106c5 || @@ -1274,129 +1282,129 @@ module mkWciInitiator(CLK, WILL_FIRE_RL_initFsm_action_l1113c14 || WILL_FIRE_RL_initFsm_action_l1114c5)) $display("Error: \"bsv/wip/OCWci.bsv\", line 1104, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1104c5] and\n [RL_initFsm_action_l1105c14, RL_initFsm_action_l1106c5,\n RL_initFsm_action_l1107c14, RL_initFsm_action_l1108c5,\n RL_initFsm_action_l1109c14, RL_initFsm_action_l1110c5,\n RL_initFsm_action_l1111c14, RL_initFsm_action_l1112c5,\n RL_initFsm_action_l1113c14, RL_initFsm_action_l1114c5] ) fired in the same\n clock cycle.\n"); - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 && initiator_reqPend == 2'd1) begin - v__h2732 = $time; + v__h2868 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 && initiator_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h2732); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h2868); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 && initiator_reqPend == 2'd2) begin - v__h2822 = $time; + v__h2958 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 && initiator_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h2822); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h2958); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 && initiator_reqPend == 2'd3) begin - v__h2911 = $time; + v__h3047 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d286 && initiator_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h2911); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h3047); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd1) begin - v__h3144 = $time; + v__h3280 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h3144); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h3280); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd2) begin - v__h3234 = $time; + v__h3370 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h3234); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h3370); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd3) begin - v__h3323 = $time; + v__h3459 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h3323); - if (RST_N) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h3459); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd1) begin - v__h3561 = $time; + v__h3697 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h3561); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h3697); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd2) begin - v__h3651 = $time; + v__h3787 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h3651); - if (RST_N) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h3787); + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd3) begin - v__h3740 = $time; + v__h3876 = $time; #0; end - if (RST_N) + if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h3740); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h3876); end // synopsys translate_on endmodule // mkWciInitiator diff --git a/rtl/mkWciTarget.v b/rtl/mkWciTarget.v index 15a62b18..5c4ac718 100644 --- a/rtl/mkWciTarget.v +++ b/rtl/mkWciTarget.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Mon Sep 24 13:38:09 EDT 2012 +// On Mon Sep 24 15:03:20 EDT 2012 // // // Ports: @@ -25,7 +25,15 @@ `ifdef BSV_ASSIGNMENT_DELAY `else -`define BSV_ASSIGNMENT_DELAY + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge `endif module mkWciTarget(wciS0_Clk, @@ -220,8 +228,8 @@ module mkWciTarget(wciS0_Clk, MUX_target_respF_q_1$write_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h3612, v__h3786, v__h3930, v__h4212, v__h4470, v__h4623; - reg [31 : 0] _theResult____h4607; + reg [63 : 0] v__h3690, v__h3865, v__h4009, v__h4302, v__h4560, v__h4715; + reg [31 : 0] _theResult____h4699; // value method wciS0_sResp assign wciS0_SResp = target_respF_q_0[33:32] ; @@ -240,7 +248,7 @@ module mkWciTarget(wciS0_Clk, SizedFIFO #(.p1width(32'd72), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) target_reqF(.RST_N(wciS0_MReset_n), + .guarded(32'd1)) target_reqF(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), .D_IN(target_reqF$D_IN), .ENQ(target_reqF$ENQ), @@ -359,7 +367,7 @@ module mkWciTarget(wciS0_Clk, assign MUX_target_respF_x_wire$wset_1__VAL_1 = target_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_target_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h4607 } ; + { 2'd1, _theResult____h4699 } ; // inlined wires assign target_wciReq$wget = @@ -564,9 +572,9 @@ module mkWciTarget(wciS0_Clk, always@(target_reqF$D_OUT or biasValue or controlReg) begin case (target_reqF$D_OUT[39:32]) - 8'h0: _theResult____h4607 = biasValue; - 8'h04: _theResult____h4607 = controlReg; - default: _theResult____h4607 = 32'd0; + 8'h0: _theResult____h4699 = biasValue; + 8'h04: _theResult____h4699 = controlReg; + default: _theResult____h4699 = 32'd0; endcase end @@ -574,7 +582,7 @@ module mkWciTarget(wciS0_Clk, always@(posedge wciS0_Clk) begin - if (!wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin operating <= `BSV_ASSIGNMENT_DELAY 1'd0; target_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; @@ -624,8 +632,8 @@ module mkWciTarget(wciS0_Clk, if (controlReg$EN) controlReg <= `BSV_ASSIGNMENT_DELAY controlReg$D_IN; end - always@(posedge wciS0_Clk or negedge wciS0_MReset_n) - if (!wciS0_MReset_n) + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) begin target_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; end @@ -667,75 +675,75 @@ module mkWciTarget(wciS0_Clk, always@(negedge wciS0_Clk) begin #0; - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_report_operating) begin - v__h4212 = $time; + v__h4302 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_report_operating) - $display("[%0d]: %m: WCI Target is Operating", v__h4212); - if (wciS0_MReset_n) + $display("[%0d]: %m: WCI Target is Operating", v__h4302); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_cfwr) begin - v__h4470 = $time; + v__h4560 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_cfwr) $display("[%0d]: %m: WCI TARGET CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h4470, + v__h4560, target_reqF$D_OUT[63:32], target_reqF$D_OUT[67:64], target_reqF$D_OUT[31:0]); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_cfrd) begin - v__h4623 = $time; + v__h4715 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_cfrd) $display("[%0d]: %m: WCI TARGET CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h4623, + v__h4715, target_reqF$D_OUT[63:32], target_reqF$D_OUT[67:64], - _theResult____h4607); - if (wciS0_MReset_n) + _theResult____h4699); + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_start) begin - v__h3612 = $time; + v__h3690 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3612, + v__h3690, target_reqF$D_OUT[36:34], target_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_complete && target_illegalEdge) begin - v__h3930 = $time; + v__h4009 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_complete && target_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h3930, + v__h4009, target_cEdge, target_cState); - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_complete && !target_illegalEdge) begin - v__h3786 = $time; + v__h3865 = $time; #0; end - if (wciS0_MReset_n) + if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_complete && !target_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3786, + v__h3865, target_cEdge, target_cState, target_nState); diff --git a/scripts/copyInBSVlibs b/scripts/copyInBSVlibs old mode 100644 new mode 100755