diff --git a/bsv/utl/CompileTime.bsv b/bsv/utl/CompileTime.bsv index 73fe0250..be17db8d 100644 --- a/bsv/utl/CompileTime.bsv +++ b/bsv/utl/CompileTime.bsv @@ -1 +1 @@ -Bit#(32) compileTime = 1391459380; // Verilog Mon Feb 3 15:29:40 EST 2014 +Bit#(32) compileTime = 1391543027; // Verilog Tue Feb 4 14:43:47 EST 2014 diff --git a/bsv/wrk/MemiTestWorker.bsv b/bsv/wrk/MemiTestWorker.bsv index 032ddc23..ef6a516d 100644 --- a/bsv/wrk/MemiTestWorker.bsv +++ b/bsv/wrk/MemiTestWorker.bsv @@ -46,6 +46,7 @@ module mkMemiTestWorker#(parameter Bool hasDebugLogic) (MemiTestWorkerIfc); Reg#(Bool) isTesting <- mkReg(False); Reg#(Bool) isWriter <- mkReg(True); Reg#(Bool) isReader <- mkReg(False); + Reg#(Bool) isCharPush <- mkReg(False); Reg#(UInt#(32)) hwordAddr <- mkReg(0); Reg#(UInt#(32)) unrollCnt <- mkReg(0); Reg#(UInt#(32)) respCnt <- mkReg(0); @@ -67,12 +68,13 @@ module mkMemiTestWorker#(parameter Bool hasDebugLogic) (MemiTestWorkerIfc); rule free_inc; freeCnt <= freeCnt + 1; endrule Bool haltOnError = unpack(tstCtrl[0]); + Bool charPerLoop = unpack(tstCtrl[1]); // set to cause write to BLUART on loop function Bit#(36) hwordAsBytes(UInt#(32) hwAddr); return ( {pack(hwordAddr), 4'h0} ); // 4b up-shifted to convert hword to Bytes endfunction - rule write_req (wci.isOperating && isTesting && isWriter && !isReader); + rule write_req (wci.isOperating && isTesting && isWriter && !isReader && !isCharPush); let d <- wgen.stream.get; wmemi.req(True, hwordAsBytes(hwordAddr), 1); // Write Request wmemi.dh(d, '1, True); // Write 16B Datahandshake @@ -98,6 +100,7 @@ module mkMemiTestWorker#(parameter Bool hasDebugLogic) (MemiTestWorkerIfc); testCycleCount <= testCycleCount + 1; wtCycStart <= freeCnt; rdDuration <= freeCnt - rdCycStart; + isCharPush <= charPerLoop; end endrule @@ -111,7 +114,13 @@ module mkMemiTestWorker#(parameter Bool hasDebugLogic) (MemiTestWorkerIfc); end wmemiRdResp <= wmemiRdResp + 1; endrule - + + rule char_push (wci.isOperating && isTesting && isWriter && !isReader && isCharPush); + wmemi.req(True, 36'h08000002C, 1); // Write Request - set bit 31 to write AXI; 2C is TX + wmemi.dh(128'h0000000000000000000000000000002B, '1, True); // Write 16B Datahandshake 2B is ASCII '+' + isCharPush <= False; + endrule + // WCI... Bit#(32) testStatus = {31'h0, pack(isReader)}; diff --git a/logs/ml605-20140204_1516/fpgaTop-ml605.srp b/logs/ml605-20140204_1516/fpgaTop-ml605.srp new file mode 100644 index 00000000..a34d659d --- /dev/null +++ b/logs/ml605-20140204_1516/fpgaTop-ml605.srp @@ -0,0 +1,14265 @@ +Release 14.7 - xst P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> +Parameter xsthdpini set to ocpihdp_v6.ini + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.06 secs + +--> + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpgaTop-ml605.prj" +Input Format : mixed + +---- Target Parameters +Output File Name : "fpgaTop" +Output Format : NGC +Target Device : xc6vlx240t-ff1156-1 + +---- Source Options +Top Module Name : fpgaTop +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Use DSP Block : auto +Automatic Register Balancing : NO + +---- Target Options +LUT Combining : off +Reduce Control Sets : off +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 32 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 2 +Power Reduction : NO +Library Search Order : fpgaTop.lso +Keep Hierarchy : soft +Netlist Hierarchy : rebuilt +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : optimize +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +---- Other Options +change_error_to_warning : "HDLCompiler:532 HDLCompiler:597" + +========================================================================= + +INFO:Xst - Changing 'HDLCompiler:532' to warning +INFO:Xst - Changing 'HDLCompiler:597' to warning + +========================================================================= +* HDL Parsing * +========================================================================= +The vhdl library search path for library \"bsv\" is now \"/home/shep/projects/ocpi/lib/hdl/bsv/bsv_v6\" +The veri library search path for library \"bsv\" is now \"/home/shep/projects/ocpi/lib/hdl/bsv/bsv_v6\" +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/ClockInvToBool.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFO.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/Ethernet_v6_v1_5.v" into library work +Parsing module . +Parsing module . +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v" Line 85. parameter declaration becomes local in pcie_upconfig_fix_3451_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v" Line 76. parameter declaration becomes local in pcie_reset_delay_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v" Line 120. parameter declaration becomes local in pcie_brams_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v" Line 86. parameter declaration becomes local in pcie_clocking_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" Line 216. parameter declaration becomes local in pcie_gtx_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 325. parameter declaration becomes local in pcie_pipe_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v" Line 103. parameter declaration becomes local in pcie_pipe_lane_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v" Line 90. parameter declaration becomes local in pcie_pipe_misc_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 85. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 87. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 88. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 89. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 90. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 91. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 93. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 94. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 95. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 96. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 107. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 108. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 109. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 110. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 90. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 91. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 92. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 93. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 94. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 95. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 96. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 97. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 98. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 99. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 100. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_tx_sync_rate_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkSMAdapter4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBiasWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTimeClient.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCRC32.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkGMAC.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkICAPWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_mux.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 200. parameter declaration becomes local in mc with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_buf.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_dec_fix.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_gen.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_merge_enc.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/clk_ibuf.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v" into library work +Parsing module . +Parsing module . +Parsing module . +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_ck_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_control_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rddata_sync.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_read.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" into library work +Parsing module . +WARNING:HDLCompiler:751 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 271: Redeclaration of ansi port app_addr is not allowed +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPSM.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPCM.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPktFork.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPktMerge.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkUUID.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCCP.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCDP4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCInf4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCApp4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCTop4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCTop16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPSerializer.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWciMonitor.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFMC150.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBLUART.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkLCDController.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" into library work +Parsing module . + +========================================================================= +* HDL Elaboration * +========================================================================= +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" Line 108: Port flash_wp_n is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBLUART.v" Line 343: Assignment to rxCtsReg ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 541: Assignment to a4l_a4wrResp_fifof_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 542: Assignment to a4l_a4wrResp_fifof_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 543: Assignment to a4l_a4rdResp_fifof_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 545: Assignment to a4l_a4rdResp_fifof_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 546: Assignment to a4ls_wrAddrVal_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 547: Assignment to a4ls_wrAddrVal_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 548: Assignment to a4ls_wrDataVal_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 549: Assignment to a4ls_wrDataVal_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 550: Assignment to a4ls_wrRespRdy_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 551: Assignment to a4ls_wrRespRdy_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 552: Assignment to a4ls_rdAddrVal_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 553: Assignment to a4ls_rdAddrVal_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 554: Assignment to a4ls_rdRespRdy_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 555: Assignment to a4ls_rdRespRdy_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 556: Assignment to a4ls_wrAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 557: Assignment to a4ls_wrAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 558: Assignment to a4ls_wrProt_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 559: Assignment to a4ls_wrProt_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 560: Assignment to a4ls_wrData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 561: Assignment to a4ls_wrData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 562: Assignment to a4ls_wrStrb_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 563: Assignment to a4ls_wrStrb_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 564: Assignment to a4ls_rdAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 565: Assignment to a4ls_rdAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 566: Assignment to a4ls_rdProt_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 567: Assignment to a4ls_rdProt_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 568: Assignment to a4l_a4wrAddr_enq_valid_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 569: Assignment to a4l_a4wrAddr_enq_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 570: Assignment to a4l_a4wrData_enq_valid_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 571: Assignment to a4l_a4wrData_enq_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 572: Assignment to a4l_a4wrResp_fifof_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 575: Assignment to a4l_a4wrResp_deq_ready_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 576: Assignment to a4l_a4wrResp_deq_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 577: Assignment to a4l_a4rdAddr_enq_valid_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 578: Assignment to a4l_a4rdAddr_enq_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 579: Assignment to a4l_a4rdResp_fifof_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 582: Assignment to a4l_a4rdResp_deq_ready_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 583: Assignment to a4l_a4rdResp_deq_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 604: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 630: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" Line 664: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1434: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1466: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1467: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1474: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1475: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1476: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1477: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1478: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1482: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1483: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1484: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1485: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1486: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1487: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1488: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1489: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1490: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1491: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1500: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1501: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1502: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1503: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1504: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1508: Assignment to wtiS_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1509: Assignment to wtiS_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1510: Assignment to wtiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1511: Assignment to wtiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1513: Assignment to nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1514: Assignment to statusReg_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1515: Assignment to statusReg_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1516: Assignment to dataBram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1523: Assignment to dataBram_0_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1527: Assignment to dataBram_0_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1531: Assignment to dataBram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1532: Assignment to dataBram_0_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1533: Assignment to dataBram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1534: Assignment to dataBram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1535: Assignment to dataBram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1536: Assignment to dataBram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1537: Assignment to dataBram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1538: Assignment to dataBram_0_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1540: Assignment to dataBram_0_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1541: Assignment to dataBram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1542: Assignment to dataBram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1549: Assignment to dataBram_0_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1554: Assignment to dataBram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1555: Assignment to dataBram_0_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1557: Assignment to dataBram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1558: Assignment to dataBram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1560: Assignment to dataBram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1561: Assignment to dataBram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1562: Assignment to dataBram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1563: Assignment to dataBram_0_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1565: Assignment to dataBram_0_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1566: Assignment to dataBram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1568: Assignment to metaBram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1575: Assignment to metaBram_0_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1579: Assignment to metaBram_0_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1583: Assignment to metaBram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1584: Assignment to metaBram_0_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1585: Assignment to metaBram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1586: Assignment to metaBram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1587: Assignment to metaBram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1588: Assignment to metaBram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1589: Assignment to metaBram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1590: Assignment to metaBram_0_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1592: Assignment to metaBram_0_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1593: Assignment to metaBram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1594: Assignment to metaBram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1601: Assignment to metaBram_0_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1606: Assignment to metaBram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1607: Assignment to metaBram_0_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1609: Assignment to metaBram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1610: Assignment to metaBram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1612: Assignment to metaBram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1613: Assignment to metaBram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1614: Assignment to metaBram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1615: Assignment to metaBram_0_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1617: Assignment to metaBram_0_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1618: Assignment to metaBram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1620: Assignment to metaBram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1627: Assignment to metaBram_1_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1631: Assignment to metaBram_1_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1635: Assignment to metaBram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1636: Assignment to metaBram_1_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1637: Assignment to metaBram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1638: Assignment to metaBram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1639: Assignment to metaBram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1640: Assignment to metaBram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1641: Assignment to metaBram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1642: Assignment to metaBram_1_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1644: Assignment to metaBram_1_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1645: Assignment to metaBram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1646: Assignment to metaBram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1653: Assignment to metaBram_1_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1658: Assignment to metaBram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1659: Assignment to metaBram_1_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1661: Assignment to metaBram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1662: Assignment to metaBram_1_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1664: Assignment to metaBram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1665: Assignment to metaBram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1666: Assignment to metaBram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1667: Assignment to metaBram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1669: Assignment to metaBram_1_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1670: Assignment to metaBram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1672: Assignment to metaBram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1679: Assignment to metaBram_2_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1683: Assignment to metaBram_2_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1687: Assignment to metaBram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1688: Assignment to metaBram_2_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1689: Assignment to metaBram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1690: Assignment to metaBram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1691: Assignment to metaBram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1692: Assignment to metaBram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1693: Assignment to metaBram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1694: Assignment to metaBram_2_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1696: Assignment to metaBram_2_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1697: Assignment to metaBram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1698: Assignment to metaBram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1705: Assignment to metaBram_2_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1710: Assignment to metaBram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1711: Assignment to metaBram_2_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1713: Assignment to metaBram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1714: Assignment to metaBram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1716: Assignment to metaBram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1717: Assignment to metaBram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1718: Assignment to metaBram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1719: Assignment to metaBram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1721: Assignment to metaBram_2_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1722: Assignment to metaBram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1724: Assignment to metaBram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1731: Assignment to metaBram_3_serverAdapterA_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1735: Assignment to metaBram_3_serverAdapterA_outData_outData_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1739: Assignment to metaBram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1740: Assignment to metaBram_3_serverAdapterA_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1741: Assignment to metaBram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1742: Assignment to metaBram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1743: Assignment to metaBram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1744: Assignment to metaBram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1745: Assignment to metaBram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1746: Assignment to metaBram_3_serverAdapterA_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1748: Assignment to metaBram_3_serverAdapterA_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1749: Assignment to metaBram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1750: Assignment to metaBram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1757: Assignment to metaBram_3_serverAdapterB_outData_outData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1762: Assignment to metaBram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1763: Assignment to metaBram_3_serverAdapterB_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1765: Assignment to metaBram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1766: Assignment to metaBram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1768: Assignment to metaBram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1769: Assignment to metaBram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1770: Assignment to metaBram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1771: Assignment to metaBram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1773: Assignment to metaBram_3_serverAdapterB_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1774: Assignment to metaBram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1776: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1777: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1778: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1779: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1780: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1781: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1782: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1783: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1784: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1785: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1786: Assignment to wti_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1787: Assignment to wti_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1788: Assignment to wti_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1789: Assignment to wti_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1790: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1794: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1801: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1802: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1812: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1813: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1815: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1816: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1817: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1819: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1820: Assignment to dataBram_0_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1824: Assignment to metaBram_0_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1829: Assignment to metaBram_1_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1834: Assignment to metaBram_2_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1839: Assignment to metaBram_3_serverAdapterA_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1844: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1845: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1846: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2103: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2127: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2689: Assignment to isFirst ignored, since the identifier is never used +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1483: Port EN_uuid is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 846: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 891: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 922: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 923: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 927: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 928: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 929: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 930: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 931: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 935: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 936: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 937: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 938: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 939: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 940: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 941: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 942: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 943: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 944: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 945: Assignment to wmemi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 949: Assignment to wmemi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 954: Assignment to wmemi_wmemiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 955: Assignment to wmemi_sCmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 956: Assignment to wmemi_sCmdAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 957: Assignment to wmemi_sDataAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 958: Assignment to wmemi_sDataAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 959: Assignment to wmemi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 960: Assignment to wmemi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 961: Assignment to wmemi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 962: Assignment to wmemi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 963: Assignment to wmemi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 964: Assignment to wmemi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 965: Assignment to wmemi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 966: Assignment to wmemi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 967: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 971: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 975: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 976: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 995: Assignment to wmemi_Em_sRespLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1169: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1193: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1257: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1278: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1326: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1347: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1468: Assignment to respCnt ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1568: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1650: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1651: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1655: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1656: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1657: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1658: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1659: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1663: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1664: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1665: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1666: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1667: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1668: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1669: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1670: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1671: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1672: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1673: Assignment to wmi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1677: Assignment to wmi_mFlagF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1678: Assignment to wmi_mFlagF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1679: Assignment to wmi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1680: Assignment to wmi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1682: Assignment to wmi_wmiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1683: Assignment to wmi_sThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1684: Assignment to wmi_sThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1685: Assignment to wmi_sDataThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1686: Assignment to wmi_sDataThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1687: Assignment to wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1688: Assignment to wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1689: Assignment to wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1690: Assignment to wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1691: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1692: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1693: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1694: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1695: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1696: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1705: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1706: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1707: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1708: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1709: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1713: Assignment to fabRespCredit_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1714: Assignment to fabRespCredit_acc_v1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1715: Assignment to fabRespCredit_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1716: Assignment to fabRespCredit_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1717: Assignment to mesgPreRequest_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1718: Assignment to mesgPreRequest_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1727: Assignment to respF_wDataIn_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1728: Assignment to respF_wDataOut_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1729: Assignment to respF_wDataOut_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1730: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1731: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1732: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1733: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1734: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1735: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1736: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1737: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1738: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1739: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1740: Assignment to wmi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1741: Assignment to wmi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1742: Assignment to wmi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1743: Assignment to wmi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1744: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1748: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1752: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1753: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1775: Assignment to wmi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1785: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1786: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1787: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1791: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1792: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1793: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1794: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1795: Assignment to respF_pwDequeue_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1797: Assignment to respF_pwClear_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1798: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1799: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1800: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1871: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1968: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2074: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2098: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2142: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2163: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2201: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2220: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2256: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2276: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2382: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2406: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2861: Assignment to firstMsgReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 787: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 830: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 831: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 835: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 836: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 837: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 838: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 839: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 843: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 844: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 845: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 846: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 847: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 848: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 849: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 850: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 851: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 852: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 861: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 862: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 863: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 864: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 865: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 869: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 870: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 872: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 873: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 874: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 875: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 876: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 877: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 878: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 879: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 880: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 881: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 882: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 883: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 884: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 885: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 886: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 890: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 894: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 895: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 905: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 906: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 908: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 909: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 910: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 912: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 913: Assignment to wsiM_reqFifo_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 915: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 916: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 917: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 918: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 919: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1019: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1043: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1128: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1152: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1349: Assignment to wci_wslv_cEdge ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1568: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1650: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1651: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1655: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1656: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1657: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1658: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1659: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1663: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1664: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1665: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1666: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1667: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1668: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1669: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1670: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1671: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1672: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1673: Assignment to wmi_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1677: Assignment to wmi_mFlagF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1678: Assignment to wmi_mFlagF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1679: Assignment to wmi_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1680: Assignment to wmi_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1682: Assignment to wmi_wmiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1683: Assignment to wmi_sThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1684: Assignment to wmi_sThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1685: Assignment to wmi_sDataThreadBusy_d_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1686: Assignment to wmi_sDataThreadBusy_d_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1687: Assignment to wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1688: Assignment to wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1689: Assignment to wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1690: Assignment to wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1691: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1692: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1693: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1694: Assignment to wsiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1695: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1696: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1705: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1706: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1707: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1708: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1709: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1713: Assignment to fabRespCredit_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1714: Assignment to fabRespCredit_acc_v1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1715: Assignment to fabRespCredit_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1716: Assignment to fabRespCredit_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1717: Assignment to mesgPreRequest_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1718: Assignment to mesgPreRequest_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1727: Assignment to respF_wDataIn_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1728: Assignment to respF_wDataOut_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1729: Assignment to respF_wDataOut_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1730: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1731: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1732: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1733: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1734: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1735: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1736: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1737: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1738: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1739: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1740: Assignment to wmi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1741: Assignment to wmi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1742: Assignment to wmi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1743: Assignment to wmi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1744: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1748: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1752: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1753: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1775: Assignment to wmi_dhF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1785: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1786: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1787: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1791: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1792: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1793: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1794: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1795: Assignment to respF_pwDequeue_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1797: Assignment to respF_pwClear_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1798: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1799: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1800: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1871: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1968: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2074: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2098: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2142: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2163: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2201: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2220: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2256: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2276: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2382: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2406: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2861: Assignment to firstMsgReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1743: Assignment to tieOff0_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1744: Assignment to tieOff0_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1745: Assignment to tieOff0_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1746: Assignment to tieOff0_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1747: Assignment to tieOff0_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1748: Assignment to tieOff0_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1749: Assignment to tieOff0_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1750: Assignment to tieOff0_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1751: Assignment to tieOff0_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1752: Assignment to tieOff0_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1753: Assignment to tieOff5_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1754: Assignment to tieOff5_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1755: Assignment to tieOff5_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1756: Assignment to tieOff5_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1757: Assignment to tieOff5_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1758: Assignment to tieOff5_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1759: Assignment to tieOff5_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1760: Assignment to tieOff5_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1761: Assignment to tieOff5_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1762: Assignment to tieOff5_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1763: Assignment to tieOff6_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1764: Assignment to tieOff6_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1765: Assignment to tieOff6_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1766: Assignment to tieOff6_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1767: Assignment to tieOff6_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1768: Assignment to tieOff6_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1769: Assignment to tieOff6_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1770: Assignment to tieOff6_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1771: Assignment to tieOff6_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1772: Assignment to tieOff6_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1773: Assignment to tieOff7_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1774: Assignment to tieOff7_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1775: Assignment to tieOff7_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1776: Assignment to tieOff7_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1777: Assignment to tieOff7_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1778: Assignment to tieOff7_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1779: Assignment to tieOff7_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1780: Assignment to tieOff7_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1781: Assignment to tieOff7_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1782: Assignment to tieOff7_wci_Es_mData_w_whas ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9396: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9471: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9548: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9625: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9702: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9779: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9859: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9935: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10011: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10087: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10163: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10235: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10311: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10387: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10463: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10511: Assignment to warmResetP_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10512: Assignment to warmResetP_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10513: Assignment to timeServ_jamFrac_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10516: Assignment to timeServ_jamFracVal_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10517: Assignment to timeServ_jamFracVal_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10518: Assignment to deviceDNA_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10519: Assignment to deviceDNA_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10522: Assignment to devDNAV_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10523: Assignment to rom_serverAdapter_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10537: Assignment to rom_serverAdapter_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10538: Assignment to rom_serverAdapter_cnt_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10540: Assignment to rom_serverAdapter_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10541: Assignment to rom_serverAdapter_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10543: Assignment to rom_serverAdapter_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10544: Assignment to rom_serverAdapter_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10545: Assignment to rom_serverAdapter_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10546: Assignment to rom_serverAdapter_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10548: Assignment to rom_serverAdapter_s1_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10549: Assignment to rom_serverAdapter_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10551: Assignment to dna_rdReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10553: Assignment to dna_shftReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10555: Assignment to uuidV_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10556: Assignment to uuidV_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10557: Assignment to wci_0_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10563: Assignment to wci_0_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10564: Assignment to wci_0_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10565: Assignment to wci_0_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10566: Assignment to wci_0_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10570: Assignment to wci_1_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10576: Assignment to wci_1_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10577: Assignment to wci_1_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10578: Assignment to wci_1_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10579: Assignment to wci_1_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10583: Assignment to wci_2_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10589: Assignment to wci_2_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10590: Assignment to wci_2_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10591: Assignment to wci_2_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10592: Assignment to wci_2_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10596: Assignment to wci_3_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10602: Assignment to wci_3_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10603: Assignment to wci_3_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10604: Assignment to wci_3_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10605: Assignment to wci_3_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10609: Assignment to wci_4_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10615: Assignment to wci_4_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10616: Assignment to wci_4_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10617: Assignment to wci_4_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10618: Assignment to wci_4_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10622: Assignment to wci_5_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10628: Assignment to wci_5_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10629: Assignment to wci_5_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10630: Assignment to wci_5_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10631: Assignment to wci_5_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10635: Assignment to wci_6_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10641: Assignment to wci_6_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10642: Assignment to wci_6_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10643: Assignment to wci_6_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10644: Assignment to wci_6_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10648: Assignment to wci_7_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10654: Assignment to wci_7_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10655: Assignment to wci_7_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10656: Assignment to wci_7_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10657: Assignment to wci_7_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10661: Assignment to wci_8_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10667: Assignment to wci_8_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10668: Assignment to wci_8_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10669: Assignment to wci_8_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10670: Assignment to wci_8_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10674: Assignment to wci_9_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10680: Assignment to wci_9_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10681: Assignment to wci_9_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10682: Assignment to wci_9_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10683: Assignment to wci_9_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10687: Assignment to wci_10_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10693: Assignment to wci_10_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10694: Assignment to wci_10_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10695: Assignment to wci_10_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10696: Assignment to wci_10_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10700: Assignment to wci_11_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10706: Assignment to wci_11_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10707: Assignment to wci_11_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10708: Assignment to wci_11_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10709: Assignment to wci_11_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10713: Assignment to wci_12_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10719: Assignment to wci_12_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10720: Assignment to wci_12_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10721: Assignment to wci_12_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10722: Assignment to wci_12_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10726: Assignment to wci_13_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10732: Assignment to wci_13_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10733: Assignment to wci_13_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10734: Assignment to wci_13_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10735: Assignment to wci_13_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10739: Assignment to wci_14_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10745: Assignment to wci_14_wciResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10746: Assignment to wci_14_sfCapSet_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10747: Assignment to wci_14_sfCapSet_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10748: Assignment to wci_14_sfCapClear_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10752: Assignment to wci_Emv_0_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10753: Assignment to wci_Emv_0_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10754: Assignment to wci_Emv_0_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10755: Assignment to wci_Emv_0_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10756: Assignment to wci_Emv_1_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10757: Assignment to wci_Emv_1_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10758: Assignment to wci_Emv_1_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10759: Assignment to wci_Emv_1_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10760: Assignment to wci_Emv_2_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10761: Assignment to wci_Emv_2_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10762: Assignment to wci_Emv_2_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10763: Assignment to wci_Emv_2_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10764: Assignment to wci_Emv_3_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10765: Assignment to wci_Emv_3_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10766: Assignment to wci_Emv_3_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10767: Assignment to wci_Emv_3_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10768: Assignment to wci_Emv_4_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10769: Assignment to wci_Emv_4_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10770: Assignment to wci_Emv_4_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10771: Assignment to wci_Emv_4_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10772: Assignment to wci_Emv_5_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10773: Assignment to wci_Emv_5_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10774: Assignment to wci_Emv_5_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10775: Assignment to wci_Emv_5_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10776: Assignment to wci_Emv_6_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10777: Assignment to wci_Emv_6_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10778: Assignment to wci_Emv_6_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10779: Assignment to wci_Emv_6_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10780: Assignment to wci_Emv_7_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10781: Assignment to wci_Emv_7_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10782: Assignment to wci_Emv_7_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10783: Assignment to wci_Emv_7_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10784: Assignment to wci_Emv_8_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10785: Assignment to wci_Emv_8_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10786: Assignment to wci_Emv_8_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10787: Assignment to wci_Emv_8_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10788: Assignment to wci_Emv_9_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10789: Assignment to wci_Emv_9_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10790: Assignment to wci_Emv_9_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10791: Assignment to wci_Emv_9_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10792: Assignment to wci_Emv_10_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10793: Assignment to wci_Emv_10_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10794: Assignment to wci_Emv_10_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10795: Assignment to wci_Emv_10_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10796: Assignment to wci_Emv_11_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10797: Assignment to wci_Emv_11_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10798: Assignment to wci_Emv_11_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10799: Assignment to wci_Emv_11_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10800: Assignment to wci_Emv_12_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10801: Assignment to wci_Emv_12_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10802: Assignment to wci_Emv_12_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10803: Assignment to wci_Emv_12_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10804: Assignment to wci_Emv_13_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10805: Assignment to wci_Emv_13_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10806: Assignment to wci_Emv_13_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10807: Assignment to wci_Emv_13_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10808: Assignment to wci_Emv_14_resp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10809: Assignment to wci_Emv_14_resp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10810: Assignment to wci_Emv_14_respData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10811: Assignment to wci_Emv_14_respData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10817: Assignment to wci_0_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10821: Assignment to wci_0_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10822: Assignment to wci_1_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10826: Assignment to wci_1_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10827: Assignment to wci_2_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10831: Assignment to wci_2_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10832: Assignment to wci_3_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10836: Assignment to wci_3_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10837: Assignment to wci_4_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10841: Assignment to wci_4_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10842: Assignment to wci_5_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10846: Assignment to wci_5_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10847: Assignment to wci_6_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10851: Assignment to wci_6_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10852: Assignment to wci_7_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10856: Assignment to wci_7_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10857: Assignment to wci_8_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10861: Assignment to wci_8_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10862: Assignment to wci_9_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10866: Assignment to wci_9_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10867: Assignment to wci_10_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10872: Assignment to wci_10_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10873: Assignment to wci_11_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10878: Assignment to wci_11_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10879: Assignment to wci_12_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10884: Assignment to wci_12_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10885: Assignment to wci_13_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10890: Assignment to wci_13_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10891: Assignment to wci_14_reqF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10896: Assignment to wci_14_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12161: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12183: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12348: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12370: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12536: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12558: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12724: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12746: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12912: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12934: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13100: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13122: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13287: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13309: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13473: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13495: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13659: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13681: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13845: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13867: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14031: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14053: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14217: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14239: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14403: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14425: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14589: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14611: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14775: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14797: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14885: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15195: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15363: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15420: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15478: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15536: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15594: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15652: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15710: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15767: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15824: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15881: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15938: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15995: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16052: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16109: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16166: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 24475: Assignment to warmResetP ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 25618: Assignment to timeServ_ppsExtCapture ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3483: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3529: Assignment to bram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3543: Assignment to bram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3550: Assignment to bram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3551: Assignment to bram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3553: Assignment to bram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3554: Assignment to bram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3555: Assignment to bram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3563: Assignment to bram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3565: Assignment to bram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3579: Assignment to bram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3585: Assignment to bram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3586: Assignment to bram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3588: Assignment to bram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3589: Assignment to bram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3590: Assignment to bram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3597: Assignment to bram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3599: Assignment to bram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3613: Assignment to bram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3620: Assignment to bram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3621: Assignment to bram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3623: Assignment to bram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3624: Assignment to bram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3625: Assignment to bram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3633: Assignment to bram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3635: Assignment to bram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3649: Assignment to bram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3655: Assignment to bram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3656: Assignment to bram_1_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3658: Assignment to bram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3659: Assignment to bram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3660: Assignment to bram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3661: Assignment to bram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3665: Assignment to bram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3667: Assignment to bram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3680: Assignment to bram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3687: Assignment to bram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3688: Assignment to bram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3690: Assignment to bram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3691: Assignment to bram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3692: Assignment to bram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3700: Assignment to bram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3702: Assignment to bram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3716: Assignment to bram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3722: Assignment to bram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3723: Assignment to bram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3725: Assignment to bram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3726: Assignment to bram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3727: Assignment to bram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3728: Assignment to bram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3732: Assignment to bram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3734: Assignment to bram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3748: Assignment to bram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3755: Assignment to bram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3756: Assignment to bram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3758: Assignment to bram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3759: Assignment to bram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3760: Assignment to bram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3768: Assignment to bram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3770: Assignment to bram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3784: Assignment to bram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3790: Assignment to bram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3791: Assignment to bram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3793: Assignment to bram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3794: Assignment to bram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3795: Assignment to bram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3796: Assignment to bram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3800: Assignment to bram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3808: Assignment to wci_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3809: Assignment to wci_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3810: Assignment to wci_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3811: Assignment to wci_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3812: Assignment to wci_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3813: Assignment to wci_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3814: Assignment to wci_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3815: Assignment to wci_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3824: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3825: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3826: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3827: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3828: Assignment to tlp_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3833: Assignment to tlp_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3837: Assignment to tlp_nearBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3840: Assignment to tlp_farBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3843: Assignment to tlp_creditReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3846: Assignment to tlp_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3847: Assignment to tlp_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3855: Assignment to tlp_nowW_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3856: Assignment to tlp_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3857: Assignment to tlp_dmaStartMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3861: Assignment to tlp_dmaDoneMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3862: Assignment to tlp_dmaDoneMark_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3870: Assignment to wmi_wmi_wmiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3871: Assignment to wmi_wmi_wmiMFlag_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3872: Assignment to wmi_wmi_wmiMFlag_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3878: Assignment to wmi_wmi_wmiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3879: Assignment to wmi_wmi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3880: Assignment to wmi_wmi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3881: Assignment to wmi_wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3882: Assignment to wmi_wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3883: Assignment to wmi_wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3884: Assignment to wmi_wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3894: Assignment to wmi_mesgStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3896: Assignment to wmi_mesgDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3901: Assignment to wmi_mesgBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3904: Assignment to wmi_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3905: Assignment to wmi_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3907: Assignment to wmi_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3908: Assignment to bml_lclBufStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3909: Assignment to bml_lclBufStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3910: Assignment to bml_lclBufDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3911: Assignment to bml_lclBufDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3912: Assignment to bml_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3913: Assignment to bml_remStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3914: Assignment to bml_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3915: Assignment to bml_remDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3916: Assignment to bml_fabDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3920: Assignment to bml_fabAvail_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3924: Assignment to bml_datumAReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3925: Assignment to bml_datumAReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3926: Assignment to bml_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3927: Assignment to bml_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3928: Assignment to wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3929: Assignment to wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3930: Assignment to wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3931: Assignment to wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3932: Assignment to wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3933: Assignment to wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3934: Assignment to wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3935: Assignment to wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3936: Assignment to wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3937: Assignment to wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3938: Assignment to wmi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3939: Assignment to wmi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3940: Assignment to wmi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3941: Assignment to wmi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3942: Assignment to wmi_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3943: Assignment to wmi_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3944: Assignment to wmi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3945: Assignment to wmi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3946: Assignment to wmi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3947: Assignment to wmi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3948: Assignment to wmi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3949: Assignment to wmi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3950: Assignment to wmi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3951: Assignment to wmi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3964: Assignment to bram_1_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3971: Assignment to bram_2_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3978: Assignment to bram_3_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3980: Assignment to wci_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3984: Assignment to wci_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3988: Assignment to wci_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3989: Assignment to wci_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4002: Assignment to wmi_wmi_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4004: Assignment to wmi_wmi_reqF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4005: Assignment to wmi_wmi_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4006: Assignment to wmi_wmi_reqF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4008: Assignment to wmi_wmi_reqF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4009: Assignment to wmi_wmi_reqF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4010: Assignment to wmi_wmi_mFlagF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4012: Assignment to wmi_wmi_mFlagF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4013: Assignment to wmi_wmi_mFlagF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4014: Assignment to wmi_wmi_mFlagF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4016: Assignment to wmi_wmi_mFlagF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4017: Assignment to wmi_wmi_mFlagF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4018: Assignment to wmi_wmi_dhF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4019: Assignment to wmi_wmi_dhF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4020: Assignment to wmi_wmi_dhF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4021: Assignment to wmi_wmi_dhF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4023: Assignment to wmi_wmi_dhF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4024: Assignment to wmi_wmi_dhF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4025: Assignment to wmi_wmi_respF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4026: Assignment to wmi_wmi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4027: Assignment to bml_lclBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4028: Assignment to bml_lclBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4029: Assignment to bml_remBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4030: Assignment to bml_remBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4031: Assignment to bml_fabBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4032: Assignment to bml_fabBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4033: Assignment to bml_crdBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4034: Assignment to bml_crdBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4035: Assignment to wmi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4036: Assignment to wmi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4037: Assignment to wmi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4038: Assignment to wmi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4039: Assignment to bml_lclBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4040: Assignment to bml_remBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4041: Assignment to bml_fabBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4042: Assignment to bml_crdBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4100: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4512: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4581: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4649: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4754: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4779: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4835: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4878: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4914: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5067: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5091: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5220: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5240: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5487: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5511: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5581: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5599: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5616: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5633: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5699: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5717: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5734: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5751: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5817: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5835: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5852: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5869: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5935: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5953: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5970: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5987: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6072: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6129: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 7301: Assignment to bml_datumAReg ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3483: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3529: Assignment to bram_0_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3543: Assignment to bram_0_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3550: Assignment to bram_0_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3551: Assignment to bram_0_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3553: Assignment to bram_0_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3554: Assignment to bram_0_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3555: Assignment to bram_0_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3563: Assignment to bram_0_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3565: Assignment to bram_0_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3579: Assignment to bram_0_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3585: Assignment to bram_0_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3586: Assignment to bram_0_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3588: Assignment to bram_0_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3589: Assignment to bram_0_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3590: Assignment to bram_0_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3597: Assignment to bram_0_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3599: Assignment to bram_1_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3613: Assignment to bram_1_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3620: Assignment to bram_1_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3621: Assignment to bram_1_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3623: Assignment to bram_1_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3624: Assignment to bram_1_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3625: Assignment to bram_1_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3633: Assignment to bram_1_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3635: Assignment to bram_1_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3649: Assignment to bram_1_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3655: Assignment to bram_1_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3656: Assignment to bram_1_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3658: Assignment to bram_1_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3659: Assignment to bram_1_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3660: Assignment to bram_1_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3661: Assignment to bram_1_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3665: Assignment to bram_1_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3667: Assignment to bram_2_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3680: Assignment to bram_2_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3687: Assignment to bram_2_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3688: Assignment to bram_2_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3690: Assignment to bram_2_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3691: Assignment to bram_2_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3692: Assignment to bram_2_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3700: Assignment to bram_2_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3702: Assignment to bram_2_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3716: Assignment to bram_2_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3722: Assignment to bram_2_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3723: Assignment to bram_2_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3725: Assignment to bram_2_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3726: Assignment to bram_2_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3727: Assignment to bram_2_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3728: Assignment to bram_2_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3732: Assignment to bram_2_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3734: Assignment to bram_3_serverAdapterA_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3748: Assignment to bram_3_serverAdapterA_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3755: Assignment to bram_3_serverAdapterA_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3756: Assignment to bram_3_serverAdapterA_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3758: Assignment to bram_3_serverAdapterA_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3759: Assignment to bram_3_serverAdapterA_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3760: Assignment to bram_3_serverAdapterA_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3768: Assignment to bram_3_serverAdapterA_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3770: Assignment to bram_3_serverAdapterB_outData_enqData_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3784: Assignment to bram_3_serverAdapterB_cnt_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3790: Assignment to bram_3_serverAdapterB_cnt_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3791: Assignment to bram_3_serverAdapterB_cnt_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3793: Assignment to bram_3_serverAdapterB_cnt_3_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3794: Assignment to bram_3_serverAdapterB_cnt_3_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3795: Assignment to bram_3_serverAdapterB_writeWithResp_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3796: Assignment to bram_3_serverAdapterB_writeWithResp_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3800: Assignment to bram_3_serverAdapterB_s1_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3808: Assignment to wci_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3809: Assignment to wci_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3810: Assignment to wci_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3811: Assignment to wci_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3812: Assignment to wci_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3813: Assignment to wci_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3814: Assignment to wci_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3815: Assignment to wci_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3824: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3825: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3826: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3827: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3828: Assignment to tlp_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3833: Assignment to tlp_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3837: Assignment to tlp_nearBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3840: Assignment to tlp_farBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3843: Assignment to tlp_creditReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3846: Assignment to tlp_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3847: Assignment to tlp_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3855: Assignment to tlp_nowW_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3856: Assignment to tlp_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3857: Assignment to tlp_dmaStartMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3861: Assignment to tlp_dmaDoneMark_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3862: Assignment to tlp_dmaDoneMark_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3870: Assignment to wmi_wmi_wmiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3871: Assignment to wmi_wmi_wmiMFlag_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3872: Assignment to wmi_wmi_wmiMFlag_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3878: Assignment to wmi_wmi_wmiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3879: Assignment to wmi_wmi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3880: Assignment to wmi_wmi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3881: Assignment to wmi_wmi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3882: Assignment to wmi_wmi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3883: Assignment to wmi_wmi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3884: Assignment to wmi_wmi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3894: Assignment to wmi_mesgStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3896: Assignment to wmi_mesgDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3901: Assignment to wmi_mesgBufReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3904: Assignment to wmi_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3905: Assignment to wmi_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3907: Assignment to wmi_nowW_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3908: Assignment to bml_lclBufStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3909: Assignment to bml_lclBufStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3910: Assignment to bml_lclBufDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3911: Assignment to bml_lclBufDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3912: Assignment to bml_remStart_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3913: Assignment to bml_remStart_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3914: Assignment to bml_remDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3915: Assignment to bml_remDone_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3916: Assignment to bml_fabDone_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3920: Assignment to bml_fabAvail_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3924: Assignment to bml_datumAReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3925: Assignment to bml_datumAReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3926: Assignment to bml_dpControl_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3927: Assignment to bml_dpControl_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3928: Assignment to wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3929: Assignment to wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3930: Assignment to wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3931: Assignment to wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3932: Assignment to wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3933: Assignment to wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3934: Assignment to wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3935: Assignment to wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3936: Assignment to wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3937: Assignment to wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3938: Assignment to wmi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3939: Assignment to wmi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3940: Assignment to wmi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3941: Assignment to wmi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3942: Assignment to wmi_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3943: Assignment to wmi_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3944: Assignment to wmi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3945: Assignment to wmi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3946: Assignment to wmi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3947: Assignment to wmi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3948: Assignment to wmi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3949: Assignment to wmi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3950: Assignment to wmi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3951: Assignment to wmi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3964: Assignment to bram_1_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3971: Assignment to bram_2_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3978: Assignment to bram_3_serverAdapterB_outData_deqCalled_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3980: Assignment to wci_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3984: Assignment to wci_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3988: Assignment to wci_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3989: Assignment to wci_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4002: Assignment to wmi_wmi_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4004: Assignment to wmi_wmi_reqF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4005: Assignment to wmi_wmi_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4006: Assignment to wmi_wmi_reqF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4008: Assignment to wmi_wmi_reqF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4009: Assignment to wmi_wmi_reqF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4010: Assignment to wmi_wmi_mFlagF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4012: Assignment to wmi_wmi_mFlagF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4013: Assignment to wmi_wmi_mFlagF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4014: Assignment to wmi_wmi_mFlagF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4016: Assignment to wmi_wmi_mFlagF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4017: Assignment to wmi_wmi_mFlagF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4018: Assignment to wmi_wmi_dhF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4019: Assignment to wmi_wmi_dhF_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4020: Assignment to wmi_wmi_dhF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4021: Assignment to wmi_wmi_dhF_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4023: Assignment to wmi_wmi_dhF_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4024: Assignment to wmi_wmi_dhF_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4025: Assignment to wmi_wmi_respF_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4026: Assignment to wmi_wmi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4027: Assignment to bml_lclBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4028: Assignment to bml_lclBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4029: Assignment to bml_remBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4030: Assignment to bml_remBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4031: Assignment to bml_fabBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4032: Assignment to bml_fabBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4033: Assignment to bml_crdBuf_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4034: Assignment to bml_crdBuf_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4035: Assignment to wmi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4036: Assignment to wmi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4037: Assignment to wmi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4038: Assignment to wmi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4039: Assignment to bml_lclBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4040: Assignment to bml_remBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4041: Assignment to bml_fabBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4042: Assignment to bml_crdBuf_modulus_bw_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4100: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4512: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4581: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4649: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4754: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4779: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4835: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4878: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4914: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5067: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5091: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5220: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5240: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5487: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5511: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5581: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5599: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5616: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5633: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5699: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5717: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5734: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5751: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5817: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5835: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5852: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5869: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5935: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5953: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5970: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5987: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6072: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6129: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 7301: Assignment to bml_datumAReg ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 118: Assignment to wti_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 119: Assignment to wti_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 120: Assignment to wti_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 140: Assignment to wti_peerIsReady ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkPktMerge.v" Line 198: Found parallel_case directive in module mkPktMerge. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkPktMerge.v" Line 240: Found parallel_case directive in module mkPktMerge. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1691: Assignment to wtiM_0_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1692: Assignment to wtiM_0_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1693: Assignment to wtiM_1_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1694: Assignment to wtiM_1_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1695: Assignment to wtiM_2_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1696: Assignment to wtiM_2_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1697: Assignment to wtiM_0_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1698: Assignment to wtiM_1_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1699: Assignment to wtiM_2_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1918: Assignment to wtiM_0_peerIsReady ignored, since the identifier is never used +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1483: Input port EN_uuid is not connected on this instance +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1243: Port sda is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 353: Port pd_PSEN is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 347: Assignment to ocb_mon_PSDONE ignored, since the identifier is never used +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 369: Module memc_ui_top does not have a parameter named OCB_MONITOR +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 379: Module memc_ui_top does not have a parameter named SIM_CAL_OPTION +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 380: Module memc_ui_top does not have a parameter named SIM_INIT_OPTION + +Elaborating module . + +Elaborating module +. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" Line 386: Assignment to dfi_odt_nom0_r3 ignored, since the identifier is never used +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" Line 432: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v" Line 146: Net does not have a driver. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v" Line 153: Net does not have a driver. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 443: Result of 64-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 444: Result of 64-bit expression is truncated to fit in 8-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 168: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 169: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 201: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v" Line 426: Result of 32-bit expression is truncated to fit in 6-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 140: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 198: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 204: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:532 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" Line 323: Index <13> is out of range [12:0] for signal . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" Line 151: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" Line 506: Result of 32-bit expression is truncated to fit in 5-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 764: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 854: Result of 8-bit expression is truncated to fit in 7-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 879: Result of 11-bit expression is truncated to fit in 10-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 888: Result of 10-bit expression is truncated to fit in 9-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 935: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 950: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 966: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 987: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1038: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1051: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1179: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1208: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1083: Found full_case directive in module phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1561: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1573: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1657: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1735: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1745: Found full_case directive in module phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" Line 232: Assignment to rst_r ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" Line 152: Assignment to dqs_ibuf_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" Line 288: Assignment to dqs_n_tfb ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v" Line 147: Assignment to mask_data_rise0_r4 ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v" Line 239: Assignment to wr_data_rise0_r4 ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v" Line 199: Assignment to dqs_oe_r ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 269: Assignment to wrdata_en_r7 ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1549: Assignment to wrlvl_done_r3 ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1634: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1758: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1761: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1764: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1767: Result of 32-bit expression is truncated to fit in 8-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 284: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 298: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 523: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 540: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 453: Assignment to wl_state_r1 ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 310: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 324: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 331: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 339: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 301: Found full_case directive in module phy_rdclk_gen. Use of full_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 173: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 180: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v" Line 163: Result of 10-bit expression is truncated to fit in 9-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 143: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 170: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 143: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 170: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 566: Result of 8-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 647: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 707: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 878: Assignment to prev_found_edge_valid_r ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 918: Result of 13-bit expression is truncated to fit in 12-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 946: Result of 13-bit expression is truncated to fit in 12-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1025: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1046: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1048: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1167: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1179: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1283: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1292: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1296: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1317: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1343: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1356: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1357: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1372: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1395: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1405: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1413: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1479: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1481: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1483: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1497: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1525: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1073: Assignment to found_two_edge_r ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1541: Result of 31-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1650: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1784: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1809: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1880: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1974: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1984: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1995: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 2037: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 2091: Result of 32-bit expression is truncated to fit in 5-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v" Line 275: Result of 32-bit expression is truncated to fit in 4-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 199: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 229: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 416: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 417: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 593: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" Line 977: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 568: Assignment to ecc_single ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 570: Assignment to ecc_err_addr ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v" Line 232: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v" Line 199: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 620: Assignment to hi_priority ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 377: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 378: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 396: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 412: Assignment to ddr3_parity ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 419: Assignment to bank_mach_next ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 423: Assignment to app_ecc_multiple_err_i ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 267: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 268: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 298: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 306: Net does not have a driver. +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 399: Input port pd_PSDONE is not connected on this instance +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1246: Size mismatch in connection of port . Formal port size is 27-bit while actual signal size is 33-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1295: Size mismatch in connection of port . Formal port size is 256-bit while actual signal size is 32-bit. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1651: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1697: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1698: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1704: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1705: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1706: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1707: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1708: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1712: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1713: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1714: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1715: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1716: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1717: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1718: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1719: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1720: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1721: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1722: Assignment to memc_wdfWren_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1726: Assignment to memc_wdfEnd_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1727: Assignment to memc_wdfEnd_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1733: Assignment to wmemi_wmemiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1739: Assignment to wmemi_wmemiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1740: Assignment to wmemi_cmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1744: Assignment to wmemi_dhAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1749: Assignment to wmemi_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1750: Assignment to wmemi_respF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1751: Assignment to wmemi_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1752: Assignment to wmemi_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1753: Assignment to wmemi_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1754: Assignment to wmemi_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1755: Assignment to memInReset_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1756: Assignment to memInReset_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1757: Assignment to wmemiReadInFlight_acc_v1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1761: Assignment to wmemiReadInFlight_acc_v2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1762: Assignment to wmemiReadInFlight_acc_v2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1763: Assignment to wmemi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1764: Assignment to wmemi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1765: Assignment to wmemi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1766: Assignment to wmemi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1767: Assignment to wmemi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1768: Assignment to wmemi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1769: Assignment to wmemi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1770: Assignment to wmemi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1771: Assignment to wmemi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1772: Assignment to wmemi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1773: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1777: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1783: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1784: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1798: Assignment to wmemi_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1799: Assignment to wmemi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1800: Assignment to wmemi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1801: Assignment to wmemi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1991: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2015: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2121: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2143: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2291: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2753: Assignment to pioReadInFlight ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2876: Assignment to dbgCtrl ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 918: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 951: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 952: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 958: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 959: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 960: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 961: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 962: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 966: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 967: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 968: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 969: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 970: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 971: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 972: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 973: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 974: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 975: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 976: Assignment to flashC_rseqFsm_start_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 980: Assignment to flashC_rseqFsm_start_reg_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 981: Assignment to flashC_rseqFsm_start_reg_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 982: Assignment to flashC_rseqFsm_abort_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 983: Assignment to flashC_rseqFsm_abort_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 984: Assignment to flashC_rseqFsm_state_fired_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 985: Assignment to flashC_rseqFsm_state_fired_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 987: Assignment to flashC_wseqFsm_start_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 991: Assignment to flashC_wseqFsm_start_reg_2_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 992: Assignment to flashC_wseqFsm_start_reg_2_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 993: Assignment to flashC_wseqFsm_abort_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 994: Assignment to flashC_wseqFsm_abort_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 995: Assignment to flashC_wseqFsm_state_fired_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 996: Assignment to flashC_wseqFsm_state_fired_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 998: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1002: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1008: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1009: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1028: Assignment to flashC_rseqFsm_state_overlap_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1055: Assignment to flashC_wseqFsm_state_overlap_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1130: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1271: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1449: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1473: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1589: Assignment to flashC_wdReg ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v" Line 106: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v" Line 106: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1227: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1264: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1265: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1273: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1274: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1275: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1276: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1277: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1281: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1282: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1283: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1284: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1285: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1286: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1287: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1288: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1289: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1290: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1297: Assignment to spiCDC_csbR_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1298: Assignment to spiCDC_doResp_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1302: Assignment to spiDAC_cGate_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1305: Assignment to spiDAC_csbR_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1306: Assignment to spiDAC_csbR_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1314: Assignment to fcCdc_pulseAction_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1315: Assignment to fcCdc_pulseAction_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1316: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1320: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1328: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1329: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1342: Assignment to spiCDC_reqF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1343: Assignment to spiCDC_reqF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1344: Assignment to spiCDC_reqF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1345: Assignment to spiCDC_reqF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1346: Assignment to spiCDC_respF_enq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1347: Assignment to spiCDC_respF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1348: Assignment to spiCDC_respF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1349: Assignment to spiCDC_respF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1350: Assignment to spiCDC_respF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1354: Assignment to spiDAC_reqF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1355: Assignment to spiDAC_reqF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1356: Assignment to spiDAC_reqF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1357: Assignment to spiDAC_reqF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1358: Assignment to spiDAC_respF_enq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1359: Assignment to spiDAC_respF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1360: Assignment to spiDAC_respF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1361: Assignment to spiDAC_respF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1362: Assignment to spiDAC_respF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1363: Assignment to fcCdc_grayCounter_pwIncrement_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1364: Assignment to fcCdc_grayCounter_pwDecrement_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1365: Assignment to oneKHz_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1366: Assignment to oneKHz_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1367: Assignment to spiCDC_sdiWs_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1368: Assignment to spiDAC_sdiWs_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1369: Assignment to fcCdc_grayCounter_wdCounterCrossing_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1719: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1743: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 2023: Assignment to splitReadInFlight ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 614: Assignment to gmii_rx_clk_O ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 624: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 626: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 627: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 628: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1023: Assignment to rxRS_rxOperateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1024: Assignment to rxRS_rxOperateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1025: Assignment to txRS_txOperateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1026: Assignment to txRS_txOperateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1035: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1051: Assignment to txRS_txDV_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1056: Assignment to txRS_txER_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1057: Assignment to txRS_txER_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1058: Assignment to txRS_underflow_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1059: Assignment to txRS_underflow_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1062: Assignment to rxRS_preambleCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1065: Assignment to rxRS_crcDbgCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1066: Assignment to txRS_preambleCnt_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1067: Assignment to txRS_preambleCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1068: Assignment to txRS_ifgCnt_incAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1078: Assignment to txRS_lenCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1085: Assignment to txRS_crcDbgCnt_decAction_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1437: Assignment to txRS_underflow ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1485: Assignment to rxRS_isSOF ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1768: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1802: Assignment to wci_wslv_wciReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1803: Assignment to wci_wslv_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1809: Assignment to wci_wslv_wEdge_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1810: Assignment to wci_wslv_wEdge_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1811: Assignment to wci_wslv_sFlagReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1812: Assignment to wci_wslv_sFlagReg_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1813: Assignment to wci_wslv_ctlAckReg_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1817: Assignment to wci_wci_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1818: Assignment to wci_wci_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1819: Assignment to wci_wci_Es_mAddrSpace_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1820: Assignment to wci_wci_Es_mAddrSpace_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1821: Assignment to wci_wci_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1822: Assignment to wci_wci_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1823: Assignment to wci_wci_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1824: Assignment to wci_wci_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1825: Assignment to wci_wci_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1826: Assignment to wci_wci_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1827: Assignment to wti_wtiReq_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1828: Assignment to wti_wtiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1829: Assignment to wti_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1830: Assignment to wti_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1831: Assignment to wsiM_reqFifo_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1832: Assignment to wsiM_reqFifo_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1833: Assignment to wsiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1836: Assignment to wsiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1837: Assignment to wsiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1846: Assignment to wsiS_wsiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1847: Assignment to wsiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1848: Assignment to wsiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1849: Assignment to wsiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1850: Assignment to wsiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1854: Assignment to wsi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1855: Assignment to wsi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1856: Assignment to wsi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1857: Assignment to wsi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1858: Assignment to wsi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1859: Assignment to wsi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1860: Assignment to wsi_Es_mByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1861: Assignment to wsi_Es_mByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1862: Assignment to wsi_Es_mReqInfo_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1863: Assignment to wsi_Es_mReqInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1864: Assignment to wci_wslv_reqF_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1868: Assignment to wci_wslv_reqF_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1874: Assignment to wci_wslv_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1875: Assignment to wci_wslv_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1885: Assignment to wsiM_reqFifo_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1886: Assignment to wsiM_reqFifo_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1887: Assignment to wsiM_sThreadBusy_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1888: Assignment to wsiS_reqFifo_r_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1889: Assignment to wsiS_reqFifo_r_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1891: Assignment to wsiS_reqFifo_r_clr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1892: Assignment to wsiS_reqFifo_doResetEnq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1893: Assignment to wsiS_reqFifo_doResetDeq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1895: Assignment to wsiS_reqFifo_doResetClr_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1896: Assignment to mdi_pwTick_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1897: Assignment to wsi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1898: Assignment to wsi_Es_mBurstPrecise_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1899: Assignment to wsi_Es_mDataInfo_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 2341: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 2365: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 3497: Assignment to txDBGPos ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 3755: Assignment to wti_nowReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1806: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1877: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1923: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2064: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2278: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2746: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2822: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" Line 719: Assignment to block_clk ignored, since the identifier is never used + +Elaborating module +. + +Elaborating module +. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1166: Assignment to LL2BADDLLPERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1167: Assignment to LL2BADTLPERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1168: Assignment to LL2PROTOCOLERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1169: Assignment to LL2REPLAYROERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1170: Assignment to LL2REPLAYTOERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1171: Assignment to LL2SUSPENDOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1172: Assignment to LL2TFCINIT1SEQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1173: Assignment to LL2TFCINIT2SEQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1252: Assignment to PL2LINKUPN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1253: Assignment to PL2RECEIVERERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1254: Assignment to PL2RECOVERYN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1255: Assignment to PL2RXELECIDLE ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1256: Assignment to PL2SUSPENDOK ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1259: Assignment to TL2ASPMSUSPENDCREDITCHECKOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1260: Assignment to TL2ASPMSUSPENDREQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1261: Assignment to TL2PPMSUSPENDOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1273: Assignment to TRNRDLLPSRCRDYN ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 336: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 337: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 338: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 339: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 340: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 341: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 342: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 343: Net does not have a driver. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 180: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 229: Result of 9-bit expression is truncated to fit in 8-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module +. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. + +Elaborating module . +"/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" Line 126. $display [ $time ] pcie_bram_top_v6 ROWS_TX 1 COLS_TX 4 +"/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" Line 127. $display [ $time ] pcie_bram_top_v6 ROWS_RX 1 COLS_RX 4 + +Elaborating module . +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v" Line 257: Port DOPB is not connected to this instance + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1886: Size mismatch in connection of port . Formal port size is 72-bit while actual signal size is 69-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1894: Size mismatch in connection of port . Formal port size is 72-bit while actual signal size is 68-bit. + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" Line 986: Assignment to rx_func_level_reset_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1065: Assignment to wmemiS_wmemiReq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1071: Assignment to wmemiS_wmemiDh_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1072: Assignment to wmemiS_cmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1077: Assignment to wmemiS_dhAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1082: Assignment to wmemiS_respF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1085: Assignment to wmemiS_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1086: Assignment to wmemiS_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1087: Assignment to wmemiS_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1088: Assignment to wmemiS_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1089: Assignment to wmemiM_reqF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1090: Assignment to wmemiM_reqF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1091: Assignment to wmemiM_dhF_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1092: Assignment to wmemiM_dhF_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1095: Assignment to wmemiM_wmemiResponse_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1096: Assignment to wmemiM_sCmdAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1097: Assignment to wmemiM_sCmdAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1098: Assignment to wmemiM_sDataAccept_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1099: Assignment to wmemiM_sDataAccept_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1100: Assignment to wmemiM_operateD_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1101: Assignment to wmemiM_operateD_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1102: Assignment to wmemiM_peerIsReady_1_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1103: Assignment to wmemiM_peerIsReady_1_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1104: Assignment to a4l_a4wrAddr_fifof_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1106: Assignment to a4l_a4wrAddr_fifof_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1107: Assignment to a4l_a4wrData_fifof_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1109: Assignment to a4l_a4wrData_fifof_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1110: Assignment to a4l_a4rdAddr_fifof_x_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1112: Assignment to a4l_a4rdAddr_fifof_x_wire_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1113: Assignment to wmemi_Es_mCmd_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1114: Assignment to wmemi_Es_mCmd_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1115: Assignment to wmemi_Es_mAddr_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1116: Assignment to wmemi_Es_mAddr_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1117: Assignment to wmemi_Es_mBurstLength_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1118: Assignment to wmemi_Es_mBurstLength_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1119: Assignment to wmemi_Es_mData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1120: Assignment to wmemi_Es_mData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1121: Assignment to wmemi_Es_mDataByteEn_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1122: Assignment to wmemi_Es_mDataByteEn_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1123: Assignment to wmemi_Em_sResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1124: Assignment to wmemi_Em_sResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1125: Assignment to wmemi_Em_sData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1126: Assignment to wmemi_Em_sData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1129: Assignment to wmemiS_respF_dequeueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1144: Assignment to a4l_a4wrAddr_deq_ready_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1145: Assignment to a4l_a4wrAddr_deq_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1146: Assignment to a4l_a4wrData_fifof_enqueueing_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1150: Assignment to a4l_a4wrData_deq_ready_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1151: Assignment to a4l_a4wrData_deq_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1152: Assignment to a4l_a4wrResp_enq_valid_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1153: Assignment to a4l_a4wrResp_enq_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1159: Assignment to a4l_a4rdAddr_deq_ready_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1160: Assignment to a4l_a4rdAddr_deq_deq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1161: Assignment to a4l_a4rdResp_enq_valid_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1162: Assignment to a4l_a4rdResp_enq_enq_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1163: Assignment to wmemi_Es_mReqLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1164: Assignment to wmemi_Es_mDataValid_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1165: Assignment to wmemi_Es_mDataLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1166: Assignment to wmemi_Em_sRespLast_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1167: Assignment to a4l_a4wrResp_data_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1168: Assignment to a4l_a4rdResp_data_wire_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1186: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1212: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1247: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1273: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1308: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1334: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1380: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1401: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1449: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1471: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1533: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1557: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" Line 1688: Assignment to wmemiM_busyWithMessage ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2062: Assignment to pciw_pci0_wTrnTxSof_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2063: Assignment to pciw_pci0_wTrnTxSof_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2064: Assignment to pciw_pci0_wTrnTxEof_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2065: Assignment to pciw_pci0_wTrnTxEof_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2066: Assignment to pciw_pci0_wTrnTxDsc_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2067: Assignment to pciw_pci0_wTrnTxDsc_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2068: Assignment to pciw_pci0_wTrnTxRem_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2069: Assignment to pciw_pci0_wTrnTxRem_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2070: Assignment to pciw_pci0_wTrnTxDat_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2071: Assignment to pciw_pci0_wTrnTxDat_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2072: Assignment to pciw_pci0_wTrnRxNpOk_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2073: Assignment to pciw_pci0_wTrnRxNpOk_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2074: Assignment to pciw_pci0_wTrnRxCplS_n_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2075: Assignment to pciw_pci0_wTrnRxCplS_n_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2076: Assignment to pciw_pcie_irq_wInterruptRdyN_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2078: Assignment to pciw_pcie_irq_wInterruptRdyN_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2079: Assignment to pciw_pcie_irq_wInterruptDo_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2081: Assignment to pciw_pcie_irq_wInterruptDo_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2082: Assignment to a4lm_wrAddrRdy_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2083: Assignment to a4lm_wrAddrRdy_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2084: Assignment to a4lm_wrDataRdy_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2085: Assignment to a4lm_wrDataRdy_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2086: Assignment to a4lm_wrRespVal_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2087: Assignment to a4lm_wrRespVal_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2088: Assignment to a4lm_rdAddrRdy_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2089: Assignment to a4lm_rdAddrRdy_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2090: Assignment to a4lm_rdRespVal_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2091: Assignment to a4lm_rdRespVal_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2092: Assignment to a4lm_wrResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2093: Assignment to a4lm_wrResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2094: Assignment to a4lm_rdData_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2095: Assignment to a4lm_rdData_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2096: Assignment to a4lm_rdResp_w_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2097: Assignment to a4lm_rdResp_w_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2110: Assignment to pciw_p2iAF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2111: Assignment to pciw_p2iAF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2112: Assignment to pciw_p2iAF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2117: Assignment to pciw_i2pAF_deq_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2119: Assignment to pciw_i2pAF_sClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2120: Assignment to pciw_i2pAF_dClear_pw_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2121: Assignment to pciw_i2pAF_deq_happened_whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2122: Assignment to infLed_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2123: Assignment to blinkLed_wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2545: Assignment to pciw_pcie_irq_rMMEnabled ignored, since the identifier is never used +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" Line 108: Input port gmii_col_i is not connected on this instance +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 982. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1027. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1072. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1117. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1162. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 598. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 606. All outputs of instance of block are unconnected in block . Underlying logic will be removed. + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v". +WARNING:Xst:2898 - Port 'gmii_col_i', unconnected in block instance 'ftop', is tied to GND. +WARNING:Xst:2898 - Port 'gmii_crs_i', unconnected in block instance 'ftop', is tied to GND. +WARNING:Xst:2898 - Port 'gmii_intr_i', unconnected in block instance 'ftop', is tied to GND. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 108: Output port of the instance is unconnected or connected to loadless signal. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1343: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1343: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1371: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1564: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1564: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1564: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1564: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1754: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1875: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 82-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 82-bit register for signal . + Found 32-bit adder for signal created at line 2126. + Found 1-bit comparator equal for signal created at line 2012 + Found 1-bit comparator equal for signal created at line 2306 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 538 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkAXBLUART.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" line 428: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" line 428: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkAXBLUART.v" line 428: Output port of the instance is unconnected or connected to loadless signal. + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 766. + Found 2-bit subtractor for signal created at line 768. + Found 6-bit subtractor for signal created at line 772. + Found 2-bit adder for signal created at line 515. + Found 2-bit adder for signal created at line 526. + Found 6-bit adder for signal created at line 714. + Found 64x8-bit Read Only RAM for signal + Summary: + inferred 1 RAM(s). + inferred 6 Adder/Subtractor(s). + inferred 211 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 35-bit register for signal . + Found 35-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 72 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 36-bit register for signal . + Found 36-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 74 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkBLUART.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 16-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 16-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 4-bit adder for signal created at line 264. + Found 16-bit adder for signal created at line 285. + Found 4-bit adder for signal created at line 294. + Found 16-bit adder for signal created at line 327. + Found 1-bit 10-to-1 multiplexer for signal created at line 302. + Found 16-bit comparator equal for signal created at line 244 + Found 16-bit comparator greater for signal created at line 285 + Found 16-bit comparator equal for signal created at line 328 + Found 16-bit comparator greater for signal created at line 329 + Found 16-bit comparator equal for signal created at line 338 + Summary: + inferred 4 Adder/Subtractor(s). + inferred 68 D-type flip-flop(s). + inferred 5 Comparator(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". +WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. + Found 3x8-bit dual-port RAM for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 81. + Found 2-bit adder for signal created at line 82. + Found 2-bit comparator equal for signal created at line 180 + Found 2-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 15 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 18 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 982: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 982: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1027: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1027: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1072: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1072: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1117: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1117: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1162: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1162: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1201: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 3-bit register for signal . + Found 2-bit subtractor for signal created at line 2082. + Found 2-bit subtractor for signal created at line 2200. + Found 2-bit subtractor for signal created at line 2534. + Found 32-bit adder for signal created at line 1415. + Found 32-bit adder for signal created at line 1416. + Found 2-bit adder for signal created at line 1422. + Found 2-bit adder for signal created at line 2081. + Found 32-bit adder for signal created at line 2168. + Found 32-bit adder for signal created at line 2187. + Found 2-bit adder for signal created at line 2199. + Found 32-bit adder for signal created at line 2225. + Found 3-bit adder for signal created at line 2469. + Found 3-bit adder for signal created at line 2469. + Found 3-bit adder for signal created at line 2480. + Found 3-bit adder for signal created at line 2480. + Found 3-bit adder for signal created at line 2488. + Found 3-bit adder for signal created at line 2488. + Found 3-bit adder for signal created at line 2496. + Found 3-bit adder for signal created at line 2496. + Found 3-bit adder for signal created at line 2504. + Found 3-bit adder for signal created at line 2504. + Found 14-bit adder for signal created at line 2512. + Found 3-bit adder for signal created at line 2515. + Found 3-bit adder for signal created at line 2535. + Found 3-bit adder for signal created at line 2536. + Found 4x3-bit Read Only RAM for signal <_n1537> + Found 1-bit 4-to-1 multiplexer for signal created at line 2566. + Found 32-bit 4-to-1 multiplexer for signal created at line 2621. + Found 1-bit 4-to-1 multiplexer for signal created at line 2646. + Found 1-bit 4-to-1 multiplexer for signal created at line 2671. + Found 34-bit 8-to-1 multiplexer for signal <_n1601> created at line 866. + Found 2-bit comparator greater for signal created at line 943 + Found 2-bit comparator greater for signal created at line 1505 + Found 1-bit comparator not equal for signal created at line 2084 + Found 1-bit comparator not equal for signal created at line 2202 + Found 3-bit comparator greater for signal created at line 2452 + Found 3-bit comparator greater for signal created at line 2454 + Found 3-bit comparator greater for signal created at line 2455 + Found 3-bit comparator greater for signal created at line 2456 + Found 3-bit comparator greater for signal created at line 2457 + Found 32-bit comparator greater for signal created at line 2476 + Found 32-bit comparator greater for signal created at line 2511 + Found 3-bit comparator greater for signal created at line 2569 + Found 3-bit comparator greater for signal created at line 2572 + Found 3-bit comparator greater for signal created at line 2575 + Found 3-bit comparator greater for signal created at line 2578 + Found 3-bit comparator greater for signal created at line 2610 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 23 Adder/Subtractor(s). + inferred 347 D-type flip-flop(s). + inferred 16 Comparator(s). + inferred 22 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 1024x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x32-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 37 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x72-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 77 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x61-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 66 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkCTop16B.v". +WARNING:Xst:2898 - Port 'EN_uuid', unconnected in block instance 'inf', is tied to GND. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1483: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1483: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 67-bit register for signal . + Summary: + inferred 70 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCApp16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" line 628: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 32-bit subtractor for signal created at line 834. + Found 32-bit subtractor for signal created at line 1046. + Found 2-bit subtractor for signal created at line 1148. + Found 32-bit subtractor for signal created at line 1381. + Found 2-bit subtractor for signal created at line 1437. + Found 2-bit subtractor for signal created at line 1438. + Found 2-bit subtractor for signal created at line 1439. + Found 2-bit adder for signal created at line 840. + Found 2-bit adder for signal created at line 870. + Found 2-bit adder for signal created at line 885. + Found 32-bit adder for signal created at line 998. + Found 32-bit adder for signal created at line 1004. + Found 32-bit adder for signal created at line 1008. + Found 32-bit adder for signal > created at line 1055. + Found 32-bit adder for signal > created at line 1056. + Found 32-bit adder for signal > created at line 1057. + Found 32-bit adder for signal > created at line 1058. + Found 32-bit adder for signal created at line 1068. + Found 2-bit adder for signal created at line 1147. + Found 32-bit adder for signal > created at line 1220. + Found 32-bit adder for signal > created at line 1221. + Found 32-bit adder for signal > created at line 1222. + Found 32-bit adder for signal > created at line 1223. + Found 32-bit adder for signal created at line 1227. + Found 32-bit adder for signal created at line 1231. + Found 32-bit adder for signal created at line 1235. + Found 4x3-bit Read Only RAM for signal <_n1596> + Found 34-bit 13-to-1 multiplexer for signal <_n1679> created at line 531. + Found 2-bit comparator greater for signal created at line 581 + Found 1-bit comparator not equal for signal created at line 1150 + Found 128-bit comparator not equal for signal created at line 1412 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 25 Adder/Subtractor(s). + inferred 1202 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 258 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 264 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1194: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1211: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 182-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 14-bit subtractor for signal created at line 1541. + Found 16-bit subtractor for signal created at line 1552. + Found 2-bit subtractor for signal created at line 1623. + Found 2-bit subtractor for signal created at line 2053. + Found 2-bit subtractor for signal created at line 2499. + Found 12-bit subtractor for signal created at line 2619. + Found 2-bit subtractor for signal created at line 2664. + Found 2-bit subtractor for signal created at line 2665. + Found 2-bit subtractor for signal created at line 2666. + Found 2-bit subtractor for signal created at line 2667. + Found 12-bit adder for signal created at line 1536. + Found 12-bit adder for signal created at line 1536. + Found 32-bit adder for signal created at line 1542. + Found 14-bit adder for signal created at line 1544. + Found 2-bit adder for signal created at line 1558. + Found 2-bit adder for signal created at line 1588. + Found 2-bit adder for signal created at line 1599. + Found 2-bit adder for signal created at line 1606. + Found 2-bit adder for signal created at line 1624. + Found 32-bit adder for signal created at line 1807. + Found 2-bit adder for signal created at line 2052. + Found 32-bit adder for signal created at line 2311. + Found 32-bit adder for signal created at line 2315. + Found 32-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2339. + Found 32-bit adder for signal created at line 2355. + Found 32-bit adder for signal created at line 2441. + Found 32-bit adder for signal created at line 2467. + Found 32-bit adder for signal created at line 2486. + Found 2-bit adder for signal created at line 2498. + Found 32-bit adder for signal created at line 2524. + Found 24-bit adder for signal created at line 2620. + Found 14-bit adder for signal created at line 2628. + Found 5-bit adder for signal created at line 2631. + Found 12-bit adder for signal created at line 2670. + Found 12-bit adder for signal created at line 2677. + Found 12-bit adder for signal created at line 2678. + Found 5-bit adder for signal created at line 2788. + Found 5-bit adder for signal created at line 2789. + Found 5-bit adder for signal created at line 2790. + Found 5-bit adder for signal created at line 2791. + Found 5-bit adder for signal created at line 2792. + Found 5-bit adder for signal created at line 2793. + Found 5-bit adder for signal created at line 2794. + Found 5-bit adder for signal created at line 2795. + Found 5-bit adder for signal created at line 2796. + Found 5-bit adder for signal created at line 2797. + Found 5-bit adder for signal created at line 2798. + Found 5-bit adder for signal created at line 2799. + Found 5-bit adder for signal created at line 2800. + Found 5-bit adder for signal created at line 2801. + Found 4x3-bit Read Only RAM for signal <_n2038> + Found 34-bit 24-to-1 multiplexer for signal <_n2107> created at line 950. + Found 2-bit comparator greater for signal created at line 1107 + Found 12-bit comparator greater for signal created at line 1252 + Found 12-bit comparator not equal for signal created at line 1386 + Found 12-bit comparator equal for signal created at line 1639 + Found 2-bit comparator greater for signal created at line 1710 + Found 14-bit comparator lessequal for signal created at line 1838 + Found 1-bit comparator not equal for signal created at line 2055 + Found 1-bit comparator not equal for signal created at line 2501 + Found 12-bit comparator not equal for signal created at line 2670 + Found 14-bit comparator equal for signal created at line 2680 + Found 4-bit comparator lessequal for signal created at line 2684 + Found 4-bit comparator lessequal for signal created at line 2686 + Found 4-bit comparator lessequal for signal created at line 2688 + Found 4-bit comparator lessequal for signal created at line 2690 + Found 4-bit comparator lessequal for signal created at line 2692 + Found 4-bit comparator lessequal for signal created at line 2694 + Found 4-bit comparator lessequal for signal created at line 2696 + Found 4-bit comparator lessequal for signal created at line 2698 + Found 4-bit comparator lessequal for signal created at line 2700 + Found 4-bit comparator lessequal for signal created at line 2702 + Found 4-bit comparator lessequal for signal created at line 2705 + Found 4-bit comparator lessequal for signal created at line 2708 + Found 4-bit comparator lessequal for signal created at line 2711 + Found 4-bit comparator lessequal for signal created at line 2715 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 1668 D-type flip-flop(s). + inferred 24 Comparator(s). + inferred 48 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO10.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 2048x169-bit dual-port RAM for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 338 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 262 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x169-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 174 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" line 620: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit subtractor for signal created at line 808. + Found 2-bit subtractor for signal created at line 998. + Found 2-bit subtractor for signal created at line 1245. + Found 2-bit subtractor for signal created at line 1318. + Found 2-bit adder for signal created at line 777. + Found 2-bit adder for signal created at line 809. + Found 2-bit adder for signal created at line 997. + Found 32-bit adder for signal created at line 1085. + Found 32-bit adder for signal created at line 1101. + Found 32-bit adder for signal created at line 1187. + Found 32-bit adder for signal created at line 1213. + Found 32-bit adder for signal created at line 1232. + Found 2-bit adder for signal created at line 1244. + Found 32-bit adder for signal created at line 1271. + Found 32-bit adder for signal > created at line 1321. + Found 32-bit adder for signal > created at line 1322. + Found 32-bit adder for signal > created at line 1323. + Found 32-bit adder for signal > created at line 1324. + Found 4x3-bit Read Only RAM for signal <_n0683> + Found 34-bit 15-to-1 multiplexer for signal <_n0763> created at line 537. + Found 2-bit comparator greater for signal created at line 579 + Found 2-bit comparator greater for signal created at line 866 + Found 1-bit comparator not equal for signal created at line 1000 + Found 1-bit comparator not equal for signal created at line 1247 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 16 Adder/Subtractor(s). + inferred 710 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 7 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1194: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1211: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 182-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 14-bit subtractor for signal created at line 1541. + Found 16-bit subtractor for signal created at line 1552. + Found 2-bit subtractor for signal created at line 1623. + Found 2-bit subtractor for signal created at line 2053. + Found 2-bit subtractor for signal created at line 2499. + Found 12-bit subtractor for signal created at line 2619. + Found 2-bit subtractor for signal created at line 2664. + Found 2-bit subtractor for signal created at line 2665. + Found 2-bit subtractor for signal created at line 2666. + Found 2-bit subtractor for signal created at line 2667. + Found 12-bit adder for signal created at line 1536. + Found 12-bit adder for signal created at line 1536. + Found 32-bit adder for signal created at line 1542. + Found 14-bit adder for signal created at line 1544. + Found 2-bit adder for signal created at line 1558. + Found 2-bit adder for signal created at line 1588. + Found 2-bit adder for signal created at line 1599. + Found 2-bit adder for signal created at line 1606. + Found 2-bit adder for signal created at line 1624. + Found 32-bit adder for signal created at line 1807. + Found 2-bit adder for signal created at line 2052. + Found 32-bit adder for signal created at line 2311. + Found 32-bit adder for signal created at line 2315. + Found 32-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2339. + Found 32-bit adder for signal created at line 2355. + Found 32-bit adder for signal created at line 2441. + Found 32-bit adder for signal created at line 2467. + Found 32-bit adder for signal created at line 2486. + Found 2-bit adder for signal created at line 2498. + Found 32-bit adder for signal created at line 2524. + Found 24-bit adder for signal created at line 2620. + Found 14-bit adder for signal created at line 2628. + Found 5-bit adder for signal created at line 2631. + Found 12-bit adder for signal created at line 2670. + Found 12-bit adder for signal created at line 2677. + Found 12-bit adder for signal created at line 2678. + Found 5-bit adder for signal created at line 2788. + Found 5-bit adder for signal created at line 2789. + Found 5-bit adder for signal created at line 2790. + Found 5-bit adder for signal created at line 2791. + Found 5-bit adder for signal created at line 2792. + Found 5-bit adder for signal created at line 2793. + Found 5-bit adder for signal created at line 2794. + Found 5-bit adder for signal created at line 2795. + Found 5-bit adder for signal created at line 2796. + Found 5-bit adder for signal created at line 2797. + Found 5-bit adder for signal created at line 2798. + Found 5-bit adder for signal created at line 2799. + Found 5-bit adder for signal created at line 2800. + Found 5-bit adder for signal created at line 2801. + Found 4x3-bit Read Only RAM for signal <_n2038> + Found 34-bit 24-to-1 multiplexer for signal <_n2110> created at line 950. + Found 2-bit comparator greater for signal created at line 1107 + Found 12-bit comparator greater for signal created at line 1252 + Found 12-bit comparator not equal for signal created at line 1386 + Found 12-bit comparator equal for signal created at line 1639 + Found 2-bit comparator greater for signal created at line 1710 + Found 14-bit comparator lessequal for signal created at line 1838 + Found 1-bit comparator not equal for signal created at line 2055 + Found 1-bit comparator not equal for signal created at line 2501 + Found 12-bit comparator not equal for signal created at line 2670 + Found 14-bit comparator equal for signal created at line 2680 + Found 4-bit comparator lessequal for signal created at line 2684 + Found 4-bit comparator lessequal for signal created at line 2686 + Found 4-bit comparator lessequal for signal created at line 2688 + Found 4-bit comparator lessequal for signal created at line 2690 + Found 4-bit comparator lessequal for signal created at line 2692 + Found 4-bit comparator lessequal for signal created at line 2694 + Found 4-bit comparator lessequal for signal created at line 2696 + Found 4-bit comparator lessequal for signal created at line 2698 + Found 4-bit comparator lessequal for signal created at line 2700 + Found 4-bit comparator lessequal for signal created at line 2702 + Found 4-bit comparator lessequal for signal created at line 2705 + Found 4-bit comparator lessequal for signal created at line 2708 + Found 4-bit comparator lessequal for signal created at line 2711 + Found 4-bit comparator lessequal for signal created at line 2715 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 1668 D-type flip-flop(s). + inferred 24 Comparator(s). + inferred 48 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkUUID.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 64-bit register for signal . + Found 64-bit register for signal . + Summary: + inferred 128 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncHandshake.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit comparator not equal for signal created at line 68 + Found 1-bit comparator equal for signal created at line 69 + Summary: + inferred 6 D-type flip-flop(s). + inferred 2 Comparator(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCInf16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2041: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2484: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2484: Output port of the instance is unconnected or connected to loadless signal. + Summary: + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCCP.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5398: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5417: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5436: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5455: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5474: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5493: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5512: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5531: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5550: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5569: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5588: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5607: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5626: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5645: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5664: Output port of the instance is unconnected or connected to loadless signal. + Found 65-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 57-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 1-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 64-bit subtractor for signal created at line 10957. + Found 50-bit subtractor for signal created at line 11922. + Found 28-bit subtractor for signal created at line 12027. + Found 50-bit subtractor for signal <_281474976710656_MINUS_timeServ_delSecond__q1> created at line 17283. + Found 4-bit subtractor for signal created at line 17480. + Found 4-bit subtractor for signal created at line 17481. + Found 32-bit adder for signal created at line 9361. + Found 1-bit adder for signal created at line 9383. + Found 1-bit adder for signal created at line 9462. + Found 1-bit adder for signal created at line 9539. + Found 1-bit adder for signal created at line 9616. + Found 1-bit adder for signal created at line 9693. + Found 1-bit adder for signal created at line 9770. + Found 1-bit adder for signal created at line 9846. + Found 1-bit adder for signal created at line 9922. + Found 1-bit adder for signal created at line 9998. + Found 1-bit adder for signal created at line 10074. + Found 1-bit adder for signal created at line 10150. + Found 1-bit adder for signal created at line 10226. + Found 1-bit adder for signal created at line 10302. + Found 1-bit adder for signal created at line 10378. + Found 1-bit adder for signal created at line 10454. + Found 7-bit adder for signal created at line 11846. + Found 50-bit adder for signal created at line 11929. + Found 8-bit adder for signal created at line 11968. + Found 28-bit adder for signal created at line 12015. + Found 28-bit adder for signal created at line 12037. + Found 28-bit adder for signal created at line 12044. + Found 3-bit adder for signal created at line 17325. + Found 3-bit adder for signal created at line 17325. + Found 32-bit adder for signal created at line 17514. + Found 32-bit adder for signal created at line 17515. + Found 32-bit adder for signal created at line 17516. + Found 32-bit adder for signal created at line 17517. + Found 32-bit adder for signal created at line 17518. + Found 32-bit adder for signal created at line 17519. + Found 32-bit adder for signal created at line 17521. + Found 32-bit adder for signal created at line 17522. + Found 50-bit adder for signal created at line 17526. + Found 32-bit adder for signal created at line 17527. + Found 32-bit adder for signal created at line 17528. + Found 32-bit adder for signal created at line 17529. + Found 32-bit adder for signal created at line 17530. + Found 32-bit adder for signal created at line 17531. + Found 32-bit adder for signal created at line 17532. + Found 32-bit adder for signal created at line 17533. + Found 32-bit adder for signal created at line 17534. + Found 32-bit shifter logical left for signal created at line 4556 + Found 32-bit shifter logical left for signal created at line 4557 + Found 32-bit shifter logical left for signal created at line 4558 + Found 32-bit shifter logical left for signal created at line 4559 + Found 32-bit shifter logical left for signal created at line 4560 + Found 32-bit shifter logical left for signal created at line 4561 + Found 32-bit shifter logical left for signal created at line 4562 + Found 32-bit shifter logical left for signal created at line 4563 + Found 32-bit shifter logical left for signal created at line 4564 + Found 32-bit shifter logical left for signal created at line 4565 + Found 32-bit shifter logical left for signal created at line 4566 + Found 32-bit shifter logical left for signal created at line 4567 + Found 32-bit shifter logical left for signal created at line 4568 + Found 32-bit shifter logical left for signal created at line 4569 + Found 32-bit shifter logical left for signal created at line 4570 + Found 32-bit 16-to-1 multiplexer for signal created at line 17629. + Found 1-bit 16-to-1 multiplexer for signal created at line 17666. + Found 1-bit 16-to-1 multiplexer for signal created at line 17735. + Found 1-bit 16-to-1 multiplexer for signal created at line 17815. + Found 1-bit 16-to-1 multiplexer for signal created at line 17883. + Found 1-bit 16-to-1 multiplexer for signal created at line 17952. + Found 1-bit 16-to-1 multiplexer for signal created at line 18020. + Found 1-bit 16-to-1 multiplexer for signal created at line 18089. + Found 1-bit 16-to-1 multiplexer for signal created at line 18157. + Found 1-bit 16-to-1 multiplexer for signal created at line 18226. + Found 1-bit 16-to-1 multiplexer for signal created at line 18294. + Found 1-bit 16-to-1 multiplexer for signal created at line 18363. + Found 1-bit 16-to-1 multiplexer for signal created at line 18431. + Found 1-bit 16-to-1 multiplexer for signal created at line 18500. + Found 1-bit 16-to-1 multiplexer for signal created at line 18568. + Found 1-bit 16-to-1 multiplexer for signal created at line 18637. + Found 1-bit 16-to-1 multiplexer for signal created at line 18705. + Found 1-bit 16-to-1 multiplexer for signal created at line 18774. + Found 1-bit 16-to-1 multiplexer for signal created at line 18843. + Found 1-bit 16-to-1 multiplexer for signal created at line 18911. + Found 1-bit 16-to-1 multiplexer for signal created at line 18979. + Found 1-bit 16-to-1 multiplexer for signal created at line 19048. + Found 1-bit 16-to-1 multiplexer for signal created at line 19116. + Found 1-bit 16-to-1 multiplexer for signal created at line 19185. + Found 1-bit 16-to-1 multiplexer for signal created at line 19253. + Found 1-bit 16-to-1 multiplexer for signal created at line 19322. + Found 1-bit 16-to-1 multiplexer for signal created at line 19390. + Found 1-bit 16-to-1 multiplexer for signal created at line 19459. + Found 1-bit 16-to-1 multiplexer for signal created at line 19527. + Found 1-bit 16-to-1 multiplexer for signal created at line 19596. + Found 1-bit 16-to-1 multiplexer for signal created at line 19663. + Found 1-bit 16-to-1 multiplexer for signal created at line 19730. + Found 1-bit 16-to-1 multiplexer for signal created at line 19843. + Found 1-bit 16-to-1 multiplexer for signal created at line 20093. + Found 1-bit 16-to-1 multiplexer for signal created at line 20162. + Found 1-bit 16-to-1 multiplexer for signal created at line 20242. + Found 1-bit 16-to-1 multiplexer for signal created at line 20447. + Found 1-bit 16-to-1 multiplexer for signal created at line 20516. + Found 1-bit 16-to-1 multiplexer for signal created at line 20721. + Found 1-bit 16-to-1 multiplexer for signal created at line 20790. + Found 1-bit 16-to-1 multiplexer for signal created at line 20995. + Found 1-bit 16-to-1 multiplexer for signal created at line 21064. + Found 1-bit 16-to-1 multiplexer for signal created at line 21269. + Found 1-bit 16-to-1 multiplexer for signal created at line 21338. + Found 1-bit 16-to-1 multiplexer for signal created at line 21543. + Found 1-bit 16-to-1 multiplexer for signal created at line 21612. + Found 1-bit 16-to-1 multiplexer for signal created at line 21817. + Found 1-bit 16-to-1 multiplexer for signal created at line 21886. + Found 1-bit 16-to-1 multiplexer for signal created at line 22091. + Found 1-bit 16-to-1 multiplexer for signal created at line 22160. + Found 1-bit 16-to-1 multiplexer for signal created at line 22365. + Found 1-bit 16-to-1 multiplexer for signal created at line 22434. + Found 1-bit 16-to-1 multiplexer for signal created at line 22639. + Found 1-bit 16-to-1 multiplexer for signal created at line 22708. + Found 1-bit 16-to-1 multiplexer for signal created at line 22913. + Found 1-bit 16-to-1 multiplexer for signal created at line 22982. + Found 1-bit 16-to-1 multiplexer for signal created at line 23187. + Found 1-bit 16-to-1 multiplexer for signal created at line 23256. + Found 1-bit 16-to-1 multiplexer for signal created at line 23461. + Found 1-bit 16-to-1 multiplexer for signal created at line 23530. + Found 1-bit 16-to-1 multiplexer for signal created at line 23735. + Found 1-bit 16-to-1 multiplexer for signal created at line 23804. + Found 1-bit 16-to-1 multiplexer for signal created at line 24005. + Found 1-bit 16-to-1 multiplexer for signal created at line 24072. + Found 1-bit 16-to-1 multiplexer for signal created at line 24169. + Found 1-bit 16-to-1 multiplexer for signal created at line 24265. + Found 32-bit 16-to-1 multiplexer for signal created at line 24421. + Found 3-bit comparator greater for signal created at line 5814 + Found 7-bit comparator lessequal for signal created at line 10554 + Found 7-bit comparator lessequal for signal created at line 10554 + Found 28-bit comparator greater for signal created at line 11964 + Found 2-bit comparator not equal for signal created at line 16408 + Found 8-bit comparator greater for signal created at line 17299 + Found 8-bit comparator greater for signal created at line 17300 + Found 24-bit comparator greater for signal created at line 17302 + Found 24-bit comparator greater for signal created at line 17304 + Found 28-bit comparator greater for signal created at line 17334 + Found 28-bit comparator greater for signal created at line 17342 + Found 28-bit comparator greater for signal created at line 17344 + Found 32-bit comparator greater for signal created at line 17376 + Found 32-bit comparator greater for signal created at line 17383 + Found 32-bit comparator greater for signal created at line 17390 + Found 32-bit comparator greater for signal created at line 17397 + Found 32-bit comparator greater for signal created at line 17404 + Found 32-bit comparator greater for signal created at line 17411 + Found 32-bit comparator greater for signal created at line 17418 + Found 32-bit comparator greater for signal created at line 17425 + Found 32-bit comparator greater for signal created at line 17432 + Found 32-bit comparator greater for signal created at line 17439 + Found 32-bit comparator greater for signal created at line 17446 + Found 32-bit comparator greater for signal created at line 17453 + Found 32-bit comparator greater for signal created at line 17460 + Found 32-bit comparator greater for signal created at line 17467 + Found 32-bit comparator greater for signal created at line 17474 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 47 Adder/Subtractor(s). + inferred 4100 D-type flip-flop(s). + inferred 27 Comparator(s). + inferred 299 Multiplexer(s). + inferred 15 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO1.v". + Found 33-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 59-bit register for signal . + Found 59-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 120 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 40-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 82 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM1Load.v". + Found 1024x32-bit single-port RAM for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 32 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 28-bit register for signal . + Found 28-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x64-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 86 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 17-bit register for signal . + Summary: + inferred 17 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO1.v". + Found 34-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 35 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTLPSerializer.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 30-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 10-bit subtractor for signal created at line 313. + Found 10-bit subtractor for signal created at line 314. + Found 2-bit subtractor for signal created at line 322. + Found 10-bit subtractor for signal created at line 323. + Found 12-bit subtractor for signal created at line 490. + Found 12-bit subtractor for signal created at line 522. + Found 2-bit adder for signal created at line 319. + Found 30-bit adder for signal created at line 321. + Found 2-bit subtractor for signal > created at line 203. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n0624> + Found 4x2-bit Read Only RAM for signal <_n0642> + Found 4x2-bit Read Only RAM for signal <_n0661> + Found 32-bit 4-to-1 multiplexer for signal created at line 548. + Summary: + inferred 4 RAM(s). + inferred 8 Adder/Subtractor(s). + inferred 283 D-type flip-flop(s). + inferred 16 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 56-bit register for signal . + Found 56-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 114 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 153-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 308 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCDP16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" line 2332: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 64-bit register for signal . + Found 64-bit register for signal . + Found 8-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 67-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 10-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 16-bit register for signal . + Found 10-bit subtractor for signal created at line 3265. + Found 10-bit subtractor for signal created at line 3268. + Found 10-bit subtractor for signal created at line 3269. + Found 10-bit subtractor for signal created at line 3271. + Found 10-bit subtractor for signal created at line 3275. + Found 4-bit subtractor for signal created at line 3276. + Found 17-bit subtractor for signal created at line 3306. + Found 10-bit subtractor for signal created at line 3316. + Found 10-bit subtractor for signal created at line 3317. + Found 10-bit subtractor for signal created at line 3319. + Found 4-bit subtractor for signal created at line 3383. + Found 10-bit subtractor for signal created at line 3448. + Found 10-bit subtractor for signal created at line 3450. + Found 10-bit subtractor for signal created at line 3456. + Found 10-bit subtractor for signal created at line 3458. + Found 10-bit subtractor for signal created at line 3464. + Found 10-bit subtractor for signal created at line 3466. + Found 2-bit subtractor for signal created at line 3503. + Found 14-bit subtractor for signal created at line 3504. + Found 14-bit subtractor for signal created at line 3508. + Found 16-bit subtractor for signal created at line 4045. + Found 16-bit subtractor for signal created at line 4066. + Found 2-bit subtractor for signal created at line 5201. + Found 2-bit subtractor for signal created at line 5406. + Found 2-bit subtractor for signal created at line 5458. + Found 2-bit subtractor for signal created at line 6550. + Found 2-bit subtractor for signal created at line 6551. + Found 2-bit subtractor for signal created at line 6552. + Found 2-bit subtractor for signal created at line 6554. + Found 2-bit subtractor for signal created at line 6555. + Found 2-bit subtractor for signal created at line 6556. + Found 13-bit subtractor for signal created at line 6664. + Found 13-bit subtractor for signal created at line 6665. + Found 2-bit subtractor for signal created at line 6782. + Found 2-bit subtractor for signal created at line 6796. + Found 12-bit subtractor for signal created at line 6799. + Found 16-bit subtractor for signal created at line 6823. + Found 16-bit subtractor for signal created at line 6825. + Found 16-bit subtractor for signal created at line 6827. + Found 16-bit subtractor for signal created at line 6829. + Found 16-bit adder for signal created at line 3013. + Found 16-bit adder for signal created at line 3017. + Found 32-bit adder for signal created at line 3033. + Found 32-bit adder for signal created at line 3037. + Found 16-bit adder for signal created at line 3041. + Found 16-bit adder for signal created at line 3061. + Found 16-bit adder for signal created at line 3065. + Found 16-bit adder for signal created at line 3069. + Found 16-bit adder for signal created at line 3073. + Found 16-bit adder for signal created at line 3077. + Found 11-bit adder for signal created at line 3128. + Found 32-bit adder for signal created at line 3277. + Found 32-bit adder for signal created at line 3278. + Found 17-bit adder for signal created at line 3296. + Found 17-bit adder for signal created at line 3298. + Found 16-bit adder for signal created at line 3384. + Found 16-bit adder for signal created at line 3385. + Found 13-bit adder for signal created at line 3452. + Found 13-bit adder for signal created at line 3454. + Found 13-bit adder for signal created at line 3460. + Found 13-bit adder for signal created at line 3462. + Found 2-bit adder for signal created at line 3473. + Found 14-bit adder for signal created at line 3502. + Found 32-bit adder for signal created at line 3509. + Found 2-bit adder for signal created at line 3517. + Found 16-bit adder for signal created at line 4236. + Found 16-bit adder for signal created at line 4263. + Found 16-bit adder for signal created at line 4304. + Found 16-bit adder for signal created at line 4330. + Found 12-bit adder for signal created at line 4460. + Found 5-bit adder for signal created at line 4548. + Found 32-bit adder for signal created at line 4640. + Found 2-bit adder for signal created at line 5200. + Found 16-bit adder for signal created at line 5381. + Found 2-bit adder for signal created at line 5405. + Found 2-bit adder for signal created at line 5457. + Found 16-bit adder for signal created at line 5557. + Found 32-bit adder for signal created at line 6384. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6471. + Found 3-bit adder for signal created at line 6471. + Found 17-bit adder for signal created at line 6690. + Found 13-bit adder for signal created at line 6704. + Found 13-bit adder for signal created at line 6706. + Found 13-bit adder for signal created at line 6708. + Found 2-bit adder for signal created at line 6712. + Found 13-bit adder for signal created at line 6715. + Found 13-bit adder for signal created at line 6717. + Found 13-bit adder for signal created at line 6719. + Found 16-bit adder for signal created at line 6822. + Found 16-bit adder for signal created at line 6824. + Found 16-bit adder for signal created at line 6826. + Found 16-bit adder for signal created at line 6828. + Found 12-bit subtractor for signal created at line 6167. + Found 2-bit subtractor for signal created at line 1969. + Found 2-bit subtractor for signal created at line 1973. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n4195> + Found 4x2-bit Read Only RAM for signal <_n4213> + Found 4x2-bit Read Only RAM for signal <_n4232> + Found 4x3-bit Read Only RAM for signal <_n4240> + Found 11-bit 4-to-1 multiplexer for signal created at line 3084. + Found 11-bit 4-to-1 multiplexer for signal created at line 3103. + Found 11-bit 4-to-1 multiplexer for signal created at line 3135. + Found 11-bit 4-to-1 multiplexer for signal created at line 3154. + Found 11-bit 4-to-1 multiplexer for signal created at line 3179. + Found 11-bit 4-to-1 multiplexer for signal created at line 3198. + Found 11-bit 4-to-1 multiplexer for signal created at line 3223. + Found 11-bit 4-to-1 multiplexer for signal created at line 3242. + Found 1-bit 4-to-1 multiplexer for signal created at line 6974. + Found 1-bit 4-to-1 multiplexer for signal created at line 6995. + Found 1-bit 4-to-1 multiplexer for signal created at line 7016. + Found 1-bit 4-to-1 multiplexer for signal created at line 7037. + Found 1-bit 4-to-1 multiplexer for signal created at line 7058. + Found 32-bit 4-to-1 multiplexer for signal created at line 7075. + Found 32-bit 4-to-1 multiplexer for signal created at line 7092. + Found 32-bit 4-to-1 multiplexer for signal created at line 7109. + Found 32-bit 4-to-1 multiplexer for signal created at line 7126. + Found 1-bit 4-to-1 multiplexer for signal created at line 7147. + Found 1-bit 4-to-1 multiplexer for signal created at line 7237. + Found 32-bit 4-to-1 multiplexer for signal created at line 7262. + Found 1-bit 4-to-1 multiplexer for signal created at line 7283. + Found 34-bit 44-to-1 multiplexer for signal <_n4508> created at line 1684. + Found 2-bit comparator greater for signal created at line 2040 + Found 2-bit comparator greater for signal created at line 3885 + Found 2-bit comparator greater for signal created at line 3890 + Found 1-bit comparator not equal for signal created at line 5203 + Found 1-bit comparator not equal for signal created at line 5408 + Found 1-bit comparator not equal for signal created at line 5460 + Found 10-bit comparator greater for signal created at line 6319 + Found 10-bit comparator greater for signal created at line 6321 + Found 10-bit comparator greater for signal created at line 6323 + Found 16-bit comparator equal for signal created at line 6380 + Found 16-bit comparator equal for signal created at line 6382 + Found 16-bit comparator equal for signal created at line 6391 + Found 16-bit comparator equal for signal created at line 6393 + Found 3-bit comparator greater for signal created at line 6399 + Found 3-bit comparator greater for signal created at line 6416 + Found 3-bit comparator greater for signal created at line 6427 + Found 3-bit comparator greater for signal created at line 6433 + Found 3-bit comparator greater for signal created at line 6447 + Found 3-bit comparator greater for signal created at line 6463 + Found 3-bit comparator greater for signal created at line 6469 + Found 3-bit comparator greater for signal created at line 6475 + Found 8-bit comparator equal for signal created at line 6489 + Found 17-bit comparator lessequal for signal created at line 6519 + Found 13-bit comparator lessequal for signal created at line 6673 + Found 10-bit comparator greater for signal created at line 6677 + Found 10-bit comparator greater for signal created at line 6679 + Found 8-bit comparator equal for signal created at line 6681 + Found 5-bit comparator equal for signal created at line 6682 + Found 3-bit comparator equal for signal created at line 6683 + Found 10-bit comparator lessequal for signal created at line 6693 + Found 10-bit comparator greater for signal created at line 6695 + Found 10-bit comparator lessequal for signal created at line 6702 + Found 10-bit comparator lessequal for signal created at line 6710 + Found 17-bit comparator lessequal for signal created at line 6818 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 RAM(s). + inferred 91 Adder/Subtractor(s). + inferred 2516 D-type flip-flop(s). + inferred 34 Comparator(s). + inferred 93 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 2048x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 153-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2448-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 153-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 2608 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 139-bit register for signal . + Found 139-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 280 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 124 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x146-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 151 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCDP16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" line 2332: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 64-bit register for signal . + Found 64-bit register for signal . + Found 8-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 67-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 10-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 16-bit register for signal . + Found 4-bit subtractor for signal created at line 3276. + Found 17-bit subtractor for signal created at line 3314. + Found 10-bit subtractor for signal created at line 3316. + Found 10-bit subtractor for signal created at line 3317. + Found 10-bit subtractor for signal created at line 3319. + Found 4-bit subtractor for signal created at line 3383. + Found 10-bit subtractor for signal created at line 3448. + Found 10-bit subtractor for signal created at line 3450. + Found 10-bit subtractor for signal created at line 3456. + Found 10-bit subtractor for signal created at line 3458. + Found 10-bit subtractor for signal created at line 3464. + Found 10-bit subtractor for signal created at line 3466. + Found 2-bit subtractor for signal created at line 3503. + Found 14-bit subtractor for signal created at line 3504. + Found 14-bit subtractor for signal created at line 3508. + Found 16-bit subtractor for signal created at line 4045. + Found 16-bit subtractor for signal created at line 4066. + Found 2-bit subtractor for signal created at line 5201. + Found 2-bit subtractor for signal created at line 5406. + Found 2-bit subtractor for signal created at line 5458. + Found 2-bit subtractor for signal created at line 6550. + Found 2-bit subtractor for signal created at line 6551. + Found 2-bit subtractor for signal created at line 6552. + Found 2-bit subtractor for signal created at line 6554. + Found 2-bit subtractor for signal created at line 6555. + Found 2-bit subtractor for signal created at line 6556. + Found 13-bit subtractor for signal created at line 6664. + Found 13-bit subtractor for signal created at line 6665. + Found 2-bit subtractor for signal created at line 6782. + Found 2-bit subtractor for signal created at line 6796. + Found 12-bit subtractor for signal created at line 6799. + Found 16-bit subtractor for signal created at line 6823. + Found 16-bit subtractor for signal created at line 6825. + Found 16-bit subtractor for signal created at line 6827. + Found 16-bit subtractor for signal created at line 6829. + Found 16-bit adder for signal created at line 3013. + Found 16-bit adder for signal created at line 3017. + Found 32-bit adder for signal created at line 3033. + Found 32-bit adder for signal created at line 3037. + Found 16-bit adder for signal created at line 3041. + Found 16-bit adder for signal created at line 3061. + Found 16-bit adder for signal created at line 3065. + Found 16-bit adder for signal created at line 3069. + Found 16-bit adder for signal created at line 3073. + Found 16-bit adder for signal created at line 3077. + Found 11-bit adder for signal created at line 3128. + Found 32-bit adder for signal created at line 3277. + Found 32-bit adder for signal created at line 3278. + Found 16-bit adder for signal created at line 3384. + Found 16-bit adder for signal created at line 3385. + Found 32-bit adder for signal created at line 3389. + Found 13-bit adder for signal created at line 3452. + Found 13-bit adder for signal created at line 3454. + Found 13-bit adder for signal created at line 3460. + Found 13-bit adder for signal created at line 3462. + Found 2-bit adder for signal created at line 3473. + Found 14-bit adder for signal created at line 3502. + Found 32-bit adder for signal created at line 3509. + Found 2-bit adder for signal created at line 3517. + Found 16-bit adder for signal created at line 4236. + Found 16-bit adder for signal created at line 4263. + Found 16-bit adder for signal created at line 4304. + Found 16-bit adder for signal created at line 4330. + Found 12-bit adder for signal created at line 4460. + Found 32-bit adder for signal created at line 4640. + Found 2-bit adder for signal created at line 5200. + Found 16-bit adder for signal created at line 5381. + Found 2-bit adder for signal created at line 5405. + Found 2-bit adder for signal created at line 5457. + Found 16-bit adder for signal created at line 5557. + Found 32-bit adder for signal created at line 6384. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6471. + Found 3-bit adder for signal created at line 6471. + Found 17-bit adder for signal created at line 6692. + Found 13-bit adder for signal created at line 6704. + Found 13-bit adder for signal created at line 6706. + Found 13-bit adder for signal created at line 6708. + Found 2-bit adder for signal created at line 6712. + Found 13-bit adder for signal created at line 6715. + Found 13-bit adder for signal created at line 6717. + Found 13-bit adder for signal created at line 6719. + Found 16-bit adder for signal created at line 6822. + Found 16-bit adder for signal created at line 6824. + Found 16-bit adder for signal created at line 6826. + Found 16-bit adder for signal created at line 6828. + Found 12-bit subtractor for signal created at line 6167. + Found 2-bit subtractor for signal created at line 1969. + Found 2-bit subtractor for signal created at line 1973. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n4136> + Found 4x2-bit Read Only RAM for signal <_n4154> + Found 4x3-bit Read Only RAM for signal <_n4169> + Found 4x2-bit Read Only RAM for signal <_n4189> + Found 11-bit 4-to-1 multiplexer for signal created at line 3084. + Found 11-bit 4-to-1 multiplexer for signal created at line 3103. + Found 11-bit 4-to-1 multiplexer for signal created at line 3135. + Found 11-bit 4-to-1 multiplexer for signal created at line 3154. + Found 11-bit 4-to-1 multiplexer for signal created at line 3179. + Found 11-bit 4-to-1 multiplexer for signal created at line 3198. + Found 11-bit 4-to-1 multiplexer for signal created at line 3223. + Found 11-bit 4-to-1 multiplexer for signal created at line 3242. + Found 1-bit 4-to-1 multiplexer for signal created at line 6974. + Found 1-bit 4-to-1 multiplexer for signal created at line 6995. + Found 1-bit 4-to-1 multiplexer for signal created at line 7016. + Found 1-bit 4-to-1 multiplexer for signal created at line 7037. + Found 1-bit 4-to-1 multiplexer for signal created at line 7058. + Found 32-bit 4-to-1 multiplexer for signal created at line 7075. + Found 32-bit 4-to-1 multiplexer for signal created at line 7092. + Found 32-bit 4-to-1 multiplexer for signal created at line 7109. + Found 32-bit 4-to-1 multiplexer for signal created at line 7126. + Found 1-bit 4-to-1 multiplexer for signal created at line 7147. + Found 1-bit 4-to-1 multiplexer for signal created at line 7237. + Found 32-bit 4-to-1 multiplexer for signal created at line 7262. + Found 1-bit 4-to-1 multiplexer for signal created at line 7283. + Found 34-bit 44-to-1 multiplexer for signal <_n4442> created at line 1684. + Found 2-bit comparator greater for signal created at line 2040 + Found 2-bit comparator greater for signal created at line 3885 + Found 2-bit comparator greater for signal created at line 3890 + Found 1-bit comparator not equal for signal created at line 5203 + Found 1-bit comparator not equal for signal created at line 5408 + Found 1-bit comparator not equal for signal created at line 5460 + Found 10-bit comparator greater for signal created at line 6319 + Found 10-bit comparator greater for signal created at line 6321 + Found 10-bit comparator greater for signal created at line 6323 + Found 16-bit comparator equal for signal created at line 6380 + Found 16-bit comparator equal for signal created at line 6382 + Found 16-bit comparator equal for signal created at line 6391 + Found 16-bit comparator equal for signal created at line 6393 + Found 3-bit comparator greater for signal created at line 6399 + Found 3-bit comparator greater for signal created at line 6416 + Found 3-bit comparator greater for signal created at line 6427 + Found 3-bit comparator greater for signal created at line 6433 + Found 3-bit comparator greater for signal created at line 6447 + Found 3-bit comparator greater for signal created at line 6463 + Found 3-bit comparator greater for signal created at line 6469 + Found 3-bit comparator greater for signal created at line 6475 + Found 17-bit comparator equal for signal created at line 6658 + Found 13-bit comparator lessequal for signal created at line 6669 + Found 10-bit comparator lessequal for signal created at line 6693 + Found 10-bit comparator greater for signal created at line 6695 + Found 10-bit comparator lessequal for signal created at line 6702 + Found 10-bit comparator lessequal for signal created at line 6710 + Found 17-bit comparator lessequal for signal created at line 6808 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 RAM(s). + inferred 87 Adder/Subtractor(s). + inferred 2502 D-type flip-flop(s). + inferred 28 Comparator(s). + inferred 93 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTimeClient.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 67-bit register for signal . + Summary: + inferred 68 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTLPSM.v". + Summary: + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkPktFork.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit shifter logical left for signal created at line 107 + Found 7-bit shifter logical left for signal created at line 107 + Found 1-bit 4-to-1 multiplexer for signal created at line 247. + Found 3-bit comparator equal for signal created at line 225 + Found 7-bit comparator equal for signal created at line 226 + Found 1-bit comparator equal for signal created at line 226 + Found 4-bit comparator equal for signal created at line 230 + Found 8-bit comparator equal for signal created at line 237 + Found 7-bit comparator equal for signal created at line 250 + Summary: + inferred 2 D-type flip-flop(s). + inferred 6 Comparator(s). + inferred 4 Multiplexer(s). + inferred 2 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkPktMerge.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1243: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1400: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit subtractor for signal created at line 1970. + Found 2-bit subtractor for signal created at line 2547. + Found 2-bit subtractor for signal created at line 2554. + Found 2-bit adder for signal created at line 1639. + Found 8-bit adder for signal created at line 1676. + Found 8-bit adder for signal created at line 1676. + Found 2-bit adder for signal created at line 1679. + Found 16-bit adder for signal created at line 1835. + Found 16-bit adder for signal created at line 1840. + Found 8-bit adder for signal created at line 1900. + Found 32-bit adder for signal created at line 1910. + Found 2-bit adder for signal created at line 1969. + Found 32-bit adder for signal created at line 2065. + Found 32-bit adder for signal created at line 2071. + Found 32-bit adder for signal created at line 2085. + Found 4x3-bit Read Only RAM for signal <_n1685> + Found 32-bit 39-to-1 multiplexer for signal <_n1795> created at line 886. + Found 34-bit 4-to-1 multiplexer for signal created at line 855. + Found 2-bit comparator greater for signal created at line 959 + Found 1-bit comparator not equal for signal created at line 1972 + Found 8-bit comparator greater for signal created at line 2317 + Found 8-bit comparator greater for signal created at line 2549 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 14 Adder/Subtractor(s). + inferred 849 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 161 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncBit.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 40-bit register for signal . + Found 40-bit register for signal . + Summary: + inferred 80 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 5-bit register for signal . + Found 5-bit register for signal . + Summary: + inferred 10 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 24-bit register for signal . + Found 24-bit register for signal . + Summary: + inferred 48 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 16-bit register for signal . + Found 16-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 64 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x177-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 177-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 199 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x128-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 128-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 150 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v". +WARNING:Xst:2898 - Port 'dbg_wr_dqs_tap_set', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_wr_dq_tap_set', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'pd_PSDONE', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_wr_tap_set_en', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_inc_rd_fps', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_dec_rd_fps', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 334: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 399: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "syn_maxfan = 10" for signal . + Found 31-bit register for signal . + Summary: + inferred 31 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v". + Set property "syn_maxfan = 10" for signal . + Set property "syn_maxfan = 10" for signal . + Found 33-bit register for signal . + Summary: + inferred 33 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 612: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v". + Set property "MAX_FANOUT = 10" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" line 628: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" line 628: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:2935 - Signal 'dfi_dram_clk_disable', unconnected in block 'mc', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'dfi_reset_n', unconnected in block 'mc', is tied to its initial value (1). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Summary: + inferred 84 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_mach.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v". +WARNING:Xst:2935 - Signal 'add_rrd_inhbt', unconnected in block 'rank_cntrl', is tied to its initial value (0). + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit subtractor for signal created at line 206. + Found 3-bit subtractor for signal created at line 267. + Found 4-bit subtractor for signal created at line 326. + Found 3-bit subtractor for signal created at line 385. + Found 3-bit adder for signal created at line 205. + Found 4-bit adder for signal created at line 329. + Found 3-bit comparator lessequal for signal created at line 271 + Summary: + inferred 5 Adder/Subtractor(s). + inferred 17 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 6 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" line 236: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" line 321: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit subtractor for signal created at line 122. + Found 6-bit subtractor for signal created at line 147. + Found 20-bit subtractor for signal created at line 175. + Found 1-bit adder for signal created at line 267. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Summary: + inferred 12 Adder/Subtractor(s). + inferred 43 D-type flip-flop(s). + inferred 18 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'req_rank_r_lcl', unconnected in block 'bank_compare', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'req_rank_ns', unconnected in block 'bank_compare', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'req_col_r<10>', unconnected in block 'bank_compare', is tied to its initial value (0). + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit shifter logical left for signal > created at line 280 + Found 3-bit comparator equal for signal created at line 221 + Found 13-bit comparator equal for signal created at line 230 + Summary: + inferred 44 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 5 Multiplexer(s). + inferred 1 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_1', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_1', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_1', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:4>', unconnected in block 'bank_queue_1', is tied to its initial value (0000). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<0>', unconnected in block 'bank_queue_1', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Summary: + inferred 5 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_2', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_2', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_2', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:5>', unconnected in block 'bank_queue_2', is tied to its initial value (000). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<1:0>', unconnected in block 'bank_queue_2', is tied to its initial value (00). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 6 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_3', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_3', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_3', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:6>', unconnected in block 'bank_queue_3', is tied to its initial value (00). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<2:0>', unconnected in block 'bank_queue_3', is tied to its initial value (000). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 7 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_4', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7>', unconnected in block 'bank_queue_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<3:0>', unconnected in block 'bank_queue_4', is tied to its initial value (0000). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 8 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'low_idle_cnt_r', unconnected in block 'bank_common', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 2-bit subtractor for signal created at line 393. + Found 6-bit subtractor for signal created at line 430. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 18 Adder/Subtractor(s). + inferred 21 D-type flip-flop(s). + inferred 14 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_mux.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 159: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 185: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 235: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:2935 - Signal 'send_cmd0_col', unconnected in block 'arb_row_col', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'send_cmd1_row', unconnected in block 'arb_row_col', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 6 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". + Found 4-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'row_mux.row_cmd_r', unconnected in block 'arb_select', is tied to its initial value (00000000000000000000). +WARNING:Xst:2935 - Signal 'col_mux.col_cmd_r', unconnected in block 'arb_select', is tied to its initial value (00000000000000000000). +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit shifter logical left for signal > created at line 349 + Found 1-bit shifter logical left for signal > created at line 351 + Found 1-bit shifter logical left for signal created at line 390 + Summary: + inferred 13 D-type flip-flop(s). + inferred 40 Multiplexer(s). + inferred 3 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'offset_r<1>', unconnected in block 'col_mach', is tied to its initial value (0). + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 11-bit register for signal >. + Found 1-bit register for signal >. + Found 11-bit register for signal . + Found 3-bit subtractor for signal created at line 260. + Found 2-bit subtractor for signal created at line 280. + Found 5-bit adder for signal created at line 377. + Found 5-bit adder for signal created at line 386. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 4 Adder/Subtractor(s). + inferred 45 D-type flip-flop(s). + inferred 10 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 955: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 955: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1131: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v". +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst - Value "0" of property "syn_replicate" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 256-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . +INFO:Xst:1799 - State 011110 is never reached in FSM . +INFO:Xst:1799 - State 100101 is never reached in FSM . +INFO:Xst:1799 - State 100100 is never reached in FSM . +INFO:Xst:1799 - State 100111 is never reached in FSM . +INFO:Xst:1799 - State 011101 is never reached in FSM . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 42 | + | Transitions | 86 | + | Inputs | 31 | + | Outputs | 43 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4-bit subtractor for signal created at line 1560. + Found 7-bit adder for signal created at line 854. + Found 10-bit adder for signal created at line 879. + Found 9-bit adder for signal created at line 888. + Found 8-bit adder for signal created at line 935. + Found 8-bit adder for signal created at line 966. + Found 2-bit adder for signal created at line 987. + Found 2-bit adder for signal created at line 1038. + Found 3-bit adder for signal created at line 1051. + Found 2-bit adder for signal created at line 1561. + Found 2-bit adder for signal created at line 1573. + Found 2-bit adder for signal created at line 1657. + Found 4-bit adder for signal created at line 1735. + Found 5-bit subtractor for signal > created at line 764. + Found 16x256-bit Read Only RAM for signal + Found 4x3-bit Read Only RAM for signal + Found 2-bit comparator greater for signal created at line 1208 + Found 32-bit comparator not equal for signal created at line 1560 + Found 2-bit comparator greater for signal created at line 1597 + WARNING:Xst:2404 - FFs/Latches <7:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1:2>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <2:10>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + Summary: + inferred 2 RAM(s). + inferred 14 Adder/Subtractor(s). + inferred 468 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 21 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_control_io.v". + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_keep = 1" for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 D-type flip-flop(s). + inferred 17 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_ck_iob.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v". + Set property "syn_maxfan = 1" for signal . + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 80 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 6-bit register for signal . + Found 6-bit register for signal . + Summary: + inferred 12 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v". + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit 4-to-1 multiplexer for signal created at line 109. + Found 4-bit 4-to-1 multiplexer for signal created at line 133. + Summary: + inferred 17 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Summary: + inferred 14 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Summary: + inferred 26 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Summary: + inferred 108 D-type flip-flop(s). + inferred 124 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 2-bit adder for signal created at line 1634. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 137 D-type flip-flop(s). + inferred 146 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 40-bit register for signal >. + Found 16-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal >. + Found 40-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <9>>. + Found 1-bit register for signal <8>>. + Found 1-bit register for signal <7>>. + Found 1-bit register for signal <6>>. + Found 1-bit register for signal <5>>. + Found 1-bit register for signal <14>>. + Found 1-bit register for signal <13>>. + Found 1-bit register for signal <12>>. + Found 1-bit register for signal <11>>. + Found 1-bit register for signal <10>>. + Found 1-bit register for signal <19>>. + Found 1-bit register for signal <18>>. + Found 1-bit register for signal <17>>. + Found 1-bit register for signal <16>>. + Found 1-bit register for signal <15>>. + Found 1-bit register for signal <24>>. + Found 1-bit register for signal <23>>. + Found 1-bit register for signal <22>>. + Found 1-bit register for signal <21>>. + Found 1-bit register for signal <20>>. + Found 1-bit register for signal <29>>. + Found 1-bit register for signal <28>>. + Found 1-bit register for signal <27>>. + Found 1-bit register for signal <26>>. + Found 1-bit register for signal <25>>. + Found 1-bit register for signal <34>>. + Found 1-bit register for signal <33>>. + Found 1-bit register for signal <32>>. + Found 1-bit register for signal <31>>. + Found 1-bit register for signal <30>>. + Found 1-bit register for signal <39>>. + Found 1-bit register for signal <38>>. + Found 1-bit register for signal <37>>. + Found 1-bit register for signal <36>>. + Found 1-bit register for signal <35>>. + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal >. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 9 | + | Transitions | 23 | + | Inputs | 10 | + | Outputs | 11 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 6-bit subtractor for signal created at line 541. + Found 4-bit subtractor for signal created at line 581. + Found 2-bit adder for signal created at line 284. + Found 2-bit adder for signal created at line 298. + Found 5-bit adder for signal created at line 492. + Found 4-bit adder for signal created at line 566. + Found 4-bit adder for signal created at line 567. + Found 4-bit adder for signal created at line 568. + Found 2-bit adder for signal created at line 586. + Found 5-bit adder for signal created at line 641. + Found 3x4-bit multiplier for signal created at line 408. + Found 1-bit 8-to-1 multiplexer for signal created at line 264. + Found 1-bit 8-to-1 multiplexer for signal created at line 285. + Found 1-bit 8-to-1 multiplexer for signal created at line 285. + Found 1-bit 8-to-1 multiplexer for signal created at line 299. + Found 5-bit 8-to-1 multiplexer for signal created at line 341. + Found 1-bit 8-to-1 multiplexer for signal created at line 512. + Found 1-bit 8-to-1 multiplexer for signal created at line 529. + Found 1-bit 16-to-1 multiplexer for signal created at line 640. + Found 1-bit 16-to-1 multiplexer for signal created at line 641. + Found 1-bit 8-to-1 multiplexer for signal created at line 665. + Found 1-bit 8-to-1 multiplexer for signal created at line 668. + Found 2-bit comparator lessequal for signal created at line 230 + Found 5-bit comparator greater for signal created at line 280 + Found 1-bit comparator equal for signal created at line 282 + Found 2-bit comparator greater for signal created at line 283 + Found 1-bit comparator equal for signal created at line 295 + Found 2-bit comparator greater for signal created at line 297 + Found 4-bit comparator lessequal for signal created at line 341 + Found 2-bit comparator lessequal for signal created at line 341 + Found 5-bit comparator greater for signal created at line 530 + Found 5-bit comparator greater for signal created at line 543 + Found 4-bit comparator lessequal for signal created at line 549 + Found 32-bit comparator equal for signal created at line 581 + Found 5-bit comparator lessequal for signal created at line 673 + Summary: + inferred 1 Multiplier(s). + inferred 10 Adder/Subtractor(s). + inferred 351 D-type flip-flop(s). + inferred 13 Comparator(s). + inferred 163 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_read.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 2-bit register for signal >. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 9-bit register for signal . + Found 2-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 11 | + | Inputs | 4 | + | Outputs | 27 | + | Clock | clk (rising_edge) | + | Reset | rst_oserdes (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4-bit adder for signal created at line 310. + Found 4-bit adder for signal created at line 324. + Found 4-bit adder for signal created at line 331. + Found 4-bit adder for signal created at line 339. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 4 Adder/Subtractor(s). + inferred 81 D-type flip-flop(s). + inferred 8 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v". + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rddata_sync.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 32-bit register for signal . + Found 256-bit register for signal . + Summary: + inferred 288 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 143. + Found 3-bit adder for signal created at line 170. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 12 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 143. + Found 3-bit adder for signal created at line 170. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 12 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v". + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 5-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 3-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 40-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 5-bit register for signal . + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 18 | + | Transitions | 42 | + | Inputs | 18 | + | Outputs | 18 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 00000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 10 | + | Transitions | 22 | + | Inputs | 10 | + | Outputs | 6 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 6 | + | Transitions | 15 | + | Inputs | 9 | + | Outputs | 5 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 6-bit subtractor for signal created at line 1284. + Found 6-bit subtractor for signal created at line 1297. + Found 6-bit subtractor for signal created at line 1395. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 4-bit adder for signal created at line 647. + Found 4-bit adder for signal created at line 707. + Found 12-bit adder for signal created at line 918. + Found 12-bit adder for signal created at line 946. + Found 3-bit adder for signal created at line 1025. + Found 5-bit adder for signal created at line 1046. + Found 31-bit adder for signal created at line 1284. + Found 6-bit adder for signal created at line 1290. + Found 32-bit adder for signal created at line 1297. + Found 3-bit adder for signal created at line 1343. + Found 5-bit adder for signal created at line 1413. + Found 7-bit adder for signal created at line 1480. + Found 32-bit adder for signal created at line 1541. + Found 6-bit adder for signal created at line 1543. + Found 3-bit adder for signal created at line 1650. + Found 5-bit adder for signal created at line 1784. + Found 3-bit adder for signal created at line 1880. + Found 5-bit adder for signal created at line 1974. + Found 2-bit adder for signal created at line 1984. + Found 3-bit adder for signal created at line 1996. + Found 3-bit adder for signal created at line 2037. + Found 5-bit subtractor for signal > created at line 1048. + Found 6-bit subtractor for signal > created at line 1293. + Found 6-bit subtractor for signal > created at line 1372. + Found 5-bit subtractor for signal > created at line 1479. + Found 5-bit subtractor for signal > created at line 1483. + Found 5-bit subtractor for signal > created at line 1497. + Found 5-bit subtractor for signal > created at line 1525. + Found 5-bit subtractor for signal > created at line 1809. + Found 5-bit subtractor for signal > created at line 2091. + Found 3x3-bit multiplier for signal created at line 599. + Found 30-bit shifter logical right for signal created at line 1996 + Found 3x3-bit multiplier for signal created at line 2021. + Found 3-bit 3-to-1 multiplexer for signal created at line 490. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 5-bit comparator lessequal for signal created at line 1289 + Found 6-bit comparator greater for signal created at line 1290 + Found 3-bit comparator greater for signal created at line 1336 + Found 6-bit comparator greater for signal created at line 1383 + Found 6-bit comparator lessequal for signal created at line 1478 + Found 7-bit comparator lessequal for signal created at line 1480 + Found 5-bit comparator lessequal for signal created at line 1756 + Found 3-bit comparator greater for signal created at line 1872 + Found 5-bit comparator lessequal for signal created at line 2013 + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <5:5>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <8:8>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <11:11>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <14:14>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <17:17>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <20:20>> (without init value) have a constant value of 0 in block . + Summary: + inferred 2 Multiplier(s). + inferred 44 Adder/Subtractor(s). + inferred 870 D-type flip-flop(s). + inferred 73 Comparator(s). + inferred 232 Multiplexer(s). + inferred 1 Combinational logic shifter(s). + inferred 3 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 6-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 9 | + | Inputs | 4 | + | Outputs | 9 | + | Clock | clk (rising_edge) | + | Reset | reset (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 5-bit adder for signal created at line 416. + Found 6-bit adder for signal created at line 502. + Found 16-bit adder for signal created at line 536. + Found 16-bit adder for signal created at line 546. + Found 4-bit adder for signal created at line 593. + Found 4-bit subtractor for signal created at line 184. + Found 5-bit subtractor for signal > created at line 417. + Found 1-bit 16-to-1 multiplexer for signal created at line 203. + Found 1-bit 16-to-1 multiplexer for signal created at line 205. + Found 1-bit 16-to-1 multiplexer for signal created at line 232. + Found 1-bit 16-to-1 multiplexer for signal created at line 233. + Summary: + inferred 6 Adder/Subtractor(s). + inferred 67 D-type flip-flop(s). + inferred 12 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_top.v". + Set property "MAX_FANOUT = 10" for signal . +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 10-bit register for signal . + Summary: + inferred 11 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v". + Found 1-bit register for signal . + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 68 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v". + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 256-bit register for signal . + Found 5-bit subtractor for signal created at line 376. + Found 4-bit adder for signal created at line 232. + Found 4-bit adder for signal created at line 252. + Found 4-bit adder for signal created at line 283. + Found 5-bit adder for signal created at line 377. + Summary: + inferred 5 Adder/Subtractor(s). + inferred 339 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'app_ecc_multiple_err_r', unconnected in block 'ui_rd_data', is tied to its initial value (0000). + Found 6-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit adder for signal created at line 224. + Found 6-bit adder for signal created at line 183. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 11 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 2-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 2-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 41 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 177-bit register for signal . + Found 177-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 356 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 128-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2048-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 128-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 2183 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 16-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetInverter.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 294 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 106 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFlashWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" line 586: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 24-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 15-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 7-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 9 | + | Transitions | 84 | + | Inputs | 8 | + | Outputs | 8 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_186_o_equal_234_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 25 | + | Transitions | 299 | + | Inputs | 11 | + | Outputs | 25 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_186_o_equal_234_o (positive) | + | Reset type | synchronous | + | Reset State | 00000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 2-bit subtractor for signal created at line 1428. + Found 2-bit subtractor for signal created at line 1565. + Found 2-bit adder for signal created at line 906. + Found 2-bit adder for signal created at line 1427. + Found 4x3-bit Read Only RAM for signal <_n0832> + Found 32-bit 7-to-1 multiplexer for signal <_n0851> created at line 508. + Found 2-bit comparator greater for signal created at line 528 + Found 1-bit comparator not equal for signal created at line 1430 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 3 Adder/Subtractor(s). + inferred 315 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 14 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 41-bit register for signal . + Found 41-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 84 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Summary: + inferred 16 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFMC150.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 820: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 891: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 956: Output port of the instance is unconnected or connected to loadless signal. + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 33-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 5-bit subtractor for signal created at line 1185. + Found 6-bit subtractor for signal created at line 1188. + Found 3-bit subtractor for signal created at line 1194. + Found 3-bit subtractor for signal created at line 1196. + Found 18-bit subtractor for signal created at line 1400. + Found 2-bit subtractor for signal created at line 1698. + Found 5-bit subtractor for signal <_31_MINUS_spiCDC_dPos_29___d230> created at line 1855. + Found 2-bit subtractor for signal created at line 1920. + Found 5-bit subtractor for signal created at line 1922. + Found 18-bit adder for signal created at line 1183. + Found 2-bit adder for signal created at line 1213. + Found 2-bit adder for signal created at line 1697. + Found 18-bit shifter logical left for signal created at line 708 + Found 4x3-bit Read Only RAM for signal <_n1004> + Found 1-bit 18-to-1 multiplexer for signal created at line 1179. + Found 1-bit 8-to-1 multiplexer for signal created at line 1207. + Found 1-bit 28-to-1 multiplexer for signal created at line 1921. + Found 1-bit 4-to-1 multiplexer for signal <_n0986> created at line 701. + Found 1-bit 4-to-1 multiplexer for signal <_n0996> created at line 700. + Found 2-bit comparator greater for signal created at line 782 + Found 1-bit comparator equal for signal created at line 969 + Found 1-bit comparator equal for signal created at line 976 + Found 1-bit comparator equal for signal created at line 1056 + Found 1-bit comparator not equal for signal created at line 1700 + Found 1-bit comparator equal for signal created at line 1848 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 11 Adder/Subtractor(s). + inferred 367 D-type flip-flop(s). + inferred 6 Comparator(s). + inferred 39 Multiplexer(s). + inferred 1 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v". + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 106. + Found 3-bit comparator greater for signal created at line 105 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 3 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockInverter.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetEither.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncReset0.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetToBool.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 106. + Found 4-bit comparator greater for signal created at line 105 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 4 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkGbeWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1447: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1459: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1478: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1478: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1503: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1517: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 32-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 22-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 113-bit register for signal . + Found 4-bit register for signal . + Found 113-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 112-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 16 | + | Inputs | 5 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_221_o_equal_658_o (positive) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 2-bit subtractor for signal created at line 1793. + Found 22-bit subtractor for signal created at line 2096. + Found 2-bit subtractor for signal created at line 2320. + Found 2-bit subtractor for signal created at line 2964. + Found 5-bit subtractor for signal created at line 2966. + Found 5-bit subtractor for signal created at line 2967. + Found 5-bit subtractor for signal created at line 2968. + Found 5-bit adder for signal created at line 1745. + Found 4-bit adder for signal created at line 1746. + Found 4-bit adder for signal created at line 1748. + Found 2-bit adder for signal created at line 1756. + Found 32-bit adder for signal created at line 2101. + Found 32-bit adder for signal created at line 2108. + Found 32-bit adder for signal created at line 2141. + Found 32-bit adder for signal created at line 2146. + Found 32-bit adder for signal created at line 2211. + Found 32-bit adder for signal created at line 2225. + Found 32-bit adder for signal created at line 2229. + Found 32-bit adder for signal created at line 2262. + Found 2-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2407. + Found 32-bit adder for signal created at line 2423. + Found 5-bit adder for signal created at line 2957. + Found 32-bit adder for signal created at line 2965. + Found 4x3-bit Read Only RAM for signal <_n2211> + Found 4x10-bit Read Only RAM for signal <_n2468> + Found 256x2-bit Read Only RAM for signal <_n2862> + Found 8-bit 15-to-1 multiplexer for signal created at line 3010. + Found 8-bit 15-to-1 multiplexer for signal created at line 3059. + Found 8-bit 15-to-1 multiplexer for signal <_n2355> created at line 1132. + Found 8-bit 15-to-1 multiplexer for signal <_n2384> created at line 3108. + Found 8-bit 15-to-1 multiplexer for signal <_n2415> created at line 1131. + Found 34-bit 32-to-1 multiplexer for signal <_n2479> created at line 1093. + Found 2-bit comparator greater for signal created at line 1245 + Found 4-bit comparator greater for signal created at line 1748 + Found 22-bit comparator greater for signal created at line 2098 + Found 32-bit comparator greater for signal created at line 2200 + Found 1-bit comparator not equal for signal created at line 2322 + Found 8-bit comparator greater for signal created at line 2782 + Found 8-bit comparator equal for signal created at line 2810 + Found 8-bit comparator equal for signal created at line 2875 + Found 8-bit comparator equal for signal created at line 2877 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 3 RAM(s). + inferred 23 Adder/Subtractor(s). + inferred 1539 D-type flip-flop(s). + inferred 9 Comparator(s). + inferred 100 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 45-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 92 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 79-bit register for signal . + Found 79-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 160 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkGMAC.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 606: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 5-bit subtractor for signal created at line 995. + Found 3-bit subtractor for signal created at line 1397. + Found 4-bit adder for signal created at line 971. + Found 12-bit adder for signal created at line 999. + Found 5-bit adder for signal created at line 1003. + Found 8-bit 4-to-1 multiplexer for signal <_n0420> created at line 518. + Found 32-bit comparator not equal for signal created at line 975 + Found 4-bit comparator greater for signal created at line 1136 + Found 12-bit comparator greater for signal created at line 1394 + Found 5-bit comparator greater for signal created at line 1396 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 Adder/Subtractor(s). + inferred 113 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 16 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 8-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkCRC32.v". + Found 32-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 8x10-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 4-bit comparator not equal for signal created at line 126 + Found 4-bit comparator not equal for signal created at line 127 + Found 4-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 48 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 16x10-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 5-bit comparator not equal for signal created at line 126 + Found 5-bit comparator not equal for signal created at line 127 + Found 5-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 56 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 36 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/Counter.v". + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 78. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/Counter.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 78. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 4 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal created at line 50 + Summary: + inferred 1 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 112-bit register for signal . + Found 112-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 226 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkLCDController.v". + Found 2-bit register for signal . + Found 24-bit register for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 5-bit register for signal . + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 15 | + | Inputs | 12 | + | Outputs | 2 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_244_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 61 | + | Inputs | 6 | + | Outputs | 11 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_244_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 140 | + | Transitions | 4472 | + | Inputs | 18 | + | Outputs | 139 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_244_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 00000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 156 | + | Inputs | 11 | + | Outputs | 10 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_244_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 156 | + | Inputs | 11 | + | Outputs | 10 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_244_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 24-bit subtractor for signal created at line 1550. + Found 8-bit adder for signal created at line 1551. + Found 5-bit adder for signal created at line 1594. + Found 4-bit adder for signal created at line 1595. + Found 8-bit 16-to-1 multiplexer for signal <_n1472> created at line 443. + Found 8-bit 16-to-1 multiplexer for signal <_n1503> created at line 443. + Found 5-bit comparator greater for signal created at line 2925 + Found 4-bit comparator greater for signal created at line 2938 + Summary: + inferred 4 Adder/Subtractor(s). + inferred 330 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 11 Multiplexer(s). + inferred 5 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". +WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. + Found 3x81-bit dual-port RAM for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 81-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 81. + Found 2-bit adder for signal created at line 82. + Found 2-bit comparator equal for signal created at line 180 + Found 2-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 88 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 14 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v". + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 709: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 99. + Found 8-bit adder for signal created at line 100. + Found 8-bit adder for signal created at line 101. + Summary: + inferred 3 Adder/Subtractor(s). + inferred 24 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. + Summary: + inferred 8 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" line 254: Output port of the instance is unconnected or connected to loadless signal. + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 4-bit subtractor for signal created at line 484. + Found 5-bit adder for signal created at line 464. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 4-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 20 | + | Inputs | 6 | + | Outputs | 11 | + | Clock | drp_clk (rising_edge) | + | Reset | Reset_n (negative) | + | Reset type | synchronous | + | Reset State | 0011 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit adder for signal created at line 180. + Found 16x32-bit Read Only RAM for signal <_n0098> + Summary: + inferred 1 RAM(s). + inferred 1 Adder/Subtractor(s). + inferred 10 D-type flip-flop(s). + inferred 7 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v". + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 26 | + | Inputs | 8 | + | Outputs | 5 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 00001 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 14 | + | Inputs | 7 | + | Outputs | 4 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 0001 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 5-bit adder for signal created at line 308. + Found 4-bit adder for signal created at line 328. + Found 4-bit adder for signal created at line 360. + Found 5-bit comparator greater for signal created at line 283 + Found 4-bit comparator lessequal for signal created at line 356 + Summary: + inferred 3 Adder/Subtractor(s). + inferred 44 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 7 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_tx_sync_rate_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 25-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 21 | + | Transitions | 40 | + | Inputs | 10 | + | Outputs | 21 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 0000000000000100000000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit adder for signal created at line 179. + Found 8-bit adder for signal created at line 180. + Found 1-bit comparator equal for signal created at line 534 + Summary: + inferred 2 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 19 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 8x8-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 4-bit comparator not equal for signal created at line 126 + Found 4-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 41 D-type flip-flop(s). + inferred 2 Comparator(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/ClockInvToBool.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkWmemiTap.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWmemiTap.v" line 760: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 35-bit register for signal . + Found 35-bit register for signal . + Found 2-bit register for signal . + Found 35-bit register for signal . + Found 35-bit register for signal . + Found 2-bit register for signal . + Found 36-bit register for signal . + Found 36-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 1673. + Found 2-bit subtractor for signal created at line 1675. + Found 2-bit subtractor for signal created at line 1677. + Found 2-bit subtractor for signal created at line 1678. + Found 2-bit subtractor for signal created at line 1683. + Found 2-bit subtractor for signal created at line 1684. + Found 2-bit adder for signal created at line 981. + Found 2-bit adder for signal created at line 993. + Found 2-bit adder for signal created at line 1003. + Found 2-bit adder for signal created at line 1014. + Found 2-bit adder for signal created at line 1025. + Found 2-bit adder for signal created at line 1040. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 1 in block . + Summary: + inferred 12 Adder/Subtractor(s). + inferred 886 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 70 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 6 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 101 + 1024x32-bit dual-port RAM : 5 + 1024x32-bit single-port RAM : 1 + 16x10-bit dual-port RAM : 1 + 16x256-bit single-port Read Only RAM : 1 + 16x32-bit single-port Read Only RAM : 4 + 2048x169-bit dual-port RAM : 2 + 2048x32-bit dual-port RAM : 8 + 256x2-bit single-port Read Only RAM : 1 + 2x128-bit dual-port RAM : 1 + 2x146-bit dual-port RAM : 2 + 2x169-bit dual-port RAM : 3 + 2x177-bit dual-port RAM : 1 + 2x32-bit dual-port RAM : 26 + 2x61-bit dual-port RAM : 2 + 2x64-bit dual-port RAM : 1 + 2x72-bit dual-port RAM : 11 + 3x8-bit dual-port RAM : 1 + 3x81-bit dual-port RAM : 2 + 4x10-bit single-port Read Only RAM : 1 + 4x16-bit single-port Read Only RAM : 3 + 4x2-bit single-port Read Only RAM : 9 + 4x3-bit single-port Read Only RAM : 12 + 64x8-bit single-port Read Only RAM : 1 + 8x10-bit dual-port RAM : 1 + 8x8-bit dual-port RAM : 1 +# Multipliers : 3 + 3x3-bit multiplier : 2 + 4x3-bit multiplier : 1 +# Adders/Subtractors : 834 + 1-bit adder : 120 + 10-bit adder : 1 + 10-bit subtractor : 16 + 11-bit adder : 2 + 12-bit adder : 15 + 12-bit subtractor : 8 + 13-bit adder : 16 + 13-bit subtractor : 2 + 14-bit adder : 7 + 14-bit subtractor : 6 + 16-bit adder : 36 + 16-bit addsub : 8 + 16-bit subtractor : 6 + 17-bit adder : 4 + 17-bit subtractor : 2 + 18-bit adder : 1 + 18-bit subtractor : 1 + 2-bit adder : 45 + 2-bit addsub : 52 + 2-bit subtractor : 80 + 20-bit subtractor : 1 + 22-bit subtractor : 1 + 24-bit adder : 2 + 24-bit subtractor : 1 + 28-bit adder : 3 + 28-bit subtractor : 1 + 3-bit adder : 64 + 3-bit subtractor : 11 + 30-bit adder : 1 + 31-bit adder : 1 + 32-bit adder : 100 + 32-bit subtractor : 3 + 4-bit adder : 31 + 4-bit addsub : 26 + 4-bit subtractor : 35 + 5-bit adder : 46 + 5-bit addsub : 4 + 5-bit subtractor : 21 + 50-bit adder : 2 + 50-bit subtractor : 2 + 6-bit adder : 12 + 6-bit subtractor : 10 + 64-bit subtractor : 1 + 7-bit adder : 3 + 8-bit adder : 23 + 9-bit adder : 1 +# Registers : 5262 + 1-bit register : 3191 + 10-bit register : 17 + 11-bit register : 2 + 112-bit register : 3 + 113-bit register : 2 + 12-bit register : 26 + 128-bit register : 12 + 129-bit register : 4 + 13-bit register : 13 + 130-bit register : 12 + 131-bit register : 8 + 139-bit register : 4 + 14-bit register : 16 + 146-bit register : 14 + 15-bit register : 5 + 153-bit register : 28 + 16-bit register : 106 + 169-bit register : 13 + 17-bit register : 20 + 177-bit register : 3 + 18-bit register : 7 + 182-bit register : 2 + 2-bit register : 309 + 20-bit register : 2 + 2048-bit register : 1 + 22-bit register : 1 + 24-bit register : 4 + 2448-bit register : 22 + 256-bit register : 3 + 27-bit register : 4 + 28-bit register : 24 + 3-bit register : 162 + 30-bit register : 1 + 31-bit register : 1 + 32-bit register : 249 + 33-bit register : 22 + 34-bit register : 41 + 35-bit register : 8 + 36-bit register : 4 + 4-bit register : 393 + 40-bit register : 34 + 41-bit register : 2 + 45-bit register : 5 + 48-bit register : 2 + 5-bit register : 105 + 50-bit register : 5 + 52-bit register : 8 + 56-bit register : 2 + 57-bit register : 1 + 59-bit register : 12 + 6-bit register : 160 + 61-bit register : 8 + 64-bit register : 19 + 65-bit register : 1 + 67-bit register : 6 + 7-bit register : 5 + 72-bit register : 26 + 79-bit register : 2 + 8-bit register : 91 + 81-bit register : 2 + 82-bit register : 2 + 9-bit register : 5 +# Comparators : 507 + 1-bit comparator equal : 91 + 1-bit comparator not equal : 95 + 10-bit comparator greater : 10 + 10-bit comparator lessequal : 6 + 12-bit comparator equal : 2 + 12-bit comparator greater : 3 + 12-bit comparator not equal : 4 + 128-bit comparator not equal : 1 + 13-bit comparator equal : 4 + 13-bit comparator lessequal : 2 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 11 + 16-bit comparator greater : 2 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 3 + 2-bit comparator equal : 74 + 2-bit comparator greater : 23 + 2-bit comparator lessequal : 2 + 2-bit comparator not equal : 10 + 22-bit comparator greater : 1 + 24-bit comparator greater : 2 + 28-bit comparator greater : 4 + 3-bit comparator equal : 8 + 3-bit comparator greater : 30 + 3-bit comparator lessequal : 5 + 32-bit comparator equal : 1 + 32-bit comparator greater : 18 + 32-bit comparator not equal : 2 + 4-bit comparator equal : 5 + 4-bit comparator greater : 4 + 4-bit comparator lessequal : 34 + 4-bit comparator not equal : 3 + 5-bit comparator equal : 2 + 5-bit comparator greater : 9 + 5-bit comparator lessequal : 4 + 5-bit comparator not equal : 2 + 6-bit comparator greater : 2 + 6-bit comparator lessequal : 1 + 7-bit comparator equal : 6 + 7-bit comparator lessequal : 3 + 8-bit comparator equal : 8 + 8-bit comparator greater : 5 +# Multiplexers : 3384 + 1-bit 10-to-1 multiplexer : 1 + 1-bit 16-to-1 multiplexer : 71 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 2-to-1 multiplexer : 1389 + 1-bit 28-to-1 multiplexer : 1 + 1-bit 4-to-1 multiplexer : 24 + 1-bit 64-to-1 multiplexer : 32 + 1-bit 8-to-1 multiplexer : 297 + 10-bit 2-to-1 multiplexer : 43 + 11-bit 2-to-1 multiplexer : 2 + 11-bit 4-to-1 multiplexer : 16 + 113-bit 2-to-1 multiplexer : 1 + 12-bit 2-to-1 multiplexer : 16 + 128-bit 16-to-1 multiplexer : 1 + 128-bit 2-to-1 multiplexer : 12 + 13-bit 2-to-1 multiplexer : 22 + 14-bit 2-to-1 multiplexer : 16 + 15-bit 2-to-1 multiplexer : 1 + 153-bit 16-to-1 multiplexer : 22 + 16-bit 2-to-1 multiplexer : 56 + 17-bit 2-to-1 multiplexer : 3 + 18-bit 2-to-1 multiplexer : 2 + 2-bit 16-to-1 multiplexer : 2 + 2-bit 2-to-1 multiplexer : 104 + 20-bit 2-to-1 multiplexer : 13 + 22-bit 2-to-1 multiplexer : 1 + 24-bit 2-to-1 multiplexer : 8 + 27-bit 2-to-1 multiplexer : 1 + 3-bit 2-to-1 multiplexer : 132 + 3-bit 3-to-1 multiplexer : 1 + 30-bit 2-to-1 multiplexer : 1 + 32-bit 16-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 320 + 32-bit 39-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 12 + 32-bit 7-to-1 multiplexer : 1 + 33-bit 2-to-1 multiplexer : 4 + 34-bit 13-to-1 multiplexer : 1 + 34-bit 15-to-1 multiplexer : 1 + 34-bit 2-to-1 multiplexer : 50 + 34-bit 24-to-1 multiplexer : 2 + 34-bit 32-to-1 multiplexer : 1 + 34-bit 4-to-1 multiplexer : 1 + 34-bit 44-to-1 multiplexer : 2 + 34-bit 8-to-1 multiplexer : 1 + 35-bit 2-to-1 multiplexer : 4 + 36-bit 2-to-1 multiplexer : 2 + 4-bit 2-to-1 multiplexer : 76 + 4-bit 4-to-1 multiplexer : 144 + 40-bit 2-to-1 multiplexer : 2 + 41-bit 2-to-1 multiplexer : 1 + 45-bit 2-to-1 multiplexer : 1 + 5-bit 2-to-1 multiplexer : 146 + 5-bit 8-to-1 multiplexer : 1 + 50-bit 2-to-1 multiplexer : 1 + 52-bit 2-to-1 multiplexer : 4 + 58-bit 2-to-1 multiplexer : 2 + 59-bit 2-to-1 multiplexer : 1 + 6-bit 2-to-1 multiplexer : 86 + 61-bit 2-to-1 multiplexer : 6 + 64-bit 2-to-1 multiplexer : 9 + 65-bit 2-to-1 multiplexer : 3 + 67-bit 2-to-1 multiplexer : 3 + 7-bit 2-to-1 multiplexer : 3 + 72-bit 2-to-1 multiplexer : 48 + 8-bit 15-to-1 multiplexer : 5 + 8-bit 16-to-1 multiplexer : 2 + 8-bit 2-to-1 multiplexer : 131 + 8-bit 4-to-1 multiplexer : 1 + 81-bit 2-to-1 multiplexer : 7 + 82-bit 2-to-1 multiplexer : 2 + 9-bit 2-to-1 multiplexer : 2 +# Logic shifters : 30 + 1-bit shifter logical left : 7 + 18-bit shifter logical left : 1 + 30-bit shifter logical right : 1 + 32-bit shifter logical left : 15 + 7-bit shifter logical left : 6 +# Tristates : 18 + 1-bit tristate buffer : 18 +# FSMs : 31 +# Xors : 77 + 1-bit xor18 : 1 + 1-bit xor2 : 21 + 12-bit xor2 : 2 + 2-bit xor2 : 12 + 22-bit xor2 : 1 + 3-bit xor2 : 27 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 4 + 8-bit xor2 : 1 + +========================================================================= +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 169-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 169-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 32-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 3-word x 8-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 3-word x 8-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 32-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 32-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 72-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 72-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 61-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 61-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 169-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 169-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 146-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 146-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 3-word x 81-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 3-word x 81-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 64-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 64-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 177-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 177-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 128-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 128-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 10-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 16-word x 10-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 8-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 8-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 64-word x 8-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 10-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 256-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block , in block , in block , in block , in block . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block , in block , in block , in block , in block . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 256-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# RAMs : 101 + 1024x32-bit dual-port block RAM : 5 + 1024x32-bit single-port block RAM : 1 + 16x10-bit dual-port distributed RAM : 1 + 16x256-bit single-port distributed Read Only RAM : 1 + 16x32-bit single-port distributed Read Only RAM : 4 + 2048x169-bit dual-port block RAM : 2 + 2048x32-bit dual-port block RAM : 8 + 256x2-bit single-port distributed Read Only RAM : 1 + 2x128-bit dual-port distributed RAM : 1 + 2x146-bit dual-port distributed RAM : 2 + 2x169-bit dual-port distributed RAM : 3 + 2x177-bit dual-port distributed RAM : 1 + 2x32-bit dual-port distributed RAM : 26 + 2x61-bit dual-port distributed RAM : 2 + 2x64-bit dual-port distributed RAM : 1 + 2x72-bit dual-port distributed RAM : 11 + 3x8-bit dual-port distributed RAM : 1 + 3x81-bit dual-port distributed RAM : 2 + 4x10-bit single-port distributed Read Only RAM : 1 + 4x16-bit single-port distributed Read Only RAM : 3 + 4x2-bit single-port distributed Read Only RAM : 9 + 4x3-bit single-port distributed Read Only RAM : 12 + 64x8-bit single-port distributed Read Only RAM : 1 + 8x10-bit dual-port distributed RAM : 1 + 8x8-bit dual-port distributed RAM : 1 +# Multipliers : 3 + 3x3-bit multiplier : 2 + 4x3-bit multiplier : 1 +# Adders/Subtractors : 424 + 1-bit adder : 101 + 10-bit subtractor : 15 + 11-bit adder : 2 + 12-bit adder : 4 + 12-bit subtractor : 8 + 13-bit adder : 16 + 13-bit subtractor : 2 + 14-bit adder : 5 + 14-bit subtractor : 4 + 16-bit adder : 13 + 16-bit subtractor : 4 + 17-bit adder : 4 + 17-bit subtractor : 2 + 18-bit subtractor : 1 + 2-bit adder : 22 + 2-bit adder carry in : 1 + 2-bit subtractor : 72 + 24-bit subtractor : 1 + 28-bit subtractor : 1 + 3-bit adder : 3 + 3-bit adder carry in : 1 + 3-bit subtractor : 8 + 32-bit adder : 40 + 32-bit subtractor : 3 + 4-bit adder : 5 + 4-bit subtractor : 30 + 5-bit adder : 4 + 5-bit addsub : 1 + 5-bit subtractor : 17 + 50-bit subtractor : 2 + 6-bit adder : 11 + 6-bit subtractor : 6 + 64-bit subtractor : 1 + 7-bit adder : 2 + 8-bit adder : 12 +# Adder Trees : 3 + 2-bit / 5-inputs adder tree : 1 + 5-bit / 9-inputs adder tree : 2 +# Counters : 402 + 1-bit up counter : 107 + 10-bit down counter : 1 + 10-bit up counter : 1 + 12-bit up counter : 9 + 16-bit down counter : 2 + 16-bit up counter : 23 + 16-bit updown counter : 8 + 18-bit up counter : 1 + 2-bit down counter : 8 + 2-bit up counter : 16 + 2-bit updown counter : 52 + 20-bit down counter : 1 + 22-bit down counter : 1 + 28-bit up counter : 3 + 3-bit down counter : 3 + 3-bit up counter : 15 + 30-bit up counter : 1 + 32-bit up counter : 57 + 4-bit down counter : 5 + 4-bit up counter : 26 + 4-bit updown counter : 26 + 5-bit down counter : 4 + 5-bit up counter : 12 + 5-bit updown counter : 3 + 6-bit down counter : 4 + 6-bit up counter : 2 + 7-bit up counter : 2 + 8-bit up counter : 8 + 9-bit up counter : 1 +# Accumulators : 40 + 12-bit up accumulator cin : 2 + 14-bit down loadable accumulator : 2 + 14-bit up accumulator : 5 + 16-bit up accumulator : 2 + 3-bit up accumulator cin : 22 + 32-bit up loadable accumulator : 1 + 4-bit up loadable accumulator : 1 + 50-bit up accumulator : 1 + 50-bit up loadable accumulator : 1 + 6-bit up accumulator : 1 + 8-bit up accumulator cin : 1 + 8-bit up loadable accumulator : 1 +# Registers : 40753 + Flip-Flops : 40753 +# Shift Registers : 3498 + 16-bit dynamic shift register : 3498 +# Comparators : 507 + 1-bit comparator equal : 91 + 1-bit comparator not equal : 95 + 10-bit comparator greater : 10 + 10-bit comparator lessequal : 6 + 12-bit comparator equal : 2 + 12-bit comparator greater : 3 + 12-bit comparator not equal : 4 + 128-bit comparator not equal : 1 + 13-bit comparator equal : 4 + 13-bit comparator lessequal : 2 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 11 + 16-bit comparator greater : 2 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 3 + 2-bit comparator equal : 74 + 2-bit comparator greater : 23 + 2-bit comparator lessequal : 2 + 2-bit comparator not equal : 10 + 22-bit comparator greater : 1 + 24-bit comparator greater : 2 + 28-bit comparator greater : 4 + 3-bit comparator equal : 8 + 3-bit comparator greater : 30 + 3-bit comparator lessequal : 5 + 32-bit comparator equal : 1 + 32-bit comparator greater : 18 + 32-bit comparator not equal : 2 + 4-bit comparator equal : 5 + 4-bit comparator greater : 4 + 4-bit comparator lessequal : 34 + 4-bit comparator not equal : 3 + 5-bit comparator equal : 2 + 5-bit comparator greater : 9 + 5-bit comparator lessequal : 4 + 5-bit comparator not equal : 2 + 6-bit comparator greater : 2 + 6-bit comparator lessequal : 1 + 7-bit comparator equal : 6 + 7-bit comparator lessequal : 3 + 8-bit comparator equal : 8 + 8-bit comparator greater : 5 +# Multiplexers : 4724 + 1-bit 10-to-1 multiplexer : 1 + 1-bit 15-to-1 multiplexer : 24 + 1-bit 16-to-1 multiplexer : 87 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 2-to-1 multiplexer : 2709 + 1-bit 28-to-1 multiplexer : 1 + 1-bit 32-to-1 multiplexer : 34 + 1-bit 4-to-1 multiplexer : 312 + 1-bit 64-to-1 multiplexer : 32 + 1-bit 8-to-1 multiplexer : 297 + 10-bit 2-to-1 multiplexer : 38 + 11-bit 2-to-1 multiplexer : 2 + 11-bit 4-to-1 multiplexer : 16 + 113-bit 2-to-1 multiplexer : 1 + 12-bit 2-to-1 multiplexer : 15 + 128-bit 2-to-1 multiplexer : 12 + 13-bit 2-to-1 multiplexer : 22 + 14-bit 2-to-1 multiplexer : 14 + 15-bit 2-to-1 multiplexer : 1 + 16-bit 2-to-1 multiplexer : 40 + 17-bit 2-to-1 multiplexer : 3 + 18-bit 2-to-1 multiplexer : 2 + 2-bit 2-to-1 multiplexer : 92 + 20-bit 2-to-1 multiplexer : 13 + 24-bit 2-to-1 multiplexer : 8 + 27-bit 2-to-1 multiplexer : 1 + 3-bit 2-to-1 multiplexer : 123 + 3-bit 3-to-1 multiplexer : 1 + 32-bit 16-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 287 + 32-bit 39-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 12 + 32-bit 7-to-1 multiplexer : 1 + 33-bit 2-to-1 multiplexer : 4 + 34-bit 13-to-1 multiplexer : 1 + 34-bit 15-to-1 multiplexer : 1 + 34-bit 2-to-1 multiplexer : 38 + 34-bit 24-to-1 multiplexer : 2 + 34-bit 4-to-1 multiplexer : 1 + 34-bit 44-to-1 multiplexer : 2 + 34-bit 8-to-1 multiplexer : 1 + 35-bit 2-to-1 multiplexer : 4 + 36-bit 2-to-1 multiplexer : 1 + 4-bit 2-to-1 multiplexer : 56 + 4-bit 4-to-1 multiplexer : 72 + 40-bit 2-to-1 multiplexer : 2 + 41-bit 2-to-1 multiplexer : 1 + 45-bit 2-to-1 multiplexer : 1 + 5-bit 2-to-1 multiplexer : 31 + 5-bit 8-to-1 multiplexer : 1 + 52-bit 2-to-1 multiplexer : 3 + 58-bit 2-to-1 multiplexer : 2 + 59-bit 2-to-1 multiplexer : 1 + 6-bit 2-to-1 multiplexer : 84 + 61-bit 2-to-1 multiplexer : 6 + 64-bit 2-to-1 multiplexer : 9 + 65-bit 2-to-1 multiplexer : 3 + 67-bit 2-to-1 multiplexer : 3 + 7-bit 2-to-1 multiplexer : 3 + 72-bit 2-to-1 multiplexer : 48 + 8-bit 15-to-1 multiplexer : 2 + 8-bit 2-to-1 multiplexer : 125 + 8-bit 4-to-1 multiplexer : 1 + 81-bit 2-to-1 multiplexer : 6 + 82-bit 2-to-1 multiplexer : 2 + 9-bit 2-to-1 multiplexer : 2 +# Logic shifters : 30 + 1-bit shifter logical left : 7 + 18-bit shifter logical left : 1 + 30-bit shifter logical right : 1 + 32-bit shifter logical left : 15 + 7-bit shifter logical left : 6 +# FSMs : 31 +# Xors : 77 + 1-bit xor18 : 1 + 1-bit xor2 : 21 + 12-bit xor2 : 2 + 2-bit xor2 : 12 + 22-bit xor2 : 1 + 3-bit xor2 : 27 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 4 + 8-bit xor2 : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +------------------- + State | Encoding +------------------- + 00001 | 000 + 00010 | 001 + 00100 | 010 + 01000 | 011 + 10000 | 100 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 0001 | 00 + 0010 | 01 + 0100 | 11 + 1000 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 0011 | 000 + 0110 | 001 + 0111 | 011 + 0001 | 010 + 1000 | 110 + 1001 | 111 + 0010 | 101 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------------------------------------- + State | Encoding +---------------------------------------------------- + 0000000000000100000000000 | 000000000000000000001 + 0010000000000000000000000 | 000000000000000000010 + 0000100000000000000000000 | 000000000000000000100 + 0100000000000000000000000 | 000000000000000001000 + 1000000000000000000000000 | 000000000000000010000 + 0000000010000000000000000 | 000000000000000100000 + 0000000100000000000000000 | 000000000000001000000 + 0000000000000000000000010 | 000000000000010000000 + 0000001000000000000000000 | 000000000000100000000 + 0000000000000000000000001 | 000000000001000000000 + 0000000000010000000000000 | 000000000010000000000 + 0000000000000000010000000 | 000000000100000000000 + 0000010000000000000000000 | 000000001000000000000 + 0000000000000000000000100 | 000000010000000000000 + 0000000000000000000001000 | 000000100000000000000 + 0000000000000000001000000 | 000001000000000000000 + 0000000000100000000000000 | 000010000000000000000 + 0001000000000000000000000 | 000100000000000000000 + 0000000000000000100000000 | 001000000000000000000 + 0000000000000001000000000 | 010000000000000000000 + 0000000000000010000000000 | 100000000000000000000 +---------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 10 | 01 + 01 | 11 +------------------- +INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . +INFO:Xst:2146 - In block , Accumulator are equivalent, XST will keep only . +INFO:Xst:2146 - In block , Accumulator are equivalent, XST will keep only . +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------ + State | Encoding +------------------------------------ + 00000 | 0000000000000000000000001 + 11000 | 0000000000000000000000010 + 00001 | 0000000000000000000000100 + 00010 | 0000000000000000000001000 + 00011 | 0000000000000000000010000 + 00100 | 0000000000000000000100000 + 00111 | 0000000000000000001000000 + 01000 | 0000000000000000010000000 + 01001 | 0000000000000000100000000 + 01010 | 0000000000000001000000000 + 01011 | 0000000000000010000000000 + 01100 | 0000000000000100000000000 + 01111 | 0000000000001000000000000 + 10000 | 0000000000010000000000000 + 10001 | 0000000000100000000000000 + 10010 | 0000000001000000000000000 + 10011 | 0000000010000000000000000 + 10100 | 0000000100000000000000000 + 10111 | 0000001000000000000000000 + 00101 | 0000010000000000000000000 + 00110 | 0000100000000000000000000 + 01101 | 0001000000000000000000000 + 01110 | 0010000000000000000000000 + 10101 | 0100000000000000000000000 + 10110 | 1000000000000000000000000 +------------------------------------ +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +-------------------- + State | Encoding +-------------------- + 0000 | 000000001 + 0111 | 000000010 + 0001 | 000000100 + 0010 | 000001000 + 0101 | 000010000 + 0110 | 000100000 + 0011 | 001000000 + 0100 | 010000000 + 1010 | 100000000 +-------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------- + State | Encoding +------------------- + 000 | 0000001 + 001 | 0000010 + 010 | 0000100 + 011 | 0001000 + 100 | 0010000 + 101 | 0100000 + 110 | 1000000 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------------------- + State | Encoding +------------------------------------------------- + 000000 | 0000000000000000000000000000000000001 + 000001 | 0000000000000000000000000000000000010 + 000010 | 0000000000000000000000000000000000100 + 000011 | 0000000000000000000000000000000001000 + 000100 | 0000000000000000000000000000000010000 + 010110 | 0000000000000000000000000000000100000 + 000101 | 0000000000000000000000000000001000000 + 000110 | 0000000000000000000000000000010000000 + 000111 | 0000000000000000000000000000100000000 + 001000 | 0000000000000000000000000001000000000 + 001001 | 0000000000000000000000000010000000000 + 001010 | 0000000000000000000000000100000000000 + 001011 | 0000000000000000000000001000000000000 + 001100 | 0000000000000000000000010000000000000 + 001101 | 0000000000000000000000100000000000000 + 010101 | 0000000000000000000001000000000000000 + 011010 | 0000000000000000000010000000000000000 + 011001 | 0000000000000000000100000000000000000 + 001111 | 0000000000000000001000000000000000000 + 010010 | 0000000000000000010000000000000000000 + 010100 | 0000000000000000100000000000000000000 + 010011 | 0000000000000001000000000000000000000 + 010111 | 0000000000000010000000000000000000000 + 011111 | 0000000000000100000000000000000000000 + 011000 | 0000000000001000000000000000000000000 + 011011 | 0000000000010000000000000000000000000 + 011100 | 0000000000100000000000000000000000000 + 010001 | 0000000001000000000000000000000000000 + 101000 | 0000000010000000000000000000000000000 + 001110 | 0000000100000000000000000000000000000 + 100011 | 0000001000000000000000000000000000000 + 101010 | 0000010000000000000000000000000000000 + 010000 | 0000100000000000000000000000000000000 + 011110 | unreached + 100000 | 0001000000000000000000000000000000000 + 100001 | 0010000000000000000000000000000000000 + 100010 | 0100000000000000000000000000000000000 + 100101 | unreached + 100100 | unreached + 100111 | unreached + 011101 | unreached + 101001 | 1000000000000000000000000000000000000 +------------------------------------------------- +INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 0000 | 0000 + 0001 | 0001 + 0100 | 0100 + 0011 | 0011 + 1000 | 1000 + 0111 | 0111 + 0110 | 0110 + 0101 | 0101 + 0010 | 0010 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +------------------- + State | Encoding +------------------- + 000 | 000 + 001 | 001 + 010 | 010 + 110 | 011 + 100 | 100 + 101 | 101 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 00000 | 00000 + 00001 | 00001 + 00010 | 00010 + 00011 | 00011 + 01100 | 01100 + 01011 | 01011 + 00100 | 00100 + 00111 | 00111 + 00101 | 00101 + 01101 | 01101 + 00110 | 00110 + 01000 | 01000 + 10010 | 10010 + 01010 | 01010 + 01111 | 01111 + 01110 | 01110 + 10000 | 10000 + 01001 | 01001 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 0000 | 0000 + 0001 | 0001 + 0010 | 0010 + 0011 | 0011 + 0100 | 0100 + 0110 | 0110 + 0101 | 0101 + 0111 | 0111 + 1000 | 1000 + 1001 | 1001 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 000 | 000 + 001 | 001 + 010 | 010 + 011 | 011 + 100 | 100 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1010 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0100 | 00000100000 + 0101 | 00001000000 + 0110 | 00010000000 + 0111 | 00100000000 + 1000 | 01000000000 + 1001 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. 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00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00111101 | 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 01000001 | 01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 10101010 | 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------------------------------------------------------------------------------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1001 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 0100 | 00100000000 + 1000 | 01000000000 + 1010 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1001 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 0100 | 00100000000 + 1000 | 01000000000 + 1010 | 10000000000 +---------------------- +INFO:Xst:1901 - Instance use_ramb36.ramb36 in unit use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 +INFO:Xst:1901 - Instance GEN2_LINK.pipe_clk_bufgmux in unit pcie_clocking_v6 of type BUFGMUX has been replaced by BUFGCTRL +INFO:Xst:1901 - Instance gmii_rxc_dly in unit mkGMAC of type IODELAY has been replaced by IODELAYE1 +INFO:Xst:1901 - Instance gmii_rx_clk in unit mkGMAC of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[0].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[1].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[2].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[3].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[4].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[5].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[6].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[7].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:638 - in unit mkLCDController Conflict on KEEP property on signal line1_fsm_state_mkFSMstate_FSM_FFd1 and line2_fsm_state_mkFSMstate_FSM_FFd1 line2_fsm_state_mkFSMstate_FSM_FFd1 signal will be lost. +WARNING:Xst:638 - in unit mkLCDController Conflict on KEEP property on signal line1_fsm_state_mkFSMstate_FSM_FFd1 and line2_fsm_state_mkFSMstate_FSM_FFd1 line2_fsm_state_mkFSMstate_FSM_FFd1 signal will be lost. + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block fpgaTop, actual ratio is 3. +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rst_final has been replicated 2 time(s) +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/rst_final has been replicated 2 time(s) +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_cmd0/app_rdy_r has been replicated 1 time(s) + +Final Macro Processing ... + +Processing Unit : + Found 10-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 16-bit shift register was found for signal and currently occupies 16 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 33-bit shift register was found for signal and currently occupies 33 logic cells (16 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 31-bit shift register was found for signal and currently occupies 31 logic cells (15 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 3-bit shift register for signal . +Unit processed. + +Processing Unit : + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 3-bit shift register for signal . + Found 16-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 5-bit shift register was found for signal and currently occupies 5 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 4-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 8-bit shift register was found for signal and currently occupies 8 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 10-bit shift register for signal . +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 35686 + Flip-Flops : 35686 +# Shift Registers : 44 + 10-bit shift register : 2 + 16-bit shift register : 5 + 2-bit shift register : 34 + 3-bit shift register : 2 + 4-bit shift register : 1 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Design Summary * +========================================================================= + +Top Level Output File Name : fpgaTop.ngc + +Primitive and Black Box Usage: +------------------------------ +# BELS : 48547 +# BUF : 102 +# GND : 221 +# INV : 1326 +# LUT1 : 2527 +# LUT2 : 3357 +# LUT3 : 4458 +# LUT4 : 4281 +# LUT5 : 7242 +# LUT6 : 14866 +# MULT_AND : 90 +# MUXCY : 4705 +# MUXF7 : 714 +# MUXF8 : 100 +# VCC : 188 +# XORCY : 4370 +# FlipFlops/Latches : 35746 +# FD : 7557 +# FD_1 : 432 +# FDC : 480 +# FDCE : 1342 +# FDE : 11196 +# FDP : 146 +# FDPE : 59 +# FDR : 2139 +# FDRE : 9957 +# FDS : 112 +# FDSE : 2314 +# ODDR : 12 +# RAMS : 829 +# RAM32M : 432 +# RAM32X1D : 68 +# RAM64X1D : 288 +# RAMB18E1 : 3 +# RAMB36E1 : 38 +# Shift Registers : 2977 +# SRL16E : 5 +# SRLC16E : 2970 +# SRLC32E : 2 +# Clock Buffers : 12 +# BUFG : 11 +# BUFGCTRL : 1 +# IO Buffers : 232 +# IBUF : 29 +# IBUFDS : 2 +# IBUFDS_GTXE1 : 2 +# IOBUF : 81 +# IOBUFDS_DIFF_OUT : 8 +# OBUF : 109 +# OBUFDS : 1 +# GigabitIOs : 4 +# GTXE1 : 4 +# Others : 302 +# BUFIODQS : 9 +# BUFR : 3 +# DNA_PORT : 1 +# IDELAYCTRL : 1 +# IODELAYE1 : 91 +# ISERDESE1 : 72 +# MMCM_ADV : 2 +# OSERDESE1 : 122 +# PCIE_2_0 : 1 + +Device utilization summary: +--------------------------- + +Selected Device : 6vlx240tff1156-1 + + +Slice Logic Utilization: + Number of Slice Registers: 35746 out of 301440 11% + Number of Slice LUTs: 43474 out of 150720 28% + Number used as Logic: 38057 out of 150720 25% + Number used as Memory: 5417 out of 58400 9% + Number used as RAM: 2440 + Number used as SRL: 2977 + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 58940 + Number with an unused Flip Flop: 23194 out of 58940 39% + Number with an unused LUT: 15466 out of 58940 26% + Number of fully used LUT-FF pairs: 20280 out of 58940 34% + Number of unique control sets: 2326 + +IO Utilization: + Number of IOs: 242 + Number of bonded IOBs: 237 out of 600 39% + +Specific Feature Utilization: + Number of Block RAM/FIFO: 40 out of 416 9% + Number using Block RAM only: 40 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +Timing Report + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | MMCM_ADV:CLKOUT0 | 550 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | MMCM_ADV:CLKOUT1 | 29533 | +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 | BUFGCTRL | 418 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDWE | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i)| 1 | +sys1_clkp | IBUF+IBUFDS_GTXE1+BUFG | 119 | +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | BUFR | 134 | +sys0_clkp | MMCM_ADV:CLKOUT1 | 6206 | +flp_cdc_clk_p | IBUFDS+BUFG | 20 | +ftop/fmc150/spiCDC_cd/cntr_2 | BUFG | 76 | +ftop/fmc150/spiDAC_cd/cntr_3 | BUFG | 31 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| BUFR | 928 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| BUFR | 1542 | +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + +Asynchronous Control Signals Information: +---------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/ctop/app/appW2/wmiM0_MDataValid(ftop/ctop/app/appW2/XST_GND:G) | NONE(ftop/ctop/app/appW2/respF_memory/Mram_RAM10) | 4 | +ftop/ctop/app/appW4/wmiM0_MAddrSpace(ftop/ctop/app/appW4/XST_GND:G) | NONE(ftop/ctop/app/appW4/respF_memory/Mram_RAM10) | 4 | +ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n_INV_4624_o(ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n_INV_4624_o1_INV_0:O) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i) | 3 | +ftop/ctop/app/appW2/respF_pwEnqueue_whas(ftop/ctop/app/appW2/respF_pwEnqueue_whas1:O) | NONE(ftop/ctop/app/appW2/respF_memory/Mram_RAM10) | 2 | +ftop/ctop/app/appW4/respF_pwEnqueue_whas(ftop/ctop/app/appW4/respF_pwEnqueue_whas1:O) | NONE(ftop/ctop/app/appW4/respF_memory/Mram_RAM10) | 2 | +ftop/ctop/inf/cp/rom_memory/DO<16>(ftop/ctop/inf/cp/rom_memory/XST_GND:G) | NONE(ftop/ctop/inf/cp/rom_memory/Mram_RAM1) | 2 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/N0(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/XST_VCC:P) | NONE(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync) | 2 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_0(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_0:Q) | NONE(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync) | 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/gbe0/gmac/CLK_GATE_rxclkBnd(ftop/gbe0/gmac/XST_VCC:P) | NONE(ftop/gbe0/gmac/rxClk_BUFR) | 1 | +ftop/gbe0/gmac/txRS_txER(ftop/gbe0/gmac/XST_GND:G) | NONE(ftop/gbe0/gmac/rxClk_BUFR) | 1 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -1 + + Minimum period: 4.758ns (Maximum Frequency: 210.172MHz) + Minimum input arrival time before clock: 1.793ns + Maximum output required time after clock: 1.923ns + Maximum combinational path delay: 0.538ns + +Timing Details: +--------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Clock period: 4.120ns (frequency: 242.729MHz) + Total number of paths / destination ports: 10946148 / 82351 +------------------------------------------------------------------------- +Delay: 8.240ns (Levels of Logic = 12) + Source: ftop/ctop/inf/cp/cpReq_26 (FF) + Destination: ftop/ctop/inf/cp/cpReq_0 (FF) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + + Data Path: ftop/ctop/inf/cp/cpReq_26 to ftop/ctop/inf/cp/cpReq_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 16 0.375 0.679 cpReq_26 (cpReq_26) + LUT3:I0->O 47 0.068 0.573 Msub_wn___1__h76499_xor<2>11 (wn___1__h76499<2>) + LUT6:I5->O 62 0.068 0.558 Mmux__theResult_____1__h7573931 (_theResult_____1__h75739<2>) + MUXF7:S->O 1 0.267 0.000 Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 (Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7) + MUXF8:I0->O 2 0.175 0.423 Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 (CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793) + LUT6:I5->O 99 0.068 0.584 _n13601<34>21 (_n13601<34>2) + LUT6:I5->O 14 0.068 0.860 WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T1 (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T) + LUT6:I1->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead1 (WILL_FIRE_RL_completeWorkerRead1) + LUT6:I5->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead5 (WILL_FIRE_RL_completeWorkerRead5) + LUT6:I5->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerRead27_SW0 (N480) + LUT6:I5->O 19 0.068 0.536 WILL_FIRE_RL_completeWorkerRead31 (WILL_FIRE_RL_completeWorkerRead) + LUT3:I2->O 7 0.068 0.457 cpRespF_ENQ1 (cpRespF_ENQ) + LUT5:I4->O 64 0.068 0.559 cpReq_EN (cpReq_EN) + FDRE:CE 0.263 cpReq_0 + ---------------------------------------- + Total 8.240ns (1.760ns logic, 6.480ns route) + (21.4% logic, 78.6% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125' + Clock period: 3.724ns (frequency: 268.528MHz) + Total number of paths / destination ports: 4781 / 823 +------------------------------------------------------------------------- +Delay: 3.724ns (Levels of Logic = 5) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/state_FSM_FFd5 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/waitcounter_4 (FF) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 rising + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 rising + + Data Path: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/state_FSM_FFd5 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/waitcounter_4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 4 0.375 0.798 state_FSM_FFd5 (state_FSM_FFd5) + LUT6:I0->O 1 0.068 0.491 nextwaitcounter2<7>112 (nextwaitcounter2<7>112) + LUT6:I4->O 2 0.068 0.423 nextwaitcounter2<7>113 (nextwaitcounter2<7>11) + LUT4:I3->O 2 0.068 0.423 nextwaitcounter2<1>31 (nextwaitcounter2<1>3) + LUT6:I5->O 14 0.068 0.863 nextwaitcounter2<0>11 (nextwaitcounter2<0>1) + LUT6:I0->O 1 0.068 0.000 nextwaitcounter<4>1 (nextwaitcounter<4>) + FDR:D 0.011 waitcounter_4 + ---------------------------------------- + Total 3.724ns (0.726ns logic, 2.998ns route) + (19.5% logic, 80.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys1_clkp' + Clock period: 3.831ns (frequency: 261.028MHz) + Total number of paths / destination ports: 6108 / 281 +------------------------------------------------------------------------- +Delay: 3.831ns (Levels of Logic = 6) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_5 (FF) + Source Clock: sys1_clkp rising + Destination Clock: sys1_clkp rising + + Data Path: ftop/gbe0/gmac/txRS_ifgCnt_value_2 to ftop/gbe0/gmac/txRS_crc/rRemainder_5 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 4 0.375 0.795 txRS_ifgCnt_value_2 (txRS_ifgCnt_value_2) + LUT6:I1->O 12 0.068 0.563 WILL_FIRE_RL_txRS_egress_SOF31 (Mmux_txRS_txData_D_IN122) + LUT6:I4->O 8 0.068 0.463 Mmux_txRS_crc_add_data11 (Mmux_txRS_crc_add_data11) + LUT2:I1->O 15 0.068 0.867 Mmux_txRS_crc_add_data21 (txRS_crc_add_data<1>) + begin scope: 'ftop/gbe0/gmac/txRS_crc:add_data<1>' + LUT6:I1->O 1 0.068 0.417 rRemainder$D_IN<5>1 (rRemainder$D_IN<5>1) + LUT5:I4->O 1 0.068 0.000 rRemainder$D_IN<5>3 (rRemainder$D_IN<5>) + FDSE:D 0.011 rRemainder_5 + ---------------------------------------- + Total 3.831ns (0.726ns logic, 3.105ns route) + (19.0% logic, 81.0% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT' + Clock period: 3.576ns (frequency: 279.622MHz) + Total number of paths / destination ports: 2172 / 314 +------------------------------------------------------------------------- +Delay: 3.576ns (Levels of Logic = 4) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Source Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + Destination Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + + Data Path: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 18 0.375 0.603 dSyncReg2 (dSyncReg2) + end scope: 'ftop/gbe0/gmac/rxRS_rxOperateS:dD_OUT' + LUT3:I1->O 49 0.068 0.931 _n0454_inv211 (WILL_FIRE_RL_rxRS_ingress_advance) + LUT6:I1->O 2 0.068 0.781 _n0454_inv2 (_n0454_inv2) + LUT5:I0->O 4 0.068 0.419 _n0454_inv1 (_n0454_inv) + FDRE:CE 0.263 rxRS_preambleCnt_value_0 + ---------------------------------------- + Total 3.576ns (0.842ns logic, 2.734ns route) + (23.5% logic, 76.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys0_clkp' + Clock period: 4.758ns (frequency: 210.172MHz) + Total number of paths / destination ports: 166460 / 12719 +------------------------------------------------------------------------- +Delay: 4.758ns (Levels of Logic = 13) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0/io_config_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/io_config_valid_r_lcl (FF) + Source Clock: sys0_clkp rising + Destination Clock: sys0_clkp rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0/io_config_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/io_config_valid_r_lcl + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 2 0.375 0.784 io_config_r_1 (io_config_r_1) + LUT6:I0->O 1 0.068 0.417 Mmux_io_config_ns41 (Mmux_io_config_ns4) + LUT6:I5->O 1 0.068 0.417 Mmux_io_config_ns42 (Mmux_io_config_ns41) + LUT5:I4->O 20 0.068 0.542 Mmux_io_config_ns43 (dfi_odt_nom1<0>) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0:io_config<1>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0:io_config<1>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0:io_config<1>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0:io_config<1>' + LUT4:I3->O 4 0.068 0.511 inhbt_wr_config11 (inhbt_wr_config) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0:inhbt_wr_config' + LUT6:I4->O 6 0.068 0.808 rtc (rtc) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0:rtc' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0:rtc' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0:rtc<2>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0:rtc<2>' + LUT6:I1->O 1 0.068 0.417 io_config_valid_ns_norst2 (io_config_valid_ns_norst2) + LUT2:I1->O 1 0.068 0.000 io_config_valid_ns_norst3 (io_config_valid_ns_norst) + FDR:D 0.011 io_config_valid_r_lcl + ---------------------------------------- + Total 4.758ns (0.862ns logic, 3.896ns route) + (18.1% logic, 81.9% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'flp_cdc_clk_p' + Clock period: 4.676ns (frequency: 213.858MHz) + Total number of paths / destination ports: 12407 / 37 +------------------------------------------------------------------------- +Delay: 4.676ns (Levels of Logic = 7) + Source: ftop/fmc150/fcCdc_grayCounter_rsCounter_16 (FF) + Destination: ftop/fmc150/fcCdc_grayCounter_rsCounter_0 (FF) + Source Clock: flp_cdc_clk_p rising + Destination Clock: flp_cdc_clk_p rising + + Data Path: ftop/fmc150/fcCdc_grayCounter_rsCounter_16 to ftop/fmc150/fcCdc_grayCounter_rsCounter_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 5 0.375 0.802 fcCdc_grayCounter_rsCounter_16 (fcCdc_grayCounter_rsCounter_16) + LUT6:I1->O 3 0.068 0.595 Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>2 (Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>1) + LUT3:I0->O 14 0.068 0.502 Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>4 (fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454) + LUT6:I5->O 13 0.068 0.571 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d49014 (IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490<0>) + LUT6:I4->O 1 0.068 0.638 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o_91 (Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o_91) + LUT6:I2->O 1 0.068 0.000 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o_4 (Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o_4) + MUXF7:I0->O 18 0.245 0.529 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o_2_f7 (IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_184_o_Mux_53_o) + LUT6:I5->O 1 0.068 0.000 Mmux_MUX_fcCdc_grayCounter_rsCounter_write_1__VAL_181 (MUX_fcCdc_grayCounter_rsCounter_write_1__VAL_1<16>) + FDC:D 0.011 fcCdc_grayCounter_rsCounter_16 + ---------------------------------------- + Total 4.676ns (1.039ns logic, 3.637ns route) + (22.2% logic, 77.8% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Clock period: 3.708ns (frequency: 269.687MHz) + Total number of paths / destination ports: 745 / 184 +------------------------------------------------------------------------- +Delay: 3.708ns (Levels of Logic = 7) + Source: ftop/fmc150/spiCDC_slowReset/reset_hold_1 (FF) + Destination: ftop/fmc150/spiCDC_reqF_head_wrapped (FF) + Source Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + Destination Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + + Data Path: ftop/fmc150/spiCDC_slowReset/reset_hold_1 to ftop/fmc150/spiCDC_reqF_head_wrapped + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 9 0.375 0.470 reset_hold_1 (reset_hold_1) + end scope: 'ftop/fmc150/spiCDC_slowReset:OUT_RST' + begin scope: 'ftop/fmc150/spiCDC_reqF_dCombinedReset:A_RST' + LUT2:I1->O 2 0.068 0.405 RST_OUT1 (RST_OUT) + end scope: 'ftop/fmc150/spiCDC_reqF_dCombinedReset:RST_OUT' + begin scope: 'ftop/fmc150/spiCDC_reqF_dInReset:RST' + INV:I->O 8 0.086 0.824 VAL1_INV_0 (VAL) + end scope: 'ftop/fmc150/spiCDC_reqF_dInReset:VAL' + LUT6:I0->O 4 0.068 0.511 MUX_spiCDC_rcv_d_write_1__SEL_21 (MUX_spiCDC_rcv_d_write_1__SEL_2) + LUT4:I2->O 1 0.068 0.399 Reset_OR_DriverANDClockEnable91 (Reset_OR_DriverANDClockEnable9) + FDRE:R 0.434 spiCDC_reqF_head_wrapped + ---------------------------------------- + Total 3.708ns (1.099ns logic, 2.609ns route) + (29.6% logic, 70.4% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Clock period: 3.785ns (frequency: 264.201MHz) + Total number of paths / destination ports: 336 / 69 +------------------------------------------------------------------------- +Delay: 3.785ns (Levels of Logic = 8) + Source: ftop/fmc150/spiDAC_slowReset/reset_hold_1 (FF) + Destination: ftop/fmc150/spiDAC_reqF_head_wrapped (FF) + Source Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + Destination Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + + Data Path: ftop/fmc150/spiDAC_slowReset/reset_hold_1 to ftop/fmc150/spiDAC_reqF_head_wrapped + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 6 0.375 0.450 reset_hold_1 (reset_hold_1) + end scope: 'ftop/fmc150/spiDAC_slowReset:OUT_RST' + begin scope: 'ftop/fmc150/spiDAC_reqF_dCombinedReset:A_RST' + LUT2:I1->O 2 0.068 0.405 RST_OUT1 (RST_OUT) + end scope: 'ftop/fmc150/spiDAC_reqF_dCombinedReset:RST_OUT' + begin scope: 'ftop/fmc150/spiDAC_reqF_dInReset:RST' + INV:I->O 5 0.086 0.444 VAL1_INV_0 (VAL) + end scope: 'ftop/fmc150/spiDAC_reqF_dInReset:VAL' + LUT6:I5->O 13 0.068 0.497 WILL_FIRE_RL_spiDAC_doxcv_d1 (WILL_FIRE_RL_spiDAC_doxcv_d) + LUT5:I4->O 2 0.068 0.423 spiDAC_reqF_head_wrapped_EN1 (spiDAC_reqF_head_wrapped_EN) + LUT3:I2->O 1 0.068 0.399 Reset_OR_DriverANDClockEnable101 (Reset_OR_DriverANDClockEnable10) + FDRE:R 0.434 spiDAC_reqF_head_wrapped + ---------------------------------------- + Total 3.785ns (1.167ns logic, 2.618ns route) + (30.8% logic, 69.2% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Clock period: 2.088ns (frequency: 478.927MHz) + Total number of paths / destination ports: 2069 / 1093 +------------------------------------------------------------------------- +Delay: 2.088ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/iserdes_q_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/iserdes_q_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.375 0.417 iserdes_q_r_2 (iserdes_q_r_2) + LUT3:I2->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 2.088ns (0.590ns logic, 1.498ns route) + (28.3% logic, 71.7% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Clock period: 2.088ns (frequency: 478.927MHz) + Total number of paths / destination ports: 3439 / 1815 +------------------------------------------------------------------------- +Delay: 2.088ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/iserdes_q_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/iserdes_q_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.375 0.417 iserdes_q_r_2 (iserdes_q_r_2) + LUT3:I2->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 2.088ns (0.590ns logic, 1.498ns route) + (28.3% logic, 71.7% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Total number of paths / destination ports: 25 / 25 +------------------------------------------------------------------------- +Offset: 1.457ns (Levels of Logic = 4) + Source: pci0_reset_n (PAD) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/reg_count_23_16_0 (FF) + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising + + Data Path: pci0_reset_n to ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/reg_count_23_16_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 pci0_reset_n_IBUF (pci0_reset_n_IBUF) + begin scope: 'ftop:pci0_rstn' + begin scope: 'ftop/pciw_pci0_pcie_ep:sys_reset_n' + begin scope: 'ftop/pciw_pci0_pcie_ep/ep:sys_reset_n' + begin scope: 'ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i:sys_reset_n' + INV:I->O 22 0.086 0.535 sys_reset_n_inv1_INV_0 (sys_reset_n_inv) + FDCE:CLR 0.434 reg_count_23_16_0 + ---------------------------------------- + Total 1.457ns (0.523ns logic, 0.934ns route) + (35.9% logic, 64.1% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT' + Total number of paths / destination ports: 10 / 10 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 3) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT rising + + Data Path: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 gmii_rxd_0_IBUF (gmii_rxd_0_IBUF) + begin scope: 'ftop:gmii_rx_rxd_i<0>' + begin scope: 'ftop/gbe0:gmii_rx_rxd_i<0>' + begin scope: 'ftop/gbe0/gmac:gmii_rx_rxd_i<0>' + FD:D 0.011 rxRS_rxData_0 + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'sys0_clkp' + Total number of paths / destination ports: 75 / 75 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 3) + Source: ppsExtIn (PAD) + Destination: ftop/ctop/inf/cp/timeServ_ppsExtSync_d1 (FF) + Destination Clock: sys0_clkp rising + + Data Path: ppsExtIn to ftop/ctop/inf/cp/timeServ_ppsExtSync_d1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 ppsExtIn_IBUF (ppsExtIn_IBUF) + begin scope: 'ftop:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop/inf:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop/inf/cp:gps_ppsSyncIn_x' + FDR:D 0.011 timeServ_ppsExtSync_d1 + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 2) + Source: flp_cdc_sdi (PAD) + Destination: ftop/fmc150/spiCDC_sdiP (FF) + Destination Clock: ftop/fmc150/spiCDC_cd/cntr_2 falling + + Data Path: flp_cdc_sdi to ftop/fmc150/spiCDC_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 flp_cdc_sdi_IBUF (flp_cdc_sdi_IBUF) + begin scope: 'ftop:flpCDC_sdi_arg' + begin scope: 'ftop/fmc150:padsCDC_sdi_arg' + FD:D 0.011 spiCDC_sdiP + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 2) + Source: flp_dac_sdi (PAD) + Destination: ftop/fmc150/spiDAC_sdiP (FF) + Destination Clock: ftop/fmc150/spiDAC_cd/cntr_3 falling + + Data Path: flp_dac_sdi to ftop/fmc150/spiDAC_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 flp_dac_sdi_IBUF (flp_dac_sdi_IBUF) + begin scope: 'ftop:flpDAC_sdi_arg' + begin scope: 'ftop/fmc150:padsDAC_sdi_arg' + FD:D 0.011 spiDAC_sdiP + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Total number of paths / destination ports: 1665 / 675 +------------------------------------------------------------------------- +Offset: 1.793ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ISERDESE1:Q3 2 0.000 0.497 u_iserdes_dqs_p (iserdes_q<2>) + LUT3:I1->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 1.793ns (0.215ns logic, 1.578ns route) + (12.0% logic, 88.0% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Total number of paths / destination ports: 999 / 405 +------------------------------------------------------------------------- +Offset: 1.793ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ISERDESE1:Q3 2 0.000 0.497 u_iserdes_dqs_p (iserdes_q<2>) + LUT3:I1->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 1.793ns (0.215ns logic, 1.578ns route) + (12.0% logic, 88.0% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Total number of paths / destination ports: 79 / 62 +------------------------------------------------------------------------- +Offset: 1.360ns (Levels of Logic = 4) + Source: ftop/flash0/flashC_tsOE (FF) + Destination: flash_io_dq<15> (PAD) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + + Data Path: ftop/flash0/flashC_tsOE to flash_io_dq<15> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.375 0.399 flashC_tsOE (flashC_tsOE) + begin scope: 'ftop/flash0/flashC_tsd:OE' + INV:I->O 16 0.086 0.497 OE_inv1_INV_0 (OE_inv) + IOBUF:T->IO 0.003 IO_15_IOBUF (IO<15>) + end scope: 'ftop/flash0/flashC_tsd:IO<15>' + end scope: 'ftop/flash0:flash_io_dq<15>' + end scope: 'ftop:flash_io_dq<15>' + ---------------------------------------- + Total 1.360ns (0.464ns logic, 0.896ns route) + (34.1% logic, 65.9% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys1_clkp' + Total number of paths / destination ports: 12 / 12 +------------------------------------------------------------------------- +Offset: 1.009ns (Levels of Logic = 3) + Source: ftop/gbe0/gmac/txRS_iobTxData_7 (FF) + Destination: gmii_txd<7> (PAD) + Source Clock: sys1_clkp rising + + Data Path: ftop/gbe0/gmac/txRS_iobTxData_7 to gmii_txd<7> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ODDR:C->Q 1 0.607 0.399 txRS_iobTxData_7 (gmii_tx_txd<7>) + end scope: 'ftop/gbe0/gmac:gmii_tx_txd<7>' + end scope: 'ftop/gbe0:gmii_tx_txd<7>' + end scope: 'ftop:gmii_tx_txd<7>' + OBUF:I->O 0.003 gmii_txd_7_OBUF (gmii_txd<7>) + ---------------------------------------- + Total 1.009ns (0.610ns logic, 0.399ns route) + (60.5% logic, 39.5% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys0_clkp' + Total number of paths / destination ports: 1228 / 1056 +------------------------------------------------------------------------- +Offset: 1.870ns (Levels of Logic = 5) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_oserdes_ck_p:RST (PAD) + Source Clock: sys0_clkp rising + + Data Path: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_oserdes_ck_p:RST + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDP:C->Q 3 0.375 0.413 rstdiv0_sync_r_32 (rstdiv0_sync_r_32) + end scope: 'ftop/dram0/memc_memc/u_infrastructure:rstdiv0' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top:rst' + BUF:I->O 10 0.086 0.458 rst_1 (rst_1) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc:rst' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0:rst' + BUF:I->O 9 0.086 0.452 rst_8 (rst_8) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io:rst' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob:rst' + OSERDESE1:RST 0.000 u_oserdes_ck_p + ---------------------------------------- + Total 1.870ns (0.547ns logic, 1.323ns route) + (29.3% logic, 70.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Total number of paths / destination ports: 5 / 4 +------------------------------------------------------------------------- +Offset: 1.923ns (Levels of Logic = 4) + Source: ftop/fmc150/spiCDC_csbR (FF) + Destination: flp_com_sclk (PAD) + Source Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + + Data Path: ftop/fmc150/spiCDC_csbR to flp_com_sclk + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDS:C->Q 2 0.375 0.405 spiCDC_csbR (spiCDC_csbR) + INV:I->O 2 0.086 0.587 spiCDC_csbR_inv1_INV_0 (padsCDC_sclkgate) + end scope: 'ftop/fmc150:padsCDC_sclkgate' + end scope: 'ftop:flpCDC_sclkgate' + LUT4:I1->O 1 0.068 0.399 flp_com_sdc2m1 (flp_com_sdc2m_OBUF) + OBUF:I->O 0.003 flp_com_sdc2m_OBUF (flp_com_sdc2m) + ---------------------------------------- + Total 1.923ns (0.532ns logic, 1.391ns route) + (27.7% logic, 72.3% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Total number of paths / destination ports: 4 / 3 +------------------------------------------------------------------------- +Offset: 1.336ns (Levels of Logic = 3) + Source: ftop/fmc150/spiDAC_sdoR (FF) + Destination: flp_com_sdc2m (PAD) + Source Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + + Data Path: ftop/fmc150/spiDAC_sdoR to flp_com_sdc2m + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.375 0.491 spiDAC_sdoR (spiDAC_sdoR) + end scope: 'ftop/fmc150:padsDAC_sdo' + end scope: 'ftop:flpDAC_sdo' + LUT4:I2->O 1 0.068 0.399 flp_com_sdc2m1 (flp_com_sdc2m_OBUF) + OBUF:I->O 0.003 flp_com_sdc2m_OBUF (flp_com_sdc2m) + ---------------------------------------- + Total 1.336ns (0.446ns logic, 0.890ns route) + (33.4% logic, 66.6% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Total number of paths / destination ports: 250 / 250 +------------------------------------------------------------------------- +Offset: 0.827ns (Levels of Logic = 2) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_39 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 (PAD) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_39 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 9 0.375 0.452 dlyval_dq_39 (dlyval_dq_39) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl:dlyval_dq<39>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:dlyval_dq<39>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob:dlyval<4>' + IODELAYE1:CNTVALUEIN4 0.000 u_odelay_dm + ---------------------------------------- + Total 0.827ns (0.375ns logic, 0.452ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Total number of paths / destination ports: 150 / 150 +------------------------------------------------------------------------- +Offset: 0.827ns (Levels of Logic = 2) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_14 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 (PAD) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_14 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 9 0.375 0.452 dlyval_dq_14 (dlyval_dq_14) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl:dlyval_dq<14>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:dlyval_dq<14>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob:dlyval<4>' + IODELAYE1:CNTVALUEIN4 0.000 u_odelay_dm + ---------------------------------------- + Total 0.827ns (0.375ns logic, 0.452ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 596 / 532 +------------------------------------------------------------------------- +Delay: 0.538ns (Levels of Logic = 3) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt:O (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:CLKB (PAD) + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt:O to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:CLKB + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + BUFIODQS:O 9 0.000 0.000 gen_ck_cpt[7].u_bufio_cpt (clk_cpt<7>) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen:clk_cpt<7>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read:clk_cpt<7>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:clk_cpt<7>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob:clk_cpt' + INV:I->O 0 0.086 0.000 iserdes_clkb1_INV_0 (iserdes_clkb) + ISERDESE1:CLKB 0.000 u_iserdes_dqs_p + ---------------------------------------- + Total 0.538ns (0.538ns logic, 0.000ns route) + (100.0% logic, 0.0% route) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- + +Clock to Setup on destination clock flp_cdc_clk_p +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +flp_cdc_clk_p | 4.676| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 1.824| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| 2.088| 0.778| | | +sys0_clkp | 2.410| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| 2.088| 0.778| | | +sys0_clkp | 2.410| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/fmc150/spiCDC_cd/cntr_2 +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/fmc150/spiCDC_cd/cntr_2 | 3.708| 0.791| | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 3.854| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/fmc150/spiDAC_cd/cntr_3 +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/fmc150/spiDAC_cd/cntr_3 | 3.785| 0.791| | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 3.951| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | 3.576| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 1.860| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +flp_cdc_clk_p | 0.857| | | | +ftop/fmc150/spiCDC_cd/cntr_2 | 5.230| | | | +ftop/fmc150/spiDAC_cd/cntr_3 | 5.350| | | | +ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT | 2.078| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 8.240| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 | 2.324| | | | +sys0_clkp | 2.712| | | | +sys1_clkp | 1.727| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 +-------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +-------------------------------------------------+---------+---------+---------+---------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125| 3.724| | | | +-------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| 1.675| | | | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| 1.675| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | 2.230| | | | +sys0_clkp | 4.758| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkp +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 2.078| | | | +sys1_clkp | 3.831| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +========================================================================= + + +Total REAL time to Xst completion: 356.00 secs +Total CPU time to Xst completion: 354.06 secs + +--> + + +Total memory usage is 1452432 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 2593 ( 0 filtered) +Number of infos : 410 ( 0 filtered) + diff --git a/logs/ml605-20140204_1516/fpgaTop.bld b/logs/ml605-20140204_1516/fpgaTop.bld new file mode 100644 index 00000000..0e8208e4 --- /dev/null +++ b/logs/ml605-20140204_1516/fpgaTop.bld @@ -0,0 +1,5926 @@ +Release 14.7 ngdbuild P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Command Line: /home/shep/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -sd +../../coregen/pcie_4243_trn_v6_gtx_x4_250 -sd ../../coregen/fft_v5_4k_strm_nat +-sd ../../coregen/ddc_4243_4ch_v5 -aul -aut -uc ml605.ucf -p xc6vlx240t-ff1156-1 +fpgaTop_csi.ngc fpgaTop.ngd + +Reading NGO file "/home/shep/projects/ocpi/build/tmp-ml605/fpgaTop_csi.ngc" ... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "ml605.ucf" ... +WARNING:NgdBuild - The value of SIM_DEVICE on instance + 'ftop/gbe0/gmac/rxClk_BUFR' of type BUFR has been changed from 'VIRTEX4' to + 'VIRTEX6' to correct post-ngdbuild and timing simulation for this primitive. + In order for functional simulation to be correct, the value of SIM_DEVICE + should be changed in this same manner in the source netlist or constraint + file. +Resolving constraint associations... +Checking Constraint Associations... +WARNING:ConstraintSystem - Constraint + [ml605.ucf(46)] was not distributed to the output pin TXOUTCLK of block + GTXD[0].GTX because the signal path to this output pin depends upon block + attribute settings. Constraint distribution does not support attribute + dependent distribution. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(113)]: NET "gmii_tx_clk" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(113)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(113)]: + NET "gmii_tx_clk" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(125)]: NET "gmii_COL" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(125)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(125)]: + NET "gmii_COL" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(126)]: NET "gmii_CRS" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(126)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(126)]: + NET "gmii_CRS" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(127)]: NET "gmii_INT" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(127)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(127)]: + NET "gmii_INT" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(281)]: NET "flp_cdc_pllstat" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(281)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(281)]: NET "flp_cdc_pllstat" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(286)]: NET "flp_mon_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(286)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(286)]: NET "flp_mon_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(287)]: NET "flp_mon_intn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(287)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(287)]: NET "flp_mon_intn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(294)]: NET "flp_adc_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(294)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(294)]: NET "flp_adc_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:58 - Constraint [ml605.ucf(761)]: INST + "*/gen_enable_ocb_mon.u_phy_ocb_mon_top/u_oserdes_ocb_mon" does not match any + design objects. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(761)]' could not be found and so the Locate + constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(768)]: INST "ftop/dram0/memc/u_infrastructure/u_mmcm_adv" not + found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(768)]' could not be found and so the Locate + constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(769)]: INST + "ftop/dram0/memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_ge + n/u_mmcm_clk_base" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(769)]' could not be + found and so the Locate constraint will be removed. + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT1: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT0: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT2: + +Done... + +Checking expanded design ... +WARNING:NgdBuild:452 - logical net 'N100' has no driver +WARNING:NgdBuild:452 - logical net 'N101' has no driver +WARNING:NgdBuild:452 - logical net 'N102' has no driver +WARNING:NgdBuild:452 - logical net 'N103' has no driver +WARNING:NgdBuild:452 - logical net 'N104' has no driver +WARNING:NgdBuild:452 - logical net 'N105' has no driver +WARNING:NgdBuild:452 - logical net 'N106' has no driver +WARNING:NgdBuild:452 - logical net 'N107' has no driver +WARNING:NgdBuild:452 - logical net 'N108' has no driver +WARNING:NgdBuild:452 - logical net 'N109' has no driver +WARNING:NgdBuild:452 - logical net 'N110' has no driver +WARNING:NgdBuild:452 - logical net 'N111' has no driver +WARNING:NgdBuild:452 - logical net 'N112' has no driver +WARNING:NgdBuild:452 - logical net 'N113' has no driver +WARNING:NgdBuild:452 - logical net 'N114' has no driver +WARNING:NgdBuild:452 - logical net 'N115' has no driver +WARNING:NgdBuild:452 - logical net 'N116' has no driver +WARNING:NgdBuild:452 - logical net 'N117' has no driver +WARNING:NgdBuild:452 - logical net 'N118' has no driver +WARNING:NgdBuild:452 - logical net 'N119' has no driver +WARNING:NgdBuild:452 - logical net 'N120' has no driver +WARNING:NgdBuild:452 - logical net 'N121' has no driver +WARNING:NgdBuild:452 - logical net 'N122' has no driver +WARNING:NgdBuild:452 - logical net 'N123' has no driver +WARNING:NgdBuild:452 - logical net 'N124' has no driver +WARNING:NgdBuild:452 - logical net 'N125' has no driver +WARNING:NgdBuild:452 - logical net 'N126' has no driver +WARNING:NgdBuild:452 - logical net 'N127' has no driver +WARNING:NgdBuild:452 - logical net 'N128' has no driver +WARNING:NgdBuild:452 - logical net 'N129' has no driver +WARNING:NgdBuild:452 - logical net 'N130' has no driver +WARNING:NgdBuild:452 - logical net 'N131' has no driver +WARNING:NgdBuild:452 - logical net 'N132' has no driver +WARNING:NgdBuild:452 - logical net 'N133' has no driver +WARNING:NgdBuild:452 - logical net 'N134' has no driver +WARNING:NgdBuild:452 - logical net 'N135' has no driver +WARNING:NgdBuild:452 - logical net 'N136' has no driver +WARNING:NgdBuild:452 - logical net 'N137' has no driver +WARNING:NgdBuild:452 - logical net 'N138' has no driver +WARNING:NgdBuild:452 - logical net 'N139' has no driver +WARNING:NgdBuild:452 - logical net 'N140' has no driver +WARNING:NgdBuild:452 - logical net 'N141' has no driver +WARNING:NgdBuild:452 - logical net 'N142' has no driver +WARNING:NgdBuild:452 - logical net 'N143' has no driver +WARNING:NgdBuild:452 - logical net 'N144' has no driver +WARNING:NgdBuild:452 - logical net 'N145' has no driver +WARNING:NgdBuild:452 - logical net 'N146' has no driver +WARNING:NgdBuild:452 - logical net 'N147' has no driver +WARNING:NgdBuild:452 - logical net 'N148' has no driver +WARNING:NgdBuild:452 - logical net 'N149' has no driver +WARNING:NgdBuild:452 - logical net 'N150' has no driver +WARNING:NgdBuild:452 - logical net 'N151' has no driver +WARNING:NgdBuild:452 - logical net 'N152' has no driver +WARNING:NgdBuild:452 - logical net 'N153' has no driver +WARNING:NgdBuild:452 - logical net 'N154' has no driver +WARNING:NgdBuild:452 - logical net 'N155' has no driver +WARNING:NgdBuild:452 - logical net 'N156' has no driver +WARNING:NgdBuild:452 - logical net 'N157' has no driver +WARNING:NgdBuild:452 - logical net 'N158' has no driver +WARNING:NgdBuild:452 - logical net 'N159' has no driver +WARNING:NgdBuild:452 - logical net 'N160' has no driver +WARNING:NgdBuild:452 - logical net 'N161' has no driver +WARNING:NgdBuild:452 - logical net 'N162' has no driver +WARNING:NgdBuild:452 - logical net 'N163' has no driver +WARNING:NgdBuild:452 - logical net 'N164' has no driver +WARNING:NgdBuild:452 - logical net 'N165' has no driver +WARNING:NgdBuild:452 - logical net 'N166' has no driver +WARNING:NgdBuild:452 - logical net 'N167' has no driver +WARNING:NgdBuild:452 - logical net 'N168' has no driver +WARNING:NgdBuild:452 - logical net 'N169' has no driver +WARNING:NgdBuild:452 - logical net 'N170' has no driver +WARNING:NgdBuild:452 - logical net 'N171' has no driver +WARNING:NgdBuild:452 - logical net 'N172' has no driver +WARNING:NgdBuild:452 - logical net 'N173' has no driver +WARNING:NgdBuild:452 - logical net 'N174' has no driver +WARNING:NgdBuild:452 - logical net 'N175' has no driver +WARNING:NgdBuild:452 - logical net 'N176' has no driver +WARNING:NgdBuild:452 - logical net 'N177' has no driver +WARNING:NgdBuild:452 - logical net 'N178' has no driver +WARNING:NgdBuild:452 - logical net 'N179' has no driver +WARNING:NgdBuild:452 - logical net 'N180' has no driver +WARNING:NgdBuild:452 - logical net 'N181' has no driver +WARNING:NgdBuild:452 - logical net 'N182' has no driver +WARNING:NgdBuild:452 - logical net 'N183' has no driver +WARNING:NgdBuild:452 - logical net 'N184' has no driver +WARNING:NgdBuild:452 - logical net 'N185' has no driver +WARNING:NgdBuild:452 - logical net 'N186' has no driver +WARNING:NgdBuild:452 - logical net 'N187' has no driver +WARNING:NgdBuild:452 - logical net 'N188' has no driver +WARNING:NgdBuild:452 - logical net 'N189' has no driver +WARNING:NgdBuild:452 - logical net 'N190' has no driver +WARNING:NgdBuild:452 - logical net 'N191' has no driver +WARNING:NgdBuild:452 - logical net 'N192' has no driver +WARNING:NgdBuild:452 - logical net 'N193' has no driver +WARNING:NgdBuild:452 - logical net 'N194' has no driver +WARNING:NgdBuild:452 - logical net 'N195' has no driver +WARNING:NgdBuild:452 - logical net 'N196' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/upads_cts_arg' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/gmii_led' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_0_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_1_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_2_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wci_m_4_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<35>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<34>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<33>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<32>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop_wmemiM0_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/axbluart_s_axi_BRESP<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/axbluart_s_axi_BRESP<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/axbluart_s_axi_RRESP<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/axbluart_s_axi_RRESP<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/dram0_wmemiS0_SRespLast' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_wmemiM0_MAddr<35>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_wmemiM0_MAddr<34>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_wmemiM0_MAddr<33>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_wmemiM0_MAddr<32>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_wmemiM0_MAddr<31>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_wmemiM0_MAddr<30>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<31>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<30>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<29>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<28>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<27>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<26>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<25>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<24>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<23>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<22>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<21>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<20>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<19>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<18>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<17>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<16>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<15>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<14>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<13>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<12>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<11>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<10>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<9>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<8>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrAddr_data<33>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrData_data<35>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrData_data<34>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrData_data<33>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_wrData_data<32>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<31>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<30>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<29>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<28>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<27>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<26>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<25>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<24>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<23>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<22>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<21>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<20>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<19>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<18>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<17>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<16>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<15>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<14>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<13>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<12>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<11>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<10>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<9>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<8>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_axiM0_rdAddr_data<33>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_wmemiS0_SRespLast' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_wmemiM0_MReqLast' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/wmemiTap_wmemiM0_MDataLast' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<9>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<8>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<4>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<3>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<4>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<3>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<2>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<2>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<15>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<14>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<13>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<12>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<11>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<10>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_to_turnoff_n' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6PHYSTATUSGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7VALIDGT' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHANISALIGNEDGT' has no driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/pd_PSINCDEC' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/dbg_wrlvl_err' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/rd_buf_full' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/hi_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/data_buf_addr<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/data_buf_addr<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/data_buf_addr<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/data_buf_addr<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/io_config<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_address1<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_dram_clk_disable' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_reset_n' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_cas_n1' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<185>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<184>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<183>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<182>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<181>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<180>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<179>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<178>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<177>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<176>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<175>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<174>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<173>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<172>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<171>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<170>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<169>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<154>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<153>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<152>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<151>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<150>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<149>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<148>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<147>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<146>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<145>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<21>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<20>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<19>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<18>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<187>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<154>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<153>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<152>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<151>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<150>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<149>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<148>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<147>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<146>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<145>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<106>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<105>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<104>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<102>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<100>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<99>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<98>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<97>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<96>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<95>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<94>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<93>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<92>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<91>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<90>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<89>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<88>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<87>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<86>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<85>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<84>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<83>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<82>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<81>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<80>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<79>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<78>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<77>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<76>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<75>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<74>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<72>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<71>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<70>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<69>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<68>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<67>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<66>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<65>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<64>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<63>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<62>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<61>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<24>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<23>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<22>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<21>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<20>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<19>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<18>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<17>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<16>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<15>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<14>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<13>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<9>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<8>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<194>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<106>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<105>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<104>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<102>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<100>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<99>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<98>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<97>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<96>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<95>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<94>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<93>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<92>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<91>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<90>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<89>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<88>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<87>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<86>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<85>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<84>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<83>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<82>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<81>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<80>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<79>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<78>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<77>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<76>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<75>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<74>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<72>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<71>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<70>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<69>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<68>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<67>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<66>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<65>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<64>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<63>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<62>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<61>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<60>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<59>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<58>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<57>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<56>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<55>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<54>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<53>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<52>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<51>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<50>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<49>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<48>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<47>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<46>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<45>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<44>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<43>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<42>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<41>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<40>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<39>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<38>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<37>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<36>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<35>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<34>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<33>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<32>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<31>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<30>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<29>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<28>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<27>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<26>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<25>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<24>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<23>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<22>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<21>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<20>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<19>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<18>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<17>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<16>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<15>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<14>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<13>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<4>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_ra' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_a<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/io_config_ns<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/m + aintenance_request.maint_grant_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<0> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<0>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<0>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<1> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<2> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<3> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/low_idle_cnt_r + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/was_priority' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/send_ + cmd0_col' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/send_ + cmd1_row' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_rsync<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_rsync<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<7>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<6>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<5>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<4>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<1>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<15>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<14>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<13>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<12>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<11>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<10>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<9>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<23>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<22>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<21>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<20>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<19>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<18>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<17>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<31>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<30>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<29>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<28>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<27>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<26>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<25>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<7>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<6>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<5>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<4>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<1>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<0>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<4>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<39>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<38>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<37>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<36>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<35>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<34>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<33>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<32>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<31>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<30>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<29>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<28>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<27>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<26>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<25>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<24>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<23>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<22>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<21>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<20>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<19>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<18>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<17>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<16>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<15>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<14>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<13>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<12>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<11>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<10>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<9>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<8>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/pd_prech_req' has no + driver + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 2574 + +Total memory usage is 840772 kilobytes + +Writing NGD file "fpgaTop.ngd" ... +Total REAL time to NGDBUILD completion: 49 sec +Total CPU time to NGDBUILD completion: 49 sec + +Writing NGDBUILD log file "fpgaTop.bld"... diff --git a/logs/ml605-20140204_1516/fpgaTop.par b/logs/ml605-20140204_1516/fpgaTop.par new file mode 100644 index 00000000..1d35cc9d --- /dev/null +++ b/logs/ml605-20140204_1516/fpgaTop.par @@ -0,0 +1,1219 @@ +Release 14.7 par P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +ar-cms520:: Tue Feb 04 15:07:58 2014 + +par -w -xe n fpgaTop_map.ncd fpgaTop.ncd fpgaTop.pcf + + +Constraints file: fpgaTop.pcf. +Loading device for application Rf_Device from file '6vlx240t.nph' in environment /home/shep/ISE/14.7/ISE_DS/ISE/. + "fpgaTop" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) + + +Device speed data version: "PRODUCTION 1.17 2013-10-13". + + + +Device Utilization Summary: + +Slice Logic Utilization: + Number of Slice Registers: 35,528 out of 301,440 11% + Number used as Flip Flops: 35,521 + Number used as Latches: 2 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 5 + Number of Slice LUTs: 43,387 out of 150,720 28% + Number used as logic: 37,439 out of 150,720 24% + Number using O6 output only: 33,860 + Number using O5 output only: 2,410 + Number using O5 and O6: 1,169 + Number used as ROM: 0 + Number used as Memory: 5,083 out of 58,400 8% + Number used as Dual Port RAM: 2,106 + Number using O6 output only: 110 + Number using O5 output only: 53 + Number using O5 and O6: 1,943 + Number used as Single Port RAM: 0 + Number used as Shift Register: 2,977 + Number using O6 output only: 2,977 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 865 + Number with same-slice register load: 733 + Number with same-slice carry load: 130 + Number with other load: 2 + +Slice Logic Distribution: + Number of occupied Slices: 16,807 out of 37,680 44% + Number of LUT Flip Flop pairs used: 51,554 + Number with an unused Flip Flop: 17,143 out of 51,554 33% + Number with an unused LUT: 8,167 out of 51,554 15% + Number of fully used LUT-FF pairs: 26,244 out of 51,554 50% + Number of slice register sites lost + to control set restrictions: 0 out of 301,440 0% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + OVERMAPPING of BRAM resources should be ignored if the design is + over-mapped for a non-BRAM resource or if placement fails. + +IO Utilization: + Number of bonded IOBs: 222 out of 600 37% + Number of LOCed IOBs: 222 out of 222 100% + IOB Flip Flops: 12 + IOB Master Pads: 9 + IOB Slave Pads: 9 + Number of bonded IPADs: 12 + Number of LOCed IPADs: 4 out of 12 33% + Number of bonded OPADs: 8 + +Specific Feature Utilization: + Number of RAMB36E1/FIFO36E1s: 38 out of 416 9% + Number using RAMB36E1 only: 38 + Number using FIFO36E1 only: 0 + Number of RAMB18E1/FIFO18E1s: 3 out of 832 1% + Number using RAMB18E1 only: 3 + Number using FIFO18E1 only: 0 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 11 + Number used as BUFGCTRLs: 1 + Number of ILOGICE1/ISERDESE1s: 65 out of 720 9% + Number used as ILOGICE1s: 0 + Number used as ISERDESE1s: 65 + Number of OLOGICE1/OSERDESE1s: 138 out of 720 19% + Number used as OLOGICE1s: 17 + Number used as OSERDESE1s: 121 + Number of BSCANs: 0 out of 4 0% + Number of BUFHCEs: 0 out of 144 0% + Number of BUFIODQSs: 8 out of 72 11% + Number of BUFRs: 3 out of 36 8% + Number of LOCed BUFRs: 2 out of 3 66% + Number of CAPTUREs: 0 out of 1 0% + Number of DSP48E1s: 0 out of 768 0% + Number of EFUSE_USRs: 0 out of 1 0% + Number of FRAME_ECCs: 0 out of 1 0% + Number of GTXE1s: 4 out of 20 20% + Number of LOCed GTXE1s: 4 out of 4 100% + Number of IBUFDS_GTXE1s: 2 out of 12 16% + Number of LOCed IBUFDS_GTXE1s: 1 out of 2 50% + Number of ICAPs: 0 out of 2 0% + Number of IDELAYCTRLs: 4 out of 18 22% + Number of IODELAYE1s: 91 out of 720 12% + Number of LOCed IODELAYE1s: 10 out of 91 10% + Number of MMCM_ADVs: 2 out of 12 16% + Number of PCIE_2_0s: 1 out of 2 50% + Number of LOCed PCIE_2_0s: 1 out of 1 100% + Number of STARTUPs: 1 out of 1 100% + Number of SYSMONs: 0 out of 1 0% + Number of TEMAC_SINGLEs: 0 out of 4 0% + + +Overall effort level (-ol): Standard +Router effort level (-rl): High + +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +Starting initial Timing Analysis. REAL time: 41 secs +Finished initial Timing Analysis. REAL time: 42 secs + +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_memory_DOB<11> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_memory_DOB<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal upads_cts_arg_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMB_D1_DPO has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/axbluart/bluart/rxF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr5_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MAddr<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MAddr<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF_sD_IN<145> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem25_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem27_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem29_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem29_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF_sD_IN<173> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MData<29> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MData<31> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr5_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<13> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr28_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr9_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<7> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr9_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MDataByteEn<13> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app_wmiM1_MDataByteEn<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_4_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_1_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_14_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_14_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMC_D1_DPO has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_1_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMB_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_1_MAddr<21> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MAddr<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<11> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_4_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_0_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_4_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_1_MByteEn<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_3_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_4_MAddr<21> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_2_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMA_D1_DPO has no load. + PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMD_D1_O has no load. PAR + will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_13_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMA_D1_DPO has no load. + PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMD_D1_O has no load. PAR + will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3_wsiM0_MBurstLength<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<19> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<17> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_3_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MByteEn<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_3_MAddr<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr8_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_2_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop_wci_m_2_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp_wci_Vm_13_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf_wci_m_2_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/gmac/txRS_txF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr5_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +Starting Router + + +Phase 1 : 263456 unrouted; REAL time: 48 secs + +Phase 2 : 226275 unrouted; REAL time: 1 mins 4 secs + +Phase 3 : 75068 unrouted; REAL time: 1 mins 58 secs + +Phase 4 : 75009 unrouted; (Setup:22447, Hold:27780, Component Switching Limit:0) REAL time: 2 mins 13 secs + +Updating file: fpgaTop.ncd with current fully routed design. + +Phase 5 : 0 unrouted; (Setup:18736, Hold:25186, Component Switching Limit:0) REAL time: 3 mins 26 secs + +Phase 6 : 0 unrouted; (Setup:16277, Hold:25186, Component Switching Limit:0) REAL time: 3 mins 45 secs + +Updating file: fpgaTop.ncd with current fully routed design. + +Phase 7 : 0 unrouted; (Setup:16277, Hold:25186, Component Switching Limit:0) REAL time: 4 mins 37 secs + +Phase 8 : 0 unrouted; (Setup:16277, Hold:25186, Component Switching Limit:0) REAL time: 4 mins 37 secs + +Phase 9 : 0 unrouted; (Setup:16277, Hold:25186, Component Switching Limit:0) REAL time: 4 mins 37 secs + +Phase 10 : 0 unrouted; (Setup:16277, Hold:100, Component Switching Limit:0) REAL time: 4 mins 44 secs + +Phase 11 : 0 unrouted; (Setup:12089, Hold:100, Component Switching Limit:0) REAL time: 4 mins 56 secs +Total REAL time to Router completion: 4 mins 56 secs +Total CPU time to Router completion: 5 mins 17 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| ftop/p125clk |BUFGCTRL_X0Y29| No | 8344 | 0.466 | 2.046 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| _tb_clk |BUFGCTRL_X0Y25| No | 2117 | 0.344 | 1.952 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep_trn_clk |BUFGCTRL_X0Y28| No | 236 | 0.148 | 1.783 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep/ep/pipe_clk |BUFGCTRL_X0Y30| No | 179 | 0.413 | 2.046 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/sys0_clk_O_BUFG | | | | | | +| | BUFGCTRL_X0Y1| No | 234 | 0.151 | 1.731 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| rsync<0> | Regional Clk|Yes | 270 | 0.181 | 1.019 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| rsync<1> | Regional Clk|Yes | 437 | 0.266 | 1.109 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/rxclkBnd | Regional Clk| No | 42 | 0.201 | 1.095 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/sys1_clk_O |BUFGCTRL_X0Y24| No | 58 | 0.186 | 1.939 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flpCDC_sclk | BUFGCTRL_X0Y2| No | 28 | 0.049 | 1.650 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flpDAC_sclk | BUFGCTRL_X0Y3| No | 16 | 0.036 | 1.634 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flp_clk_O_BUFG | BUFGCTRL_X0Y0| No | 9 | 0.006 | 1.610 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep/ep/TxOutClk_bufg |BUFGCTRL_X0Y31| No | 6 | 0.018 | 1.640 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| /clk_mem |BUFGCTRL_X0Y26| No | 186 | 0.164 | 1.901 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/ctop/inf/cp/dna | | | | | | +| _cnt<0> | Local| | 11 | 0.000 | 1.811 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_infrastructure/u_ | | | | | | +| mmcm_adv_ML_NEW_I1 | Local| | 3 | 0.000 | 1.756 | ++---------------------+--------------+------+------+------------+-------------+ +|MMCM_PHASE_CALIBRATI | | | | | | +|ON_ML_LUT2_309_ML_NE | | | | | | +| W_CLK | Local| | 3 | 0.453 | 0.679 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +|ep/ep/pcie_clocking_ | | | | | | +|i/mmcm_adv_i_ML_NEW_ | | | | | | +| I1 | Local| | 3 | 0.000 | 2.048 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +|ep/ep/pcie_clocking_ | | | | | | +|i/mmcm_adv_i_ML_NEW_ | | | | | | +| OUT | Local| | 2 | 0.000 | 0.480 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_infrastructure/u_ | | | | | | +| mmcm_adv_ML_NEW_OUT | Local| | 2 | 0.000 | 0.480 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<7> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| /clk_wr_i | Local| | 10 | 0.402 | 1.403 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<6> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<2> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<3> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<4> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<5> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<0> | Local| | 18 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_clk_O | | | | | | +| | Local| | 8 | 0.000 | 2.396 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<1> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|MMCM_PHASE_CALIBRATI | | | | | | +|ON_ML_LUT2_301_ML_NE | | | | | | +| W_CLK | Local| | 2 | 0.000 | 0.477 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + +* The fanout is the number of component pins not the individual BEL loads, +for example SLICE loads not FF loads. + +Timing Score: 12189 (Setup: 12089, Hold: 100, Component Switching Limit: 0) + +WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. + + Review the timing report using Timing Analyzer (In ISE select "Post-Place & + Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint. + + Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options + are set in the tools for timing closure. + + Increase the PAR Effort Level setting to "high" + + Use the Xilinx "SmartXplorer" script to try special combinations of + options known to produce very good results. + + Visit the Xilinx technical support web at http://support.xilinx.com and go to + either "Troubleshoot->Tech Tips->Timing & Constraints" or " + TechXclusives->Timing Closure" for tips and suggestions for meeting timing + in your design. + +Number of Timing Constraints that were not applied: 13 + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +---------------------------------------------------------------------------------------------------------- + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +---------------------------------------------------------------------------------------------------------- +* TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_ | SETUP | -0.251ns| 8.251ns| 37| 4466 + PCICLK / 2 HIGH 50% PRIORITY 100 | HOLD | -0.100ns| | 1| 100 +---------------------------------------------------------------------------------------------------------- +* TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_ | SETUP | -0.204ns| 4.204ns| 94| 7060 + PCICLK HIGH 50% PRIORITY 1 | HOLD | 0.000ns| | 0| 0 + | MINPERIOD | 0.000ns| 4.000ns| 0| 0 +---------------------------------------------------------------------------------------------------------- +* TS_ftop_dram0_memc_memc_u_infrastructure_ | SETUP | -0.120ns| 5.120ns| 23| 563 + clk_pll = PERIOD TIMEGRP "ftop_dr | HOLD | 0.057ns| | 0| 0 + am0_memc_memc_u_infrastructure_clk_pll" T | | | | | + S_SYS0CLK HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + Pin to Pin Skew Constraint | MAXDELAY | 0.108ns| 0.450ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 | SETUP | 1.006ns| 3.994ns| 0| 0 + MHz HIGH 50% | HOLD | 0.078ns| | 0| 0 + | MINPERIOD | 0.239ns| 4.761ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VAL | SETUP | 0.610ns| -0.110ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.671ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VAL | SETUP | 0.643ns| -0.143ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.602ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VAL | SETUP | 0.647ns| -0.147ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.547ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VAL | SETUP | 0.666ns| -0.166ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.574ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VAL | SETUP | 0.707ns| -0.207ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.482ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VAL | SETUP | 0.729ns| -0.229ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.500ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VAL | SETUP | 0.736ns| -0.236ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.449ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALI | SETUP | 0.743ns| -0.243ns| 0| 0 + D 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.457ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VAL | SETUP | 0.778ns| -0.278ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.414ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALI | SETUP | 0.979ns| -0.479ns| 0| 0 + D 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.076ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_ | SETUP | 1.049ns| 6.951ns| 0| 0 + CLK" 125 MHz HIGH 50% | HOLD | 0.068ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_u_infrastructure_ | MINPERIOD | 1.071ns| 1.429ns| 0| 0 + clk_mem_pll = PERIOD TIMEGRP "fto | | | | | + p_dram0_memc_memc_u_infrastructure_clk_me | | | | | + m_pll" TS_SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 M | MINPERIOD | 2.462ns| 1.538ns| 0| 0 + Hz HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GT | SETUP | 2.993ns| 5.007ns| 0| 0 + X_CLK" 125 MHz HIGH 50% | HOLD | 0.060ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER | N/A | N/A| N/A| N/A| N/A + COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER | N/A | N/A| N/A| N/A| N/A + COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_clk_wr_i = PERIOD | N/A | N/A| N/A| N/A| N/A + TIMEGRP "ftop_dram0_memc_memc_cl | | | | | + k_wr_i" TS_SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + + +Derived Constraint Report +Review Timing Report for more details on the following derived constraints. +To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" +or "Run Timing Analysis" from Timing Analyzer (timingan). +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 5.000ns| 4.761ns| 5.120ns| 0| 23| 91995| 75774| +| TS_ftop_dram0_memc_memc_u_infr| 5.000ns| 5.120ns| N/A| 23| 0| 75774| 0| +| astructure_clk_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_u_infr| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| +| astructure_clk_mem_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0| +| _i | | | | | | | | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +Derived Constraints for TS_PCICLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_PCICLK | 4.000ns| 1.538ns| 4.204ns| 0| 132| 0| 11123906| +| TS_CLK_125 | 8.000ns| 8.251ns| N/A| 38| 0| 11104609| 0| +| TS_CLK_250 | 4.000ns| 4.204ns| N/A| 94| 0| 19297| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +3 constraints not met. +INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the + constraint is not analyzed due to the following: No paths covered by this + constraint; Other constraints intersect with this constraint; or This + constraint was disabled by a Path Tracing Control. Please run the Timespec + Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. + + +Generating Pad Report. + +All signals are completely routed. + +WARNING:Par:283 - There are 534 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + +Total REAL time to PAR completion: 5 mins 14 secs +Total CPU time to PAR completion: 5 mins 35 secs + +Peak Memory Usage: 2266 MB + +Placer: Placement generated during map. +Routing: Completed - No errors found. +Timing: Completed - 155 errors found. + +Number of error messages: 0 +Number of warning messages: 557 +Number of info messages: 0 + +Writing design to file fpgaTop.ncd + + + +PAR done! diff --git a/logs/ml605-20140204_1516/fpgaTop.twr b/logs/ml605-20140204_1516/fpgaTop.twr new file mode 100644 index 00000000..b1be1c9d --- /dev/null +++ b/logs/ml605-20140204_1516/fpgaTop.twr @@ -0,0 +1,10827 @@ +-------------------------------------------------------------------------------- +Release 14.7 Trace (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +/home/shep/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 20 -fastpaths -xml +fpgaTop.twx fpgaTop.ncd -o fpgaTop.twr fpgaTop.pcf + +Design file: fpgaTop.ncd +Physical constraint file: fpgaTop.pcf +Device,package,speed: xc6vlx240t,ff1156,C,-1 (PRODUCTION 1.17 2013-10-13, STEPPING level 0) +Report level: verbose report, limited to 20 items per constraint + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. + +================================================================================ +Timing constraint: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 91995 paths analyzed, 3686 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.761ns. +-------------------------------------------------------------------------------- +Slack (setup path): 1.006ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_3 (FF) + Requirement: 5.000ns + Data Path Delay: 3.900ns (Levels of Logic = 3) + Clock Path Skew: -0.059ns (1.006 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_refFreeSamp_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y92.CE net (fanout=33) 1.005 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y92.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_3 + ------------------------------------------------- --------------------------- + Total 3.900ns (1.301ns logic, 2.599ns route) + (33.4% logic, 66.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.006ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_2 (FF) + Requirement: 5.000ns + Data Path Delay: 3.900ns (Levels of Logic = 3) + Clock Path Skew: -0.059ns (1.006 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_refFreeSamp_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y92.CE net (fanout=33) 1.005 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y92.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_2 + ------------------------------------------------- --------------------------- + Total 3.900ns (1.301ns logic, 2.599ns route) + (33.4% logic, 66.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.006ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_1 (FF) + Requirement: 5.000ns + Data Path Delay: 3.900ns (Levels of Logic = 3) + Clock Path Skew: -0.059ns (1.006 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_refFreeSamp_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y92.CE net (fanout=33) 1.005 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y92.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_1 + ------------------------------------------------- --------------------------- + Total 3.900ns (1.301ns logic, 2.599ns route) + (33.4% logic, 66.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.006ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_0 (FF) + Requirement: 5.000ns + Data Path Delay: 3.900ns (Levels of Logic = 3) + Clock Path Skew: -0.059ns (1.006 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_refFreeSamp_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y92.CE net (fanout=33) 1.005 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y92.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_0 + ------------------------------------------------- --------------------------- + Total 3.900ns (1.301ns logic, 2.599ns route) + (33.4% logic, 66.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.020ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_4 (FF) + Requirement: 5.000ns + Data Path Delay: 3.886ns (Levels of Logic = 3) + Clock Path Skew: -0.059ns (1.006 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_refFreeSamp_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y93.CE net (fanout=33) 0.991 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y93.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<7> + ftop/ctop/inf/cp/timeServ_refFreeSamp_4 + ------------------------------------------------- --------------------------- + Total 3.886ns (1.301ns logic, 2.585ns route) + (33.5% logic, 66.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.020ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_7 (FF) + Requirement: 5.000ns + Data Path Delay: 3.886ns (Levels of Logic = 3) + Clock Path Skew: -0.059ns (1.006 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_refFreeSamp_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y93.CE net (fanout=33) 0.991 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y93.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<7> + ftop/ctop/inf/cp/timeServ_refFreeSamp_7 + ------------------------------------------------- --------------------------- + Total 3.886ns (1.301ns logic, 2.585ns route) + (33.5% logic, 66.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.020ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_5 (FF) + Requirement: 5.000ns + Data Path Delay: 3.886ns (Levels of Logic = 3) + Clock Path Skew: -0.059ns (1.006 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_refFreeSamp_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y93.CE net (fanout=33) 0.991 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y93.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<7> + ftop/ctop/inf/cp/timeServ_refFreeSamp_5 + ------------------------------------------------- --------------------------- + Total 3.886ns (1.301ns logic, 2.585ns route) + (33.5% logic, 66.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.020ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_6 (FF) + Requirement: 5.000ns + Data Path Delay: 3.886ns (Levels of Logic = 3) + Clock Path Skew: -0.059ns (1.006 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_refFreeSamp_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y93.CE net (fanout=33) 0.991 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y93.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<7> + ftop/ctop/inf/cp/timeServ_refFreeSamp_6 + ------------------------------------------------- --------------------------- + Total 3.886ns (1.301ns logic, 2.585ns route) + (33.5% logic, 66.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_13 (FF) + Requirement: 5.000ns + Data Path Delay: 3.862ns (Levels of Logic = 3) + Clock Path Skew: -0.079ns (0.986 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_delSecond_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X16Y94.CE net (fanout=33) 1.001 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X16Y94.CLK Tceck 0.284 ftop/ctop/inf/cp/timeServ_delSecond<15> + ftop/ctop/inf/cp/timeServ_delSecond_13 + ------------------------------------------------- --------------------------- + Total 3.862ns (1.267ns logic, 2.595ns route) + (32.8% logic, 67.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_15 (FF) + Requirement: 5.000ns + Data Path Delay: 3.862ns (Levels of Logic = 3) + Clock Path Skew: -0.079ns (0.986 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_delSecond_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X16Y94.CE net (fanout=33) 1.001 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X16Y94.CLK Tceck 0.284 ftop/ctop/inf/cp/timeServ_delSecond<15> + ftop/ctop/inf/cp/timeServ_delSecond_15 + ------------------------------------------------- --------------------------- + Total 3.862ns (1.267ns logic, 2.595ns route) + (32.8% logic, 67.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_12 (FF) + Requirement: 5.000ns + Data Path Delay: 3.862ns (Levels of Logic = 3) + Clock Path Skew: -0.079ns (0.986 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_delSecond_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X16Y94.CE net (fanout=33) 1.001 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X16Y94.CLK Tceck 0.284 ftop/ctop/inf/cp/timeServ_delSecond<15> + ftop/ctop/inf/cp/timeServ_delSecond_12 + ------------------------------------------------- --------------------------- + Total 3.862ns (1.267ns logic, 2.595ns route) + (32.8% logic, 67.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.024ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_16 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_14 (FF) + Requirement: 5.000ns + Data Path Delay: 3.862ns (Levels of Logic = 3) + Clock Path Skew: -0.079ns (0.986 - 1.065) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_16 to ftop/ctop/inf/cp/timeServ_delSecond_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y103.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<19> + ftop/ctop/inf/cp/timeServ_refFromRise_16 + SLICE_X2Y101.D1 net (fanout=4) 0.849 ftop/ctop/inf/cp/timeServ_refFromRise<16> + SLICE_X2Y101.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X16Y94.CE net (fanout=33) 1.001 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X16Y94.CLK Tceck 0.284 ftop/ctop/inf/cp/timeServ_delSecond<15> + ftop/ctop/inf/cp/timeServ_delSecond_14 + ------------------------------------------------- --------------------------- + Total 3.862ns (1.267ns logic, 2.595ns route) + (32.8% logic, 67.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_3 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_3 (FF) + Requirement: 5.000ns + Data Path Delay: 3.884ns (Levels of Logic = 3) + Clock Path Skew: -0.053ns (1.006 - 1.059) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_3 to ftop/ctop/inf/cp/timeServ_refFreeSamp_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y99.DQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<3> + ftop/ctop/inf/cp/timeServ_refFromRise_3 + SLICE_X2Y101.A2 net (fanout=3) 0.743 ftop/ctop/inf/cp/timeServ_refFromRise<3> + SLICE_X2Y101.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y92.CE net (fanout=33) 1.005 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y92.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_3 + ------------------------------------------------- --------------------------- + Total 3.884ns (1.391ns logic, 2.493ns route) + (35.8% logic, 64.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_3 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_2 (FF) + Requirement: 5.000ns + Data Path Delay: 3.884ns (Levels of Logic = 3) + Clock Path Skew: -0.053ns (1.006 - 1.059) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_3 to ftop/ctop/inf/cp/timeServ_refFreeSamp_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y99.DQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<3> + ftop/ctop/inf/cp/timeServ_refFromRise_3 + SLICE_X2Y101.A2 net (fanout=3) 0.743 ftop/ctop/inf/cp/timeServ_refFromRise<3> + SLICE_X2Y101.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y92.CE net (fanout=33) 1.005 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y92.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_2 + ------------------------------------------------- --------------------------- + Total 3.884ns (1.391ns logic, 2.493ns route) + (35.8% logic, 64.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_3 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_1 (FF) + Requirement: 5.000ns + Data Path Delay: 3.884ns (Levels of Logic = 3) + Clock Path Skew: -0.053ns (1.006 - 1.059) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_3 to ftop/ctop/inf/cp/timeServ_refFreeSamp_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y99.DQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<3> + ftop/ctop/inf/cp/timeServ_refFromRise_3 + SLICE_X2Y101.A2 net (fanout=3) 0.743 ftop/ctop/inf/cp/timeServ_refFromRise<3> + SLICE_X2Y101.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y92.CE net (fanout=33) 1.005 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y92.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_1 + ------------------------------------------------- --------------------------- + Total 3.884ns (1.391ns logic, 2.493ns route) + (35.8% logic, 64.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.028ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_3 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_0 (FF) + Requirement: 5.000ns + Data Path Delay: 3.884ns (Levels of Logic = 3) + Clock Path Skew: -0.053ns (1.006 - 1.059) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_3 to ftop/ctop/inf/cp/timeServ_refFreeSamp_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y99.DQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<3> + ftop/ctop/inf/cp/timeServ_refFromRise_3 + SLICE_X2Y101.A2 net (fanout=3) 0.743 ftop/ctop/inf/cp/timeServ_refFromRise<3> + SLICE_X2Y101.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<3> + SLICE_X2Y102.BMUX Tcinb 0.215 ftop/ctop/inf/cp/timeServ_ppsLost + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D5 net (fanout=4) 0.745 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULE_199800000___d48_INV_1111_o_cy<5> + SLICE_X10Y99.D Tilo 0.068 ftop/ctop/inf/cp/timeServ_jamFracVal<27> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X5Y92.CE net (fanout=33) 1.005 ftop/ctop/inf/cp/timeServ_delSecond_EN + SLICE_X5Y92.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_0 + ------------------------------------------------- --------------------------- + Total 3.884ns (1.391ns logic, 2.493ns route) + (35.8% logic, 64.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.032ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_now_4 (FF) + Requirement: 5.000ns + Data Path Delay: 3.813ns (Levels of Logic = 1) + Clock Path Skew: -0.120ns (0.955 - 1.075) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_now_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X7Y114.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X7Y115.A3 net (fanout=3) 0.469 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X7Y115.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_nowInCC/sync/dSyncReg2 + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sRDY1 + SLICE_X28Y85.CE net (fanout=32) 2.655 ftop/ctop/inf/cp/timeServ_nowInCC_sRDY + SLICE_X28Y85.CLK Tceck 0.284 ftop/ctop/cpNow<7> + ftop/ctop/inf/cp/timeServ_now_4 + ------------------------------------------------- --------------------------- + Total 3.813ns (0.689ns logic, 3.124ns route) + (18.1% logic, 81.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.032ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_now_7 (FF) + Requirement: 5.000ns + Data Path Delay: 3.813ns (Levels of Logic = 1) + Clock Path Skew: -0.120ns (0.955 - 1.075) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_now_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X7Y114.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X7Y115.A3 net (fanout=3) 0.469 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X7Y115.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_nowInCC/sync/dSyncReg2 + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sRDY1 + SLICE_X28Y85.CE net (fanout=32) 2.655 ftop/ctop/inf/cp/timeServ_nowInCC_sRDY + SLICE_X28Y85.CLK Tceck 0.284 ftop/ctop/cpNow<7> + ftop/ctop/inf/cp/timeServ_now_7 + ------------------------------------------------- --------------------------- + Total 3.813ns (0.689ns logic, 3.124ns route) + (18.1% logic, 81.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.032ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_now_5 (FF) + Requirement: 5.000ns + Data Path Delay: 3.813ns (Levels of Logic = 1) + Clock Path Skew: -0.120ns (0.955 - 1.075) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_now_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X7Y114.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X7Y115.A3 net (fanout=3) 0.469 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X7Y115.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_nowInCC/sync/dSyncReg2 + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sRDY1 + SLICE_X28Y85.CE net (fanout=32) 2.655 ftop/ctop/inf/cp/timeServ_nowInCC_sRDY + SLICE_X28Y85.CLK Tceck 0.284 ftop/ctop/cpNow<7> + ftop/ctop/inf/cp/timeServ_now_5 + ------------------------------------------------- --------------------------- + Total 3.813ns (0.689ns logic, 3.124ns route) + (18.1% logic, 81.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.032ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_now_6 (FF) + Requirement: 5.000ns + Data Path Delay: 3.813ns (Levels of Logic = 1) + Clock Path Skew: -0.120ns (0.955 - 1.075) + Source Clock: ftop/sys0_clk_O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_now_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X7Y114.CQ Tcko 0.337 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X7Y115.A3 net (fanout=3) 0.469 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X7Y115.A Tilo 0.068 ftop/ctop/inf/cp/timeServ_nowInCC/sync/dSyncReg2 + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sRDY1 + SLICE_X28Y85.CE net (fanout=32) 2.655 ftop/ctop/inf/cp/timeServ_nowInCC_sRDY + SLICE_X28Y85.CLK Tceck 0.284 ftop/ctop/cpNow<7> + ftop/ctop/inf/cp/timeServ_now_6 + ------------------------------------------------- --------------------------- + Total 3.813ns (0.689ns logic, 3.124ns route) + (18.1% logic, 81.9% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.078ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_14 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_30 (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.481 - 0.443) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_14 to ftop/ctop/inf/cp/timeServ_jamFracVal_30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X13Y100.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<15> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_14 + SLICE_X10Y100.CX net (fanout=1) 0.107 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<14> + SLICE_X10Y100.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<31> + ftop/ctop/inf/cp/timeServ_jamFracVal_30 + ------------------------------------------------- --------------------------- + Total 0.116ns (0.009ns logic, 0.107ns route) + (7.8% logic, 92.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.078ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_12 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_28 (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.481 - 0.443) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_12 to ftop/ctop/inf/cp/timeServ_jamFracVal_28 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X13Y100.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<15> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_12 + SLICE_X10Y100.AX net (fanout=1) 0.107 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<12> + SLICE_X10Y100.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<31> + ftop/ctop/inf/cp/timeServ_jamFracVal_28 + ------------------------------------------------- --------------------------- + Total 0.116ns (0.009ns logic, 0.107ns route) + (7.8% logic, 92.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.082ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_19 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_35 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.482 - 0.446) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_19 to ftop/ctop/inf/cp/timeServ_jamFracVal_35 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X17Y104.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<19> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_19 + SLICE_X15Y104.DX net (fanout=1) 0.096 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<19> + SLICE_X15Y104.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<35> + ftop/ctop/inf/cp/timeServ_jamFracVal_35 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.082ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_17 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_33 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.482 - 0.446) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_17 to ftop/ctop/inf/cp/timeServ_jamFracVal_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X17Y104.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<19> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_17 + SLICE_X15Y104.BX net (fanout=1) 0.096 ftop/ctop/inf/cp/timeServ_setRefF_dD_OUT<17> + SLICE_X15Y104.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_jamFracVal<35> + ftop/ctop/inf/cp/timeServ_jamFracVal_33 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 (FF) + Destination: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.103ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.061 - 0.050) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 to ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y148.DQ Tcko 0.098 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<3> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 + SLICE_X110Y148.AX net (fanout=1) 0.094 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<3> + SLICE_X110Y148.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<7> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 + ------------------------------------------------- --------------------------- + Total 0.103ns (0.009ns logic, 0.094ns route) + (8.7% logic, 91.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refPerCount_23 (FF) + Destination: ftop/ctop/inf/cp/timeServ_ppsDrive (FF) + Requirement: 0.000ns + Data Path Delay: 0.104ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refPerCount_23 to ftop/ctop/inf/cp/timeServ_ppsDrive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y121.DQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_refPerCount<23> + ftop/ctop/inf/cp/timeServ_refPerCount_23 + SLICE_X15Y121.B6 net (fanout=2) 0.046 ftop/ctop/inf/cp/timeServ_refPerCount<23> + SLICE_X15Y121.CLK Tah (-Th) 0.057 ftop/ctop/inf/cp/timeServ_ppsDrive + ftop/ctop/inf/cp/timeServ_ppsDrive_D_IN34 + ftop/ctop/inf/cp/timeServ_ppsDrive + ------------------------------------------------- --------------------------- + Total 0.104ns (0.058ns logic, 0.046ns route) + (55.8% logic, 44.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.094ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dEnqPtr_1 (FF) + Destination: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.104ns (Levels of Logic = 1) + Clock Path Skew: 0.010ns (0.057 - 0.047) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dEnqPtr_1 to ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y105.BQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_setRefF/dEnqPtr<1> + ftop/ctop/inf/cp/timeServ_setRefF/dEnqPtr_1 + SLICE_X21Y105.D6 net (fanout=3) 0.046 ftop/ctop/inf/cp/timeServ_setRefF/dEnqPtr<1> + SLICE_X21Y105.CLK Tah (-Th) 0.057 ftop/ctop/inf/cp/timeServ_setRefF_dEMPTY_N + ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg_PWR_47_o_MUX_2436_o1 + ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg + ------------------------------------------------- --------------------------- + Total 0.104ns (0.058ns logic, 0.046ns route) + (55.8% logic, 44.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.098ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.134ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.497 - 0.461) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_2 to ftop/ctop/inf/cp/timeServ_refFreeSamp_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y92.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<3> + ftop/ctop/inf/cp/timeServ_refFreeCount_2 + SLICE_X5Y92.CX net (fanout=4) 0.112 ftop/ctop/inf/cp/timeServ_refFreeCount<2> + SLICE_X5Y92.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_2 + ------------------------------------------------- --------------------------- + Total 0.134ns (0.022ns logic, 0.112ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.098ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_27 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_27 (FF) + Requirement: 0.000ns + Data Path Delay: 0.132ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.489 - 0.455) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_27 to ftop/ctop/inf/cp/timeServ_refFreeSamp_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y98.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<27> + ftop/ctop/inf/cp/timeServ_refFreeCount_27 + SLICE_X5Y98.DX net (fanout=3) 0.110 ftop/ctop/inf/cp/timeServ_refFreeCount<27> + SLICE_X5Y98.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refFreeSamp<27> + ftop/ctop/inf/cp/timeServ_refFreeSamp_27 + ------------------------------------------------- --------------------------- + Total 0.132ns (0.022ns logic, 0.110ns route) + (16.7% logic, 83.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.098ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_now_37 (FF) + Destination: ftop/ctop/inf/itc1/now/sDataSyncIn_37 (FF) + Requirement: 0.000ns + Data Path Delay: 0.110ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.056 - 0.044) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_now_37 to ftop/ctop/inf/itc1/now/sDataSyncIn_37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y97.BQ Tcko 0.098 ftop/ctop/cpNow<39> + ftop/ctop/inf/cp/timeServ_now_37 + SLICE_X42Y95.BX net (fanout=2) 0.101 ftop/ctop/cpNow<37> + SLICE_X42Y95.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/itc1/now/sDataSyncIn<39> + ftop/ctop/inf/itc1/now/sDataSyncIn_37 + ------------------------------------------------- --------------------------- + Total 0.110ns (0.009ns logic, 0.101ns route) + (8.2% logic, 91.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.098ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_now_39 (FF) + Destination: ftop/ctop/inf/itc1/now/sDataSyncIn_39 (FF) + Requirement: 0.000ns + Data Path Delay: 0.110ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.056 - 0.044) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_now_39 to ftop/ctop/inf/itc1/now/sDataSyncIn_39 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y97.DQ Tcko 0.098 ftop/ctop/cpNow<39> + ftop/ctop/inf/cp/timeServ_now_39 + SLICE_X42Y95.DX net (fanout=2) 0.101 ftop/ctop/cpNow<39> + SLICE_X42Y95.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/itc1/now/sDataSyncIn<39> + ftop/ctop/inf/itc1/now/sDataSyncIn_39 + ------------------------------------------------- --------------------------- + Total 0.110ns (0.009ns logic, 0.101ns route) + (8.2% logic, 91.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.099ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_6 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_6 (FF) + Requirement: 0.000ns + Data Path Delay: 0.134ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.495 - 0.460) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_6 to ftop/ctop/inf/cp/timeServ_refFreeSamp_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y93.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<7> + ftop/ctop/inf/cp/timeServ_refFreeCount_6 + SLICE_X5Y93.CX net (fanout=4) 0.112 ftop/ctop/inf/cp/timeServ_refFreeCount<6> + SLICE_X5Y93.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refFreeSamp<7> + ftop/ctop/inf/cp/timeServ_refFreeSamp_6 + ------------------------------------------------- --------------------------- + Total 0.134ns (0.022ns logic, 0.112ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.099ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_now_36 (FF) + Destination: ftop/ctop/inf/itc1/now/sDataSyncIn_36 (FF) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.056 - 0.044) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_now_36 to ftop/ctop/inf/itc1/now/sDataSyncIn_36 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y97.AQ Tcko 0.098 ftop/ctop/cpNow<39> + ftop/ctop/inf/cp/timeServ_now_36 + SLICE_X42Y95.AX net (fanout=2) 0.102 ftop/ctop/cpNow<36> + SLICE_X42Y95.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/itc1/now/sDataSyncIn<39> + ftop/ctop/inf/itc1/now/sDataSyncIn_36 + ------------------------------------------------- --------------------------- + Total 0.111ns (0.009ns logic, 0.102ns route) + (8.1% logic, 91.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.099ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_10 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_10 (FF) + Requirement: 0.000ns + Data Path Delay: 0.134ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.494 - 0.459) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_10 to ftop/ctop/inf/cp/timeServ_refFreeSamp_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y94.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<11> + ftop/ctop/inf/cp/timeServ_refFreeCount_10 + SLICE_X5Y94.CX net (fanout=4) 0.112 ftop/ctop/inf/cp/timeServ_refFreeCount<10> + SLICE_X5Y94.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refFreeSamp<11> + ftop/ctop/inf/cp/timeServ_refFreeSamp_10 + ------------------------------------------------- --------------------------- + Total 0.134ns (0.022ns logic, 0.112ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.099ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_8 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_8 (FF) + Requirement: 0.000ns + Data Path Delay: 0.134ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.494 - 0.459) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_8 to ftop/ctop/inf/cp/timeServ_refFreeSamp_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y94.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<11> + ftop/ctop/inf/cp/timeServ_refFreeCount_8 + SLICE_X5Y94.AX net (fanout=4) 0.112 ftop/ctop/inf/cp/timeServ_refFreeCount<8> + SLICE_X5Y94.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refFreeSamp<11> + ftop/ctop/inf/cp/timeServ_refFreeSamp_8 + ------------------------------------------------- --------------------------- + Total 0.134ns (0.022ns logic, 0.112ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.099ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_1 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.135ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.497 - 0.461) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_1 to ftop/ctop/inf/cp/timeServ_refFreeSamp_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y92.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<3> + ftop/ctop/inf/cp/timeServ_refFreeCount_1 + SLICE_X5Y92.BX net (fanout=4) 0.113 ftop/ctop/inf/cp/timeServ_refFreeCount<1> + SLICE_X5Y92.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_1 + ------------------------------------------------- --------------------------- + Total 0.135ns (0.022ns logic, 0.113ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.099ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_4 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.134ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.495 - 0.460) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_4 to ftop/ctop/inf/cp/timeServ_refFreeSamp_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y93.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<7> + ftop/ctop/inf/cp/timeServ_refFreeCount_4 + SLICE_X5Y93.AX net (fanout=4) 0.112 ftop/ctop/inf/cp/timeServ_refFreeCount<4> + SLICE_X5Y93.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refFreeSamp<7> + ftop/ctop/inf/cp/timeServ_refFreeSamp_4 + ------------------------------------------------- --------------------------- + Total 0.134ns (0.022ns logic, 0.112ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.099ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_3 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.135ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.497 - 0.461) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_3 to ftop/ctop/inf/cp/timeServ_refFreeSamp_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y92.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<3> + ftop/ctop/inf/cp/timeServ_refFreeCount_3 + SLICE_X5Y92.DX net (fanout=4) 0.113 ftop/ctop/inf/cp/timeServ_refFreeCount<3> + SLICE_X5Y92.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refFreeSamp<3> + ftop/ctop/inf/cp/timeServ_refFreeSamp_3 + ------------------------------------------------- --------------------------- + Total 0.135ns (0.022ns logic, 0.113ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.099ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_now_38 (FF) + Destination: ftop/ctop/inf/itc1/now/sDataSyncIn_38 (FF) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.056 - 0.044) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_now_38 to ftop/ctop/inf/itc1/now/sDataSyncIn_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X43Y97.CQ Tcko 0.098 ftop/ctop/cpNow<39> + ftop/ctop/inf/cp/timeServ_now_38 + SLICE_X42Y95.CX net (fanout=2) 0.102 ftop/ctop/cpNow<38> + SLICE_X42Y95.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/itc1/now/sDataSyncIn<39> + ftop/ctop/inf/itc1/now/sDataSyncIn_38 + ------------------------------------------------- --------------------------- + Total 0.111ns (0.009ns logic, 0.102ns route) + (8.1% logic, 91.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.100ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_refFreeCount_5 (FF) + Destination: ftop/ctop/inf/cp/timeServ_refFreeSamp_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.135ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.495 - 0.460) + Source Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk_O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_refFreeCount_5 to ftop/ctop/inf/cp/timeServ_refFreeSamp_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y93.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_refFreeCount<7> + ftop/ctop/inf/cp/timeServ_refFreeCount_5 + SLICE_X5Y93.BX net (fanout=4) 0.113 ftop/ctop/inf/cp/timeServ_refFreeCount<5> + SLICE_X5Y93.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_refFreeSamp<7> + ftop/ctop/inf/cp/timeServ_refFreeSamp_5 + ------------------------------------------------- --------------------------- + Total 0.135ns (0.022ns logic, 0.113ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate1/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate1/REFCLK + Location pin: IDELAYCTRL_X1Y3.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK + Location pin: IDELAYCTRL_X1Y4.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate5/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate5/REFCLK + Location pin: IDELAYCTRL_X2Y1.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate7/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate7/REFCLK + Location pin: IDELAYCTRL_X2Y3.REFCLK + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 1.072ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT0 + Location pin: MMCM_ADV_X0Y6.CLKOUT0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- +Slack: 1.072ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT2 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT2 + Location pin: MMCM_ADV_X0Y6.CLKOUT2 + Clock network: ftop/dram0/memc_memc/clk_wr_i +-------------------------------------------------------------------------------- +Slack: 2.200ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 2.200ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 3.571ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/sys0_clk_O_BUFG/I0 + Logical resource: ftop/sys0_clk_O_BUFG/I0 + Location pin: BUFGCTRL_X0Y1.I0 + Clock network: ftop/sys0_clk_O +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKIN(Finmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk_O_BUFG +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKFBOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKFBOUT + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKFBOUT + Location pin: MMCM_ADV_X0Y6.CLKFBOUT + Clock network: ftop/dram0/memc_memc/u_infrastructure/clkfbout_pll +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT1 + Location pin: MMCM_ADV_X0Y6.CLKOUT1 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_pll +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dLastState/SR + Location pin: SLICE_X0Y113.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg1/SR + Location pin: SLICE_X0Y113.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/dSyncReg2/SR + Location pin: SLICE_X0Y113.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsDisablePPS/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dLastState/SR + Location pin: SLICE_X1Y89.SR + Clock network: ftop/ctop/inf/cp/timeServ_disableServo/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg1/SR + Location pin: SLICE_X1Y89.SR + Clock network: ftop/ctop/inf/cp/timeServ_disableServo/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dSyncReg2/SR + Location pin: SLICE_X1Y89.SR + Clock network: ftop/ctop/inf/cp/timeServ_disableServo/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsOutMode/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsOutMode/sync/dSyncReg1/SR + Location pin: SLICE_X1Y104.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsOutMode/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsOutMode/sync/dSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsOutMode/sync/dSyncReg2/SR + Location pin: SLICE_X1Y104.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsOutMode/sync/sRST_inv +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 MHz HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.538ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y15.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y15.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y14.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y14.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y13.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y13.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y12.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y12.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk_O +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% +PRIORITY 100; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 11104609 paths analyzed, 145861 endpoints analyzed, 38 failing endpoints + 38 timing errors detected. (37 setup errors, 1 hold error, 0 component switching limit errors) + Minimum period is 8.251ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.251ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_15 (FF) + Requirement: 8.000ns + Data Path Delay: 7.982ns (Levels of Logic = 10) + Clock Path Skew: -0.200ns (1.551 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y82.CE net (fanout=12) 0.522 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<15> + ftop/ctop/inf/cp/cpRespF/data1_reg_15 + ------------------------------------------------- --------------------------- + Total 7.982ns (1.503ns logic, 6.479ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.225ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_15 (FF) + Requirement: 8.000ns + Data Path Delay: 7.956ns (Levels of Logic = 10) + Clock Path Skew: -0.200ns (1.551 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X75Y64.A6 net (fanout=75) 0.477 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X75Y64.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T1 + SLICE_X75Y64.B2 net (fanout=25) 0.592 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T + SLICE_X75Y64.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X77Y65.C4 net (fanout=1) 0.400 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y82.CE net (fanout=12) 0.522 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<15> + ftop/ctop/inf/cp/cpRespF/data1_reg_15 + ------------------------------------------------- --------------------------- + Total 7.956ns (1.503ns logic, 6.453ns route) + (18.9% logic, 81.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.214ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_15 (FF) + Requirement: 8.000ns + Data Path Delay: 7.945ns (Levels of Logic = 10) + Clock Path Skew: -0.200ns (1.551 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X68Y62.B6 net (fanout=75) 0.340 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X68Y62.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_D_OUT<25> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T1 + SLICE_X77Y63.D6 net (fanout=14) 0.536 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T + SLICE_X77Y63.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead10 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead10 + SLICE_X77Y65.C3 net (fanout=1) 0.582 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead10 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y82.CE net (fanout=12) 0.522 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<15> + ftop/ctop/inf/cp/cpRespF/data1_reg_15 + ------------------------------------------------- --------------------------- + Total 7.945ns (1.503ns logic, 6.442ns route) + (18.9% logic, 81.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.177ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_15 (FF) + Requirement: 8.000ns + Data Path Delay: 7.908ns (Levels of Logic = 10) + Clock Path Skew: -0.200ns (1.551 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y68.C6 net (fanout=75) 0.482 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y68.C Tilo 0.068 ftop/ctop/inf/cp/wci_12_respF_D_OUT<19> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T1 + SLICE_X72Y64.D6 net (fanout=27) 0.509 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y82.CE net (fanout=12) 0.522 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<15> + ftop/ctop/inf/cp/cpRespF/data1_reg_15 + ------------------------------------------------- --------------------------- + Total 7.908ns (1.503ns logic, 6.405ns route) + (19.0% logic, 81.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.172ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_4_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_15 (FF) + Requirement: 8.000ns + Data Path Delay: 7.910ns (Levels of Logic = 9) + Clock Path Skew: -0.193ns (1.551 - 1.744) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_4_respF/empty_reg to ftop/ctop/inf/cp/cpRespF/data1_reg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y62.BQ Tcko 0.337 ftop/ctop/inf/cp/wci_4_respF_EMPTY_N + ftop/ctop/inf/cp/wci_4_respF/empty_reg + SLICE_X83Y59.D6 net (fanout=24) 0.549 ftop/ctop/inf/cp/wci_4_respF_EMPTY_N + SLICE_X83Y59.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_busy + ftop/ctop/inf/cp/wci_4_busy_wci_4_respF_FULL_N_AND_4368_o1 + SLICE_X85Y65.C2 net (fanout=2) 0.934 ftop/ctop/inf/cp/wci_4_busy_wci_4_respF_FULL_N_AND_4368_o + SLICE_X85Y65.BMUX Topcb 0.412 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_51 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y82.CE net (fanout=12) 0.522 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<15> + ftop/ctop/inf/cp/cpRespF/data1_reg_15 + ------------------------------------------------- --------------------------- + Total 7.910ns (1.611ns logic, 6.299ns route) + (20.4% logic, 79.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.169ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_15 (FF) + Requirement: 8.000ns + Data Path Delay: 7.900ns (Levels of Logic = 10) + Clock Path Skew: -0.200ns (1.551 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X73Y64.A6 net (fanout=75) 0.318 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X73Y64.A Tilo 0.068 ftop/ctop/inf/cp/wci_14_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T1 + SLICE_X73Y65.D2 net (fanout=6) 0.736 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T + SLICE_X73Y65.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead29 + SLICE_X73Y65.C6 net (fanout=1) 0.110 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead29 + SLICE_X73Y65.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30 + SLICE_X77Y66.A2 net (fanout=1) 0.710 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y82.CE net (fanout=12) 0.522 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<15> + ftop/ctop/inf/cp/cpRespF/data1_reg_15 + ------------------------------------------------- --------------------------- + Total 7.900ns (1.503ns logic, 6.397ns route) + (19.0% logic, 81.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.162ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_15 (FF) + Requirement: 8.000ns + Data Path Delay: 7.893ns (Levels of Logic = 9) + Clock Path Skew: -0.200ns (1.551 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X79Y60.C6 net (fanout=9) 0.717 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X79Y60.C Tilo 0.068 ftop/ctop/inf/cp/dispatched_EN1112 + ftop/ctop/inf/cp/_n13601<34>2_REPLICA_52 + SLICE_X77Y58.C6 net (fanout=5) 0.394 ftop/ctop/inf/cp/_n13601<34>2_REPLICA_52 + SLICE_X77Y58.C Tilo 0.068 ftop/ctop/inf/cp/wci_11_respF_D_OUT<19> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T1 + SLICE_X73Y65.C3 net (fanout=25) 0.893 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T + SLICE_X73Y65.C Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead29 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30 + SLICE_X77Y66.A2 net (fanout=1) 0.710 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead30 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y82.CE net (fanout=12) 0.522 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<15> + ftop/ctop/inf/cp/cpRespF/data1_reg_15 + ------------------------------------------------- --------------------------- + Total 7.893ns (1.435ns logic, 6.458ns route) + (18.2% logic, 81.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.151ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_14 (FF) + Requirement: 8.000ns + Data Path Delay: 7.882ns (Levels of Logic = 10) + Clock Path Skew: -0.200ns (1.551 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y83.CE net (fanout=12) 0.422 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y83.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF/data1_reg_14 + ------------------------------------------------- --------------------------- + Total 7.882ns (1.503ns logic, 6.379ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.151ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_12 (FF) + Requirement: 8.000ns + Data Path Delay: 7.882ns (Levels of Logic = 10) + Clock Path Skew: -0.200ns (1.551 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y83.CE net (fanout=12) 0.422 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y83.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF/data1_reg_12 + ------------------------------------------------- --------------------------- + Total 7.882ns (1.503ns logic, 6.379ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.150ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_17 (FF) + Requirement: 8.000ns + Data Path Delay: 7.879ns (Levels of Logic = 10) + Clock Path Skew: -0.202ns (1.549 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X85Y86.CE net (fanout=12) 0.419 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X85Y86.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<19> + ftop/ctop/inf/cp/cpRespF/data1_reg_17 + ------------------------------------------------- --------------------------- + Total 7.879ns (1.503ns logic, 6.376ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.150ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_16 (FF) + Requirement: 8.000ns + Data Path Delay: 7.879ns (Levels of Logic = 10) + Clock Path Skew: -0.202ns (1.549 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X85Y86.CE net (fanout=12) 0.419 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X85Y86.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<19> + ftop/ctop/inf/cp/cpRespF/data1_reg_16 + ------------------------------------------------- --------------------------- + Total 7.879ns (1.503ns logic, 6.376ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.150ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_18 (FF) + Requirement: 8.000ns + Data Path Delay: 7.879ns (Levels of Logic = 10) + Clock Path Skew: -0.202ns (1.549 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X85Y86.CE net (fanout=12) 0.419 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X85Y86.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<19> + ftop/ctop/inf/cp/cpRespF/data1_reg_18 + ------------------------------------------------- --------------------------- + Total 7.879ns (1.503ns logic, 6.376ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.150ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_19 (FF) + Requirement: 8.000ns + Data Path Delay: 7.879ns (Levels of Logic = 10) + Clock Path Skew: -0.202ns (1.549 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X85Y86.CE net (fanout=12) 0.419 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X85Y86.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<19> + ftop/ctop/inf/cp/cpRespF/data1_reg_19 + ------------------------------------------------- --------------------------- + Total 7.879ns (1.503ns logic, 6.376ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.146ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_4_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_15 (FF) + Requirement: 8.000ns + Data Path Delay: 7.884ns (Levels of Logic = 9) + Clock Path Skew: -0.193ns (1.551 - 1.744) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_4_respF/empty_reg to ftop/ctop/inf/cp/cpRespF/data1_reg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y62.BQ Tcko 0.337 ftop/ctop/inf/cp/wci_4_respF_EMPTY_N + ftop/ctop/inf/cp/wci_4_respF/empty_reg + SLICE_X83Y59.D6 net (fanout=24) 0.549 ftop/ctop/inf/cp/wci_4_respF_EMPTY_N + SLICE_X83Y59.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_busy + ftop/ctop/inf/cp/wci_4_busy_wci_4_respF_FULL_N_AND_4368_o1 + SLICE_X85Y65.C2 net (fanout=2) 0.934 ftop/ctop/inf/cp/wci_4_busy_wci_4_respF_FULL_N_AND_4368_o + SLICE_X85Y65.BMUX Topcb 0.412 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_51 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X75Y64.A6 net (fanout=75) 0.477 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X75Y64.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T1 + SLICE_X75Y64.B2 net (fanout=25) 0.592 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T + SLICE_X75Y64.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X77Y65.C4 net (fanout=1) 0.400 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead8 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y82.CE net (fanout=12) 0.522 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<15> + ftop/ctop/inf/cp/cpRespF/data1_reg_15 + ------------------------------------------------- --------------------------- + Total 7.884ns (1.611ns logic, 6.273ns route) + (20.4% logic, 79.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.138ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_6 (FF) + Requirement: 8.000ns + Data Path Delay: 7.868ns (Levels of Logic = 10) + Clock Path Skew: -0.201ns (1.550 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X85Y85.CE net (fanout=12) 0.408 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X85Y85.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<7> + ftop/ctop/inf/cp/cpRespF/data1_reg_6 + ------------------------------------------------- --------------------------- + Total 7.868ns (1.503ns logic, 6.365ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.138ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_4 (FF) + Requirement: 8.000ns + Data Path Delay: 7.868ns (Levels of Logic = 10) + Clock Path Skew: -0.201ns (1.550 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X85Y85.CE net (fanout=12) 0.408 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X85Y85.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<7> + ftop/ctop/inf/cp/cpRespF/data1_reg_4 + ------------------------------------------------- --------------------------- + Total 7.868ns (1.503ns logic, 6.365ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.138ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_7 (FF) + Requirement: 8.000ns + Data Path Delay: 7.868ns (Levels of Logic = 10) + Clock Path Skew: -0.201ns (1.550 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X85Y85.CE net (fanout=12) 0.408 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X85Y85.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<7> + ftop/ctop/inf/cp/cpRespF/data1_reg_7 + ------------------------------------------------- --------------------------- + Total 7.868ns (1.503ns logic, 6.365ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.138ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_5 (FF) + Requirement: 8.000ns + Data Path Delay: 7.868ns (Levels of Logic = 10) + Clock Path Skew: -0.201ns (1.550 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X71Y64.D6 net (fanout=75) 0.450 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X71Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T1 + SLICE_X72Y64.D2 net (fanout=14) 0.615 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X85Y85.CE net (fanout=12) 0.408 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X85Y85.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<7> + ftop/ctop/inf/cp/cpRespF/data1_reg_5 + ------------------------------------------------- --------------------------- + Total 7.868ns (1.503ns logic, 6.365ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.135ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_15 (FF) + Requirement: 8.000ns + Data Path Delay: 7.866ns (Levels of Logic = 10) + Clock Path Skew: -0.200ns (1.551 - 1.751) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpRespF/data1_reg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X86Y65.AQ Tcko 0.337 ftop/ctop/inf/cp/cpReq<26> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X87Y61.B3 net (fanout=37) 0.628 ftop/ctop/inf/cp/cpReq<24> + SLICE_X87Y61.B Tilo 0.068 ftop/ctop/inf/cp/wci_2_reqF_cntr_r + ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d24372111 + SLICE_X85Y67.D6 net (fanout=6) 0.528 ftop/ctop/inf/cp/cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437211 + SLICE_X85Y67.D Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573941 + SLICE_X85Y65.BX net (fanout=31) 0.507 ftop/ctop/inf/cp/_theResult_____1__h75739<3> + SLICE_X85Y65.BMUX Tbxb 0.236 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X70Y63.B6 net (fanout=75) 0.208 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X70Y63.B Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T1 + SLICE_X72Y64.D1 net (fanout=12) 0.741 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T + SLICE_X72Y64.D Tilo 0.068 ftop/ctop/inf/cp/wci_5_respF_D_OUT<31> + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C5 net (fanout=1) 0.430 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead9 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y82.CE net (fanout=12) 0.522 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<15> + ftop/ctop/inf/cp/cpRespF/data1_reg_15 + ------------------------------------------------- --------------------------- + Total 7.866ns (1.503ns logic, 6.363ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.135ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_4_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpRespF/data1_reg_15 (FF) + Requirement: 8.000ns + Data Path Delay: 7.873ns (Levels of Logic = 9) + Clock Path Skew: -0.193ns (1.551 - 1.744) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_4_respF/empty_reg to ftop/ctop/inf/cp/cpRespF/data1_reg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y62.BQ Tcko 0.337 ftop/ctop/inf/cp/wci_4_respF_EMPTY_N + ftop/ctop/inf/cp/wci_4_respF/empty_reg + SLICE_X83Y59.D6 net (fanout=24) 0.549 ftop/ctop/inf/cp/wci_4_respF_EMPTY_N + SLICE_X83Y59.D Tilo 0.068 ftop/ctop/inf/cp/wci_4_busy + ftop/ctop/inf/cp/wci_4_busy_wci_4_respF_FULL_N_AND_4368_o1 + SLICE_X85Y65.C2 net (fanout=2) 0.934 ftop/ctop/inf/cp/wci_4_busy_wci_4_respF_FULL_N_AND_4368_o + SLICE_X85Y65.BMUX Topcb 0.412 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_51 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X70Y63.D6 net (fanout=9) 0.779 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X70Y63.D Tilo 0.068 ftop/ctop/inf/cp/_n13601<34>2 + ftop/ctop/inf/cp/_n13601<34>21 + SLICE_X68Y62.B6 net (fanout=75) 0.340 ftop/ctop/inf/cp/_n13601<34>2 + SLICE_X68Y62.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF_D_OUT<25> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T1 + SLICE_X77Y63.D6 net (fanout=14) 0.536 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T + SLICE_X77Y63.D Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead10 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead10 + SLICE_X77Y65.C3 net (fanout=1) 0.582 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead10 + SLICE_X77Y65.C Tilo 0.068 ftop/ctop/inf/cp/wci_5_wReset_n + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A3 net (fanout=1) 0.461 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead19 + SLICE_X77Y66.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead31 + SLICE_X87Y83.A6 net (fanout=20) 1.298 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X87Y83.A Tilo 0.068 ftop/ctop/inf/cp/cpRespF/data1_reg<14> + ftop/ctop/inf/cp/cpRespF_ENQ1 + SLICE_X86Y84.C6 net (fanout=7) 0.261 ftop/ctop/inf/cp/cpRespF_ENQ + SLICE_X86Y84.C Tilo 0.068 ftop/ctop/inf/cp_server_response_get<39> + ftop/ctop/inf/cp/cpRespF/d1di1 + SLICE_X87Y82.CE net (fanout=12) 0.522 ftop/ctop/inf/cp/cpRespF/d1di + SLICE_X87Y82.CLK Tceck 0.318 ftop/ctop/inf/cp/cpRespF/data1_reg<15> + ftop/ctop/inf/cp/cpRespF/data1_reg_15 + ------------------------------------------------- --------------------------- + Total 7.873ns (1.611ns logic, 6.262ns route) + (20.5% logic, 79.5% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% PRIORITY 100; +-------------------------------------------------------------------------------- +Slack (hold path): -0.100ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pAF_head_wrapped (FF) + Destination: ftop/pciw_i2pAF_tail_wrapped (FF) + Requirement: 0.000ns + Data Path Delay: 0.161ns (Levels of Logic = 1) + Clock Path Skew: 0.072ns (1.154 - 1.082) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pAF_head_wrapped to ftop/pciw_i2pAF_tail_wrapped + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y159.AQ Tcko 0.098 ftop/pciw_i2pAF_head_wrapped + ftop/pciw_i2pAF_head_wrapped + SLICE_X135Y159.A6 net (fanout=7) 0.118 ftop/pciw_i2pAF_head_wrapped + SLICE_X135Y159.CLK Tah (-Th) 0.055 ftop/pciw_i2pAF_tail_wrapped + ftop/WILL_FIRE_RL_pciw_i2pAF_enq_update_tail11 + ftop/pciw_i2pAF_tail_wrapped + ------------------------------------------------- --------------------------- + Total 0.161ns (0.043ns logic, 0.118ns route) + (26.7% logic, 73.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.010ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_6 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_6_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.269ns (Levels of Logic = 0) + Clock Path Skew: 0.070ns (1.192 - 1.122) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_6 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_6_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y185.CQ Tcko 0.115 ftop/pciw_p2iS<7> + ftop/pciw_p2iS_6 + SLICE_X128Y185.CX net (fanout=1) 0.184 ftop/pciw_p2iS<6> + SLICE_X128Y185.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<7> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_6_0 + ------------------------------------------------- --------------------------- + Total 0.269ns (0.085ns logic, 0.184ns route) + (31.6% logic, 68.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.012ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_5 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_5_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.271ns (Levels of Logic = 0) + Clock Path Skew: 0.070ns (1.192 - 1.122) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_5 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_5_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y185.BQ Tcko 0.115 ftop/pciw_p2iS<7> + ftop/pciw_p2iS_5 + SLICE_X128Y185.BX net (fanout=1) 0.183 ftop/pciw_p2iS<5> + SLICE_X128Y185.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<7> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_5_0 + ------------------------------------------------- --------------------------- + Total 0.271ns (0.088ns logic, 0.183ns route) + (32.5% logic, 67.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/wci_9_pageWindow_8 (FF) + Destination: ftop/ctop/inf/cp/wci_9_respF/D_OUT_8 (FF) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 1) + Clock Path Skew: 0.112ns (0.786 - 0.674) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/wci_9_pageWindow_8 to ftop/ctop/inf/cp/wci_9_respF/D_OUT_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y80.AQ Tcko 0.098 ftop/ctop/inf/cp/wci_9_pageWindow<11> + ftop/ctop/inf/cp/wci_9_pageWindow_8 + SLICE_X63Y79.B6 net (fanout=1) 0.088 ftop/ctop/inf/cp/wci_9_pageWindow<8> + SLICE_X63Y79.CLK Tah (-Th) 0.057 ftop/ctop/inf/cp/wci_9_respF_D_OUT<9> + ftop/ctop/inf/cp/_n13698<26> + ftop/ctop/inf/cp/wci_9_respF/D_OUT_8 + ------------------------------------------------- --------------------------- + Total 0.129ns (0.041ns logic, 0.088ns route) + (31.8% logic, 68.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.055ns (Levels of Logic = 0) + Clock Path Skew: 0.033ns (0.478 - 0.445) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X161Y101.CQ Tcko 0.098 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.D1 net (fanout=10) 0.236 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/_n0101<5> + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMB + ------------------------------------------------- --------------------------- + Total 0.055ns (-0.181ns logic, 0.236ns route) + (-329.1% logic, 429.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.055ns (Levels of Logic = 0) + Clock Path Skew: 0.033ns (0.478 - 0.445) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X161Y101.CQ Tcko 0.098 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.D1 net (fanout=10) 0.236 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/_n0101<5> + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.055ns (-0.181ns logic, 0.236ns route) + (-329.1% logic, 429.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.055ns (Levels of Logic = 0) + Clock Path Skew: 0.033ns (0.478 - 0.445) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X161Y101.CQ Tcko 0.098 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.D1 net (fanout=10) 0.236 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/_n0101<5> + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMC + ------------------------------------------------- --------------------------- + Total 0.055ns (-0.181ns logic, 0.236ns route) + (-329.1% logic, 429.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pciDevice/sDataSyncIn_13 (FF) + Destination: ftop/pciw_pciDevice/dD_OUT_13 (FF) + Requirement: 0.000ns + Data Path Delay: 0.284ns (Levels of Logic = 0) + Clock Path Skew: 0.073ns (1.150 - 1.077) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pciDevice/sDataSyncIn_13 to ftop/pciw_pciDevice/dD_OUT_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y115.BQ Tcko 0.098 ftop/pciw_pciDevice/sDataSyncIn<15> + ftop/pciw_pciDevice/sDataSyncIn_13 + SLICE_X120Y115.BX net (fanout=1) 0.275 ftop/pciw_pciDevice/sDataSyncIn<13> + SLICE_X120Y115.CLK Tckdi (-Th) 0.089 ftop/pciw_pciDevice_dD_OUT<15> + ftop/pciw_pciDevice/dD_OUT_13 + ------------------------------------------------- --------------------------- + Total 0.284ns (0.009ns logic, 0.275ns route) + (3.2% logic, 96.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.055ns (Levels of Logic = 0) + Clock Path Skew: 0.033ns (0.478 - 0.445) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X161Y101.CQ Tcko 0.098 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.D1 net (fanout=10) 0.236 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/_n0101<5> + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.055ns (-0.181ns logic, 0.236ns route) + (-329.1% logic, 429.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD (RAM) + Requirement: 0.000ns + Data Path Delay: 0.055ns (Levels of Logic = 0) + Clock Path Skew: 0.033ns (0.478 - 0.445) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X161Y101.CQ Tcko 0.098 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.D1 net (fanout=10) 0.236 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/_n0101<5> + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD + ------------------------------------------------- --------------------------- + Total 0.055ns (-0.181ns logic, 0.236ns route) + (-329.1% logic, 429.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.055ns (Levels of Logic = 0) + Clock Path Skew: 0.033ns (0.478 - 0.445) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X161Y101.CQ Tcko 0.098 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.D1 net (fanout=10) 0.236 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/_n0101<5> + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 0.055ns (-0.181ns logic, 0.236ns route) + (-329.1% logic, 429.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMC_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.055ns (Levels of Logic = 0) + Clock Path Skew: 0.033ns (0.478 - 0.445) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X161Y101.CQ Tcko 0.098 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.D1 net (fanout=10) 0.236 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/_n0101<5> + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 0.055ns (-0.181ns logic, 0.236ns route) + (-329.1% logic, 429.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.055ns (Levels of Logic = 0) + Clock Path Skew: 0.033ns (0.478 - 0.445) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X161Y101.CQ Tcko 0.098 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.D1 net (fanout=10) 0.236 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/tail_0_0 + SLICE_X158Y101.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/_n0101<5> + ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMA + ------------------------------------------------- --------------------------- + Total 0.055ns (-0.181ns logic, 0.236ns route) + (-329.1% logic, 429.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_71 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_71_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.278ns (Levels of Logic = 0) + Clock Path Skew: 0.067ns (1.203 - 1.136) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_71 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_71_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y188.DQ Tcko 0.098 ftop/pciw_p2iS<71> + ftop/pciw_p2iS_71 + SLICE_X138Y181.DX net (fanout=1) 0.218 ftop/pciw_p2iS<71> + SLICE_X138Y181.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<71> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_71_0 + ------------------------------------------------- --------------------------- + Total 0.278ns (0.060ns logic, 0.218ns route) + (21.6% logic, 78.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.023ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_68 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_68_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.279ns (Levels of Logic = 0) + Clock Path Skew: 0.067ns (1.203 - 1.136) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_68 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_68_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y188.AQ Tcko 0.098 ftop/pciw_p2iS<71> + ftop/pciw_p2iS_68 + SLICE_X138Y181.AX net (fanout=1) 0.217 ftop/pciw_p2iS<68> + SLICE_X138Y181.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<71> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_68_0 + ------------------------------------------------- --------------------------- + Total 0.279ns (0.062ns logic, 0.217ns route) + (22.2% logic, 77.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.023ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pciDevice/sDataSyncIn_15 (FF) + Destination: ftop/pciw_pciDevice/dD_OUT_15 (FF) + Requirement: 0.000ns + Data Path Delay: 0.285ns (Levels of Logic = 0) + Clock Path Skew: 0.073ns (1.150 - 1.077) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pciDevice/sDataSyncIn_15 to ftop/pciw_pciDevice/dD_OUT_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y115.DQ Tcko 0.098 ftop/pciw_pciDevice/sDataSyncIn<15> + ftop/pciw_pciDevice/sDataSyncIn_15 + SLICE_X120Y115.DX net (fanout=1) 0.276 ftop/pciw_pciDevice/sDataSyncIn<15> + SLICE_X120Y115.CLK Tckdi (-Th) 0.089 ftop/pciw_pciDevice_dD_OUT<15> + ftop/pciw_pciDevice/dD_OUT_15 + ------------------------------------------------- --------------------------- + Total 0.285ns (0.009ns logic, 0.276ns route) + (3.2% logic, 96.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.025ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_96 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_96_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.283ns (Levels of Logic = 0) + Clock Path Skew: 0.069ns (1.201 - 1.132) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_96 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_96_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y189.AQ Tcko 0.098 ftop/pciw_p2iS<99> + ftop/pciw_p2iS_96 + SLICE_X138Y180.AX net (fanout=1) 0.221 ftop/pciw_p2iS<96> + SLICE_X138Y180.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<99> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_96_0 + ------------------------------------------------- --------------------------- + Total 0.283ns (0.062ns logic, 0.221ns route) + (21.9% logic, 78.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_70 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_70_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.283ns (Levels of Logic = 0) + Clock Path Skew: 0.067ns (1.203 - 1.136) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_70 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_70_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y188.CQ Tcko 0.098 ftop/pciw_p2iS<71> + ftop/pciw_p2iS_70 + SLICE_X138Y181.CX net (fanout=1) 0.215 ftop/pciw_p2iS<70> + SLICE_X138Y181.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi_D_OUT<71> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_59_o_dat[15][152]_wide_mux_5_OUT_70_0 + ------------------------------------------------- --------------------------- + Total 0.283ns (0.068ns logic, 0.215ns route) + (24.0% logic, 76.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/wci_9_wStatus_20 (FF) + Destination: ftop/ctop/inf/cp/wci_9_respF/D_OUT_20 (FF) + Requirement: 0.000ns + Data Path Delay: 0.137ns (Levels of Logic = 1) + Clock Path Skew: 0.110ns (0.786 - 0.676) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/wci_9_wStatus_20 to ftop/ctop/inf/cp/wci_9_respF/D_OUT_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X63Y80.DQ Tcko 0.098 ftop/ctop/inf/cp/wci_9_wStatus<20> + ftop/ctop/inf/cp/wci_9_wStatus_20 + SLICE_X62Y78.C6 net (fanout=1) 0.095 ftop/ctop/inf/cp/wci_9_wStatus<20> + SLICE_X62Y78.CLK Tah (-Th) 0.056 ftop/ctop/inf/cp/wci_9_respF_D_OUT<21> + ftop/ctop/inf/cp/_n13698<14>1 + ftop/ctop/inf/cp/wci_9_respF/D_OUT_20 + ------------------------------------------------- --------------------------- + Total 0.137ns (0.042ns logic, 0.095ns route) + (30.7% logic, 69.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.028ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/wmemiTap/wmemiM_dhF_q_0_137 (FF) + Destination: ftop/dram0/wmemi_dhF/data1_reg_137 (FF) + Requirement: 0.000ns + Data Path Delay: 0.135ns (Levels of Logic = 0) + Clock Path Skew: 0.107ns (0.752 - 0.645) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/wmemiTap/wmemiM_dhF_q_0_137 to ftop/dram0/wmemi_dhF/data1_reg_137 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y199.BQ Tcko 0.115 ftop/wmemiTap_wmemiM0_MData<123> + ftop/wmemiTap/wmemiM_dhF_q_0_137 + SLICE_X21Y200.AX net (fanout=2) 0.096 ftop/wmemiTap_wmemiM0_MData<121> + SLICE_X21Y200.CLK Tckdi (-Th) 0.076 ftop/dram0/wmemi_dhF/data1_reg<140> + ftop/dram0/wmemi_dhF/data1_reg_137 + ------------------------------------------------- --------------------------- + Total 0.135ns (0.039ns logic, 0.096ns route) + (28.9% logic, 71.1% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% PRIORITY 100; +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/DCLK + Location pin: GTXE1_X0Y15.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/DCLK + Location pin: GTXE1_X0Y14.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/DCLK + Location pin: GTXE1_X0Y13.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/DCLK + Location pin: GTXE1_X0Y12.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Location pin: GTXE1_X0Y15.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y15.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Location pin: GTXE1_X0Y15.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y15.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Location pin: GTXE1_X0Y14.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y14.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Location pin: GTXE1_X0Y14.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y14.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Location pin: GTXE1_X0Y13.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y13.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Location pin: GTXE1_X0Y13.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y13.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Location pin: GTXE1_X0Y12.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y12.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Location pin: GTXE1_X0Y12.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y12.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% +PRIORITY 1; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 19297 paths analyzed, 6214 endpoints analyzed, 94 failing endpoints + 94 timing errors detected. (94 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.204ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.204ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMD_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.015ns (Levels of Logic = 2) + Clock Path Skew: -0.126ns (0.964 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X138Y151.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X138Y151.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 4.015ns (1.108ns logic, 2.907ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.204ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMD (RAM) + Requirement: 4.000ns + Data Path Delay: 4.015ns (Levels of Logic = 2) + Clock Path Skew: -0.126ns (0.964 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X138Y151.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X138Y151.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMD + ------------------------------------------------- --------------------------- + Total 4.015ns (1.108ns logic, 2.907ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.204ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMC_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.015ns (Levels of Logic = 2) + Clock Path Skew: -0.126ns (0.964 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X138Y151.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X138Y151.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 4.015ns (1.108ns logic, 2.907ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.204ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMC (RAM) + Requirement: 4.000ns + Data Path Delay: 4.015ns (Levels of Logic = 2) + Clock Path Skew: -0.126ns (0.964 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X138Y151.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X138Y151.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMC + ------------------------------------------------- --------------------------- + Total 4.015ns (1.108ns logic, 2.907ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.204ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.015ns (Levels of Logic = 2) + Clock Path Skew: -0.126ns (0.964 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X138Y151.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X138Y151.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 4.015ns (1.108ns logic, 2.907ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.204ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 4.015ns (Levels of Logic = 2) + Clock Path Skew: -0.126ns (0.964 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X138Y151.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X138Y151.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMB + ------------------------------------------------- --------------------------- + Total 4.015ns (1.108ns logic, 2.907ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.204ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.015ns (Levels of Logic = 2) + Clock Path Skew: -0.126ns (0.964 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X138Y151.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X138Y151.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 4.015ns (1.108ns logic, 2.907ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.204ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr5_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 4.015ns (Levels of Logic = 2) + Clock Path Skew: -0.126ns (0.964 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr5_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X138Y151.CE net (fanout=13) 0.573 ftop/pciw_fI2P/BUS_0003 + SLICE_X138Y151.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<29> + ftop/pciw_fI2P/Mram_arr5_RAMA + ------------------------------------------------- --------------------------- + Total 4.015ns (1.108ns logic, 2.907ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.199ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.013ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X142Y149.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X142Y149.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 4.013ns (1.108ns logic, 2.905ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.199ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 4.013ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X142Y149.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X142Y149.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMA + ------------------------------------------------- --------------------------- + Total 4.013ns (1.108ns logic, 2.905ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.199ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMC_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.013ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X142Y149.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X142Y149.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 4.013ns (1.108ns logic, 2.905ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.199ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMD_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.013ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X142Y149.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X142Y149.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 4.013ns (1.108ns logic, 2.905ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.199ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 4.013ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X142Y149.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X142Y149.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 4.013ns (1.108ns logic, 2.905ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.199ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 4.013ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X142Y149.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X142Y149.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMB + ------------------------------------------------- --------------------------- + Total 4.013ns (1.108ns logic, 2.905ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.199ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMC (RAM) + Requirement: 4.000ns + Data Path Delay: 4.013ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X142Y149.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X142Y149.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMC + ------------------------------------------------- --------------------------- + Total 4.013ns (1.108ns logic, 2.905ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.199ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr4_RAMD (RAM) + Requirement: 4.000ns + Data Path Delay: 4.013ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr4_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X142Y149.CE net (fanout=13) 0.571 ftop/pciw_fI2P/BUS_0003 + SLICE_X142Y149.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<23> + ftop/pciw_fI2P/Mram_arr4_RAMD + ------------------------------------------------- --------------------------- + Total 4.013ns (1.108ns logic, 2.905ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.147ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr143/SP (RAM) + Requirement: 4.000ns + Data Path Delay: 3.961ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr143/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X140Y157.CE net (fanout=13) 0.519 ftop/pciw_fI2P/BUS_0003 + SLICE_X140Y157.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<79> + ftop/pciw_fI2P/Mram_arr143/SP + ------------------------------------------------- --------------------------- + Total 3.961ns (1.108ns logic, 2.853ns route) + (28.0% logic, 72.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.147ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr142/SP (RAM) + Requirement: 4.000ns + Data Path Delay: 3.961ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr142/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X140Y157.CE net (fanout=13) 0.519 ftop/pciw_fI2P/BUS_0003 + SLICE_X140Y157.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<79> + ftop/pciw_fI2P/Mram_arr142/SP + ------------------------------------------------- --------------------------- + Total 3.961ns (1.108ns logic, 2.853ns route) + (28.0% logic, 72.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.147ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr143/DP (RAM) + Requirement: 4.000ns + Data Path Delay: 3.961ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr143/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X140Y157.CE net (fanout=13) 0.519 ftop/pciw_fI2P/BUS_0003 + SLICE_X140Y157.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<79> + ftop/pciw_fI2P/Mram_arr143/DP + ------------------------------------------------- --------------------------- + Total 3.961ns (1.108ns logic, 2.853ns route) + (28.0% logic, 72.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.147ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_fI2P/Mram_arr142/DP (RAM) + Requirement: 4.000ns + Data Path Delay: 3.961ns (Levels of Logic = 2) + Clock Path Skew: -0.123ns (0.967 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_fI2P/Mram_arr142/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + PCIE_X0Y1.TRNTDSTRDYNTpcicko_TRN 0.564 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + SLICE_X146Y152.A6 net (fanout=73) 1.792 ftop/pciw_pci0_pcie_ep_trn_tdst_rdy_n + SLICE_X146Y152.A Tilo 0.068 ftop/pciw_fI2P/_n0181_inv + ftop/pciw_pci0_pwTrnTx_whas1 + SLICE_X143Y156.A6 net (fanout=60) 0.542 ftop/pciw_pci0_pwTrnTx_whas + SLICE_X143Y156.A Tilo 0.068 ftop/pciw_pci0_pwTrnTx_whas_REPLICA_60 + ftop/pciw_fI2P/Mmux_BUS_000311 + SLICE_X140Y157.CE net (fanout=13) 0.519 ftop/pciw_fI2P/BUS_0003 + SLICE_X140Y157.CLK Tceck 0.408 ftop/pciw_fI2P/_n0117<79> + ftop/pciw_fI2P/Mram_arr142/DP + ------------------------------------------------- --------------------------- + Total 3.961ns (1.108ns logic, 2.853ns route) + (28.0% logic, 72.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% PRIORITY 1; +-------------------------------------------------------------------------------- +Slack (hold path): 0.000ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_58 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_58 (FF) + Requirement: 0.000ns + Data Path Delay: 0.267ns (Levels of Logic = 1) + Clock Path Skew: 0.078ns (1.154 - 1.076) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_58 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_58 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y156.CQ Tcko 0.115 ftop/pciw_i2pS<59> + ftop/pciw_i2pS_58 + SLICE_X135Y157.C1 net (fanout=1) 0.208 ftop/pciw_i2pS<58> + SLICE_X135Y157.CLK Tah (-Th) 0.056 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<59> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN541 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_58 + ------------------------------------------------- --------------------------- + Total 0.267ns (0.059ns logic, 0.208ns route) + (22.1% logic, 77.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.000ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_17 (FF) + Requirement: 0.000ns + Data Path Delay: 0.265ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.150 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.DQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X134Y149.B2 net (fanout=75) 0.227 ftop/pciw_i2pS<135> + SLICE_X134Y149.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<19> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN91 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_17 + ------------------------------------------------- --------------------------- + Total 0.265ns (0.038ns logic, 0.227ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.001ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_7 (FF) + Requirement: 0.000ns + Data Path Delay: 0.268ns (Levels of Logic = 1) + Clock Path Skew: 0.078ns (1.152 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.DQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X135Y151.D4 net (fanout=75) 0.210 ftop/pciw_i2pS<135> + SLICE_X135Y151.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<7> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN781 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_7 + ------------------------------------------------- --------------------------- + Total 0.268ns (0.058ns logic, 0.210ns route) + (21.6% logic, 78.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.001ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_16 (FF) + Requirement: 0.000ns + Data Path Delay: 0.266ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.150 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.DQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X134Y149.A2 net (fanout=75) 0.227 ftop/pciw_i2pS<135> + SLICE_X134Y149.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<19> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN82 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_16 + ------------------------------------------------- --------------------------- + Total 0.266ns (0.039ns logic, 0.227ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.005ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_55 (FF) + Requirement: 0.000ns + Data Path Delay: 0.272ns (Levels of Logic = 1) + Clock Path Skew: 0.078ns (1.152 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_55 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.DQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X134Y152.D4 net (fanout=75) 0.234 ftop/pciw_i2pS<135> + SLICE_X134Y152.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<55> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN511 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_55 + ------------------------------------------------- --------------------------- + Total 0.272ns (0.038ns logic, 0.234ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.005ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 1) + Clock Path Skew: 0.076ns (1.150 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.DQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X134Y149.D2 net (fanout=75) 0.232 ftop/pciw_i2pS<135> + SLICE_X134Y149.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<19> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN111 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_19 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.038ns logic, 0.232ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.006ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_55 (FF) + Requirement: 0.000ns + Data Path Delay: 0.273ns (Levels of Logic = 1) + Clock Path Skew: 0.078ns (1.152 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_55 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.CQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X134Y152.D3 net (fanout=76) 0.235 ftop/pciw_i2pS<134> + SLICE_X134Y152.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<55> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN511 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_55 + ------------------------------------------------- --------------------------- + Total 0.273ns (0.038ns logic, 0.235ns route) + (13.9% logic, 86.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.009ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.276ns (Levels of Logic = 1) + Clock Path Skew: 0.078ns (1.152 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.DQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X135Y151.A4 net (fanout=75) 0.216 ftop/pciw_i2pS<135> + SLICE_X135Y151.CLK Tah (-Th) 0.055 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<7> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN451 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_4 + ------------------------------------------------- --------------------------- + Total 0.276ns (0.060ns logic, 0.216ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.010ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.277ns (Levels of Logic = 1) + Clock Path Skew: 0.078ns (1.152 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.CQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X135Y151.B3 net (fanout=76) 0.219 ftop/pciw_i2pS<134> + SLICE_X135Y151.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<7> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN561 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_5 + ------------------------------------------------- --------------------------- + Total 0.277ns (0.058ns logic, 0.219ns route) + (20.9% logic, 79.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.010ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_135 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_52 (FF) + Requirement: 0.000ns + Data Path Delay: 0.277ns (Levels of Logic = 1) + Clock Path Skew: 0.078ns (1.152 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_135 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_52 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.DQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_135 + SLICE_X134Y152.A4 net (fanout=75) 0.238 ftop/pciw_i2pS<135> + SLICE_X134Y152.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<55> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN481 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_52 + ------------------------------------------------- --------------------------- + Total 0.277ns (0.039ns logic, 0.238ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.010ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_46 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_46 (FF) + Requirement: 0.000ns + Data Path Delay: 0.279ns (Levels of Logic = 1) + Clock Path Skew: 0.080ns (1.215 - 1.135) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_46 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_46 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y160.CQ Tcko 0.098 ftop/pciw_i2pS<47> + ftop/pciw_i2pS_46 + SLICE_X136Y160.C2 net (fanout=1) 0.257 ftop/pciw_i2pS<46> + SLICE_X136Y160.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<47> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN411 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_46 + ------------------------------------------------- --------------------------- + Total 0.279ns (0.022ns logic, 0.257ns route) + (7.9% logic, 92.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.011ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_52 (FF) + Requirement: 0.000ns + Data Path Delay: 0.278ns (Levels of Logic = 1) + Clock Path Skew: 0.078ns (1.152 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_52 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.CQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X134Y152.A3 net (fanout=76) 0.239 ftop/pciw_i2pS<134> + SLICE_X134Y152.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<55> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN481 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_52 + ------------------------------------------------- --------------------------- + Total 0.278ns (0.039ns logic, 0.239ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.021ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_134 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 (FF) + Requirement: 0.000ns + Data Path Delay: 0.292ns (Levels of Logic = 1) + Clock Path Skew: 0.082ns (1.156 - 1.074) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_134 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y148.CQ Tcko 0.115 ftop/pciw_i2pS<135> + ftop/pciw_i2pS_134 + SLICE_X136Y152.B5 net (fanout=76) 0.254 ftop/pciw_i2pS<134> + SLICE_X136Y152.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<81> + ftop/MUX_pciw_Prelude_inst_changeSpecialWires_2_rg_write_1__SEL_13 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 + ------------------------------------------------- --------------------------- + Total 0.292ns (0.038ns logic, 0.254ns route) + (13.0% logic, 87.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.023ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_15 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_15 (FF) + Requirement: 0.000ns + Data Path Delay: 0.291ns (Levels of Logic = 1) + Clock Path Skew: 0.079ns (1.158 - 1.079) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_15 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y149.DQ Tcko 0.098 ftop/pciw_i2pS<15> + ftop/pciw_i2pS_15 + SLICE_X136Y156.D3 net (fanout=1) 0.270 ftop/pciw_i2pS<15> + SLICE_X136Y156.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<15> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN71 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_15 + ------------------------------------------------- --------------------------- + Total 0.291ns (0.021ns logic, 0.270ns route) + (7.2% logic, 92.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.025ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr7_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.063ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.482 - 0.444) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr7_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y171.BQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X146Y170.D2 net (fanout=18) 0.244 ftop/pciw_fP2I/tail<1> + SLICE_X146Y170.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<41> + ftop/pciw_fP2I/Mram_arr7_RAMB + ------------------------------------------------- --------------------------- + Total 0.063ns (-0.181ns logic, 0.244ns route) + (-287.3% logic, 387.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.025ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_12 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_12 (FF) + Requirement: 0.000ns + Data Path Delay: 0.293ns (Levels of Logic = 1) + Clock Path Skew: 0.079ns (1.158 - 1.079) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_12 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y149.AQ Tcko 0.098 ftop/pciw_i2pS<15> + ftop/pciw_i2pS_12 + SLICE_X136Y156.A5 net (fanout=1) 0.271 ftop/pciw_i2pS<12> + SLICE_X136Y156.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<15> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg_D_IN410 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_12 + ------------------------------------------------- --------------------------- + Total 0.293ns (0.022ns logic, 0.271ns route) + (7.5% logic, 92.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.025ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr7_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.063ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.482 - 0.444) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr7_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y171.BQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X146Y170.D2 net (fanout=18) 0.244 ftop/pciw_fP2I/tail<1> + SLICE_X146Y170.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<41> + ftop/pciw_fP2I/Mram_arr7_RAMA + ------------------------------------------------- --------------------------- + Total 0.063ns (-0.181ns logic, 0.244ns route) + (-287.3% logic, 387.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.025ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr7_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.063ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.482 - 0.444) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr7_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y171.BQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X146Y170.D2 net (fanout=18) 0.244 ftop/pciw_fP2I/tail<1> + SLICE_X146Y170.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<41> + ftop/pciw_fP2I/Mram_arr7_RAMC + ------------------------------------------------- --------------------------- + Total 0.063ns (-0.181ns logic, 0.244ns route) + (-287.3% logic, 387.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.025ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr7_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.063ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.482 - 0.444) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr7_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y171.BQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X146Y170.D2 net (fanout=18) 0.244 ftop/pciw_fP2I/tail<1> + SLICE_X146Y170.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<41> + ftop/pciw_fP2I/Mram_arr7_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.063ns (-0.181ns logic, 0.244ns route) + (-287.3% logic, 387.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.025ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_fP2I/tail_1 (FF) + Destination: ftop/pciw_fP2I/Mram_arr7_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.063ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.482 - 0.444) + Source Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep_trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_fP2I/tail_1 to ftop/pciw_fP2I/Mram_arr7_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y171.BQ Tcko 0.098 ftop/pciw_fP2I/tail<1> + ftop/pciw_fP2I/tail_1 + SLICE_X146Y170.D2 net (fanout=18) 0.244 ftop/pciw_fP2I/tail<1> + SLICE_X146Y170.CLK Tah (-Th) 0.279 ftop/pciw_fP2I/_n0117<41> + ftop/pciw_fP2I/Mram_arr7_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.063ns (-0.181ns logic, 0.244ns route) + (-287.3% logic, 387.3% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% PRIORITY 1; +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Location pin: GTXE1_X0Y15.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y15.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Location pin: GTXE1_X0Y15.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y15.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Location pin: GTXE1_X0Y14.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y14.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Location pin: GTXE1_X0Y14.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y14.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Location pin: GTXE1_X0Y13.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y13.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Location pin: GTXE1_X0Y13.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y13.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Location pin: GTXE1_X0Y12.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y12.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Location pin: GTXE1_X0Y12.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y12.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tpciper_PIPECLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Location pin: PCIE_X0Y1.PIPECLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Location pin: RAMB36_X6Y26.CLKARDCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKB) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKBWRCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKBWRCLKL + Location pin: RAMB36_X6Y26.CLKBWRCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Location pin: RAMB36_X7Y28.CLKARDCLKL + Clock network: ftop/pciw_pci0_pcie_ep_trn_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 2442 paths analyzed, 535 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 6.951ns. +-------------------------------------------------------------------------------- +Slack (setup path): 1.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_11 (FF) + Requirement: 8.000ns + Data Path Delay: 6.732ns (Levels of Logic = 4) + Clock Path Skew: -0.184ns (0.650 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X94Y0.CE net (fanout=9) 1.565 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X94Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<11> + ftop/gbe0/gmac/rxRS_crc/rRemainder_11 + ------------------------------------------------- --------------------------- + Total 6.732ns (0.927ns logic, 5.805ns route) + (13.8% logic, 86.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_10 (FF) + Requirement: 8.000ns + Data Path Delay: 6.732ns (Levels of Logic = 4) + Clock Path Skew: -0.184ns (0.650 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X94Y0.CE net (fanout=9) 1.565 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X94Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<11> + ftop/gbe0/gmac/rxRS_crc/rRemainder_10 + ------------------------------------------------- --------------------------- + Total 6.732ns (0.927ns logic, 5.805ns route) + (13.8% logic, 86.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_9 (FF) + Requirement: 8.000ns + Data Path Delay: 6.732ns (Levels of Logic = 4) + Clock Path Skew: -0.184ns (0.650 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X94Y0.CE net (fanout=9) 1.565 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X94Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<11> + ftop/gbe0/gmac/rxRS_crc/rRemainder_9 + ------------------------------------------------- --------------------------- + Total 6.732ns (0.927ns logic, 5.805ns route) + (13.8% logic, 86.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_8 (FF) + Requirement: 8.000ns + Data Path Delay: 6.732ns (Levels of Logic = 4) + Clock Path Skew: -0.184ns (0.650 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X94Y0.CE net (fanout=9) 1.565 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X94Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<11> + ftop/gbe0/gmac/rxRS_crc/rRemainder_8 + ------------------------------------------------- --------------------------- + Total 6.732ns (0.927ns logic, 5.805ns route) + (13.8% logic, 86.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.173ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_24 (FF) + Requirement: 8.000ns + Data Path Delay: 6.611ns (Levels of Logic = 4) + Clock Path Skew: -0.181ns (0.653 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_24 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X97Y0.CE net (fanout=9) 1.444 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X97Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<27> + ftop/gbe0/gmac/rxRS_crc/rRemainder_24 + ------------------------------------------------- --------------------------- + Total 6.611ns (0.927ns logic, 5.684ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.173ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_27 (FF) + Requirement: 8.000ns + Data Path Delay: 6.611ns (Levels of Logic = 4) + Clock Path Skew: -0.181ns (0.653 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X97Y0.CE net (fanout=9) 1.444 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X97Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<27> + ftop/gbe0/gmac/rxRS_crc/rRemainder_27 + ------------------------------------------------- --------------------------- + Total 6.611ns (0.927ns logic, 5.684ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.173ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_25 (FF) + Requirement: 8.000ns + Data Path Delay: 6.611ns (Levels of Logic = 4) + Clock Path Skew: -0.181ns (0.653 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X97Y0.CE net (fanout=9) 1.444 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X97Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<27> + ftop/gbe0/gmac/rxRS_crc/rRemainder_25 + ------------------------------------------------- --------------------------- + Total 6.611ns (0.927ns logic, 5.684ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.173ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_26 (FF) + Requirement: 8.000ns + Data Path Delay: 6.611ns (Levels of Logic = 4) + Clock Path Skew: -0.181ns (0.653 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X97Y0.CE net (fanout=9) 1.444 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X97Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<27> + ftop/gbe0/gmac/rxRS_crc/rRemainder_26 + ------------------------------------------------- --------------------------- + Total 6.611ns (0.927ns logic, 5.684ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.191ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_17 (FF) + Requirement: 8.000ns + Data Path Delay: 6.593ns (Levels of Logic = 4) + Clock Path Skew: -0.181ns (0.653 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X97Y1.CE net (fanout=9) 1.426 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X97Y1.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<19> + ftop/gbe0/gmac/rxRS_crc/rRemainder_17 + ------------------------------------------------- --------------------------- + Total 6.593ns (0.927ns logic, 5.666ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.191ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_19 (FF) + Requirement: 8.000ns + Data Path Delay: 6.593ns (Levels of Logic = 4) + Clock Path Skew: -0.181ns (0.653 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X97Y1.CE net (fanout=9) 1.426 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X97Y1.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<19> + ftop/gbe0/gmac/rxRS_crc/rRemainder_19 + ------------------------------------------------- --------------------------- + Total 6.593ns (0.927ns logic, 5.666ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.191ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_16 (FF) + Requirement: 8.000ns + Data Path Delay: 6.593ns (Levels of Logic = 4) + Clock Path Skew: -0.181ns (0.653 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X97Y1.CE net (fanout=9) 1.426 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X97Y1.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<19> + ftop/gbe0/gmac/rxRS_crc/rRemainder_16 + ------------------------------------------------- --------------------------- + Total 6.593ns (0.927ns logic, 5.666ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.191ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_18 (FF) + Requirement: 8.000ns + Data Path Delay: 6.593ns (Levels of Logic = 4) + Clock Path Skew: -0.181ns (0.653 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X97Y1.CE net (fanout=9) 1.426 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X97Y1.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<19> + ftop/gbe0/gmac/rxRS_crc/rRemainder_18 + ------------------------------------------------- --------------------------- + Total 6.593ns (0.927ns logic, 5.666ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.193ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_3 (FF) + Requirement: 8.000ns + Data Path Delay: 6.599ns (Levels of Logic = 4) + Clock Path Skew: -0.173ns (0.661 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X98Y0.CE net (fanout=9) 1.432 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X98Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<3> + ftop/gbe0/gmac/rxRS_crc/rRemainder_3 + ------------------------------------------------- --------------------------- + Total 6.599ns (0.927ns logic, 5.672ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.193ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_2 (FF) + Requirement: 8.000ns + Data Path Delay: 6.599ns (Levels of Logic = 4) + Clock Path Skew: -0.173ns (0.661 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X98Y0.CE net (fanout=9) 1.432 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X98Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<3> + ftop/gbe0/gmac/rxRS_crc/rRemainder_2 + ------------------------------------------------- --------------------------- + Total 6.599ns (0.927ns logic, 5.672ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.193ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_1 (FF) + Requirement: 8.000ns + Data Path Delay: 6.599ns (Levels of Logic = 4) + Clock Path Skew: -0.173ns (0.661 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X98Y0.CE net (fanout=9) 1.432 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X98Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<3> + ftop/gbe0/gmac/rxRS_crc/rRemainder_1 + ------------------------------------------------- --------------------------- + Total 6.599ns (0.927ns logic, 5.672ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.193ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_0 (FF) + Requirement: 8.000ns + Data Path Delay: 6.599ns (Levels of Logic = 4) + Clock Path Skew: -0.173ns (0.661 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X98Y0.CE net (fanout=9) 1.432 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X98Y0.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<3> + ftop/gbe0/gmac/rxRS_crc/rRemainder_0 + ------------------------------------------------- --------------------------- + Total 6.599ns (0.927ns logic, 5.672ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.311ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 6.481ns (Levels of Logic = 4) + Clock Path Skew: -0.173ns (0.661 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X99Y1.CE net (fanout=9) 1.314 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X99Y1.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 6.481ns (0.927ns logic, 5.554ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.311ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_7 (FF) + Requirement: 8.000ns + Data Path Delay: 6.481ns (Levels of Logic = 4) + Clock Path Skew: -0.173ns (0.661 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X99Y1.CE net (fanout=9) 1.314 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X99Y1.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_7 + ------------------------------------------------- --------------------------- + Total 6.481ns (0.927ns logic, 5.554ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.311ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_5 (FF) + Requirement: 8.000ns + Data Path Delay: 6.481ns (Levels of Logic = 4) + Clock Path Skew: -0.173ns (0.661 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X99Y1.CE net (fanout=9) 1.314 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X99Y1.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_5 + ------------------------------------------------- --------------------------- + Total 6.481ns (0.927ns logic, 5.554ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.311ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_6 (FF) + Requirement: 8.000ns + Data Path Delay: 6.481ns (Levels of Logic = 4) + Clock Path Skew: -0.173ns (0.661 - 0.834) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_crc/rRemainder_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y9.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X110Y20.D5 net (fanout=18) 1.372 ftop/gbe0/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X110Y20.D Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1_SW0 + SLICE_X110Y20.C6 net (fanout=1) 0.123 ftop/gbe0/gmac/N2 + SLICE_X110Y20.C Tilo 0.068 ftop/gbe0/gmac/N2 + ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A5 net (fanout=13) 1.383 ftop/gbe0/gmac/rxRS_rxF_sENQ1 + SLICE_X100Y3.A Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder<31> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X109Y18.B1 net (fanout=33) 1.362 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X109Y18.B Tilo 0.068 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + ftop/gbe0/gmac/rxRS_crc/rRemainder$EN11 + SLICE_X99Y1.CE net (fanout=9) 1.314 ftop/gbe0/gmac/rxRS_crc/rRemainder$EN + SLICE_X99Y1.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_crc/rRemainder<7> + ftop/gbe0/gmac/rxRS_crc/rRemainder_6 + ------------------------------------------------- --------------------------- + Total 6.481ns (0.927ns logic, 5.554ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.105ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.BMUX Tshcko 0.148 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X134Y21.D2 net (fanout=5) 0.236 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X134Y21.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP + ------------------------------------------------- --------------------------- + Total 0.105ns (-0.131ns logic, 0.236ns route) + (-124.8% logic, 224.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.105ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.BMUX Tshcko 0.148 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X134Y21.D2 net (fanout=5) 0.236 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X134Y21.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP + ------------------------------------------------- --------------------------- + Total 0.105ns (-0.131ns logic, 0.236ns route) + (-124.8% logic, 224.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.105ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.BMUX Tshcko 0.148 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X134Y21.D2 net (fanout=5) 0.236 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X134Y21.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP + ------------------------------------------------- --------------------------- + Total 0.105ns (-0.131ns logic, 0.236ns route) + (-124.8% logic, 224.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.105ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.BMUX Tshcko 0.148 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X134Y21.D2 net (fanout=5) 0.236 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X134Y21.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP + ------------------------------------------------- --------------------------- + Total 0.105ns (-0.131ns logic, 0.236ns route) + (-124.8% logic, 224.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.105ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.BMUX Tshcko 0.148 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X134Y21.D2 net (fanout=5) 0.236 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X134Y21.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 0.105ns (-0.131ns logic, 0.236ns route) + (-124.8% logic, 224.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.105ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.BMUX Tshcko 0.148 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X134Y21.D2 net (fanout=5) 0.236 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X134Y21.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP + ------------------------------------------------- --------------------------- + Total 0.105ns (-0.131ns logic, 0.236ns route) + (-124.8% logic, 224.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.105ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.BMUX Tshcko 0.148 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X134Y21.D2 net (fanout=5) 0.236 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X134Y21.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP + ------------------------------------------------- --------------------------- + Total 0.105ns (-0.131ns logic, 0.236ns route) + (-124.8% logic, 224.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.105ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.BMUX Tshcko 0.148 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X134Y21.D2 net (fanout=5) 0.236 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X134Y21.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP + ------------------------------------------------- --------------------------- + Total 0.105ns (-0.131ns logic, 0.236ns route) + (-124.8% logic, 224.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.086ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_3 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.032ns (0.394 - 0.362) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_3 to ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y22.DQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<3> + ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_3 + SLICE_X133Y22.DX net (fanout=1) 0.096 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<3> + SLICE_X133Y22.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxF/sDeqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.086ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.032ns (0.394 - 0.362) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_1 to ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y22.BQ Tcko 0.098 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<3> + ftop/gbe0/gmac/rxRS_rxF/sSyncReg1_1 + SLICE_X133Y22.BX net (fanout=1) 0.096 ftop/gbe0/gmac/rxRS_rxF/sSyncReg1<1> + SLICE_X133Y22.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/rxRS_rxF/sDeqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X134Y21.D3 net (fanout=5) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X134Y21.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP + ------------------------------------------------- --------------------------- + Total 0.129ns (-0.099ns logic, 0.228ns route) + (-76.7% logic, 176.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X134Y21.D3 net (fanout=5) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X134Y21.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP + ------------------------------------------------- --------------------------- + Total 0.129ns (-0.099ns logic, 0.228ns route) + (-76.7% logic, 176.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X134Y21.D3 net (fanout=5) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X134Y21.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP + ------------------------------------------------- --------------------------- + Total 0.129ns (-0.099ns logic, 0.228ns route) + (-76.7% logic, 176.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X134Y21.D3 net (fanout=5) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X134Y21.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP + ------------------------------------------------- --------------------------- + Total 0.129ns (-0.099ns logic, 0.228ns route) + (-76.7% logic, 176.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X134Y21.D3 net (fanout=5) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X134Y21.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 0.129ns (-0.099ns logic, 0.228ns route) + (-76.7% logic, 176.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X134Y21.D3 net (fanout=5) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X134Y21.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP + ------------------------------------------------- --------------------------- + Total 0.129ns (-0.099ns logic, 0.228ns route) + (-76.7% logic, 176.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X134Y21.D3 net (fanout=5) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X134Y21.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP + ------------------------------------------------- --------------------------- + Total 0.129ns (-0.099ns logic, 0.228ns route) + (-76.7% logic, 176.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.129ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.395 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X134Y21.D3 net (fanout=5) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X134Y21.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP + ------------------------------------------------- --------------------------- + Total 0.129ns (-0.099ns logic, 0.228ns route) + (-76.7% logic, 176.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.098ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_crc/rRemainder_11 (FF) + Destination: ftop/gbe0/gmac/rxRS_crc/rRemainder_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.137ns (Levels of Logic = 1) + Clock Path Skew: 0.039ns (0.320 - 0.281) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_crc/rRemainder_11 to ftop/gbe0/gmac/rxRS_crc/rRemainder_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X94Y0.DQ Tcko 0.098 ftop/gbe0/gmac/rxRS_crc/rRemainder<11> + ftop/gbe0/gmac/rxRS_crc/rRemainder_11 + SLICE_X97Y1.D6 net (fanout=2) 0.096 ftop/gbe0/gmac/rxRS_crc/rRemainder<11> + SLICE_X97Y1.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/rxRS_crc/rRemainder<19> + ftop/gbe0/gmac/rxRS_crc/rRemainder$D_IN<19>1 + ftop/gbe0/gmac/rxRS_crc/rRemainder_19 + ------------------------------------------------- --------------------------- + Total 0.137ns (0.041ns logic, 0.096ns route) + (29.9% logic, 70.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.104ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.142ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.396 - 0.358) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X132Y21.BMUX Tshcko 0.148 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X134Y22.D2 net (fanout=5) 0.273 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X134Y22.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA + ------------------------------------------------- --------------------------- + Total 0.142ns (-0.131ns logic, 0.273ns route) + (-92.3% logic, 192.3% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 4.668ns (period - min period limit) + Period: 8.000ns + Min period limit: 3.332ns (300.120MHz) (Tbrper_I) + Physical resource: ftop/gbe0/gmac/rxClk_BUFR/I + Logical resource: ftop/gbe0/gmac/rxClk_BUFR/I + Location pin: BUFR_X2Y3.I + Clock network: ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP/CLK + Location pin: SLICE_X134Y21.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA/CLK + Location pin: SLICE_X134Y22.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA/CLK + Location pin: SLICE_X134Y22.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1/CLK + Location pin: SLICE_X134Y22.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 6107 paths analyzed, 683 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 5.007ns. +-------------------------------------------------------------------------------- +Slack (setup path): 2.993ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 (FF) + Destination: ftop/gbe0/gmac/txRS_iobTxData_7 (FF) + Requirement: 8.000ns + Data Path Delay: 5.039ns (Levels of Logic = 1) + Clock Path Skew: 0.067ns (1.097 - 1.030) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 to ftop/gbe0/gmac/txRS_iobTxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y50.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txRst_OUT_RST + ftop/gbe0/gmac/txRS_txRst/reset_hold_1 + SLICE_X140Y51.A5 net (fanout=4) 0.437 ftop/gbe0/gmac/txRS_txRst_OUT_RST + SLICE_X140Y51.A Tilo 0.068 ftop/ctop/app/appW2/wmi_sFlagReg<11> + ftop/gbe0/gmac/txRS_iobTxClk_reset/RESET_OUT1_INV_0 + OLOGIC_X2Y71.SR net (fanout=11) 3.504 ftop/gbe0/gmac/txRS_iobTxClk_reset_RESET_OUT + OLOGIC_X2Y71.CLK Tosrck 0.693 gmii_txd_7_OBUF + ftop/gbe0/gmac/txRS_iobTxData_7 + ------------------------------------------------- --------------------------- + Total 5.039ns (1.098ns logic, 3.941ns route) + (21.8% logic, 78.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.094ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_7 (FF) + Requirement: 8.000ns + Data Path Delay: 4.664ns (Levels of Logic = 5) + Clock Path Skew: -0.207ns (1.493 - 1.700) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y36.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X152Y43.D6 net (fanout=13) 0.780 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X152Y43.D Tilo 0.068 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF31 + SLICE_X145Y45.C1 net (fanout=12) 0.917 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D3 net (fanout=8) 0.339 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data12 + SLICE_X154Y53.B1 net (fanout=14) 1.428 ftop/gbe0/gmac/txRS_crc_add_data<0> + SLICE_X154Y53.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<7>_SW0 + SLICE_X154Y53.A2 net (fanout=1) 0.474 ftop/gbe0/gmac/txRS_crc/N0 + SLICE_X154Y53.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<7> + ftop/gbe0/gmac/txRS_crc/rRemainder_7 + ------------------------------------------------- --------------------------- + Total 4.664ns (0.726ns logic, 3.938ns route) + (15.6% logic, 84.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.112ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 (FF) + Destination: ftop/gbe0/gmac/txRS_iobTxData_6 (FF) + Requirement: 8.000ns + Data Path Delay: 4.920ns (Levels of Logic = 1) + Clock Path Skew: 0.067ns (1.097 - 1.030) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 to ftop/gbe0/gmac/txRS_iobTxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y50.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txRst_OUT_RST + ftop/gbe0/gmac/txRS_txRst/reset_hold_1 + SLICE_X140Y51.A5 net (fanout=4) 0.437 ftop/gbe0/gmac/txRS_txRst_OUT_RST + SLICE_X140Y51.A Tilo 0.068 ftop/ctop/app/appW2/wmi_sFlagReg<11> + ftop/gbe0/gmac/txRS_iobTxClk_reset/RESET_OUT1_INV_0 + OLOGIC_X2Y70.SR net (fanout=11) 3.385 ftop/gbe0/gmac/txRS_iobTxClk_reset_RESET_OUT + OLOGIC_X2Y70.CLK Tosrck 0.693 gmii_txd_6_OBUF + ftop/gbe0/gmac/txRS_iobTxData_6 + ------------------------------------------------- --------------------------- + Total 4.920ns (1.098ns logic, 3.822ns route) + (22.3% logic, 77.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.150ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_7 (FF) + Requirement: 8.000ns + Data Path Delay: 4.754ns (Levels of Logic = 5) + Clock Path Skew: -0.061ns (0.980 - 1.041) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_crc/rRemainder_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y43.CQ Tcko 0.337 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X146Y39.D2 net (fanout=44) 1.291 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X146Y39.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X145Y45.C6 net (fanout=13) 0.540 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D3 net (fanout=8) 0.339 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data12 + SLICE_X154Y53.B1 net (fanout=14) 1.428 ftop/gbe0/gmac/txRS_crc_add_data<0> + SLICE_X154Y53.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<7>_SW0 + SLICE_X154Y53.A2 net (fanout=1) 0.474 ftop/gbe0/gmac/txRS_crc/N0 + SLICE_X154Y53.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<7> + ftop/gbe0/gmac/txRS_crc/rRemainder_7 + ------------------------------------------------- --------------------------- + Total 4.754ns (0.682ns logic, 4.072ns route) + (14.3% logic, 85.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.201ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_1 (FF) + Requirement: 8.000ns + Data Path Delay: 4.556ns (Levels of Logic = 5) + Clock Path Skew: -0.208ns (1.492 - 1.700) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y36.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X152Y43.D6 net (fanout=13) 0.780 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X152Y43.D Tilo 0.068 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF31 + SLICE_X145Y45.C1 net (fanout=12) 0.917 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D3 net (fanout=8) 0.339 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data12 + SLICE_X154Y54.B1 net (fanout=14) 1.545 ftop/gbe0/gmac/txRS_crc_add_data<0> + SLICE_X154Y54.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>41 + SLICE_X154Y54.C6 net (fanout=2) 0.249 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>_bdd2 + SLICE_X154Y54.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>21 + ftop/gbe0/gmac/txRS_crc/rRemainder_1 + ------------------------------------------------- --------------------------- + Total 4.556ns (0.726ns logic, 3.830ns route) + (15.9% logic, 84.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.233ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 (FF) + Destination: ftop/gbe0/gmac/txRS_iobTxData_5 (FF) + Requirement: 8.000ns + Data Path Delay: 4.799ns (Levels of Logic = 1) + Clock Path Skew: 0.067ns (1.097 - 1.030) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 to ftop/gbe0/gmac/txRS_iobTxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y50.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txRst_OUT_RST + ftop/gbe0/gmac/txRS_txRst/reset_hold_1 + SLICE_X140Y51.A5 net (fanout=4) 0.437 ftop/gbe0/gmac/txRS_txRst_OUT_RST + SLICE_X140Y51.A Tilo 0.068 ftop/ctop/app/appW2/wmi_sFlagReg<11> + ftop/gbe0/gmac/txRS_iobTxClk_reset/RESET_OUT1_INV_0 + OLOGIC_X2Y69.SR net (fanout=11) 3.264 ftop/gbe0/gmac/txRS_iobTxClk_reset_RESET_OUT + OLOGIC_X2Y69.CLK Tosrck 0.693 gmii_txd_5_OBUF + ftop/gbe0/gmac/txRS_iobTxData_5 + ------------------------------------------------- --------------------------- + Total 4.799ns (1.098ns logic, 3.701ns route) + (22.9% logic, 77.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.257ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_1 (FF) + Requirement: 8.000ns + Data Path Delay: 4.646ns (Levels of Logic = 5) + Clock Path Skew: -0.062ns (0.979 - 1.041) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_crc/rRemainder_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y43.CQ Tcko 0.337 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X146Y39.D2 net (fanout=44) 1.291 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X146Y39.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X145Y45.C6 net (fanout=13) 0.540 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D3 net (fanout=8) 0.339 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data12 + SLICE_X154Y54.B1 net (fanout=14) 1.545 ftop/gbe0/gmac/txRS_crc_add_data<0> + SLICE_X154Y54.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>41 + SLICE_X154Y54.C6 net (fanout=2) 0.249 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>_bdd2 + SLICE_X154Y54.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>21 + ftop/gbe0/gmac/txRS_crc/rRemainder_1 + ------------------------------------------------- --------------------------- + Total 4.646ns (0.682ns logic, 3.964ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.320ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_7 (FF) + Requirement: 8.000ns + Data Path Delay: 4.449ns (Levels of Logic = 5) + Clock Path Skew: -0.196ns (1.493 - 1.689) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y26.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X146Y39.D4 net (fanout=38) 0.986 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X146Y39.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X145Y45.C6 net (fanout=13) 0.540 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D3 net (fanout=8) 0.339 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data12 + SLICE_X154Y53.B1 net (fanout=14) 1.428 ftop/gbe0/gmac/txRS_crc_add_data<0> + SLICE_X154Y53.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<7>_SW0 + SLICE_X154Y53.A2 net (fanout=1) 0.474 ftop/gbe0/gmac/txRS_crc/N0 + SLICE_X154Y53.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<7> + ftop/gbe0/gmac/txRS_crc/rRemainder_7 + ------------------------------------------------- --------------------------- + Total 4.449ns (0.682ns logic, 3.767ns route) + (15.3% logic, 84.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.329ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_13 (FF) + Requirement: 8.000ns + Data Path Delay: 4.428ns (Levels of Logic = 5) + Clock Path Skew: -0.208ns (1.492 - 1.700) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y36.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X152Y43.D6 net (fanout=13) 0.780 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X152Y43.D Tilo 0.068 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF31 + SLICE_X145Y45.C1 net (fanout=12) 0.917 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X147Y51.A3 net (fanout=8) 0.766 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X147Y51.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<31> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data31 + SLICE_X152Y51.B1 net (fanout=14) 0.804 ftop/gbe0/gmac/txRS_crc_add_data<2> + SLICE_X152Y51.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<13>1 + SLICE_X152Y51.A2 net (fanout=1) 0.478 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<13>1 + SLICE_X152Y51.CLK Tas 0.030 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<13>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_13 + ------------------------------------------------- --------------------------- + Total 4.428ns (0.683ns logic, 3.745ns route) + (15.4% logic, 84.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.330ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_2 (FF) + Requirement: 8.000ns + Data Path Delay: 4.427ns (Levels of Logic = 5) + Clock Path Skew: -0.208ns (1.492 - 1.700) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y36.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X152Y43.D6 net (fanout=13) 0.780 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X152Y43.D Tilo 0.068 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF31 + SLICE_X145Y45.C1 net (fanout=12) 0.917 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D3 net (fanout=8) 0.339 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data12 + SLICE_X154Y54.B1 net (fanout=14) 1.545 ftop/gbe0/gmac/txRS_crc_add_data<0> + SLICE_X154Y54.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>41 + SLICE_X154Y54.D6 net (fanout=2) 0.123 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>_bdd2 + SLICE_X154Y54.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<2>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_2 + ------------------------------------------------- --------------------------- + Total 4.427ns (0.723ns logic, 3.704ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.354ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 (FF) + Destination: ftop/gbe0/gmac/txRS_iobTxData_4 (FF) + Requirement: 8.000ns + Data Path Delay: 4.678ns (Levels of Logic = 1) + Clock Path Skew: 0.067ns (1.097 - 1.030) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 to ftop/gbe0/gmac/txRS_iobTxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y50.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txRst_OUT_RST + ftop/gbe0/gmac/txRS_txRst/reset_hold_1 + SLICE_X140Y51.A5 net (fanout=4) 0.437 ftop/gbe0/gmac/txRS_txRst_OUT_RST + SLICE_X140Y51.A Tilo 0.068 ftop/ctop/app/appW2/wmi_sFlagReg<11> + ftop/gbe0/gmac/txRS_iobTxClk_reset/RESET_OUT1_INV_0 + OLOGIC_X2Y68.SR net (fanout=11) 3.143 ftop/gbe0/gmac/txRS_iobTxClk_reset_RESET_OUT + OLOGIC_X2Y68.CLK Tosrck 0.693 gmii_txd_4_OBUF + ftop/gbe0/gmac/txRS_iobTxData_4 + ------------------------------------------------- --------------------------- + Total 4.678ns (1.098ns logic, 3.580ns route) + (23.5% logic, 76.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.367ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 4.391ns (Levels of Logic = 5) + Clock Path Skew: -0.207ns (1.493 - 1.700) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y36.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X152Y43.D6 net (fanout=13) 0.780 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X152Y43.D Tilo 0.068 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF31 + SLICE_X145Y45.C1 net (fanout=12) 0.917 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y51.A3 net (fanout=8) 0.634 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y51.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<1> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X154Y52.C4 net (fanout=15) 0.866 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X154Y52.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1_SW0 + SLICE_X154Y52.B3 net (fanout=1) 0.471 ftop/gbe0/gmac/txRS_crc/N32 + SLICE_X154Y52.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 4.391ns (0.723ns logic, 3.668ns route) + (16.5% logic, 83.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.385ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_13 (FF) + Requirement: 8.000ns + Data Path Delay: 4.518ns (Levels of Logic = 5) + Clock Path Skew: -0.062ns (0.979 - 1.041) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_crc/rRemainder_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y43.CQ Tcko 0.337 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X146Y39.D2 net (fanout=44) 1.291 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X146Y39.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X145Y45.C6 net (fanout=13) 0.540 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X147Y51.A3 net (fanout=8) 0.766 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X147Y51.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<31> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data31 + SLICE_X152Y51.B1 net (fanout=14) 0.804 ftop/gbe0/gmac/txRS_crc_add_data<2> + SLICE_X152Y51.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<13>1 + SLICE_X152Y51.A2 net (fanout=1) 0.478 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<13>1 + SLICE_X152Y51.CLK Tas 0.030 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<13>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_13 + ------------------------------------------------- --------------------------- + Total 4.518ns (0.639ns logic, 3.879ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.386ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_2 (FF) + Requirement: 8.000ns + Data Path Delay: 4.517ns (Levels of Logic = 5) + Clock Path Skew: -0.062ns (0.979 - 1.041) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_crc/rRemainder_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y43.CQ Tcko 0.337 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X146Y39.D2 net (fanout=44) 1.291 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X146Y39.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X145Y45.C6 net (fanout=13) 0.540 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D3 net (fanout=8) 0.339 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data12 + SLICE_X154Y54.B1 net (fanout=14) 1.545 ftop/gbe0/gmac/txRS_crc_add_data<0> + SLICE_X154Y54.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>41 + SLICE_X154Y54.D6 net (fanout=2) 0.123 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>_bdd2 + SLICE_X154Y54.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<2>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_2 + ------------------------------------------------- --------------------------- + Total 4.517ns (0.679ns logic, 3.838ns route) + (15.0% logic, 85.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.423ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_4 (FF) + Requirement: 8.000ns + Data Path Delay: 4.481ns (Levels of Logic = 5) + Clock Path Skew: -0.061ns (0.980 - 1.041) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_crc/rRemainder_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y43.CQ Tcko 0.337 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X146Y39.D2 net (fanout=44) 1.291 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X146Y39.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X145Y45.C6 net (fanout=13) 0.540 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y51.A3 net (fanout=8) 0.634 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y51.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<1> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data21 + SLICE_X154Y52.C4 net (fanout=15) 0.866 ftop/gbe0/gmac/txRS_crc_add_data<1> + SLICE_X154Y52.C Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1_SW0 + SLICE_X154Y52.B3 net (fanout=1) 0.471 ftop/gbe0/gmac/txRS_crc/N32 + SLICE_X154Y52.CLK Tas 0.070 ftop/gbe0/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<4>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_4 + ------------------------------------------------- --------------------------- + Total 4.481ns (0.679ns logic, 3.802ns route) + (15.2% logic, 84.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.424ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_6 (FF) + Requirement: 8.000ns + Data Path Delay: 4.335ns (Levels of Logic = 5) + Clock Path Skew: -0.206ns (1.494 - 1.700) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y36.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X152Y43.D6 net (fanout=13) 0.780 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X152Y43.D Tilo 0.068 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF31 + SLICE_X145Y45.C1 net (fanout=12) 0.917 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y50.A6 net (fanout=8) 0.392 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y50.A Tilo 0.068 ftop/gbe0/gmac/txRS_txData<5> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data71 + SLICE_X154Y51.D1 net (fanout=14) 1.399 ftop/gbe0/gmac/txRS_crc_add_data<6> + SLICE_X154Y51.D Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<6> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<6>1 + SLICE_X154Y51.C6 net (fanout=1) 0.121 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<6>1 + SLICE_X154Y51.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<6> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<6>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_6 + ------------------------------------------------- --------------------------- + Total 4.335ns (0.726ns logic, 3.609ns route) + (16.7% logic, 83.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.426ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_7 (FF) + Requirement: 8.000ns + Data Path Delay: 4.332ns (Levels of Logic = 5) + Clock Path Skew: -0.207ns (1.493 - 1.700) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y36.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X145Y45.B3 net (fanout=13) 0.784 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X145Y45.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11_SW0 + SLICE_X145Y45.C2 net (fanout=1) 0.581 ftop/gbe0/gmac/N6 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D3 net (fanout=8) 0.339 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data12 + SLICE_X154Y53.B1 net (fanout=14) 1.428 ftop/gbe0/gmac/txRS_crc_add_data<0> + SLICE_X154Y53.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<7>_SW0 + SLICE_X154Y53.A2 net (fanout=1) 0.474 ftop/gbe0/gmac/txRS_crc/N0 + SLICE_X154Y53.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<9> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<7> + ftop/gbe0/gmac/txRS_crc/rRemainder_7 + ------------------------------------------------- --------------------------- + Total 4.332ns (0.726ns logic, 3.606ns route) + (16.8% logic, 83.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.427ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_1 (FF) + Requirement: 8.000ns + Data Path Delay: 4.341ns (Levels of Logic = 5) + Clock Path Skew: -0.197ns (1.492 - 1.689) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 to ftop/gbe0/gmac/txRS_crc/rRemainder_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y26.AQ Tcko 0.337 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + SLICE_X146Y39.D4 net (fanout=38) 0.986 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + SLICE_X146Y39.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF11 + SLICE_X145Y45.C6 net (fanout=13) 0.540 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF1 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D3 net (fanout=8) 0.339 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X145Y45.D Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data12 + SLICE_X154Y54.B1 net (fanout=14) 1.545 ftop/gbe0/gmac/txRS_crc_add_data<0> + SLICE_X154Y54.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>41 + SLICE_X154Y54.C6 net (fanout=2) 0.249 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>_bdd2 + SLICE_X154Y54.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<2> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<1>21 + ftop/gbe0/gmac/txRS_crc/rRemainder_1 + ------------------------------------------------- --------------------------- + Total 4.341ns (0.682ns logic, 3.659ns route) + (15.7% logic, 84.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.435ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_13 (FF) + Requirement: 8.000ns + Data Path Delay: 4.322ns (Levels of Logic = 5) + Clock Path Skew: -0.208ns (1.492 - 1.700) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y36.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X152Y43.D6 net (fanout=13) 0.780 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X152Y43.D Tilo 0.068 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF31 + SLICE_X145Y45.C1 net (fanout=12) 0.917 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X144Y50.D5 net (fanout=8) 0.484 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X144Y50.D Tilo 0.068 ftop/gbe0/gmac/txRS_txData<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data51 + SLICE_X152Y51.B2 net (fanout=14) 0.980 ftop/gbe0/gmac/txRS_crc_add_data<4> + SLICE_X152Y51.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<13>1 + SLICE_X152Y51.A2 net (fanout=1) 0.478 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<13>1 + SLICE_X152Y51.CLK Tas 0.030 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<13>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_13 + ------------------------------------------------- --------------------------- + Total 4.322ns (0.683ns logic, 3.639ns route) + (15.8% logic, 84.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.474ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 4.282ns (Levels of Logic = 5) + Clock Path Skew: -0.209ns (1.491 - 1.700) + Source Clock: ftop/sys1_clk_O rising at 0.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 to ftop/gbe0/gmac/txRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X146Y36.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + SLICE_X152Y43.D6 net (fanout=13) 0.780 ftop/gbe0/gmac/txRS_txF_dD_OUT<8> + SLICE_X152Y43.D Tilo 0.068 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_SOF31 + SLICE_X145Y45.C1 net (fanout=12) 0.917 ftop/gbe0/gmac/Mmux_txRS_txData_D_IN122 + SLICE_X145Y45.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF_dD_OUT<7> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X147Y50.B5 net (fanout=8) 0.484 ftop/gbe0/gmac/Mmux_txRS_crc_add_data11 + SLICE_X147Y50.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc_add_data<5> + ftop/gbe0/gmac/Mmux_txRS_crc_add_data61 + SLICE_X150Y52.D3 net (fanout=14) 0.905 ftop/gbe0/gmac/txRS_crc_add_data<5> + SLICE_X150Y52.D Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<12>1 + SLICE_X150Y52.C2 net (fanout=1) 0.470 ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<12>1 + SLICE_X150Y52.CLK Tas 0.073 ftop/gbe0/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<12>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 4.282ns (0.726ns logic, 3.556ns route) + (17.0% logic, 83.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.060ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_31 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.071ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.061 - 0.050) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_31 to ftop/gbe0/gmac/txRS_crc/rRemainder_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y51.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_crc/rRemainder<31> + ftop/gbe0/gmac/txRS_crc/rRemainder_31 + SLICE_X146Y51.A6 net (fanout=15) 0.049 ftop/gbe0/gmac/txRS_crc/rRemainder<31> + SLICE_X146Y51.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<19>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_19 + ------------------------------------------------- --------------------------- + Total 0.071ns (0.022ns logic, 0.049ns route) + (31.0% logic, 69.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.097ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.109ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y36.DQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + SLICE_X149Y36.B6 net (fanout=4) 0.051 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + SLICE_X149Y36.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<4>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + ------------------------------------------------- --------------------------- + Total 0.109ns (0.058ns logic, 0.051ns route) + (53.2% logic, 46.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.101ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.112ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.065 - 0.054) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X149Y36.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + SLICE_X148Y35.DX net (fanout=2) 0.103 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<4> + SLICE_X148Y35.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + ------------------------------------------------- --------------------------- + Total 0.112ns (0.009ns logic, 0.103ns route) + (8.0% logic, 92.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.102ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/phyRst/rstSync/reset_hold_0 (FF) + Destination: ftop/gbe0/phyRst/rstSync/reset_hold_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 0) + Clock Path Skew: 0.013ns (0.066 - 0.053) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/phyRst/rstSync/reset_hold_0 to ftop/gbe0/phyRst/rstSync/reset_hold_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y35.AQ Tcko 0.098 ftop/gbe0/phyRst/rstSync/reset_hold<0> + ftop/gbe0/phyRst/rstSync/reset_hold_0 + SLICE_X93Y36.AX net (fanout=1) 0.093 ftop/gbe0/phyRst/rstSync/reset_hold<0> + SLICE_X93Y36.CLK Tckdi (-Th) 0.076 gmii_rstn_OBUF + ftop/gbe0/phyRst/rstSync/reset_hold_1 + ------------------------------------------------- --------------------------- + Total 0.115ns (0.022ns logic, 0.093ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.104ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_doPad (FF) + Destination: ftop/gbe0/gmac/txRS_unfBit/sSyncReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.141ns (Levels of Logic = 1) + Clock Path Skew: 0.037ns (0.490 - 0.453) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_doPad to ftop/gbe0/gmac/txRS_unfBit/sSyncReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y38.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_doPad + ftop/gbe0/gmac/txRS_doPad + SLICE_X148Y38.A5 net (fanout=5) 0.119 ftop/gbe0/gmac/txRS_doPad + SLICE_X148Y38.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_unfBit/sSyncReg + ftop/gbe0/gmac/txRS_unfBit_sD_IN21 + ftop/gbe0/gmac/txRS_unfBit/sSyncReg + ------------------------------------------------- --------------------------- + Total 0.141ns (0.022ns logic, 0.119ns route) + (15.6% logic, 84.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.106ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 (FF) + Destination: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.058 - 0.049) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 to ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y27.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 + SLICE_X145Y26.AX net (fanout=1) 0.093 ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1 + SLICE_X145Y26.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txOperateS_dD_OUT + ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2 + ------------------------------------------------- --------------------------- + Total 0.115ns (0.022ns logic, 0.093ns route) + (19.1% logic, 80.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.107ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_28 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_30 (FF) + Requirement: 0.000ns + Data Path Delay: 0.143ns (Levels of Logic = 1) + Clock Path Skew: 0.036ns (0.485 - 0.449) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_28 to ftop/gbe0/gmac/txRS_crc/rRemainder_30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y51.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_crc/rRemainder<28> + ftop/gbe0/gmac/txRS_crc/rRemainder_28 + SLICE_X148Y51.D6 net (fanout=15) 0.122 ftop/gbe0/gmac/txRS_crc/rRemainder<28> + SLICE_X148Y51.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_crc/rRemainder<30> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<30>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_30 + ------------------------------------------------- --------------------------- + Total 0.143ns (0.021ns logic, 0.122ns route) + (14.7% logic, 85.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.110ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.110ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X149Y36.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + SLICE_X149Y36.A5 net (fanout=2) 0.067 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<4> + SLICE_X149Y36.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<3>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + ------------------------------------------------- --------------------------- + Total 0.110ns (0.043ns logic, 0.067ns route) + (39.1% logic, 60.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_preambleCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_preambleCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_preambleCnt_value_2 to ftop/gbe0/gmac/txRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y44.CQ Tcko 0.115 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/txRS_preambleCnt_value_2 + SLICE_X148Y44.C5 net (fanout=5) 0.077 ftop/gbe0/gmac/txRS_preambleCnt_value<2> + SLICE_X148Y44.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_preambleCnt_value_xor<2>11 + ftop/gbe0/gmac/txRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.116ns (0.039ns logic, 0.077ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.118ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_2 to ftop/gbe0/gmac/txRS_ifgCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y43.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/txRS_ifgCnt_value_2 + SLICE_X153Y43.C5 net (fanout=4) 0.076 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + SLICE_X153Y43.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<2>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.042ns logic, 0.076ns route) + (35.6% logic, 64.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.126ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y36.CQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + SLICE_X148Y36.C5 net (fanout=5) 0.087 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<2> + SLICE_X148Y36.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT_1_xo<0>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.039ns logic, 0.087ns route) + (31.0% logic, 69.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.131ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.131ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y36.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + SLICE_X148Y36.A5 net (fanout=6) 0.092 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<0> + SLICE_X148Y36.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_INV_4074_o1_INV_0 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + ------------------------------------------------- --------------------------- + Total 0.131ns (0.039ns logic, 0.092ns route) + (29.8% logic, 70.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.134ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.134ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y36.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + SLICE_X148Y36.D5 net (fanout=6) 0.096 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<0> + SLICE_X148Y36.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT_2_xo<0>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + ------------------------------------------------- --------------------------- + Total 0.134ns (0.038ns logic, 0.096ns route) + (28.4% logic, 71.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.137ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.137ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X149Y36.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + SLICE_X149Y36.B4 net (fanout=2) 0.096 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + SLICE_X149Y36.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<4>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + ------------------------------------------------- --------------------------- + Total 0.137ns (0.041ns logic, 0.096ns route) + (29.9% logic, 70.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.137ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.137ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_emitFCS_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y43.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X147Y43.C5 net (fanout=44) 0.095 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X147Y43.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/Mmux_txRS_emitFCS_D_IN22 + ftop/gbe0/gmac/txRS_emitFCS_1 + ------------------------------------------------- --------------------------- + Total 0.137ns (0.042ns logic, 0.095ns route) + (30.7% logic, 69.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.138ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_1 (FF) + Destination: ftop/gbe0/gmac/txRS_emitFCS_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.138ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_1 to ftop/gbe0/gmac/txRS_emitFCS_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y43.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_1 + SLICE_X147Y43.B5 net (fanout=44) 0.097 ftop/gbe0/gmac/txRS_emitFCS<1> + SLICE_X147Y43.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/Mmux_txRS_emitFCS_D_IN11 + ftop/gbe0/gmac/txRS_emitFCS_0 + ------------------------------------------------- --------------------------- + Total 0.138ns (0.041ns logic, 0.097ns route) + (29.7% logic, 70.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.141ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txActive (FF) + Requirement: 0.000ns + Data Path Delay: 0.153ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_0 to ftop/gbe0/gmac/txRS_txActive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X147Y43.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_0 + SLICE_X147Y42.D6 net (fanout=35) 0.112 ftop/gbe0/gmac/txRS_emitFCS<0> + SLICE_X147Y42.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_txActive + ftop/gbe0/gmac/_n0425 + ftop/gbe0/gmac/txRS_txActive + ------------------------------------------------- --------------------------- + Total 0.153ns (0.041ns logic, 0.112ns route) + (26.8% logic, 73.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.143ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_26 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_12 (FF) + Requirement: 0.000ns + Data Path Delay: 0.180ns (Levels of Logic = 1) + Clock Path Skew: 0.037ns (0.485 - 0.448) + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_26 to ftop/gbe0/gmac/txRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X152Y53.DQ Tcko 0.115 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/txRS_crc/rRemainder_26 + SLICE_X150Y52.C6 net (fanout=15) 0.121 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + SLICE_X150Y52.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<12>3 + ftop/gbe0/gmac/txRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 0.180ns (0.059ns logic, 0.121ns route) + (32.8% logic, 67.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.144ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.144ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_0 to ftop/gbe0/gmac/txRS_ifgCnt_value_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y43.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/txRS_ifgCnt_value_0 + SLICE_X153Y43.B6 net (fanout=6) 0.103 ftop/gbe0/gmac/txRS_ifgCnt_value<0> + SLICE_X153Y43.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<1>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_1 + ------------------------------------------------- --------------------------- + Total 0.144ns (0.041ns logic, 0.103ns route) + (28.5% logic, 71.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.145ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.145ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk_O rising at 8.000ns + Destination Clock: ftop/sys1_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X148Y36.DQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + SLICE_X148Y36.D4 net (fanout=4) 0.107 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + SLICE_X148Y36.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT_2_xo<0>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + ------------------------------------------------- --------------------------- + Total 0.145ns (0.038ns logic, 0.107ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 6.571ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/sys1_clk/I0 + Logical resource: ftop/sys1_clk/I0 + Location pin: BUFGCTRL_X0Y24.I0 + Clock network: ftop/sys1_clki_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_tx_en_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxEna/CK + Location pin: OLOGIC_X2Y63.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_tx_er_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxErr/CK + Location pin: OLOGIC_X2Y62.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_0_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData/CK + Location pin: OLOGIC_X2Y64.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_1_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_1/CK + Location pin: OLOGIC_X2Y65.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_2_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_2/CK + Location pin: OLOGIC_X2Y66.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_3_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_3/CK + Location pin: OLOGIC_X2Y67.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_4_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_4/CK + Location pin: OLOGIC_X2Y68.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_5_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_5/CK + Location pin: OLOGIC_X2Y69.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_6_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_6/CK + Location pin: OLOGIC_X2Y70.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_7_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_7/CK + Location pin: OLOGIC_X2Y71.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_gtx_clk_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxClk/CK + Location pin: OLOGIC_X2Y46.CLK + Clock network: ftop/sys1_clk_O +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/phyRst/rstSync/reset_hold<0>/SR + Logical resource: ftop/gbe0/phyRst/rstSync/reset_hold_0/SR + Location pin: SLICE_X93Y35.SR + Clock network: ftop/gbe0/phyRst/rstSync/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: gmii_rstn_OBUF/SR + Logical resource: ftop/gbe0/phyRst/rstSync/reset_hold_1/SR + Location pin: SLICE_X93Y36.SR + Clock network: ftop/gbe0/phyRst/rstSync/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold<0>/SR + Logical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold_0/SR + Location pin: SLICE_X142Y50.SR + Clock network: ftop/gbe0/gmac/txRS_txRst/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txRst_OUT_RST/SR + Logical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold_1/SR + Location pin: SLICE_X143Y50.SR + Clock network: ftop/gbe0/gmac/txRS_txRst/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txOperateS_dD_OUT/SR + Logical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2/SR + Location pin: SLICE_X145Y26.SR + Clock network: ftop/gbe0/gmac/txRS_txOperateS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1/SR + Logical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1/SR + Location pin: SLICE_X145Y27.SR + Clock network: ftop/gbe0/gmac/txRS_txOperateS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txF/dEnqPtr<3>/SR + Logical resource: ftop/gbe0/gmac/txRS_txF/dSyncReg1_0/SR + Location pin: SLICE_X148Y34.SR + Clock network: ftop/gbe0/gmac/txRS_txF/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txF/dEnqPtr<3>/SR + Logical resource: ftop/gbe0/gmac/txRS_txF/dEnqPtr_0/SR + Location pin: SLICE_X148Y34.SR + Clock network: ftop/gbe0/gmac/txRS_txF/sRST_inv +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD +TIMEGRP "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 75774 paths analyzed, 22660 endpoints analyzed, 23 failing endpoints + 23 timing errors detected. (23 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 5.120ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.120ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_cpt_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.967ns (Levels of Logic = 3) + Clock Path Skew: -0.095ns (1.537 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_cpt_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y212.C6 net (fanout=7) 0.515 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y212.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_cpt_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_2 + SLICE_X35Y212.SR net (fanout=7) 0.485 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_2 + SLICE_X35Y212.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_cpt_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_cpt_r + ------------------------------------------------- --------------------------- + Total 4.967ns (1.054ns logic, 3.913ns route) + (21.2% logic, 78.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.075ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pol_min_rsync_marg_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.955ns (Levels of Logic = 3) + Clock Path Skew: -0.062ns (1.570 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pol_min_rsync_marg_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y212.C6 net (fanout=7) 0.515 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y212.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_cpt_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_2 + SLICE_X43Y213.SR net (fanout=7) 0.473 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_2 + SLICE_X43Y213.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<107> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pol_min_rsync_marg_r + ------------------------------------------------- --------------------------- + Total 4.955ns (1.054ns logic, 3.901ns route) + (21.3% logic, 78.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.059ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rden_wait_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.935ns (Levels of Logic = 3) + Clock Path Skew: -0.066ns (1.566 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rden_wait_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X38Y214.B6 net (fanout=7) 0.422 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X38Y214.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_1 + SLICE_X41Y211.SR net (fanout=6) 0.546 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_1 + SLICE_X41Y211.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rden_wait_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rden_wait_r + ------------------------------------------------- --------------------------- + Total 4.935ns (1.054ns logic, 3.881ns route) + (21.4% logic, 78.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.034ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_9 (FF) + Requirement: 5.000ns + Data Path Delay: 4.881ns (Levels of Logic = 3) + Clock Path Skew: -0.095ns (1.537 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D6 net (fanout=7) 0.517 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<84> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y216.SR net (fanout=6) 0.397 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y216.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_9 + ------------------------------------------------- --------------------------- + Total 4.881ns (1.054ns logic, 3.827ns route) + (21.6% logic, 78.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.034ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_8 (FF) + Requirement: 5.000ns + Data Path Delay: 4.881ns (Levels of Logic = 3) + Clock Path Skew: -0.095ns (1.537 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D6 net (fanout=7) 0.517 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<84> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y216.SR net (fanout=6) 0.397 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y216.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_8 + ------------------------------------------------- --------------------------- + Total 4.881ns (1.054ns logic, 3.827ns route) + (21.6% logic, 78.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.034ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_11 (FF) + Requirement: 5.000ns + Data Path Delay: 4.881ns (Levels of Logic = 3) + Clock Path Skew: -0.095ns (1.537 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D6 net (fanout=7) 0.517 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<84> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y216.SR net (fanout=6) 0.397 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y216.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_11 + ------------------------------------------------- --------------------------- + Total 4.881ns (1.054ns logic, 3.827ns route) + (21.6% logic, 78.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.034ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_10 (FF) + Requirement: 5.000ns + Data Path Delay: 4.881ns (Levels of Logic = 3) + Clock Path Skew: -0.095ns (1.537 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D6 net (fanout=7) 0.517 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<84> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y216.SR net (fanout=6) 0.397 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y216.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_10 + ------------------------------------------------- --------------------------- + Total 4.881ns (1.054ns logic, 3.827ns route) + (21.6% logic, 78.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.029ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_valid_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.869ns (Levels of Logic = 3) + Clock Path Skew: -0.102ns (1.530 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_valid_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y212.C6 net (fanout=7) 0.515 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y212.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_cpt_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_2 + SLICE_X33Y215.SR net (fanout=7) 0.387 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_2 + SLICE_X33Y215.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<23> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/old_sr_valid_r + ------------------------------------------------- --------------------------- + Total 4.869ns (1.054ns logic, 3.815ns route) + (21.6% logic, 78.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.016ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_2 (FF) + Requirement: 5.000ns + Data Path Delay: 4.866ns (Levels of Logic = 3) + Clock Path Skew: -0.092ns (1.540 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D6 net (fanout=7) 0.517 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<84> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y214.SR net (fanout=6) 0.382 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y214.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_2 + ------------------------------------------------- --------------------------- + Total 4.866ns (1.054ns logic, 3.812ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.016ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_3 (FF) + Requirement: 5.000ns + Data Path Delay: 4.866ns (Levels of Logic = 3) + Clock Path Skew: -0.092ns (1.540 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D6 net (fanout=7) 0.517 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<84> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y214.SR net (fanout=6) 0.382 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y214.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_3 + ------------------------------------------------- --------------------------- + Total 4.866ns (1.054ns logic, 3.812ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.016ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_0 (FF) + Requirement: 5.000ns + Data Path Delay: 4.866ns (Levels of Logic = 3) + Clock Path Skew: -0.092ns (1.540 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D6 net (fanout=7) 0.517 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<84> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y214.SR net (fanout=6) 0.382 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y214.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_0 + ------------------------------------------------- --------------------------- + Total 4.866ns (1.054ns logic, 3.812ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.016ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.866ns (Levels of Logic = 3) + Clock Path Skew: -0.092ns (1.540 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D6 net (fanout=7) 0.517 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<84> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y214.SR net (fanout=6) 0.382 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y214.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_1 + ------------------------------------------------- --------------------------- + Total 4.866ns (1.054ns logic, 3.812ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.015ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_clkdiv_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.872ns (Levels of Logic = 3) + Clock Path Skew: -0.085ns (1.547 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_clkdiv_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y212.C6 net (fanout=7) 0.515 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y212.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_cpt_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_2 + SLICE_X39Y210.SR net (fanout=7) 0.390 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_2 + SLICE_X39Y210.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_clkdiv_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_clkdiv_r + ------------------------------------------------- --------------------------- + Total 4.872ns (1.054ns logic, 3.818ns route) + (21.6% logic, 78.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.009ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_valid_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.853ns (Levels of Logic = 3) + Clock Path Skew: -0.098ns (1.534 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_valid_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y212.C6 net (fanout=7) 0.515 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y212.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/new_cnt_cpt_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_2 + SLICE_X35Y215.SR net (fanout=7) 0.371 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_2 + SLICE_X35Y215.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_valid_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_valid_r + ------------------------------------------------- --------------------------- + Total 4.853ns (1.054ns logic, 3.799ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.009ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.848ns (Levels of Logic = 3) + Clock Path Skew: -0.103ns (1.018 - 1.121) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X46Y190.A6 net (fanout=11) 0.600 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X46Y190.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<243> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_20 + SLICE_X53Y182.D6 net (fanout=9) 0.722 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_20 + SLICE_X53Y182.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + SLICE_X55Y171.SR net (fanout=5) 0.841 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + SLICE_X55Y171.CLK Tsrck 0.513 ftop/dram0/memc_memc_dbg_cpt_second_edge_cnt<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_4 + ------------------------------------------------- --------------------------- + Total 4.848ns (1.054ns logic, 3.794ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.009ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.848ns (Levels of Logic = 3) + Clock Path Skew: -0.103ns (1.018 - 1.121) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X46Y190.A6 net (fanout=11) 0.600 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X46Y190.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<243> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_20 + SLICE_X53Y182.D6 net (fanout=9) 0.722 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_20 + SLICE_X53Y182.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + SLICE_X55Y171.SR net (fanout=5) 0.841 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + SLICE_X55Y171.CLK Tsrck 0.513 ftop/dram0/memc_memc_dbg_cpt_second_edge_cnt<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_1 + ------------------------------------------------- --------------------------- + Total 4.848ns (1.054ns logic, 3.794ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.009ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_2 (FF) + Requirement: 5.000ns + Data Path Delay: 4.848ns (Levels of Logic = 3) + Clock Path Skew: -0.103ns (1.018 - 1.121) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X46Y190.A6 net (fanout=11) 0.600 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X46Y190.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<243> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_20 + SLICE_X53Y182.D6 net (fanout=9) 0.722 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_20 + SLICE_X53Y182.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + SLICE_X55Y171.SR net (fanout=5) 0.841 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + SLICE_X55Y171.CLK Tsrck 0.513 ftop/dram0/memc_memc_dbg_cpt_second_edge_cnt<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_2 + ------------------------------------------------- --------------------------- + Total 4.848ns (1.054ns logic, 3.794ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.009ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_3 (FF) + Requirement: 5.000ns + Data Path Delay: 4.848ns (Levels of Logic = 3) + Clock Path Skew: -0.103ns (1.018 - 1.121) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X46Y190.A6 net (fanout=11) 0.600 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X46Y190.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<243> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_20 + SLICE_X53Y182.D6 net (fanout=9) 0.722 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_20 + SLICE_X53Y182.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + SLICE_X55Y171.SR net (fanout=5) 0.841 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_6 + SLICE_X55Y171.CLK Tsrck 0.513 ftop/dram0/memc_memc_dbg_cpt_second_edge_cnt<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_cpt_second_edge_taps<0>_3 + ------------------------------------------------- --------------------------- + Total 4.848ns (1.054ns logic, 3.794ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.008ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/idel_tap_cnt_cpt_r_4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.852ns (Levels of Logic = 3) + Clock Path Skew: -0.098ns (1.534 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/idel_tap_cnt_cpt_r_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y211.A6 net (fanout=7) 0.524 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X35Y211.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_idel_tap_cnt_cpt_r_val + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_idel_tap_cnt_cpt_r_val1 + SLICE_X33Y211.SR net (fanout=3) 0.361 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_idel_tap_cnt_cpt_r_val + SLICE_X33Y211.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<47> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/idel_tap_cnt_cpt_r_4 + ------------------------------------------------- --------------------------- + Total 4.852ns (1.054ns logic, 3.798ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.003ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.851ns (Levels of Logic = 3) + Clock Path Skew: -0.094ns (1.538 - 1.632) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y184.DQ Tcko 0.337 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_32 + SLICE_X43Y195.C6 net (fanout=270) 1.631 ftop/dram0/memc_memc/rst + SLICE_X43Y195.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_13 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B6 net (fanout=11) 1.282 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X33Y217.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/store_sr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D6 net (fanout=7) 0.517 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/rst_19 + SLICE_X30Y213.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<84> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val1 + SLICE_X29Y215.SR net (fanout=6) 0.367 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/Mcount_detect_edge_cnt0_r_val + SLICE_X29Y215.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r<7> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/detect_edge_cnt0_r_4 + ------------------------------------------------- --------------------------- + Total 4.851ns (1.054ns logic, 3.797ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.057ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_02 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.066ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.055 - 0.046) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_02 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X19Y216.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_02 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_02 + SLICE_X18Y216.C6 net (fanout=1) 0.044 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_02 + SLICE_X18Y216.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r[2][1]_prev_sr_rise0_r[2][1]_equal_278_o21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_2 + ------------------------------------------------- --------------------------- + Total 0.066ns (0.022ns logic, 0.044ns route) + (33.3% logic, 66.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.063ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_12 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_12 (FF) + Requirement: 0.000ns + Data Path Delay: 0.098ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.478 - 0.443) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_12 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X17Y217.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_15 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_12 + SLICE_X18Y216.CX net (fanout=5) 0.113 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_12 + SLICE_X18Y216.CLK Tckdi (-Th) 0.113 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise0_r_12 + ------------------------------------------------- --------------------------- + Total 0.098ns (-0.015ns logic, 0.113ns route) + (-15.3% logic, 115.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.065ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/mask_data_fall1_r1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/mask_data_fall1_r2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.173ns (Levels of Logic = 0) + Clock Path Skew: 0.108ns (0.800 - 0.692) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/mask_data_fall1_r1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/mask_data_fall1_r2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X67Y198.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/mask_data_fall1_r1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/mask_data_fall1_r1 + SLICE_X66Y200.AX net (fanout=3) 0.151 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/mask_data_fall1_r1 + SLICE_X66Y200.CLK Tckdi (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/out_d1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/mask_data_fall1_r2 + ------------------------------------------------- --------------------------- + Total 0.173ns (0.022ns logic, 0.151ns route) + (12.7% logic, 87.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.067ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cnt_eye_size_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/found_stable_eye_r (FF) + Requirement: 0.000ns + Data Path Delay: 0.076ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.055 - 0.046) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cnt_eye_size_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/found_stable_eye_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X19Y223.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<66> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cnt_eye_size_r_1 + SLICE_X18Y223.A6 net (fanout=3) 0.054 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<66> + SLICE_X18Y223.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<42> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/GND_168_o_GND_168_o_equal_360_o<2>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/found_stable_eye_r + ------------------------------------------------- --------------------------- + Total 0.076ns (0.022ns logic, 0.054ns route) + (28.9% logic, 71.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.067ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_17 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_rise0_r_7 (FF) + Requirement: 0.000ns + Data Path Delay: 0.076ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.053 - 0.044) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_17 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_rise0_r_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X15Y217.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_17 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_17 + SLICE_X14Y217.D6 net (fanout=5) 0.055 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_17 + SLICE_X14Y217.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_rise0_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r[7][1]_pat_rise0[3][1]_equal_572_o<1>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/pat_match_rise0_r_7 + ------------------------------------------------- --------------------------- + Total 0.076ns (0.021ns logic, 0.055ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.068ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<0>_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.077ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.050 - 0.041) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<0>_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X29Y219.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r_1 + SLICE_X28Y219.A6 net (fanout=5) 0.055 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_r<1> + SLICE_X28Y219.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<0><4> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_max_cnt_rd_dly_r[4]_cal2_dly_cnt_r[4]_sub_787_OUT<2>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<0>_2 + ------------------------------------------------- --------------------------- + Total 0.077ns (0.022ns logic, 0.055ns route) + (28.6% logic, 71.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.071ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_15 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.080ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.053 - 0.044) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_15 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X17Y217.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_15 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_15 + SLICE_X16Y217.B6 net (fanout=5) 0.059 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r_15 + SLICE_X16Y217.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise0_r[5][1]_prev_sr_rise0_r[5][1]_equal_305_o21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise0_r_5 + ------------------------------------------------- --------------------------- + Total 0.080ns (0.021ns logic, 0.059ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.075ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_52 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.513 - 0.477) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_52 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X59Y191.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<55> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_52 + SLICE_X60Y190.AI net (fanout=1) 0.100 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<52> + SLICE_X60Y190.CLK Tdh (-Th) 0.087 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<49> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMA + ------------------------------------------------- --------------------------- + Total 0.111ns (0.011ns logic, 0.100ns route) + (9.9% logic, 90.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.041ns (0.494 - 0.453) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X46Y154.AQ Tcko 0.115 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X50Y152.D1 net (fanout=23) 0.282 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X50Y152.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMC + ------------------------------------------------- --------------------------- + Total 0.118ns (-0.164ns logic, 0.282ns route) + (-139.0% logic, 239.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMD (RAM) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.041ns (0.494 - 0.453) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X46Y154.AQ Tcko 0.115 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X50Y152.D1 net (fanout=23) 0.282 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X50Y152.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMD + ------------------------------------------------- --------------------------- + Total 0.118ns (-0.164ns logic, 0.282ns route) + (-139.0% logic, 239.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMC_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.041ns (0.494 - 0.453) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X46Y154.AQ Tcko 0.115 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X50Y152.D1 net (fanout=23) 0.282 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X50Y152.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 0.118ns (-0.164ns logic, 0.282ns route) + (-139.0% logic, 239.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.041ns (0.494 - 0.453) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X46Y154.AQ Tcko 0.115 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X50Y152.D1 net (fanout=23) 0.282 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X50Y152.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.118ns (-0.164ns logic, 0.282ns route) + (-139.0% logic, 239.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.041ns (0.494 - 0.453) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X46Y154.AQ Tcko 0.115 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X50Y152.D1 net (fanout=23) 0.282 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X50Y152.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.118ns (-0.164ns logic, 0.282ns route) + (-139.0% logic, 239.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.041ns (0.494 - 0.453) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X46Y154.AQ Tcko 0.115 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X50Y152.D1 net (fanout=23) 0.282 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X50Y152.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMB + ------------------------------------------------- --------------------------- + Total 0.118ns (-0.164ns logic, 0.282ns route) + (-139.0% logic, 239.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.041ns (0.494 - 0.453) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X46Y154.AQ Tcko 0.115 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X50Y152.D1 net (fanout=23) 0.282 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X50Y152.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 0.118ns (-0.164ns logic, 0.282ns route) + (-139.0% logic, 239.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr_0 (FF) + Destination: ftop/dram0/lrespF/Mram_fifoMem20_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.041ns (0.494 - 0.453) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr_0 to ftop/dram0/lrespF/Mram_fifoMem20_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X46Y154.AQ Tcko 0.115 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_0 + SLICE_X50Y152.D1 net (fanout=23) 0.282 ftop/dram0/lrespF/sGEnqPtr<0> + SLICE_X50Y152.CLK Tah (-Th) 0.279 ftop/dram0/lrespF/_n0091<119> + ftop/dram0/lrespF/Mram_fifoMem20_RAMA + ------------------------------------------------- --------------------------- + Total 0.118ns (-0.164ns logic, 0.282ns route) + (-139.0% logic, 239.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.078ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_fall0_r_02 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_fall0_r_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.113ns (Levels of Logic = 1) + Clock Path Skew: 0.035ns (0.484 - 0.449) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_fall0_r_02 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_fall0_r_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y221.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_fall0_r_02 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_fall0_r_02 + SLICE_X8Y221.C6 net (fanout=1) 0.091 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_fall0_r_02 + SLICE_X8Y221.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_fall0_r_3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r[2][1]_prev_sr_fall0_r[2][1]_equal_279_o21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_fall0_r_2 + ------------------------------------------------- --------------------------- + Total 0.113ns (0.022ns logic, 0.091ns route) + (19.5% logic, 80.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.080ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/occupied_counter.occ_cnt_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/occupied_counter.occ_cnt_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.092ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/occupied_counter.occ_cnt_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/occupied_counter.occ_cnt_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X94Y206.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/occupied_counter.occ_cnt<1> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/occupied_counter.occ_cnt_1 + SLICE_X95Y206.A6 net (fanout=3) 0.049 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/occupied_counter.occ_cnt<1> + SLICE_X95Y206.CLK Tah (-Th) 0.055 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/occupied_counter.occ_cnt<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_data_end_GND_176_o_select_33_OUT<2>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/occupied_counter.occ_cnt_2 + ------------------------------------------------- --------------------------- + Total 0.092ns (0.043ns logic, 0.049ns route) + (46.7% logic, 53.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise1_r_17 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise1_r_7 (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.033ns (0.482 - 0.449) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise1_r_17 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise1_r_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X15Y213.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise1_r_17 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise1_r_17 + SLICE_X16Y213.D6 net (fanout=1) 0.093 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise1_r_17 + SLICE_X16Y213.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise1_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise1_r[7][1]_prev_sr_rise1_r[7][1]_equal_325_o21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise1_r_7 + ------------------------------------------------- --------------------------- + Total 0.114ns (0.021ns logic, 0.093ns route) + (18.4% logic, 81.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise1_r_16 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise1_r_6 (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.033ns (0.482 - 0.449) + Source Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc_tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise1_r_16 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise1_r_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X15Y213.CQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise1_r_17 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise1_r_16 + SLICE_X16Y213.C6 net (fanout=1) 0.092 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_rise1_r_16 + SLICE_X16Y213.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise1_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_rise1_r[6][1]_prev_sr_rise1_r[6][1]_equal_316_o21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_rise1_r_6 + ------------------------------------------------- --------------------------- + Total 0.114ns (0.022ns logic, 0.092ns route) + (19.3% logic, 80.7% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMA/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMA/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMA_D1/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMA_D1/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMB/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMB/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMB_D1/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMB_D1/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMC/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMC/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMC_D1/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMC_D1/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMD/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMD/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMD_D1/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<101>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem17_RAMD_D1/CLK + Location pin: SLICE_X44Y152.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<29>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem5_RAMA/CLK + Location pin: SLICE_X44Y158.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<29>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem5_RAMA/CLK + Location pin: SLICE_X44Y158.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<29>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem5_RAMA_D1/CLK + Location pin: SLICE_X44Y158.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<29>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem5_RAMA_D1/CLK + Location pin: SLICE_X44Y158.CLK + Clock network: ftop/dram0/memc_memc_tb_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll = +PERIOD TIMEGRP "ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll" +TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.429ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll" TS_SYS0CLK * 2 + HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 1.071ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Location pin: BUFGCTRL_X0Y26.I0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- +Slack: 997.500ns (max period limit - period) + Period: 2.500ns + Max period limit: 1000.000ns (1.000MHz) (Tbcper_I) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Location pin: BUFGCTRL_X0Y26.I0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_clk_wr_i = PERIOD TIMEGRP +"ftop_dram0_memc_memc_clk_wr_i" TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.110ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.610ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<7> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_7 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.131ns (Levels of Logic = 1) + Clock Path Delay: 1.266ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<7> to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC13.I Tiopi 0.369 gmii_rxd<7> + gmii_rxd<7> + gmii_rxd_7_IBUF + SLICE_X92Y43.DX net (fanout=1) 0.767 gmii_rxd_7_IBUF + SLICE_X92Y43.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_7 + ------------------------------------------------- --------------------------- + Total 1.131ns (0.364ns logic, 0.767ns route) + (32.2% logic, 67.8% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y43.CLK net (fanout=42) 0.351 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.266ns (0.774ns logic, 0.492ns route) + (61.1% logic, 38.9% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.671ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<7> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_7 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.702ns (Levels of Logic = 1) + Clock Path Delay: 2.506ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<7> to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC13.I Tiopi 0.669 gmii_rxd<7> + gmii_rxd<7> + gmii_rxd_7_IBUF + SLICE_X92Y43.DX net (fanout=1) 1.201 gmii_rxd_7_IBUF + SLICE_X92Y43.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_7 + ------------------------------------------------- --------------------------- + Total 1.702ns (0.501ns logic, 1.201ns route) + (29.4% logic, 70.6% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y43.CLK net (fanout=42) 0.895 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.506ns (1.227ns logic, 1.279ns route) + (49.0% logic, 51.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.143ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.643ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<6> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_6 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.098ns (Levels of Logic = 1) + Clock Path Delay: 1.266ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<6> to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC12.I Tiopi 0.374 gmii_rxd<6> + gmii_rxd<6> + gmii_rxd_6_IBUF + SLICE_X92Y43.CX net (fanout=1) 0.729 gmii_rxd_6_IBUF + SLICE_X92Y43.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_6 + ------------------------------------------------- --------------------------- + Total 1.098ns (0.369ns logic, 0.729ns route) + (33.6% logic, 66.4% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y43.CLK net (fanout=42) 0.351 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.266ns (0.774ns logic, 0.492ns route) + (61.1% logic, 38.9% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.602ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<6> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_6 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.633ns (Levels of Logic = 1) + Clock Path Delay: 2.506ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<6> to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC12.I Tiopi 0.672 gmii_rxd<6> + gmii_rxd<6> + gmii_rxd_6_IBUF + SLICE_X92Y43.CX net (fanout=1) 1.129 gmii_rxd_6_IBUF + SLICE_X92Y43.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_6 + ------------------------------------------------- --------------------------- + Total 1.633ns (0.504ns logic, 1.129ns route) + (30.9% logic, 69.1% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y43.CLK net (fanout=42) 0.895 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.506ns (1.227ns logic, 1.279ns route) + (49.0% logic, 51.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.166ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.666ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<5> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_5 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.075ns (Levels of Logic = 1) + Clock Path Delay: 1.266ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<5> to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AD11.I Tiopi 0.390 gmii_rxd<5> + gmii_rxd<5> + gmii_rxd_5_IBUF + SLICE_X92Y43.BX net (fanout=1) 0.690 gmii_rxd_5_IBUF + SLICE_X92Y43.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_5 + ------------------------------------------------- --------------------------- + Total 1.075ns (0.385ns logic, 0.690ns route) + (35.8% logic, 64.2% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y43.CLK net (fanout=42) 0.351 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.266ns (0.774ns logic, 0.492ns route) + (61.1% logic, 38.9% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.574ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<5> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_5 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.605ns (Levels of Logic = 1) + Clock Path Delay: 2.506ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<5> to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AD11.I Tiopi 0.686 gmii_rxd<5> + gmii_rxd<5> + gmii_rxd_5_IBUF + SLICE_X92Y43.BX net (fanout=1) 1.087 gmii_rxd_5_IBUF + SLICE_X92Y43.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_5 + ------------------------------------------------- --------------------------- + Total 1.605ns (0.518ns logic, 1.087ns route) + (32.3% logic, 67.7% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y43.CLK net (fanout=42) 0.895 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.506ns (1.227ns logic, 1.279ns route) + (49.0% logic, 51.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.207ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.707ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<4> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_4 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.034ns (Levels of Logic = 1) + Clock Path Delay: 1.266ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<4> to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM12.I Tiopi 0.433 gmii_rxd<4> + gmii_rxd<4> + gmii_rxd_4_IBUF + SLICE_X92Y43.AX net (fanout=1) 0.606 gmii_rxd_4_IBUF + SLICE_X92Y43.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_4 + ------------------------------------------------- --------------------------- + Total 1.034ns (0.428ns logic, 0.606ns route) + (41.4% logic, 58.6% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y43.CLK net (fanout=42) 0.351 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.266ns (0.774ns logic, 0.492ns route) + (61.1% logic, 38.9% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.482ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<4> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_4 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.513ns (Levels of Logic = 1) + Clock Path Delay: 2.506ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<4> to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM12.I Tiopi 0.723 gmii_rxd<4> + gmii_rxd<4> + gmii_rxd_4_IBUF + SLICE_X92Y43.AX net (fanout=1) 0.958 gmii_rxd_4_IBUF + SLICE_X92Y43.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_4 + ------------------------------------------------- --------------------------- + Total 1.513ns (0.555ns logic, 0.958ns route) + (36.7% logic, 63.3% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y43.CLK net (fanout=42) 0.895 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.506ns (1.227ns logic, 1.279ns route) + (49.0% logic, 51.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.147ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.647ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<3> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_3 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.140ns (Levels of Logic = 1) + Clock Path Delay: 1.312ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<3> to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN12.I Tiopi 0.435 gmii_rxd<3> + gmii_rxd<3> + gmii_rxd_3_IBUF + SLICE_X92Y37.DX net (fanout=1) 0.710 gmii_rxd_3_IBUF + SLICE_X92Y37.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_3 + ------------------------------------------------- --------------------------- + Total 1.140ns (0.430ns logic, 0.710ns route) + (37.7% logic, 62.3% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y37.CLK net (fanout=42) 0.397 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.312ns (0.774ns logic, 0.538ns route) + (59.0% logic, 41.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.547ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<3> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_3 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.632ns (Levels of Logic = 1) + Clock Path Delay: 2.560ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<3> to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN12.I Tiopi 0.725 gmii_rxd<3> + gmii_rxd<3> + gmii_rxd_3_IBUF + SLICE_X92Y37.DX net (fanout=1) 1.075 gmii_rxd_3_IBUF + SLICE_X92Y37.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_3 + ------------------------------------------------- --------------------------- + Total 1.632ns (0.557ns logic, 1.075ns route) + (34.1% logic, 65.9% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y37.CLK net (fanout=42) 0.949 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.560ns (1.227ns logic, 1.333ns route) + (47.9% logic, 52.1% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.229ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.729ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<2> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_2 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.058ns (Levels of Logic = 1) + Clock Path Delay: 1.312ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<2> to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AE14.I Tiopi 0.375 gmii_rxd<2> + gmii_rxd<2> + gmii_rxd_2_IBUF + SLICE_X92Y37.CX net (fanout=1) 0.688 gmii_rxd_2_IBUF + SLICE_X92Y37.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_2 + ------------------------------------------------- --------------------------- + Total 1.058ns (0.370ns logic, 0.688ns route) + (35.0% logic, 65.0% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y37.CLK net (fanout=42) 0.397 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.312ns (0.774ns logic, 0.538ns route) + (59.0% logic, 41.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.500ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<2> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_2 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.585ns (Levels of Logic = 1) + Clock Path Delay: 2.560ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<2> to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AE14.I Tiopi 0.673 gmii_rxd<2> + gmii_rxd<2> + gmii_rxd_2_IBUF + SLICE_X92Y37.CX net (fanout=1) 1.080 gmii_rxd_2_IBUF + SLICE_X92Y37.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_2 + ------------------------------------------------- --------------------------- + Total 1.585ns (0.505ns logic, 1.080ns route) + (31.9% logic, 68.1% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y37.CLK net (fanout=42) 0.949 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.560ns (1.227ns logic, 1.333ns route) + (47.9% logic, 52.1% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.278ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.778ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<1> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_1 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.009ns (Levels of Logic = 1) + Clock Path Delay: 1.312ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<1> to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AF14.I Tiopi 0.381 gmii_rxd<1> + gmii_rxd<1> + gmii_rxd_1_IBUF + SLICE_X92Y37.BX net (fanout=1) 0.633 gmii_rxd_1_IBUF + SLICE_X92Y37.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_1 + ------------------------------------------------- --------------------------- + Total 1.009ns (0.376ns logic, 0.633ns route) + (37.3% logic, 62.7% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y37.CLK net (fanout=42) 0.397 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.312ns (0.774ns logic, 0.538ns route) + (59.0% logic, 41.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.414ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<1> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_1 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.499ns (Levels of Logic = 1) + Clock Path Delay: 2.560ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<1> to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AF14.I Tiopi 0.678 gmii_rxd<1> + gmii_rxd<1> + gmii_rxd_1_IBUF + SLICE_X92Y37.BX net (fanout=1) 0.989 gmii_rxd_1_IBUF + SLICE_X92Y37.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_1 + ------------------------------------------------- --------------------------- + Total 1.499ns (0.510ns logic, 0.989ns route) + (34.0% logic, 66.0% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y37.CLK net (fanout=42) 0.949 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.560ns (1.227ns logic, 1.333ns route) + (47.9% logic, 52.1% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.236ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.736ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.051ns (Levels of Logic = 1) + Clock Path Delay: 1.312ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN13.I Tiopi 0.435 gmii_rxd<0> + gmii_rxd<0> + gmii_rxd_0_IBUF + SLICE_X92Y37.AX net (fanout=1) 0.621 gmii_rxd_0_IBUF + SLICE_X92Y37.CLK Tdick -0.005 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_0 + ------------------------------------------------- --------------------------- + Total 1.051ns (0.430ns logic, 0.621ns route) + (40.9% logic, 59.1% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y37.CLK net (fanout=42) 0.397 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.312ns (0.774ns logic, 0.538ns route) + (59.0% logic, 41.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.449ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.534ns (Levels of Logic = 1) + Clock Path Delay: 2.560ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN13.I Tiopi 0.725 gmii_rxd<0> + gmii_rxd<0> + gmii_rxd_0_IBUF + SLICE_X92Y37.AX net (fanout=1) 0.977 gmii_rxd_0_IBUF + SLICE_X92Y37.CLK Tckdi (-Th) 0.168 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_0 + ------------------------------------------------- --------------------------- + Total 1.534ns (0.557ns logic, 0.977ns route) + (36.3% logic, 63.7% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X92Y37.CLK net (fanout=42) 0.949 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.560ns (1.227ns logic, 1.333ns route) + (47.9% logic, 52.1% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.243ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.743ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rx_dv (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.048ns (Levels of Logic = 1) + Clock Path Delay: 1.316ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rx_dv to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM13.I Tiopi 0.425 gmii_rx_dv + gmii_rx_dv + gmii_rx_dv_IBUF + SLICE_X95Y38.CX net (fanout=1) 0.619 gmii_rx_dv_IBUF + SLICE_X95Y38.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + ------------------------------------------------- --------------------------- + Total 1.048ns (0.429ns logic, 0.619ns route) + (40.9% logic, 59.1% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X95Y38.CLK net (fanout=42) 0.401 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.316ns (0.774ns logic, 0.542ns route) + (58.8% logic, 41.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.457ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rx_dv (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.549ns (Levels of Logic = 1) + Clock Path Delay: 2.567ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rx_dv to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM13.I Tiopi 0.716 gmii_rx_dv + gmii_rx_dv + gmii_rx_dv_IBUF + SLICE_X95Y38.CX net (fanout=1) 0.972 gmii_rx_dv_IBUF + SLICE_X95Y38.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + ------------------------------------------------- --------------------------- + Total 1.549ns (0.577ns logic, 0.972ns route) + (37.2% logic, 62.8% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X95Y38.CLK net (fanout=42) 0.956 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.567ns (1.227ns logic, 1.340ns route) + (47.8% logic, 52.2% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.479ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.979ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rx_er (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.761ns (Levels of Logic = 1) + Clock Path Delay: 1.265ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rx_er to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AG12.I Tiopi 0.393 gmii_rx_er + gmii_rx_er + gmii_rx_er_IBUF + SLICE_X93Y46.AX net (fanout=1) 0.364 gmii_rx_er_IBUF + SLICE_X93Y46.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 0.761ns (0.397ns logic, 0.364ns route) + (52.2% logic, 47.8% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X93Y46.CLK net (fanout=42) 0.350 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.265ns (0.774ns logic, 0.491ns route) + (61.2% logic, 38.8% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.076ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rx_er (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.106ns (Levels of Logic = 1) + Clock Path Delay: 2.505ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rx_er to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AG12.I Tiopi 0.689 gmii_rx_er + gmii_rx_er + gmii_rx_er_IBUF + SLICE_X93Y46.AX net (fanout=1) 0.556 gmii_rx_er_IBUF + SLICE_X93Y46.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 1.106ns (0.550ns logic, 0.556ns route) + (49.7% logic, 50.3% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly_DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X93Y46.CLK net (fanout=42) 0.894 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.505ns (1.227ns logic, 1.278ns route) + (49.0% logic, 51.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: Pin to Pin Skew Constraint; + + 1 path analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- +Slack: 0.108ns (maxskew - uncertainty - (arrival1 - arrival2)) + Max skew: 0.450ns + Arrival 1: 2.658ns ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Arrival 2: 2.505ns ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/USERCLK + Clock Uncertainty: 0.189ns + +-------------------------------------------------------------------------------- + + +Derived Constraint Report +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 5.000ns| 4.761ns| 5.120ns| 0| 23| 91995| 75774| +| TS_ftop_dram0_memc_memc_u_infr| 5.000ns| 5.120ns| N/A| 23| 0| 75774| 0| +| astructure_clk_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_u_infr| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| +| astructure_clk_mem_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0| +| _i | | | | | | | | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +Derived Constraints for TS_PCICLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_PCICLK | 4.000ns| 1.538ns| 4.204ns| 0| 132| 0| 11123906| +| TS_CLK_125 | 8.000ns| 8.251ns| N/A| 38| 0| 11104609| 0| +| TS_CLK_250 | 4.000ns| 4.204ns| N/A| 94| 0| 19297| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +3 constraints not met. + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Setup/Hold to clock gmii_rx_clk +------------+------------+------------+------------+------------+------------------+--------+ + |Max Setup to| Process |Max Hold to | Process | | Clock | +Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | +------------+------------+------------+------------+------------+------------------+--------+ +gmii_rx_dv | -0.243(R)| FAST | 1.043(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rx_er | -0.479(R)| FAST | 1.424(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<0> | -0.236(R)| FAST | 1.051(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<1> | -0.278(R)| FAST | 1.086(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<2> | -0.229(R)| FAST | 1.000(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<3> | -0.147(R)| FAST | 0.953(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<4> | -0.207(R)| FAST | 1.018(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<5> | -0.166(R)| FAST | 0.926(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<6> | -0.143(R)| FAST | 0.898(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<7> | -0.110(R)| FAST | 0.829(R)| SLOW |ftop/rxclkBnd | 0.000| +------------+------------+------------+------------+------------+------------------+--------+ + +Clock to Setup on destination clock gmii_rx_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +gmii_rx_clk | 6.951| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 5.120| | | | +sys0_clkp | 5.120| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 5.120| | | | +sys0_clkp | 5.120| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys1_clkn | 5.007| | | | +sys1_clkp | 5.007| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys1_clkn | 5.007| | | | +sys1_clkp | 5.007| | | | +---------------+---------+---------+---------+---------+ + +COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.719; Ideal Clock Offset To Actual Clock 0.531; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<7> | -0.110(R)| FAST | 0.829(R)| SLOW | 0.610| 1.671| -0.531| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.110| - | 0.829| - | 0.610| 1.671| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.755; Ideal Clock Offset To Actual Clock 0.480; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<6> | -0.143(R)| FAST | 0.898(R)| SLOW | 0.643| 1.602| -0.480| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.143| - | 0.898| - | 0.643| 1.602| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.760; Ideal Clock Offset To Actual Clock 0.454; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<5> | -0.166(R)| FAST | 0.926(R)| SLOW | 0.666| 1.574| -0.454| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.166| - | 0.926| - | 0.666| 1.574| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.811; Ideal Clock Offset To Actual Clock 0.388; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<4> | -0.207(R)| FAST | 1.018(R)| SLOW | 0.707| 1.482| -0.388| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.207| - | 1.018| - | 0.707| 1.482| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.806; Ideal Clock Offset To Actual Clock 0.450; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<3> | -0.147(R)| FAST | 0.953(R)| SLOW | 0.647| 1.547| -0.450| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.147| - | 0.953| - | 0.647| 1.547| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.771; Ideal Clock Offset To Actual Clock 0.386; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<2> | -0.229(R)| FAST | 1.000(R)| SLOW | 0.729| 1.500| -0.386| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.229| - | 1.000| - | 0.729| 1.500| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.808; Ideal Clock Offset To Actual Clock 0.318; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<1> | -0.278(R)| FAST | 1.086(R)| SLOW | 0.778| 1.414| -0.318| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.278| - | 1.086| - | 0.778| 1.414| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.815; Ideal Clock Offset To Actual Clock 0.357; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<0> | -0.236(R)| FAST | 1.051(R)| SLOW | 0.736| 1.449| -0.357| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.236| - | 1.051| - | 0.736| 1.449| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.800; Ideal Clock Offset To Actual Clock 0.357; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rx_dv | -0.243(R)| FAST | 1.043(R)| SLOW | 0.743| 1.457| -0.357| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.243| - | 1.043| - | 0.743| 1.457| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.945; Ideal Clock Offset To Actual Clock 0.049; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rx_er | -0.479(R)| FAST | 1.424(R)| SLOW | 0.979| 1.076| -0.049| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.479| - | 1.424| - | 0.979| 1.076| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + + +Timing summary: +--------------- + +Timing errors: 155 Score: 12189 (Setup/Max: 12089, Hold: 100) + +Constraints cover 11300234 paths, 0 nets, and 221646 connections + +Design statistics: + Minimum period: 8.251ns{1} (Maximum frequency: 121.197MHz) + + +------------------------------------Footnotes----------------------------------- +1) The minimum period statistic assumes all single cycle delays. + +Analysis completed Tue Feb 4 15:14:27 2014 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 1684 MB + + + diff --git a/logs/ml605-20140204_1516/fpgaTop_map.mrp b/logs/ml605-20140204_1516/fpgaTop_map.mrp new file mode 100644 index 00000000..2f2f9c9d --- /dev/null +++ b/logs/ml605-20140204_1516/fpgaTop_map.mrp @@ -0,0 +1,8289 @@ +Release 14.7 Map P.20131013 (lin64) +Xilinx Mapping Report File for Design 'fpgaTop' + +Design Information +------------------ +Command Line : map -p xc6vlx240t-ff1156-1 -w -logic_opt on -xe n -mt on -t 1 -register_duplication on -ir off -pr off +-lc off -power off -o fpgaTop_map.ncd fpgaTop.ngd fpgaTop.pcf +Target Device : xc6vlx240t +Target Package : ff1156 +Target Speed : -1 +Mapper Version : virtex6 -- $Revision: 1.55 $ +Mapped Date : Tue Feb 4 14:54:21 2014 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 600 +Slice Logic Utilization: + Number of Slice Registers: 35,528 out of 301,440 11% + Number used as Flip Flops: 35,521 + Number used as Latches: 2 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 5 + Number of Slice LUTs: 43,387 out of 150,720 28% + Number used as logic: 37,439 out of 150,720 24% + Number using O6 output only: 33,860 + Number using O5 output only: 2,410 + Number using O5 and O6: 1,169 + Number used as ROM: 0 + Number used as Memory: 5,083 out of 58,400 8% + Number used as Dual Port RAM: 2,106 + Number using O6 output only: 110 + Number using O5 output only: 53 + Number using O5 and O6: 1,943 + Number used as Single Port RAM: 0 + Number used as Shift Register: 2,977 + Number using O6 output only: 2,977 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 865 + Number with same-slice register load: 733 + Number with same-slice carry load: 130 + Number with other load: 2 + +Slice Logic Distribution: + Number of occupied Slices: 16,807 out of 37,680 44% + Number of LUT Flip Flop pairs used: 51,554 + Number with an unused Flip Flop: 17,143 out of 51,554 33% + Number with an unused LUT: 8,167 out of 51,554 15% + Number of fully used LUT-FF pairs: 26,244 out of 51,554 50% + Number of unique control sets: 1,992 + Number of slice register sites lost + to control set restrictions: 9,595 out of 301,440 3% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + OVERMAPPING of BRAM resources should be ignored if the design is + over-mapped for a non-BRAM resource or if placement fails. + +IO Utilization: + Number of bonded IOBs: 222 out of 600 37% + Number of LOCed IOBs: 222 out of 222 100% + IOB Flip Flops: 12 + IOB Master Pads: 9 + IOB Slave Pads: 9 + Number of bonded IPADs: 12 + Number of LOCed IPADs: 4 out of 12 33% + Number of bonded OPADs: 8 + +Specific Feature Utilization: + Number of RAMB36E1/FIFO36E1s: 38 out of 416 9% + Number using RAMB36E1 only: 38 + Number using FIFO36E1 only: 0 + Number of RAMB18E1/FIFO18E1s: 3 out of 832 1% + Number using RAMB18E1 only: 3 + Number using FIFO18E1 only: 0 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 11 + Number used as BUFGCTRLs: 1 + Number of ILOGICE1/ISERDESE1s: 65 out of 720 9% + Number used as ILOGICE1s: 0 + Number used as ISERDESE1s: 65 + Number of OLOGICE1/OSERDESE1s: 138 out of 720 19% + Number used as OLOGICE1s: 17 + Number used as OSERDESE1s: 121 + Number of BSCANs: 0 out of 4 0% + Number of BUFHCEs: 0 out of 144 0% + Number of BUFIODQSs: 8 out of 72 11% + Number of BUFRs: 3 out of 36 8% + Number of LOCed BUFRs: 2 out of 3 66% + Number of CAPTUREs: 0 out of 1 0% + Number of DSP48E1s: 0 out of 768 0% + Number of EFUSE_USRs: 0 out of 1 0% + Number of FRAME_ECCs: 0 out of 1 0% + Number of GTXE1s: 4 out of 20 20% + Number of LOCed GTXE1s: 4 out of 4 100% + Number of IBUFDS_GTXE1s: 2 out of 12 16% + Number of LOCed IBUFDS_GTXE1s: 1 out of 2 50% + Number of ICAPs: 0 out of 2 0% + Number of IDELAYCTRLs: 4 out of 18 22% + Number of IODELAYE1s: 91 out of 720 12% + Number of LOCed IODELAYE1s: 10 out of 91 10% + Number of MMCM_ADVs: 2 out of 12 16% + Number of PCIE_2_0s: 1 out of 2 50% + Number of LOCed PCIE_2_0s: 1 out of 1 100% + Number of STARTUPs: 1 out of 1 100% + Number of SYSMONs: 0 out of 1 0% + Number of TEMAC_SINGLEs: 0 out of 4 0% + +Average Fanout of Non-Clock Nets: 4.12 + +Peak Memory Usage: 2471 MB +Total REAL time to MAP completion: 13 mins 36 secs +Total CPU time to MAP completion (all processors): 14 mins 26 secs + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_10_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_11_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_12_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_13_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_14_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_15_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_0_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_1_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_2_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_3_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_4_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_5_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_6_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_7_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_8_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_9_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[5].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[2].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col1.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[6].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[3].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[0].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col0.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[7].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[4].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[1].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[5].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[2].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col1.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[6].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[3].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[0].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col0.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[7].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[4].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[1].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync + (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync + (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. + The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:2045 - The MMCM_ADV block has CLKOUT pins + that do not drive the same kind of BUFFER load. Routing from the different buffer types will not be phase aligned. + +Section 3 - Informational +------------------------- +INFO:Map:284 - Map is running with the multi-threading option on. Map currently + supports the use of up to 2 processors. Based on the the user options and + machine load, Map will use 2 processors during this run. +INFO:LIT:243 - Logical network N100 has no load. +INFO:LIT:395 - The above info message is repeated 4337 more times for the + following (max. 5 shown): + N101, + N102, + N103, + N104, + N105 + To see the details of these info messages, please use the -detail switch. +INFO:MapLib:562 - No environment variables are currently set. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs. +INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: + 0.000 to 85.000 Celsius) +INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to + 1.050 Volts) +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report + (.mrp). +INFO:Pack:1650 - Map created a placed design. + +Section 4 - Removed Logic Summary +--------------------------------- + 378 block(s) removed + 421 block(s) optimized away +1789 signal(s) removed + +Section 5 - Removed Logic +------------------------- + +The trimmed logic report below shows the logic removed from your design due to +sourceless or loadless signals, and VCC or ground connections. If the removal +of a signal or symbol results in the subsequent removal of an additional signal +or symbol, the message explaining that second removal will be indented. This +indentation will be repeated as a chain of related logic is removed. + +To quickly locate the original cause for the removal of a chain of logic, look +above the place where that logic is listed in the trimming report, then locate +the lines that are least indented (begin at the leftmost edge). + +Loadless block "ftop/ctop/inf/cpTlp/Msub_byteCount__h207611" (ROM) removed. +Loadless block "ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]11" (ROM) removed. +Loadless block "ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]11" (ROM) removed. +Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram +[0].RAM32M0" (RAM32M) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<4>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<3>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<2>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<1>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<0>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_0" (FF) removed. +Loadless block "ftop/gbe0/gmac/gmii_rx_clk" (BUFIODQS) removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<31>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<30>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<29>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<28>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<27>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<26>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<25>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<24>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<23>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<22>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<21>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<20>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<19>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<18>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<17>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<16>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<15>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<12>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<7>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<6>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<5>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<4>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<3>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<2>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<1>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<0>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<12>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<15>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_powerstate<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_powerstate<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_lane_reversal_mode<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_lane_reversal_mode<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_sel_link_width<1>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_sel_link_width<0>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tcfg_req_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_terr_drop_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_rsrc_dsc_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_rerrfwd_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_rd_wr_done_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_err_cpl_rdy_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_rdy_n" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msienable" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msixenable" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msixfm" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_pme_en" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_pme_status" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_gen2_capable" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_partner_gen2_supported" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_upcfg_capable" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_received_hot_rst" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<6>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<5>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<4>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<63>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<62>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<61>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<60>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<59>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<58>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<57>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<56>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<55>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<54>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<53>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<52>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<51>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<50>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<49>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<48>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<47>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<46>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<45>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<44>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<43>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<42>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<41>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<40>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<39>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<38>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<37>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<36>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<35>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<34>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<33>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<32>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<31>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<30>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<29>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<28>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<27>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<26>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<25>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<24>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<23>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<22>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<21>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<20>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<19>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<18>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<17>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<16>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<15>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<14>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<13>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<12>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<63>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<62>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<61>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<60>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<59>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<58>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<57>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<56>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<55>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<54>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<53>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<52>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<51>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<50>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<49>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<48>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<47>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<46>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<45>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<44>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<43>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<42>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<41>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<40>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<39>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<38>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<37>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<36>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<35>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<34>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<33>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<32>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<31>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<30>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<29>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<28>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<27>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<26>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<25>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<24>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<23>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<22>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<21>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<20>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<19>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<18>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<17>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<16>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<15>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<14>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<13>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<12>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXRADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXRADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXRADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXRADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXWADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXWADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXMARGIN<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXMARGIN<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLRXPMSTATE<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLRXPMSTATE<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGAERECRCCHECKEN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGAERECRCGENEN" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGERRAERHEADERLOGSETN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTA" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTB" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTC" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTD" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTA" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTB" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTC" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTD" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRCOR" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRFATAL" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRNONFATAL" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMASNAK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMETO" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMETOACK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMPME" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDSETSLOTPOWERLIMIT" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDUNLOCK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVASREQL1N" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVENTERL1N" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVENTERL23N" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVREQACKN" is sourceless +and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGSLOTCONTROLELECTROMECHILCTLPULSE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTION" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONTYPE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRA" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRB" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRC" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRD" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRE" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRF" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRG" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRH" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRI" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRJ" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRK" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDRDY" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/LNKCLKEN" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXRESET" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLPHYLNKUPN" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/RECEIVEDFUNCLVLRSTN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/TRNRECRCERRN" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/TRNTDLLPDSTRDYN" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<15>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<14>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<13>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<12>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<11>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<10>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<9>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<8>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<7>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<6>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<5>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<4>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<0>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<31>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<30>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<29>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<28>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<27>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<26>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<25>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<24>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<23>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<22>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<21>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<20>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<19>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<18>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<17>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<16>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<47>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<46>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<45>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<44>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<43>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<42>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<41>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<40>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<39>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<38>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<37>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<36>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<35>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<34>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<33>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<32>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<63>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<62>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<61>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<60>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<59>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<58>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<57>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<56>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<55>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<54>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<53>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<52>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<51>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<50>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<49>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<48>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<71>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<70>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<69>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<71>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<70>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<69>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<68>" +is sourceless and has been removed. +The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty" is sourceless and has been +removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/_n008211" (ROM) removed. + The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/_n0082" is sourceless and has been +removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty" (SFF) removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty_glue_set" (ROM) +removed. + The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty_glue_set" is sourceless and +has been removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<31>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<30>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<29>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<28>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<27>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<26>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<25>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory_DOB<24>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<31>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<30>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<29>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<28>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<27>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<26>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<25>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<24>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<23>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<22>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<21>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<20>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<19>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory_DOB<18>" is sourceless and has been +removed. +The signal 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is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<6>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<5>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<4>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<3>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<2>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<1>" is sourceless and has been +removed. +The signal "ftop/cap0/metaBram_0_memory/DOA<0>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<31>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<30>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<29>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<28>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<27>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<26>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<25>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<24>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<23>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<22>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<21>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<20>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<19>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<18>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<17>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<16>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<15>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<14>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<13>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<12>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<11>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<10>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<9>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<8>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<7>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<6>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<5>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<4>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<3>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<2>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<1>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<0>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<39>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<38>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<37>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<36>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<35>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<34>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<33>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_cpt_tap_cnt<32>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dqs_n_tap_cnt<32>" is sourceless and has +been removed. + Sourceless block "ftop/dram0/memc_memc/scl_inst" (MUX) removed. + The signal "ftop/dram0/memc_memc/scl" is sourceless and has been removed. + Sourceless block "ftop/dram0/memc_memc/sda_inst" (MUX) removed. + The signal "ftop/dram0/memc_memc/sda" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<39>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<38>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<37>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<36>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<35>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<34>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<33>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc_dbg_dq_tap_cnt<32>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/N1" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<39>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<38>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<37>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<36>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<35>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<34>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<33>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<32>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<31>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<30>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<29>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<28>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<27>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<26>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<25>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<24>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<23>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<22>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<21>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<20>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<19>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<18>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<17>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<16>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<15>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<14>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<13>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<12>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<11>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<10>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<9>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<8>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<7>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<6>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<5>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<4>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<3>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<2>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<1>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<0>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/ddr_parity" is sourceless and has +been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<9>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<8>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<7>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<6>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<5>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<4>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<3>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<2>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<1>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<0>" +is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<0>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<0>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/inv_dqs<0>1 +" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<97>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<99>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<100>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<101>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<102>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<103>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<104>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<105>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<106>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<107>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<160>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<161>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<162>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<163>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<164>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<165>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<166>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<167>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<168>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<169>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<170>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<171>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<172>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<173>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<174>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<175>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<176>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<177>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<178>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<179>" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_infrastructure/PSDONE" is sourceless and has +been removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[100].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[101].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[102].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[103].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[104].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[105].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[106].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[107].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[97].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[99].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[160].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[161].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[162].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[163].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[164].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[165].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[166].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[167].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[168].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[169].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[170].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[171].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[172].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[173].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[174].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[175].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[176].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[177].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[178].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[179].u_RAM64X1D" (RAM64X1D) removed. +Unused block "ftop/dram0/memc_memc/XST_GND" (ZERO) removed. +Unused block "ftop/dram0/memc_memc/XST_VCC" (ONE) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/u_out_ +parity" (OSERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. + +Optimized Block(s): +TYPE BLOCK +VCC XST_VCC +GND ftop/XST_GND +VCC ftop/XST_VCC +GND ftop/axbluart/bluart/XST_GND +VCC ftop/axbluart/bluart/XST_VCC +GND ftop/axbluart/bluart/rxF/XST_GND +GND ftop/cap0/XST_GND +VCC ftop/cap0/XST_VCC +GND ftop/cap0/dataBram_0_memory/XST_GND +VCC ftop/cap0/dataBram_0_memory/XST_VCC +GND ftop/cap0/dataBram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_0_memory/XST_GND +VCC ftop/cap0/metaBram_0_memory/XST_VCC +GND ftop/cap0/metaBram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_1_memory/XST_GND +VCC ftop/cap0/metaBram_1_memory/XST_VCC +GND ftop/cap0/metaBram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_2_memory/XST_GND +VCC ftop/cap0/metaBram_2_memory/XST_VCC +GND ftop/cap0/metaBram_2_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_3_memory/XST_GND +VCC ftop/cap0/metaBram_3_memory/XST_VCC +GND ftop/cap0/metaBram_3_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/wci_wslv_reqF/XST_GND +GND ftop/cap0/wsiS_reqFifo/XST_GND +VCC ftop/cap0/wsiS_reqFifo/XST_VCC +GND ftop/ctop/app/XST_GND +GND ftop/ctop/app/appW1/XST_GND +VCC ftop/ctop/app/appW1/XST_VCC +GND ftop/ctop/app/appW1/rgen_gsF/XST_GND +GND ftop/ctop/app/appW1/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW2/XST_GND +VCC ftop/ctop/app/appW2/XST_VCC +GND ftop/ctop/app/appW2/respF_memory/XST_GND +VCC ftop/ctop/app/appW2/respF_memory/XST_VCC +GND ftop/ctop/app/appW2/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW3/XST_GND +VCC ftop/ctop/app/appW3/XST_VCC +GND ftop/ctop/app/appW3/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW3/wsiS_reqFifo/XST_GND +GND ftop/ctop/app/appW4/XST_GND +VCC ftop/ctop/app/appW4/XST_VCC +GND ftop/ctop/app/appW4/respF_memory/XST_GND +VCC ftop/ctop/app/appW4/respF_memory/XST_VCC +GND ftop/ctop/app/appW4/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW4/wsiS_reqFifo/XST_GND +GND ftop/ctop/app/id/XST_GND +VCC ftop/ctop/app/id/XST_VCC +GND ftop/ctop/inf/cp/XST_GND +VCC ftop/ctop/inf/cp/XST_VCC +GND ftop/ctop/inf/cp/rom_memory/XST_GND +VCC ftop/ctop/inf/cp/rom_memory/XST_VCC +GND ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/XST_GND +GND ftop/ctop/inf/cp/timeServ_setRefF/XST_GND +VCC ftop/ctop/inf/cp/wci_10_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_11_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_12_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_13_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_14_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_1_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_2_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_3_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_4_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_8_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_9_mReset/rstSync/XST_VCC +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h207610 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20762 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20763 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20764 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20765 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20766 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20767 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20768 + optimized to 1 +LUT2 ftop/ctop/inf/cpTlp/Msub_byteCount__h20769 + optimized to 1 +GND ftop/ctop/inf/cpTlp/XST_GND +VCC ftop/ctop/inf/cpTlp/XST_VCC +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]10 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]2 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]3 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]4 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]5 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]6 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]7 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]8 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]9 + optimized to 1 +GND ftop/ctop/inf/dp0/XST_GND +VCC ftop/ctop/inf/dp0/XST_VCC +GND ftop/ctop/inf/dp0/bram_0_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_0_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_1_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_1_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_2_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_2_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_3_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_3_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/wci_reqF/XST_GND +GND ftop/ctop/inf/dp0/wmi_wmi_mFlagF/XST_GND +GND ftop/ctop/inf/dp0/wmi_wmi_reqF/XST_GND +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]10 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]2 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]3 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]4 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]5 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]6 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]7 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]8 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]9 + optimized to 1 +GND ftop/ctop/inf/dp1/XST_GND +VCC ftop/ctop/inf/dp1/XST_VCC +GND ftop/ctop/inf/dp1/bram_0_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_0_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_1_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_1_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_2_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_2_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_3_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_3_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/wci_reqF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_dhF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_mFlagF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_reqF/XST_GND +GND ftop/dram0/XST_GND +VCC ftop/dram0/XST_VCC +GND ftop/dram0/dbg_dqs_n_tap_cnt/XST_GND +GND ftop/dram0/dbg_dqs_p_tap_cnt/XST_GND +GND ftop/dram0/dbg_rdlvl_err/XST_GND +GND ftop/dram0/lreqF/XST_GND +GND ftop/dram0/lrespF/XST_GND +GND ftop/dram0/memc_memc/u_infrastructure/XST_GND +VCC ftop/dram0/memc_memc/u_infrastructure/XST_VCC +GND ftop/dram0/memc_memc/u_iodelay_ctrl/XST_GND +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_state0/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].ra +nk_cntrl0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].ra +nk_cntrl0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/XST +_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/XST +_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd +_top/gen_pd[0].gen_pd_inst.u_phy_pd/XST_GND +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wr +lvl/XST_GND +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[ +0].u_phy_ck_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[ +0].u_phy_ck_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/XST_G +ND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/XST_V +CC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[0].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[0].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[1].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[1].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[2].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[2].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[3].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[3].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[4].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[4].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[5].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[5].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[6].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[6].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[7].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[7].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[0 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[0 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[8 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[8 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +0].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +0].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +1].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +1].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +2].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +2].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +3].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +3].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +4].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +4].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +5].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +5].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +6].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +6].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +7].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +7].u_phy_dqs_iob/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk +_gen/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk +_gen/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctr +l_sync/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c0.u_rddata_sync_c0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c0.u_rddata_sync_c0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c1.u_rddata_sync_c1/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c1.u_rddata_sync_c1/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/XST_VCC +VCC ftop/dram0/memc_rst_stretch_n/XST_VCC +GND ftop/dram0/wci_wslv_reqF/XST_GND +GND ftop/flash0/XST_GND +VCC ftop/flash0/XST_VCC +GND ftop/flash0/wci_wslv_reqF/XST_GND +GND ftop/fmc150/XST_GND +VCC ftop/fmc150/XST_VCC +VCC ftop/fmc150/fcCdc_testRst/XST_VCC +VCC ftop/fmc150/spiCDC_slowReset/XST_VCC +VCC ftop/fmc150/spiDAC_slowReset/XST_VCC +GND ftop/fmc150/wci_wslv_reqF/XST_GND +GND ftop/gbe0/XST_GND +VCC ftop/gbe0/XST_VCC +GND ftop/gbe0/gmac/XST_GND +VCC ftop/gbe0/gmac/XST_VCC +GND ftop/gbe0/gmac/rxRS_rxF/XST_GND +VCC ftop/gbe0/gmac/rxRS_rxRst/XST_VCC +GND ftop/gbe0/gmac/txRS_txF/XST_GND +VCC ftop/gbe0/gmac/txRS_txRst/XST_VCC +GND ftop/gbe0/mdi_rPlayIndex/XST_GND +VCC ftop/gbe0/phyRst/rstSync/XST_VCC +GND ftop/gbe0/wci_wslv_reqF/XST_GND +GND ftop/lcd_ctrl/XST_GND +VCC ftop/lcd_ctrl/XST_VCC +GND ftop/pciw_fI2P/XST_GND +GND ftop/pciw_fP2I/XST_GND +VCC ftop/pciw_p125rst/XST_VCC +VCC ftop/pciw_p250rst/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XS +T_VCC +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/XS +T_GND +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/XST_VCC +VCC ftop/sys0_rst/XST_VCC +GND ftop/wmemiTap/XST_GND +VCC ftop/wmemiTap/XST_VCC +LUT2 ftop/ctop/inf/noc_sm2/pktFork/fo1/Result<2>_SW0 + optimized to 0 + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Term | Strength | Rate | | | Delay | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| ddr3_addr<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<3> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<4> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<5> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<6> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<7> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<8> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<9> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<10> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<11> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<12> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_cas_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ck_n<0> | IOBS | OUTPUT | DIFF_SSTL15 | | | | | | | +| ddr3_ck_p<0> | IOBM | OUTPUT | DIFF_SSTL15 | | | | OSERDES | | | +| ddr3_cke<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_cs_n<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_dm<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<3> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<4> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<5> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<6> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<7> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dq<0> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<1> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<2> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<3> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<4> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<5> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<6> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<7> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<8> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<9> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<10> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<11> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<12> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<13> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<14> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<15> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<16> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<17> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<18> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<19> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<20> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<21> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<22> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<23> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<24> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<25> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<26> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<27> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<28> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<29> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<30> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<31> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<32> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<33> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<34> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<35> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<36> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<37> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<38> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<39> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<40> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<41> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<42> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<43> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<44> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<45> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<46> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<47> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<48> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<49> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<50> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<51> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<52> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<53> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<54> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<55> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<56> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<57> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<58> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<59> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<60> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<61> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<62> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<63> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dqs_n<0> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<1> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<2> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<3> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<4> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<5> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<6> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<7> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_p<0> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dqs_p<1> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<2> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<3> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<4> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<5> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<6> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<7> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_odt<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ras_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_reset_n | IOB | OUTPUT | SSTL15 | | | | ODDR | | | +| ddr3_we_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| flash_addr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_ce_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_oe_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_wait | IOB | INPUT | LVCMOS25 | | | | | | | +| flash_we_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_clk_n | IOB | INPUT | LVDS_25 | TRUE | | | | | | +| flp_cdc_clk_p | IOB | INPUT | LVDS_25 | TRUE | | | | | | +| flp_cdc_csb | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_pdn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_refen | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_rstn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_sdi | IOB | INPUT | LVCMOS25 | | | | | | | +| flp_com_sclk | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_com_sdc2m | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_dac_csb | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_dac_sdi | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_gtx_clk | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_rstn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| gmii_rx_clk | IOB | INPUT | LVCMOS25 | | | | | | FIXED | +| gmii_rx_dv | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rx_er | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<0> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<1> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<2> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<3> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<4> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<5> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<6> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<7> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_tx_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_tx_er | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| lcd_db<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_e | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_rs | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_rw | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| mdio_mdc | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| mdio_mdd | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| pci0_clkn | IPAD | INPUT | | | | | | | | +| pci0_clkp | IPAD | INPUT | | | | | | | | +| pci0_reset_n | IOB | INPUT | LVCMOS25 | | | | | PULLUP | | +| pci_exp_rxn<0> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<1> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<2> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<3> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<0> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<1> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<2> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<3> | IPAD | INPUT | | | | | | | | +| pci_exp_txn<0> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<1> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<2> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<3> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<0> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<1> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<2> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<3> | OPAD | OUTPUT | | | | | | | | +| ppsExtIn | IOB | INPUT | LVCMOS25 | | | | | | | +| ppsOut | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| sys0_clkn | IOB | INPUT | LVDS_25 | FALSE | | | | | | +| sys0_clkp | IOB | INPUT | LVDS_25 | FALSE | | | | | | +| sys1_clkn | IPAD | INPUT | | | | | | | | +| sys1_clkp | IPAD | INPUT | | | | | | | | +| upads_cts_arg | IOB | INPUT | LVCMOS25 | | | | | | | +| upads_rts | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| upads_rx_arg | IOB | INPUT | LVCMOS25 | | | | | | | +| upads_tx | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + +Area Group "AG_pcie0" + No COMPRESSION specified for Area Group "AG_pcie0" + RANGE: SLICE_X136Y147:SLICE_X155Y120 + Slice Logic Utilization: + Number of Slice Registers: 460 out of 4,480 10% + Number of Slice LUTs: 688 out of 2,240 30% + Number used as logic: 682 + Number used as Memory: 6 + Slice Logic Distribution: + Number of occupied Slices: 260 out of 560 46% + Number of LUT Flip Flop pairs used: 756 + Number with an unused Flip Flop: 324 out of 756 42% + Number with an unused LUT: 58 out of 756 7% + Number of fully used LUT-FF pairs: 374 out of 756 49% + Number of RAMB36E1/FIFO36E1s: 8 + Number using RAMB36E1 only: 8 + Number using FIFO36E1 only: 0 + + +Section 10 - Timing Report +-------------------------- +A logic-level (pre-route) timing report can be generated by using Xilinx static +timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the +mapped NCD and PCF files. Please note that this timing report will be generated +using estimated delay information. For accurate numbers, please generate a +timing report with the post Place and Route NCD file. + +For more information about the Timing Analyzer, consult the Xilinx Timing +Analyzer Reference Manual; for more information about TRCE, consult the Xilinx +Command Line Tools User Guide "TRACE" chapter. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +Use the "-detail" map option to print out Control Set Information. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. diff --git a/rtl/mkCTop16B.v b/rtl/mkCTop16B.v index 98e8e131..c7f1e061 100644 --- a/rtl/mkCTop16B.v +++ b/rtl/mkCTop16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Feb 3 15:31:29 EST 2014 +// On Tue Feb 4 14:45:38 EST 2014 // // // Ports: diff --git a/rtl/mkFTop_ml605.v b/rtl/mkFTop_ml605.v index 6383984c..13e4e120 100644 --- a/rtl/mkFTop_ml605.v +++ b/rtl/mkFTop_ml605.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Feb 3 15:31:34 EST 2014 +// On Tue Feb 4 14:45:44 EST 2014 // // // Ports: diff --git a/rtl/mkMemiTestWorker.v b/rtl/mkMemiTestWorker.v index 290f59b3..c9ad1193 100644 --- a/rtl/mkMemiTestWorker.v +++ b/rtl/mkMemiTestWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Feb 3 15:05:00 EST 2014 +// On Tue Feb 4 14:43:52 EST 2014 // // // Ports: @@ -257,6 +257,10 @@ module mkMemiTestWorker(wciS0_Clk, wire [31 : 0] hwordAddr_D_IN; wire hwordAddr_EN; + // register isCharPush + reg isCharPush; + wire isCharPush_D_IN, isCharPush_EN; + // register isReader reg isReader; wire isReader_D_IN, isReader_EN; @@ -489,7 +493,8 @@ module mkMemiTestWorker(wciS0_Clk, wmemi_respF_FULL_N; // rule scheduling signals - wire WILL_FIRE_RL_read_req, + wire WILL_FIRE_RL_char_push, + WILL_FIRE_RL_read_req, WILL_FIRE_RL_read_resp, WILL_FIRE_RL_wci_cfrd, WILL_FIRE_RL_wci_cfwr, @@ -510,29 +515,31 @@ module mkMemiTestWorker(wciS0_Clk, WILL_FIRE_RL_write_req; // inputs to muxes for submodule ports - reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2; + reg [51 : 0] MUX_wmemi_reqF_q_0_write_1__VAL_1; + reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1; wire [145 : 0] MUX_wmemi_dhF_q_0_write_1__VAL_1, MUX_wmemi_dhF_q_0_write_1__VAL_2, - MUX_wmemi_dhF_q_1_write_1__VAL_1; - wire [51 : 0] MUX_wmemi_reqF_q_0_write_1__VAL_1, - MUX_wmemi_reqF_q_0_write_1__VAL_2, - MUX_wmemi_reqF_q_1_write_1__VAL_1, + MUX_wmemi_dhF_q_1_write_1__VAL_2, + MUX_wmemi_dhF_x_wire_wset_1__VAL_1; + wire [51 : 0] MUX_wmemi_reqF_q_0_write_1__VAL_2, + MUX_wmemi_reqF_q_1_write_1__VAL_2, MUX_wmemi_reqF_x_wire_wset_1__VAL_1, MUX_wmemi_reqF_x_wire_wset_1__VAL_2; - wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1, - MUX_wci_wslv_respF_q_1_write_1__VAL_1, + wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2, + MUX_wci_wslv_respF_q_1_write_1__VAL_2, MUX_wci_wslv_respF_x_wire_wset_1__VAL_1, MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; wire [31 : 0] MUX_unrollCnt_write_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2, MUX_wmemi_dhF_cntr_r_write_1__VAL_2, MUX_wmemi_reqF_cntr_r_write_1__VAL_2; - wire MUX_isReader_write_1__SEL_1, + wire MUX_isCharPush_write_1__SEL_1, MUX_isReader_write_1__SEL_2, MUX_isTesting_write_1__SEL_1, MUX_unrollCnt_write_1__SEL_1, MUX_wci_wslv_illegalEdge_write_1__SEL_1, - MUX_wci_wslv_illegalEdge_write_1__VAL_1, + MUX_wci_wslv_illegalEdge_write_1__SEL_2, + MUX_wci_wslv_illegalEdge_write_1__VAL_2, MUX_wci_wslv_respF_q_0_write_1__SEL_1, MUX_wci_wslv_respF_q_0_write_1__SEL_2, MUX_wci_wslv_respF_q_1_write_1__SEL_1, @@ -547,20 +554,21 @@ module mkMemiTestWorker(wciS0_Clk, MUX_wmemi_reqF_q_1_write_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h14155, v__h14921, v__h3568, v__h3743, v__h3887; - reg [31 : 0] g_data__h14736; - wire [35 : 0] addr__h13592; - wire [31 : 0] rdat__h14758, testStatus__h14232; + reg [63 : 0] v__h14270, v__h15171, v__h3568, v__h3743, v__h3887; + reg [31 : 0] g_data__h14986; + wire [35 : 0] addr__h13652; + wire [31 : 0] rdat__h15008, testStatus__h14482; wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, wmemi_dhF_cntr_r_84_MINUS_1___d193, wmemi_reqF_cntr_r_61_MINUS_1___d170; - wire NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311, + wire NOT_rgen_gsF_first__12_EQ_wmemi_respF_first__1_ETC___d316, _dfoo1, _dfoo11, _dfoo3, _dfoo5, _dfoo7, - _dfoo9; + _dfoo9, + wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -649,6 +657,14 @@ module mkMemiTestWorker(wciS0_Clk, .FULL_N(wmemi_respF_FULL_N), .EMPTY_N(wmemi_respF_EMPTY_N)); + // rule RL_char_push + assign WILL_FIRE_RL_char_push = + wmemi_reqF_cntr_r != 2'd2 && wmemi_dhF_cntr_r != 2'd2 && + wmemi_operateD && + wmemi_peerIsReady && + wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272 && + isCharPush ; + // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N && @@ -662,10 +678,8 @@ module mkMemiTestWorker(wciS0_Clk, wmemi_operateD && wmemi_peerIsReady && wgen_gsF_EMPTY_N && - wci_wslv_cState == 3'd2 && - isTesting && - isWriter && - !isReader ; + wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272 && + !isCharPush ; // rule RL_read_req assign WILL_FIRE_RL_read_req = @@ -751,20 +765,20 @@ module mkMemiTestWorker(wciS0_Clk, // rule RL_wmemi_dhF_incCtr assign WILL_FIRE_RL_wmemi_dhF_incCtr = - WILL_FIRE_RL_write_req && WILL_FIRE_RL_write_req && + wmemi_dhF_x_wire_whas && wmemi_dhF_enqueueing_whas && !wmemi_dhF_dequeueing_whas ; // rule RL_wmemi_dhF_decCtr assign WILL_FIRE_RL_wmemi_dhF_decCtr = - wmemi_dhF_dequeueing_whas && !WILL_FIRE_RL_write_req ; + wmemi_dhF_dequeueing_whas && !wmemi_dhF_enqueueing_whas ; // rule RL_wmemi_dhF_both assign WILL_FIRE_RL_wmemi_dhF_both = - WILL_FIRE_RL_write_req && wmemi_dhF_dequeueing_whas && - WILL_FIRE_RL_write_req ; + wmemi_dhF_x_wire_whas && wmemi_dhF_dequeueing_whas && + wmemi_dhF_enqueueing_whas ; // inputs to muxes for submodule ports - assign MUX_isReader_write_1__SEL_1 = + assign MUX_isCharPush_write_1__SEL_1 = WILL_FIRE_RL_read_req && unrollCnt == 32'd1 ; assign MUX_isReader_write_1__SEL_2 = WILL_FIRE_RL_write_req && unrollCnt == 32'd1 ; @@ -776,6 +790,8 @@ module mkMemiTestWorker(wciS0_Clk, WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[63:32] == 32'h00000030 ; assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + assign MUX_wci_wslv_illegalEdge_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -789,43 +805,39 @@ module mkMemiTestWorker(wciS0_Clk, wci_wslv_reqF_D_OUT[36:34] == 3'd6 || wci_wslv_reqF_D_OUT[36:34] == 3'd7) ; assign MUX_wci_wslv_respF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; - assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; - assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_cntr_r == 2'd1 ; + assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wmemi_dhF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wmemi_dhF_both && _dfoo11 ; - assign MUX_wmemi_dhF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd0 ; + assign MUX_wmemi_dhF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmemi_dhF_both && _dfoo11 ; assign MUX_wmemi_dhF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wmemi_dhF_both && _dfoo9 ; - assign MUX_wmemi_dhF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd1 ; + assign MUX_wmemi_dhF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmemi_dhF_both && _dfoo9 ; assign MUX_wmemi_reqF_q_0_write_1__SEL_1 = - WILL_FIRE_RL_wmemi_reqF_both && _dfoo7 ; - assign MUX_wmemi_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_cntr_r == 2'd0 ; + assign MUX_wmemi_reqF_q_0_write_1__SEL_2 = + WILL_FIRE_RL_wmemi_reqF_both && _dfoo7 ; assign MUX_wmemi_reqF_q_1_write_1__SEL_1 = - WILL_FIRE_RL_wmemi_reqF_both && _dfoo5 ; - assign MUX_wmemi_reqF_q_1_write_1__SEL_2 = WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_cntr_r == 2'd1 ; + assign MUX_wmemi_reqF_q_1_write_1__SEL_2 = + WILL_FIRE_RL_wmemi_reqF_both && _dfoo5 ; assign MUX_unrollCnt_write_1__VAL_2 = (unrollCnt == 32'd1) ? seqLen : unrollCnt - 32'd1 ; - assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 = + assign MUX_wci_wslv_illegalEdge_write_1__VAL_2 = wci_wslv_reqF_D_OUT[36:34] != 3'd4 && wci_wslv_reqF_D_OUT[36:34] != 3'd5 && wci_wslv_reqF_D_OUT[36:34] != 3'd6 ; assign MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 = wci_wslv_respF_cntr_r + 2'd1 ; - assign MUX_wci_wslv_respF_q_0_write_1__VAL_1 = - (wci_wslv_respF_cntr_r == 2'd1) ? - MUX_wci_wslv_respF_q_0_write_1__VAL_2 : - wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_wci_cfrd or @@ -833,50 +845,72 @@ module mkMemiTestWorker(wciS0_Clk, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wci_wslv_ctl_op_complete: - MUX_wci_wslv_respF_q_0_write_1__VAL_2 = + MUX_wci_wslv_respF_q_0_write_1__VAL_1 = MUX_wci_wslv_respF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_wci_cfrd: - MUX_wci_wslv_respF_q_0_write_1__VAL_2 = + MUX_wci_wslv_respF_q_0_write_1__VAL_1 = MUX_wci_wslv_respF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_wci_cfwr: - MUX_wci_wslv_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201; - default: MUX_wci_wslv_respF_q_0_write_1__VAL_2 = + MUX_wci_wslv_respF_q_0_write_1__VAL_1 = 34'h1C0DE4201; + default: MUX_wci_wslv_respF_q_0_write_1__VAL_1 = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_wslv_respF_q_1_write_1__VAL_1 = + assign MUX_wci_wslv_respF_q_0_write_1__VAL_2 = + (wci_wslv_respF_cntr_r == 2'd1) ? + MUX_wci_wslv_respF_q_0_write_1__VAL_1 : + wci_wslv_respF_q_1 ; + assign MUX_wci_wslv_respF_q_1_write_1__VAL_2 = (wci_wslv_respF_cntr_r == 2'd2) ? - MUX_wci_wslv_respF_q_0_write_1__VAL_2 : + MUX_wci_wslv_respF_q_0_write_1__VAL_1 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, g_data__h14736 } ; + assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, g_data__h14986 } ; assign MUX_wmemi_dhF_cntr_r_write_1__VAL_2 = wmemi_dhF_cntr_r + 2'd1 ; assign MUX_wmemi_dhF_q_0_write_1__VAL_1 = + WILL_FIRE_RL_write_req ? + MUX_wmemi_dhF_x_wire_wset_1__VAL_1 : + 146'h30000000000000000000000000000002BFFFF ; + assign MUX_wmemi_dhF_q_0_write_1__VAL_2 = (wmemi_dhF_cntr_r == 2'd1) ? - MUX_wmemi_dhF_q_0_write_1__VAL_2 : + MUX_wmemi_dhF_q_0_write_1__VAL_1 : wmemi_dhF_q_1 ; - assign MUX_wmemi_dhF_q_0_write_1__VAL_2 = - { 2'd3, wgen_gsF_D_OUT, 16'd65535 } ; - assign MUX_wmemi_dhF_q_1_write_1__VAL_1 = + assign MUX_wmemi_dhF_q_1_write_1__VAL_2 = (wmemi_dhF_cntr_r == 2'd2) ? - MUX_wmemi_dhF_q_0_write_1__VAL_2 : + MUX_wmemi_dhF_q_0_write_1__VAL_1 : 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + assign MUX_wmemi_dhF_x_wire_wset_1__VAL_1 = + { 2'd3, wgen_gsF_D_OUT, 16'd65535 } ; assign MUX_wmemi_reqF_cntr_r_write_1__VAL_2 = wmemi_reqF_cntr_r + 2'd1 ; - assign MUX_wmemi_reqF_q_0_write_1__VAL_1 = + always@(WILL_FIRE_RL_write_req or + MUX_wmemi_reqF_x_wire_wset_1__VAL_1 or + WILL_FIRE_RL_read_req or + MUX_wmemi_reqF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_char_push) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_write_req: + MUX_wmemi_reqF_q_0_write_1__VAL_1 = + MUX_wmemi_reqF_x_wire_wset_1__VAL_1; + WILL_FIRE_RL_read_req: + MUX_wmemi_reqF_q_0_write_1__VAL_1 = + MUX_wmemi_reqF_x_wire_wset_1__VAL_2; + WILL_FIRE_RL_char_push: + MUX_wmemi_reqF_q_0_write_1__VAL_1 = 52'h308000002C001; + default: MUX_wmemi_reqF_q_0_write_1__VAL_1 = + 52'hAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wmemi_reqF_q_0_write_1__VAL_2 = (wmemi_reqF_cntr_r == 2'd1) ? - MUX_wmemi_reqF_q_0_write_1__VAL_2 : + MUX_wmemi_reqF_q_0_write_1__VAL_1 : wmemi_reqF_q_1 ; - assign MUX_wmemi_reqF_q_0_write_1__VAL_2 = - WILL_FIRE_RL_write_req ? - MUX_wmemi_reqF_x_wire_wset_1__VAL_1 : - MUX_wmemi_reqF_x_wire_wset_1__VAL_2 ; - assign MUX_wmemi_reqF_q_1_write_1__VAL_1 = + assign MUX_wmemi_reqF_q_1_write_1__VAL_2 = (wmemi_reqF_cntr_r == 2'd2) ? - MUX_wmemi_reqF_q_0_write_1__VAL_2 : + MUX_wmemi_reqF_q_0_write_1__VAL_1 : 52'h0AAAAAAAAAAAA ; - assign MUX_wmemi_reqF_x_wire_wset_1__VAL_1 = { 4'd3, addr__h13592, 12'd1 } ; - assign MUX_wmemi_reqF_x_wire_wset_1__VAL_2 = { 4'd5, addr__h13592, 12'd1 } ; + assign MUX_wmemi_reqF_x_wire_wset_1__VAL_1 = { 4'd3, addr__h13652, 12'd1 } ; + assign MUX_wmemi_reqF_x_wire_wset_1__VAL_2 = { 4'd5, addr__h13652, 12'd1 } ; // inlined wires assign wci_wslv_wciReq_wget = @@ -886,7 +920,7 @@ module mkMemiTestWorker(wciS0_Clk, wciS0_MAddr, wciS0_MData } ; assign wci_wslv_wciReq_whas = 1'd1 ; - assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_2 ; + assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_1 ; assign wci_wslv_respF_x_wire_whas = WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ; @@ -908,11 +942,13 @@ module mkMemiTestWorker(wciS0_Clk, assign wci_wci_Es_mAddr_w_whas = 1'd1 ; assign wci_wci_Es_mData_w_wget = wciS0_MData ; assign wci_wci_Es_mData_w_whas = 1'd1 ; - assign wmemi_reqF_x_wire_wget = MUX_wmemi_reqF_q_0_write_1__VAL_2 ; + assign wmemi_reqF_x_wire_wget = MUX_wmemi_reqF_q_0_write_1__VAL_1 ; assign wmemi_reqF_x_wire_whas = - WILL_FIRE_RL_write_req || WILL_FIRE_RL_read_req ; - assign wmemi_dhF_x_wire_wget = MUX_wmemi_dhF_q_0_write_1__VAL_2 ; - assign wmemi_dhF_x_wire_whas = WILL_FIRE_RL_write_req ; + WILL_FIRE_RL_write_req || WILL_FIRE_RL_read_req || + WILL_FIRE_RL_char_push ; + assign wmemi_dhF_x_wire_wget = MUX_wmemi_dhF_q_0_write_1__VAL_1 ; + assign wmemi_dhF_x_wire_whas = + WILL_FIRE_RL_write_req || WILL_FIRE_RL_char_push ; assign wmemi_wmemiResponse_wget = { wmemiM0_SResp, wmemiM0_SRespLast, wmemiM0_SData } ; assign wmemi_wmemiResponse_whas = 1'd1 ; @@ -948,10 +984,12 @@ module mkMemiTestWorker(wciS0_Clk, wci_wslv_reqF_EMPTY_N && !wci_wslv_reqF_D_OUT[68] && wci_wslv_reqF_D_OUT[71:69] == 3'd2 ; assign wmemi_reqF_enqueueing_whas = - WILL_FIRE_RL_read_req || WILL_FIRE_RL_write_req ; + WILL_FIRE_RL_char_push || WILL_FIRE_RL_read_req || + WILL_FIRE_RL_write_req ; assign wmemi_reqF_dequeueing_whas = wmemiM0_SCmdAccept && wmemi_reqF_cntr_r != 2'd0 ; - assign wmemi_dhF_enqueueing_whas = WILL_FIRE_RL_write_req ; + assign wmemi_dhF_enqueueing_whas = + WILL_FIRE_RL_char_push || WILL_FIRE_RL_write_req ; assign wmemi_dhF_dequeueing_whas = wmemiM0_SDataAccept && wmemi_dhF_cntr_r != 2'd0 ; assign wmemi_Em_sRespLast_w_whas = wmemiM0_SRespLast ; @@ -960,7 +998,7 @@ module mkMemiTestWorker(wciS0_Clk, assign errorCount_D_IN = errorCount + 32'd1 ; assign errorCount_EN = WILL_FIRE_RL_read_resp && - NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311 ; + NOT_rgen_gsF_first__12_EQ_wmemi_respF_first__1_ETC___d316 ; // register freeCnt assign freeCnt_D_IN = freeCnt + 32'd1 ; @@ -968,10 +1006,16 @@ module mkMemiTestWorker(wciS0_Clk, // register hwordAddr assign hwordAddr_D_IN = (unrollCnt == 32'd1) ? 32'd0 : hwordAddr + 32'd1 ; - assign hwordAddr_EN = wmemi_reqF_enqueueing_whas ; + assign hwordAddr_EN = WILL_FIRE_RL_read_req || WILL_FIRE_RL_write_req ; + + // register isCharPush + assign isCharPush_D_IN = MUX_isCharPush_write_1__SEL_1 && tstCtrl[1] ; + assign isCharPush_EN = + WILL_FIRE_RL_read_req && unrollCnt == 32'd1 || + WILL_FIRE_RL_char_push ; // register isReader - assign isReader_D_IN = !MUX_isReader_write_1__SEL_1 ; + assign isReader_D_IN = !MUX_isCharPush_write_1__SEL_1 ; assign isReader_EN = WILL_FIRE_RL_read_req && unrollCnt == 32'd1 || WILL_FIRE_RL_write_req && unrollCnt == 32'd1 ; @@ -982,7 +1026,7 @@ module mkMemiTestWorker(wciS0_Clk, wci_wslv_reqF_D_OUT[63:32] == 32'h00000030 ; assign isTesting_EN = WILL_FIRE_RL_read_resp && - NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311 && + NOT_rgen_gsF_first__12_EQ_wmemi_respF_first__1_ETC___d316 && tstCtrl[0] || WILL_FIRE_RL_wci_cfwr && (wci_wslv_reqF_D_OUT[63:32] == 32'h00000030 || @@ -1000,7 +1044,7 @@ module mkMemiTestWorker(wciS0_Clk, // register rdDuration assign rdDuration_D_IN = freeCnt - rdCycStart ; - assign rdDuration_EN = MUX_isReader_write_1__SEL_1 ; + assign rdDuration_EN = MUX_isCharPush_write_1__SEL_1 ; // register respCnt assign respCnt_D_IN = 32'h0 ; @@ -1022,7 +1066,7 @@ module mkMemiTestWorker(wciS0_Clk, // register testCycleCount assign testCycleCount_D_IN = testCycleCount + 32'd1 ; - assign testCycleCount_EN = MUX_isReader_write_1__SEL_1 ; + assign testCycleCount_EN = MUX_isCharPush_write_1__SEL_1 ; // register tstCtrl assign tstCtrl_D_IN = wci_wslv_reqF_D_OUT[31:0] ; @@ -1067,11 +1111,11 @@ module mkMemiTestWorker(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge_D_IN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 && - MUX_wci_wslv_illegalEdge_write_1__VAL_1 ; + !MUX_wci_wslv_illegalEdge_write_1__SEL_1 && + MUX_wci_wslv_illegalEdge_write_1__VAL_2 ; assign wci_wslv_illegalEdge_EN = - MUX_wci_wslv_illegalEdge_write_1__SEL_1 || - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || + MUX_wci_wslv_illegalEdge_write_1__SEL_2 ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ; @@ -1134,23 +1178,23 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wci_wslv_respF_q_0_EN = - WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_cntr_r == 2'd0 || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 always@(MUX_wci_wslv_respF_q_1_write_1__SEL_1 or - MUX_wci_wslv_respF_q_1_write_1__VAL_1 or + MUX_wci_wslv_respF_q_0_write_1__VAL_1 or MUX_wci_wslv_respF_q_1_write_1__SEL_2 or - MUX_wci_wslv_respF_q_0_write_1__VAL_2 or + MUX_wci_wslv_respF_q_1_write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wci_wslv_respF_q_1_write_1__SEL_1: - wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_1; + wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_1; MUX_wci_wslv_respF_q_1_write_1__SEL_2: - wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2; + wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_2; WILL_FIRE_RL_wci_wslv_respF_decCtr: wci_wslv_respF_q_1_D_IN = 34'h0AAAAAAAA; default: wci_wslv_respF_q_1_D_IN = @@ -1158,9 +1202,9 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wci_wslv_respF_q_1_EN = - WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_cntr_r == 2'd1 || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -1221,21 +1265,21 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wmemi_dhF_q_0_EN = - WILL_FIRE_RL_wmemi_dhF_both && _dfoo11 || WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmemi_dhF_both && _dfoo11 || WILL_FIRE_RL_wmemi_dhF_decCtr ; // register wmemi_dhF_q_1 always@(MUX_wmemi_dhF_q_1_write_1__SEL_1 or - MUX_wmemi_dhF_q_1_write_1__VAL_1 or + MUX_wmemi_dhF_q_0_write_1__VAL_1 or MUX_wmemi_dhF_q_1_write_1__SEL_2 or - MUX_wmemi_dhF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr) + MUX_wmemi_dhF_q_1_write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmemi_dhF_q_1_write_1__SEL_1: - wmemi_dhF_q_1_D_IN = MUX_wmemi_dhF_q_1_write_1__VAL_1; + wmemi_dhF_q_1_D_IN = MUX_wmemi_dhF_q_0_write_1__VAL_1; MUX_wmemi_dhF_q_1_write_1__SEL_2: - wmemi_dhF_q_1_D_IN = MUX_wmemi_dhF_q_0_write_1__VAL_2; + wmemi_dhF_q_1_D_IN = MUX_wmemi_dhF_q_1_write_1__VAL_2; WILL_FIRE_RL_wmemi_dhF_decCtr: wmemi_dhF_q_1_D_IN = 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; default: wmemi_dhF_q_1_D_IN = @@ -1243,8 +1287,8 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wmemi_dhF_q_1_EN = - WILL_FIRE_RL_wmemi_dhF_both && _dfoo9 || WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmemi_dhF_both && _dfoo9 || WILL_FIRE_RL_wmemi_dhF_decCtr ; // register wmemi_errorSticky @@ -1290,29 +1334,29 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wmemi_reqF_q_0_EN = - WILL_FIRE_RL_wmemi_reqF_both && _dfoo7 || WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmemi_reqF_both && _dfoo7 || WILL_FIRE_RL_wmemi_reqF_decCtr ; // register wmemi_reqF_q_1 always@(MUX_wmemi_reqF_q_1_write_1__SEL_1 or - MUX_wmemi_reqF_q_1_write_1__VAL_1 or + MUX_wmemi_reqF_q_0_write_1__VAL_1 or MUX_wmemi_reqF_q_1_write_1__SEL_2 or - MUX_wmemi_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmemi_reqF_decCtr) + MUX_wmemi_reqF_q_1_write_1__VAL_2 or WILL_FIRE_RL_wmemi_reqF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmemi_reqF_q_1_write_1__SEL_1: - wmemi_reqF_q_1_D_IN = MUX_wmemi_reqF_q_1_write_1__VAL_1; + wmemi_reqF_q_1_D_IN = MUX_wmemi_reqF_q_0_write_1__VAL_1; MUX_wmemi_reqF_q_1_write_1__SEL_2: - wmemi_reqF_q_1_D_IN = MUX_wmemi_reqF_q_0_write_1__VAL_2; + wmemi_reqF_q_1_D_IN = MUX_wmemi_reqF_q_1_write_1__VAL_2; WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_1_D_IN = 52'h0AAAAAAAAAAAA; default: wmemi_reqF_q_1_D_IN = 52'hAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign wmemi_reqF_q_1_EN = - WILL_FIRE_RL_wmemi_reqF_both && _dfoo5 || WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmemi_reqF_both && _dfoo5 || WILL_FIRE_RL_wmemi_reqF_decCtr ; // register wmemi_statusR @@ -1331,7 +1375,7 @@ module mkMemiTestWorker(wciS0_Clk, // register wtCycStart assign wtCycStart_D_IN = freeCnt ; - assign wtCycStart_EN = MUX_isReader_write_1__SEL_1 ; + assign wtCycStart_EN = MUX_isCharPush_write_1__SEL_1 ; // register wtDuration assign wtDuration_D_IN = freeCnt - wtCycStart ; @@ -1364,7 +1408,7 @@ module mkMemiTestWorker(wciS0_Clk, assign wmemi_respF_CLR = 1'b0 ; // remaining internal signals - assign NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311 = + assign NOT_rgen_gsF_first__12_EQ_wmemi_respF_first__1_ETC___d316 = rgen_gsF_D_OUT != wmemi_respF_D_OUT[127:0] ; assign _dfoo1 = wci_wslv_respF_cntr_r != 2'd2 || @@ -1384,9 +1428,11 @@ module mkMemiTestWorker(wciS0_Clk, assign _dfoo9 = wmemi_dhF_cntr_r != 2'd2 || wmemi_dhF_cntr_r_84_MINUS_1___d193 == 2'd1 ; - assign addr__h13592 = { hwordAddr, 4'h0 } ; - assign rdat__h14758 = { 24'd0, wmemi_statusR } ; - assign testStatus__h14232 = { 31'h0, isReader } ; + assign addr__h13652 = { hwordAddr, 4'h0 } ; + assign rdat__h15008 = { 24'd0, wmemi_statusR } ; + assign testStatus__h14482 = { 31'h0, isReader } ; + assign wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272 = + wci_wslv_cState == 3'd2 && isTesting && isWriter && !isReader ; assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = wci_wslv_respF_cntr_r - 2'd1 ; assign wmemi_dhF_cntr_r_84_MINUS_1___d193 = wmemi_dhF_cntr_r - 2'd1 ; @@ -1394,26 +1440,26 @@ module mkMemiTestWorker(wciS0_Clk, always@(wci_wslv_reqF_D_OUT or tstCtrl or seqLen or - rdat__h14758 or + rdat__h15008 or testCycleCount or errorCount or wtDuration or rdDuration or - wmemiWrReq or wmemiRdReq or wmemiRdResp or testStatus__h14232) + wmemiWrReq or wmemiRdReq or wmemiRdResp or testStatus__h14482) begin case (wci_wslv_reqF_D_OUT[63:32]) - 32'h0: g_data__h14736 = tstCtrl; - 32'h00000004: g_data__h14736 = seqLen; - 32'h00000008: g_data__h14736 = rdat__h14758; - 32'h0000000C: g_data__h14736 = testCycleCount; - 32'h00000010: g_data__h14736 = errorCount; - 32'h00000014: g_data__h14736 = wtDuration; - 32'h00000018: g_data__h14736 = rdDuration; - 32'h0000001C: g_data__h14736 = wmemiWrReq; - 32'h00000020: g_data__h14736 = wmemiRdReq; - 32'h00000024: g_data__h14736 = wmemiRdResp; - 32'h00000028: g_data__h14736 = testStatus__h14232; - default: g_data__h14736 = 32'd0; + 32'h0: g_data__h14986 = tstCtrl; + 32'h00000004: g_data__h14986 = seqLen; + 32'h00000008: g_data__h14986 = rdat__h15008; + 32'h0000000C: g_data__h14986 = testCycleCount; + 32'h00000010: g_data__h14986 = errorCount; + 32'h00000014: g_data__h14986 = wtDuration; + 32'h00000018: g_data__h14986 = rdDuration; + 32'h0000001C: g_data__h14986 = wmemiWrReq; + 32'h00000020: g_data__h14986 = wmemiRdReq; + 32'h00000024: g_data__h14986 = wmemiRdResp; + 32'h00000028: g_data__h14986 = testStatus__h14482; + default: g_data__h14986 = 32'd0; endcase end @@ -1426,6 +1472,7 @@ module mkMemiTestWorker(wciS0_Clk, errorCount <= `BSV_ASSIGNMENT_DELAY 32'd0; freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; hwordAddr <= `BSV_ASSIGNMENT_DELAY 32'd0; + isCharPush <= `BSV_ASSIGNMENT_DELAY 1'd0; isReader <= `BSV_ASSIGNMENT_DELAY 1'd0; isTesting <= `BSV_ASSIGNMENT_DELAY 1'd0; isWriter <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -1477,6 +1524,8 @@ module mkMemiTestWorker(wciS0_Clk, errorCount <= `BSV_ASSIGNMENT_DELAY errorCount_D_IN; if (freeCnt_EN) freeCnt <= `BSV_ASSIGNMENT_DELAY freeCnt_D_IN; if (hwordAddr_EN) hwordAddr <= `BSV_ASSIGNMENT_DELAY hwordAddr_D_IN; + if (isCharPush_EN) + isCharPush <= `BSV_ASSIGNMENT_DELAY isCharPush_D_IN; if (isReader_EN) isReader <= `BSV_ASSIGNMENT_DELAY isReader_D_IN; if (isTesting_EN) isTesting <= `BSV_ASSIGNMENT_DELAY isTesting_D_IN; if (isWriter_EN) isWriter <= `BSV_ASSIGNMENT_DELAY isWriter_D_IN; @@ -1584,6 +1633,7 @@ module mkMemiTestWorker(wciS0_Clk, errorCount = 32'hAAAAAAAA; freeCnt = 32'hAAAAAAAA; hwordAddr = 32'hAAAAAAAA; + isCharPush = 1'h0; isReader = 1'h0; isTesting = 1'h0; isWriter = 1'h0; @@ -1639,16 +1689,16 @@ module mkMemiTestWorker(wciS0_Clk, #0; if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_read_resp && - NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311) + NOT_rgen_gsF_first__12_EQ_wmemi_respF_first__1_ETC___d316) begin - v__h14155 = $time; + v__h14270 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_read_resp && - NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311) + NOT_rgen_gsF_first__12_EQ_wmemi_respF_first__1_ETC___d316) $display("[%0d]: %m: read_resp MISMATCH: exp:%0x got:%0x", - v__h14155, + v__h14270, rgen_gsF_D_OUT, wmemi_respF_D_OUT[127:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) @@ -1666,42 +1716,42 @@ module mkMemiTestWorker(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h14921 = $time; + v__h15171 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) - $display("[%0d]: %m: Starting MemiTestWorker", v__h14921); + $display("[%0d]: %m: Starting MemiTestWorker", v__h15171); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) - $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 128, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) - $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 128, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) - $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 128, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) - $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); + $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 128, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) - $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 128, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) - $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 128, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) - $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 128, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) - $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 128, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) - $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 128, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) - $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 128, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin diff --git a/rtl/mkOCApp16B.v b/rtl/mkOCApp16B.v index 07d9ccbc..beb4abdf 100644 --- a/rtl/mkOCApp16B.v +++ b/rtl/mkOCApp16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Feb 3 15:05:12 EST 2014 +// On Tue Feb 4 14:43:55 EST 2014 // // // Ports: diff --git a/rtl/mkOCCP.v b/rtl/mkOCCP.v index 1892e906..c1ab05ca 100644 --- a/rtl/mkOCCP.v +++ b/rtl/mkOCCP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Feb 3 15:31:07 EST 2014 +// On Tue Feb 4 14:45:17 EST 2014 // // // Ports: @@ -3891,17 +3891,17 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_9_wrkBusy; // inputs to muxes for submodule ports - reg [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_1, + reg [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_2, MUX_wci_10_reqF_q_0_write_1__VAL_1, MUX_wci_11_reqF_q_0_write_1__VAL_1, MUX_wci_12_reqF_q_0_write_1__VAL_1, MUX_wci_13_reqF_q_0_write_1__VAL_1, MUX_wci_14_reqF_q_0_write_1__VAL_1, - MUX_wci_1_reqF_q_0_write_1__VAL_1, - MUX_wci_2_reqF_q_0_write_1__VAL_1, - MUX_wci_3_reqF_q_0_write_1__VAL_1, - MUX_wci_4_reqF_q_0_write_1__VAL_1, - MUX_wci_5_reqF_q_0_write_1__VAL_1, + MUX_wci_1_reqF_q_0_write_1__VAL_2, + MUX_wci_2_reqF_q_0_write_1__VAL_2, + MUX_wci_3_reqF_q_0_write_1__VAL_2, + MUX_wci_4_reqF_q_0_write_1__VAL_2, + MUX_wci_5_reqF_q_0_write_1__VAL_2, MUX_wci_6_reqF_q_0_write_1__VAL_1, MUX_wci_7_reqF_q_0_write_1__VAL_1, MUX_wci_8_reqF_q_0_write_1__VAL_1, @@ -3951,7 +3951,7 @@ module mkOCCP(pciDevice, MUX_wci_9_reqERR_write_1__VAL_1, MUX_wci_9_reqFAIL_write_1__VAL_1, MUX_wci_9_reqTO_write_1__VAL_1; - wire [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_2, + wire [71 : 0] MUX_wci_0_reqF_q_0_write_1__VAL_1, MUX_wci_0_reqF_x_wire_wset_1__VAL_1, MUX_wci_0_reqF_x_wire_wset_1__VAL_2, MUX_wci_0_reqF_x_wire_wset_1__VAL_3, @@ -3970,19 +3970,19 @@ module mkOCCP(pciDevice, MUX_wci_14_reqF_q_0_write_1__VAL_2, MUX_wci_14_reqF_x_wire_wset_1__VAL_2, MUX_wci_14_reqF_x_wire_wset_1__VAL_3, - MUX_wci_1_reqF_q_0_write_1__VAL_2, + MUX_wci_1_reqF_q_0_write_1__VAL_1, MUX_wci_1_reqF_x_wire_wset_1__VAL_2, MUX_wci_1_reqF_x_wire_wset_1__VAL_3, - MUX_wci_2_reqF_q_0_write_1__VAL_2, + MUX_wci_2_reqF_q_0_write_1__VAL_1, MUX_wci_2_reqF_x_wire_wset_1__VAL_2, MUX_wci_2_reqF_x_wire_wset_1__VAL_3, - MUX_wci_3_reqF_q_0_write_1__VAL_2, + MUX_wci_3_reqF_q_0_write_1__VAL_1, MUX_wci_3_reqF_x_wire_wset_1__VAL_2, MUX_wci_3_reqF_x_wire_wset_1__VAL_3, - MUX_wci_4_reqF_q_0_write_1__VAL_2, + MUX_wci_4_reqF_q_0_write_1__VAL_1, MUX_wci_4_reqF_x_wire_wset_1__VAL_2, MUX_wci_4_reqF_x_wire_wset_1__VAL_3, - MUX_wci_5_reqF_q_0_write_1__VAL_2, + MUX_wci_5_reqF_q_0_write_1__VAL_1, MUX_wci_5_reqF_x_wire_wset_1__VAL_2, MUX_wci_5_reqF_x_wire_wset_1__VAL_3, MUX_wci_6_reqF_q_0_write_1__VAL_2, @@ -4099,7 +4099,7 @@ module mkOCCP(pciDevice, MUX_wci_0_reqFAIL_write_1__SEL_1, MUX_wci_0_reqF_cntr_r_write_1__VAL_1, MUX_wci_0_reqF_cntr_r_write_1__VAL_2, - MUX_wci_0_reqF_q_0_write_1__SEL_1, + MUX_wci_0_reqF_q_0_write_1__SEL_2, MUX_wci_0_reqPend_write_1__SEL_1, MUX_wci_0_reqTO_write_1__SEL_1, MUX_wci_0_respF_enq_1__SEL_6, @@ -4165,7 +4165,7 @@ module mkOCCP(pciDevice, MUX_wci_1_reqFAIL_write_1__SEL_1, MUX_wci_1_reqF_cntr_r_write_1__VAL_1, MUX_wci_1_reqF_cntr_r_write_1__VAL_2, - MUX_wci_1_reqF_q_0_write_1__SEL_1, + MUX_wci_1_reqF_q_0_write_1__SEL_2, MUX_wci_1_reqPend_write_1__SEL_1, MUX_wci_1_reqTO_write_1__SEL_1, MUX_wci_1_respF_enq_1__SEL_6, @@ -4176,7 +4176,7 @@ module mkOCCP(pciDevice, MUX_wci_2_reqFAIL_write_1__SEL_1, MUX_wci_2_reqF_cntr_r_write_1__VAL_1, MUX_wci_2_reqF_cntr_r_write_1__VAL_2, - MUX_wci_2_reqF_q_0_write_1__SEL_1, + MUX_wci_2_reqF_q_0_write_1__SEL_2, MUX_wci_2_reqPend_write_1__SEL_1, MUX_wci_2_reqTO_write_1__SEL_1, MUX_wci_2_respF_enq_1__SEL_6, @@ -4187,7 +4187,7 @@ module mkOCCP(pciDevice, MUX_wci_3_reqFAIL_write_1__SEL_1, MUX_wci_3_reqF_cntr_r_write_1__VAL_1, MUX_wci_3_reqF_cntr_r_write_1__VAL_2, - MUX_wci_3_reqF_q_0_write_1__SEL_1, + MUX_wci_3_reqF_q_0_write_1__SEL_2, MUX_wci_3_reqPend_write_1__SEL_1, MUX_wci_3_reqTO_write_1__SEL_1, MUX_wci_3_respF_enq_1__SEL_6, @@ -4198,7 +4198,7 @@ module mkOCCP(pciDevice, MUX_wci_4_reqFAIL_write_1__SEL_1, MUX_wci_4_reqF_cntr_r_write_1__VAL_1, MUX_wci_4_reqF_cntr_r_write_1__VAL_2, - MUX_wci_4_reqF_q_0_write_1__SEL_1, + MUX_wci_4_reqF_q_0_write_1__SEL_2, MUX_wci_4_reqPend_write_1__SEL_1, MUX_wci_4_reqTO_write_1__SEL_1, MUX_wci_4_respF_enq_1__SEL_6, @@ -4209,7 +4209,7 @@ module mkOCCP(pciDevice, MUX_wci_5_reqFAIL_write_1__SEL_1, MUX_wci_5_reqF_cntr_r_write_1__VAL_1, MUX_wci_5_reqF_cntr_r_write_1__VAL_2, - MUX_wci_5_reqF_q_0_write_1__SEL_1, + MUX_wci_5_reqF_q_0_write_1__SEL_2, MUX_wci_5_reqPend_write_1__SEL_1, MUX_wci_5_reqTO_write_1__SEL_1, MUX_wci_5_respF_enq_1__SEL_6, @@ -8488,7 +8488,7 @@ module mkOCCP(pciDevice, wci_0_wciResponse_wget[33:32] == 2'd2 && (wci_0_reqPend == 2'd1 || wci_0_reqPend == 2'd2 || wci_0_reqPend == 2'd3) ; - assign MUX_wci_0_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_0_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_0_reqF_incCtr && !wci_0_reqF_cntr_r ; assign MUX_wci_0_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_0_wrkBusy && @@ -8716,7 +8716,7 @@ module mkOCCP(pciDevice, wci_1_wciResponse_wget[33:32] == 2'd2 && (wci_1_reqPend == 2'd1 || wci_1_reqPend == 2'd2 || wci_1_reqPend == 2'd3) ; - assign MUX_wci_1_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_1_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_1_reqF_incCtr && !wci_1_reqF_cntr_r ; assign MUX_wci_1_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_1_wrkBusy && @@ -8754,7 +8754,7 @@ module mkOCCP(pciDevice, wci_2_wciResponse_wget[33:32] == 2'd2 && (wci_2_reqPend == 2'd1 || wci_2_reqPend == 2'd2 || wci_2_reqPend == 2'd3) ; - assign MUX_wci_2_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_2_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_2_reqF_incCtr && !wci_2_reqF_cntr_r ; assign MUX_wci_2_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_2_wrkBusy && @@ -8792,7 +8792,7 @@ module mkOCCP(pciDevice, wci_3_wciResponse_wget[33:32] == 2'd2 && (wci_3_reqPend == 2'd1 || wci_3_reqPend == 2'd2 || wci_3_reqPend == 2'd3) ; - assign MUX_wci_3_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_3_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_3_reqF_incCtr && !wci_3_reqF_cntr_r ; assign MUX_wci_3_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_3_wrkBusy && @@ -8830,7 +8830,7 @@ module mkOCCP(pciDevice, wci_4_wciResponse_wget[33:32] == 2'd2 && (wci_4_reqPend == 2'd1 || wci_4_reqPend == 2'd2 || wci_4_reqPend == 2'd3) ; - assign MUX_wci_4_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_4_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_4_reqF_incCtr && !wci_4_reqF_cntr_r ; assign MUX_wci_4_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_4_wrkBusy && @@ -8868,7 +8868,7 @@ module mkOCCP(pciDevice, wci_5_wciResponse_wget[33:32] == 2'd2 && (wci_5_reqPend == 2'd1 || wci_5_reqPend == 2'd2 || wci_5_reqPend == 2'd3) ; - assign MUX_wci_5_reqF_q_0_write_1__SEL_1 = + assign MUX_wci_5_reqF_q_0_write_1__SEL_2 = WILL_FIRE_RL_wci_5_reqF_incCtr && !wci_5_reqF_cntr_r ; assign MUX_wci_5_reqPend_write_1__SEL_1 = WILL_FIRE_RL_wci_5_wrkBusy && @@ -9382,6 +9382,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_0_reqF_cntr_r_write_1__VAL_1 = wci_0_reqF_cntr_r + 1'd1 ; assign MUX_wci_0_reqF_cntr_r_write_1__VAL_2 = wci_0_reqF_cntr_r - 1'd1 ; + assign MUX_wci_0_reqF_q_0_write_1__VAL_1 = + wci_0_reqF_cntr_r ? + MUX_wci_0_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T or @@ -9391,22 +9395,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T: - MUX_wci_0_reqF_q_0_write_1__VAL_1 = + MUX_wci_0_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T: - MUX_wci_0_reqF_q_0_write_1__VAL_1 = + MUX_wci_0_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T: - MUX_wci_0_reqF_q_0_write_1__VAL_1 = + MUX_wci_0_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_0_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_0_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_0_reqF_q_0_write_1__VAL_2 = - wci_0_reqF_cntr_r ? - MUX_wci_0_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_0_reqF_x_wire_wset_1__VAL_1 = { 8'd79, x_addr__h96606, 32'hAAAAAAAA } ; assign MUX_wci_0_reqF_x_wire_wset_1__VAL_2 = @@ -9845,6 +9845,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_1_reqF_cntr_r_write_1__VAL_1 = wci_1_reqF_cntr_r + 1'd1 ; assign MUX_wci_1_reqF_cntr_r_write_1__VAL_2 = wci_1_reqF_cntr_r - 1'd1 ; + assign MUX_wci_1_reqF_q_0_write_1__VAL_1 = + wci_1_reqF_cntr_r ? + MUX_wci_1_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T or @@ -9854,22 +9858,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T: - MUX_wci_1_reqF_q_0_write_1__VAL_1 = + MUX_wci_1_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T: - MUX_wci_1_reqF_q_0_write_1__VAL_1 = + MUX_wci_1_reqF_q_0_write_1__VAL_2 = MUX_wci_1_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T: - MUX_wci_1_reqF_q_0_write_1__VAL_1 = + MUX_wci_1_reqF_q_0_write_1__VAL_2 = MUX_wci_1_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_1_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_1_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_1_reqF_q_0_write_1__VAL_2 = - wci_1_reqF_cntr_r ? - MUX_wci_1_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_1_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h77105, cpReq[59:28] } ; assign MUX_wci_1_reqF_x_wire_wset_1__VAL_3 = @@ -9921,6 +9921,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_2_reqF_cntr_r_write_1__VAL_1 = wci_2_reqF_cntr_r + 1'd1 ; assign MUX_wci_2_reqF_cntr_r_write_1__VAL_2 = wci_2_reqF_cntr_r - 1'd1 ; + assign MUX_wci_2_reqF_q_0_write_1__VAL_1 = + wci_2_reqF_cntr_r ? + MUX_wci_2_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T or @@ -9930,22 +9934,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T: - MUX_wci_2_reqF_q_0_write_1__VAL_1 = + MUX_wci_2_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T: - MUX_wci_2_reqF_q_0_write_1__VAL_1 = + MUX_wci_2_reqF_q_0_write_1__VAL_2 = MUX_wci_2_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T: - MUX_wci_2_reqF_q_0_write_1__VAL_1 = + MUX_wci_2_reqF_q_0_write_1__VAL_2 = MUX_wci_2_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_2_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_2_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_2_reqF_q_0_write_1__VAL_2 = - wci_2_reqF_cntr_r ? - MUX_wci_2_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_2_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h77173, cpReq[59:28] } ; assign MUX_wci_2_reqF_x_wire_wset_1__VAL_3 = @@ -9997,6 +9997,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_3_reqF_cntr_r_write_1__VAL_1 = wci_3_reqF_cntr_r + 1'd1 ; assign MUX_wci_3_reqF_cntr_r_write_1__VAL_2 = wci_3_reqF_cntr_r - 1'd1 ; + assign MUX_wci_3_reqF_q_0_write_1__VAL_1 = + wci_3_reqF_cntr_r ? + MUX_wci_3_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T or @@ -10006,22 +10010,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T: - MUX_wci_3_reqF_q_0_write_1__VAL_1 = + MUX_wci_3_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T: - MUX_wci_3_reqF_q_0_write_1__VAL_1 = + MUX_wci_3_reqF_q_0_write_1__VAL_2 = MUX_wci_3_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T: - MUX_wci_3_reqF_q_0_write_1__VAL_1 = + MUX_wci_3_reqF_q_0_write_1__VAL_2 = MUX_wci_3_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_3_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_3_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_3_reqF_q_0_write_1__VAL_2 = - wci_3_reqF_cntr_r ? - MUX_wci_3_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_3_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h77241, cpReq[59:28] } ; assign MUX_wci_3_reqF_x_wire_wset_1__VAL_3 = @@ -10073,6 +10073,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_4_reqF_cntr_r_write_1__VAL_1 = wci_4_reqF_cntr_r + 1'd1 ; assign MUX_wci_4_reqF_cntr_r_write_1__VAL_2 = wci_4_reqF_cntr_r - 1'd1 ; + assign MUX_wci_4_reqF_q_0_write_1__VAL_1 = + wci_4_reqF_cntr_r ? + MUX_wci_4_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T or @@ -10082,22 +10086,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T: - MUX_wci_4_reqF_q_0_write_1__VAL_1 = + MUX_wci_4_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T: - MUX_wci_4_reqF_q_0_write_1__VAL_1 = + MUX_wci_4_reqF_q_0_write_1__VAL_2 = MUX_wci_4_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T: - MUX_wci_4_reqF_q_0_write_1__VAL_1 = + MUX_wci_4_reqF_q_0_write_1__VAL_2 = MUX_wci_4_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_4_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_4_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_4_reqF_q_0_write_1__VAL_2 = - wci_4_reqF_cntr_r ? - MUX_wci_4_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_4_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h77309, cpReq[59:28] } ; assign MUX_wci_4_reqF_x_wire_wset_1__VAL_3 = @@ -10149,6 +10149,10 @@ module mkOCCP(pciDevice, end assign MUX_wci_5_reqF_cntr_r_write_1__VAL_1 = wci_5_reqF_cntr_r + 1'd1 ; assign MUX_wci_5_reqF_cntr_r_write_1__VAL_2 = wci_5_reqF_cntr_r - 1'd1 ; + assign MUX_wci_5_reqF_q_0_write_1__VAL_1 = + wci_5_reqF_cntr_r ? + MUX_wci_5_reqF_q_0_write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T or MUX_wci_0_reqF_x_wire_wset_1__VAL_1 or WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T or @@ -10158,22 +10162,18 @@ module mkOCCP(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T: - MUX_wci_5_reqF_q_0_write_1__VAL_1 = + MUX_wci_5_reqF_q_0_write_1__VAL_2 = MUX_wci_0_reqF_x_wire_wset_1__VAL_1; WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T: - MUX_wci_5_reqF_q_0_write_1__VAL_1 = + MUX_wci_5_reqF_q_0_write_1__VAL_2 = MUX_wci_5_reqF_x_wire_wset_1__VAL_2; WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T: - MUX_wci_5_reqF_q_0_write_1__VAL_1 = + MUX_wci_5_reqF_q_0_write_1__VAL_2 = MUX_wci_5_reqF_x_wire_wset_1__VAL_3; - default: MUX_wci_5_reqF_q_0_write_1__VAL_1 = + default: MUX_wci_5_reqF_q_0_write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_5_reqF_q_0_write_1__VAL_2 = - wci_5_reqF_cntr_r ? - MUX_wci_5_reqF_q_0_write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; assign MUX_wci_5_reqF_x_wire_wset_1__VAL_2 = { 4'd3, cpReq[3:0], wciAddr__h77377, cpReq[59:28] } ; assign MUX_wci_5_reqF_x_wire_wset_1__VAL_3 = @@ -10554,7 +10554,7 @@ module mkOCCP(pciDevice, assign dna_shftReg_1_whas = dna_cnt >= 7'd3 && dna_cnt <= 7'd116 ; assign uuidV_wget = uuid_arg ; assign uuidV_whas = 1'd1 ; - assign wci_0_reqF_x_wire_wget = MUX_wci_0_reqF_q_0_write_1__VAL_1 ; + assign wci_0_reqF_x_wire_wget = MUX_wci_0_reqF_q_0_write_1__VAL_2 ; assign wci_0_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T || @@ -10567,7 +10567,7 @@ module mkOCCP(pciDevice, assign wci_0_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; - assign wci_1_reqF_x_wire_wget = MUX_wci_1_reqF_q_0_write_1__VAL_1 ; + assign wci_1_reqF_x_wire_wget = MUX_wci_1_reqF_q_0_write_1__VAL_2 ; assign wci_1_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T || @@ -10580,7 +10580,7 @@ module mkOCCP(pciDevice, assign wci_1_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; - assign wci_2_reqF_x_wire_wget = MUX_wci_2_reqF_q_0_write_1__VAL_1 ; + assign wci_2_reqF_x_wire_wget = MUX_wci_2_reqF_q_0_write_1__VAL_2 ; assign wci_2_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T || @@ -10593,7 +10593,7 @@ module mkOCCP(pciDevice, assign wci_2_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; - assign wci_3_reqF_x_wire_wget = MUX_wci_3_reqF_q_0_write_1__VAL_1 ; + assign wci_3_reqF_x_wire_wget = MUX_wci_3_reqF_q_0_write_1__VAL_2 ; assign wci_3_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T || @@ -10606,7 +10606,7 @@ module mkOCCP(pciDevice, assign wci_3_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; - assign wci_4_reqF_x_wire_wget = MUX_wci_4_reqF_q_0_write_1__VAL_1 ; + assign wci_4_reqF_x_wire_wget = MUX_wci_4_reqF_q_0_write_1__VAL_2 ; assign wci_4_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T || @@ -10619,7 +10619,7 @@ module mkOCCP(pciDevice, assign wci_4_sfCapClear_1_whas = WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; - assign wci_5_reqF_x_wire_wget = MUX_wci_5_reqF_q_0_write_1__VAL_1 ; + assign wci_5_reqF_x_wire_wget = MUX_wci_5_reqF_q_0_write_1__VAL_2 ; assign wci_5_reqF_x_wire_whas = WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T || @@ -12153,15 +12153,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_0_reqF_decCtr ; // register wci_0_reqF_q_0 - always@(MUX_wci_0_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_0_reqF_both or MUX_wci_0_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_0_reqF_both or + MUX_wci_0_reqF_q_0_write_1__SEL_2 or MUX_wci_0_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_0_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_0_reqF_q_0_write_1__SEL_1: - wci_0_reqF_q_0_D_IN = MUX_wci_0_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_0_reqF_both: + wci_0_reqF_q_0_D_IN = MUX_wci_0_reqF_q_0_write_1__VAL_1; + MUX_wci_0_reqF_q_0_write_1__SEL_2: wci_0_reqF_q_0_D_IN = MUX_wci_0_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_0_reqF_decCtr: wci_0_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -12170,8 +12170,8 @@ module mkOCCP(pciDevice, endcase end assign wci_0_reqF_q_0_EN = - WILL_FIRE_RL_wci_0_reqF_incCtr && !wci_0_reqF_cntr_r || WILL_FIRE_RL_wci_0_reqF_both || + WILL_FIRE_RL_wci_0_reqF_incCtr && !wci_0_reqF_cntr_r || WILL_FIRE_RL_wci_0_reqF_decCtr ; // register wci_0_reqPend @@ -13279,15 +13279,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_1_reqF_decCtr ; // register wci_1_reqF_q_0 - always@(MUX_wci_1_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_1_reqF_both or MUX_wci_1_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_1_reqF_both or + MUX_wci_1_reqF_q_0_write_1__SEL_2 or MUX_wci_1_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_1_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_1_reqF_q_0_write_1__SEL_1: - wci_1_reqF_q_0_D_IN = MUX_wci_1_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_1_reqF_both: + wci_1_reqF_q_0_D_IN = MUX_wci_1_reqF_q_0_write_1__VAL_1; + MUX_wci_1_reqF_q_0_write_1__SEL_2: wci_1_reqF_q_0_D_IN = MUX_wci_1_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_1_reqF_decCtr: wci_1_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -13296,8 +13296,8 @@ module mkOCCP(pciDevice, endcase end assign wci_1_reqF_q_0_EN = - WILL_FIRE_RL_wci_1_reqF_incCtr && !wci_1_reqF_cntr_r || WILL_FIRE_RL_wci_1_reqF_both || + WILL_FIRE_RL_wci_1_reqF_incCtr && !wci_1_reqF_cntr_r || WILL_FIRE_RL_wci_1_reqF_decCtr ; // register wci_1_reqPend @@ -13465,15 +13465,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_2_reqF_decCtr ; // register wci_2_reqF_q_0 - always@(MUX_wci_2_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_2_reqF_both or MUX_wci_2_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_2_reqF_both or + MUX_wci_2_reqF_q_0_write_1__SEL_2 or MUX_wci_2_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_2_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_2_reqF_q_0_write_1__SEL_1: - wci_2_reqF_q_0_D_IN = MUX_wci_2_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_2_reqF_both: + wci_2_reqF_q_0_D_IN = MUX_wci_2_reqF_q_0_write_1__VAL_1; + MUX_wci_2_reqF_q_0_write_1__SEL_2: wci_2_reqF_q_0_D_IN = MUX_wci_2_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_2_reqF_decCtr: wci_2_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -13482,8 +13482,8 @@ module mkOCCP(pciDevice, endcase end assign wci_2_reqF_q_0_EN = - WILL_FIRE_RL_wci_2_reqF_incCtr && !wci_2_reqF_cntr_r || WILL_FIRE_RL_wci_2_reqF_both || + WILL_FIRE_RL_wci_2_reqF_incCtr && !wci_2_reqF_cntr_r || WILL_FIRE_RL_wci_2_reqF_decCtr ; // register wci_2_reqPend @@ -13651,15 +13651,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_3_reqF_decCtr ; // register wci_3_reqF_q_0 - always@(MUX_wci_3_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_3_reqF_both or MUX_wci_3_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_3_reqF_both or + MUX_wci_3_reqF_q_0_write_1__SEL_2 or MUX_wci_3_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_3_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_3_reqF_q_0_write_1__SEL_1: - wci_3_reqF_q_0_D_IN = MUX_wci_3_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_3_reqF_both: + wci_3_reqF_q_0_D_IN = MUX_wci_3_reqF_q_0_write_1__VAL_1; + MUX_wci_3_reqF_q_0_write_1__SEL_2: wci_3_reqF_q_0_D_IN = MUX_wci_3_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_3_reqF_decCtr: wci_3_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -13668,8 +13668,8 @@ module mkOCCP(pciDevice, endcase end assign wci_3_reqF_q_0_EN = - WILL_FIRE_RL_wci_3_reqF_incCtr && !wci_3_reqF_cntr_r || WILL_FIRE_RL_wci_3_reqF_both || + WILL_FIRE_RL_wci_3_reqF_incCtr && !wci_3_reqF_cntr_r || WILL_FIRE_RL_wci_3_reqF_decCtr ; // register wci_3_reqPend @@ -13837,15 +13837,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_4_reqF_decCtr ; // register wci_4_reqF_q_0 - always@(MUX_wci_4_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_4_reqF_both or MUX_wci_4_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_4_reqF_both or + MUX_wci_4_reqF_q_0_write_1__SEL_2 or MUX_wci_4_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_4_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_4_reqF_q_0_write_1__SEL_1: - wci_4_reqF_q_0_D_IN = MUX_wci_4_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_4_reqF_both: + wci_4_reqF_q_0_D_IN = MUX_wci_4_reqF_q_0_write_1__VAL_1; + MUX_wci_4_reqF_q_0_write_1__SEL_2: wci_4_reqF_q_0_D_IN = MUX_wci_4_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_4_reqF_decCtr: wci_4_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -13854,8 +13854,8 @@ module mkOCCP(pciDevice, endcase end assign wci_4_reqF_q_0_EN = - WILL_FIRE_RL_wci_4_reqF_incCtr && !wci_4_reqF_cntr_r || WILL_FIRE_RL_wci_4_reqF_both || + WILL_FIRE_RL_wci_4_reqF_incCtr && !wci_4_reqF_cntr_r || WILL_FIRE_RL_wci_4_reqF_decCtr ; // register wci_4_reqPend @@ -14023,15 +14023,15 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_wci_5_reqF_decCtr ; // register wci_5_reqF_q_0 - always@(MUX_wci_5_reqF_q_0_write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_5_reqF_both or MUX_wci_5_reqF_q_0_write_1__VAL_1 or - WILL_FIRE_RL_wci_5_reqF_both or + MUX_wci_5_reqF_q_0_write_1__SEL_2 or MUX_wci_5_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_5_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_5_reqF_q_0_write_1__SEL_1: - wci_5_reqF_q_0_D_IN = MUX_wci_5_reqF_q_0_write_1__VAL_1; WILL_FIRE_RL_wci_5_reqF_both: + wci_5_reqF_q_0_D_IN = MUX_wci_5_reqF_q_0_write_1__VAL_1; + MUX_wci_5_reqF_q_0_write_1__SEL_2: wci_5_reqF_q_0_D_IN = MUX_wci_5_reqF_q_0_write_1__VAL_2; WILL_FIRE_RL_wci_5_reqF_decCtr: wci_5_reqF_q_0_D_IN = 72'h0000000000AAAAAAAA; @@ -14040,8 +14040,8 @@ module mkOCCP(pciDevice, endcase end assign wci_5_reqF_q_0_EN = - WILL_FIRE_RL_wci_5_reqF_incCtr && !wci_5_reqF_cntr_r || WILL_FIRE_RL_wci_5_reqF_both || + WILL_FIRE_RL_wci_5_reqF_incCtr && !wci_5_reqF_cntr_r || WILL_FIRE_RL_wci_5_reqF_decCtr ; // register wci_5_reqPend @@ -24330,7 +24330,7 @@ module mkOCCP(pciDevice, 32'h00000001; 8'h0C: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = - 32'd1391459380; + 32'd1391543027; 8'h10: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = { 17'd0, x__h104311 }; diff --git a/rtl/mkOCInf16B.v b/rtl/mkOCInf16B.v index fb942190..2beb4efa 100644 --- a/rtl/mkOCInf16B.v +++ b/rtl/mkOCInf16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Mon Feb 3 15:31:24 EST 2014 +// On Tue Feb 4 14:45:35 EST 2014 // // // Ports: