diff --git a/rtl/mkBiasWorker16B.v b/rtl/mkBiasWorker16B.v index 6a2611d0..9dd62482 100644 --- a/rtl/mkBiasWorker16B.v +++ b/rtl/mkBiasWorker16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:44:59 EDT 2012 +// On Mon Sep 24 13:38:19 EDT 2012 // // // Ports: diff --git a/rtl/mkBiasWorker32B.v b/rtl/mkBiasWorker32B.v index d654d14f..940ebf84 100644 --- a/rtl/mkBiasWorker32B.v +++ b/rtl/mkBiasWorker32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:02 EDT 2012 +// On Mon Sep 24 13:38:20 EDT 2012 // // // Ports: diff --git a/rtl/mkBiasWorker4B.v b/rtl/mkBiasWorker4B.v index 4015086f..5704cc2b 100644 --- a/rtl/mkBiasWorker4B.v +++ b/rtl/mkBiasWorker4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:00 EDT 2012 +// On Mon Sep 24 13:38:17 EDT 2012 // // // Ports: @@ -521,7 +521,7 @@ module mkBiasWorker4B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2; wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, - MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__VAL_2; wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, @@ -537,8 +537,8 @@ module mkBiasWorker4B(wciS0_Clk, MUX_wci_wslv_illegalEdge$write_1__VAL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, MUX_wci_wslv_respF_q_1$write_1__SEL_2, - MUX_wsiM_reqFifo_q_0$write_1__SEL_2, - MUX_wsiM_reqFifo_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals @@ -751,9 +751,9 @@ module mkBiasWorker4B(wciS0_Clk, assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_c_r == 2'd1 ; - assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; - assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N && @@ -797,16 +797,16 @@ module mkBiasWorker4B(wciS0_Clk, assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { wsiS_reqFifo$D_OUT[60:44], x_data__h10151, wsiS_reqFifo$D_OUT[11:0] } ; - assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = + (wsiM_reqFifo_c_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 = (wsiM_reqFifo_c_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : 61'h00000AAAAAAAAA00 ; // inlined wires @@ -855,7 +855,7 @@ module mkBiasWorker4B(wciS0_Clk, assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; assign wsiS_sThreadBusy_dw$whas = wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; - assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ; + assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ; assign wsiM_reqFifo_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wsiM_operateD_1$wget = 1'd1 ; @@ -1108,16 +1108,16 @@ module mkBiasWorker4B(wciS0_Clk, WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or - MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or + WILL_FIRE_RL_wsiM_reqFifo_both or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; - MUX_wsiM_reqFifo_q_0$write_1__SEL_2: + WILL_FIRE_RL_wsiM_reqFifo_both: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1; @@ -1126,22 +1126,22 @@ module mkBiasWorker4B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or - MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or + WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; WILL_FIRE_RL_wsiM_reqFifo_both: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; - MUX_wsiM_reqFifo_q_1$write_1__SEL_2: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00; default: wsiM_reqFifo_q_1$D_IN = @@ -1149,8 +1149,8 @@ module mkBiasWorker4B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d diff --git a/rtl/mkBiasWorker8B.v b/rtl/mkBiasWorker8B.v index 0c8ed8e2..e0617042 100644 --- a/rtl/mkBiasWorker8B.v +++ b/rtl/mkBiasWorker8B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:01 EDT 2012 +// On Mon Sep 24 13:38:18 EDT 2012 // // // Ports: diff --git a/rtl/mkEDCPAdapter.v b/rtl/mkEDCPAdapter.v index 8baf1532..4f57766d 100644 --- a/rtl/mkEDCPAdapter.v +++ b/rtl/mkEDCPAdapter.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Thu Sep 20 13:30:54 EDT 2012 +// On Mon Sep 24 13:38:00 EDT 2012 // // // Ports: @@ -289,13 +289,7 @@ module mkEDCPAdapter(CLK, // rule scheduling signals wire WILL_FIRE_RL_cp_to_dcp_response, WILL_FIRE_RL_dcp_to_cp_request, - WILL_FIRE_RL_ecp_egress, WILL_FIRE_RL_ecp_ingress, - WILL_FIRE_RL_edpFsm_action_l236c14, - WILL_FIRE_RL_edpFsm_action_l237c14, - WILL_FIRE_RL_edpFsm_action_l238c14, - WILL_FIRE_RL_edpFsm_action_l239c14, - WILL_FIRE_RL_edpFsm_action_l241c16, WILL_FIRE_RL_edpFsm_action_l243c16, WILL_FIRE_RL_edpFsm_action_l244c16, WILL_FIRE_RL_edpFsm_fsm_start, @@ -314,7 +308,13 @@ module mkEDCPAdapter(CLK, MUX_ecpRespF$enq_1__VAL_7; wire MUX_dcpRespF$enq_1__SEL_1, MUX_doInFlight$write_1__SEL_1, - MUX_edpFsm_state_mkFSMstate$write_1__SEL_1; + MUX_edpFsm_start_reg$write_1__SEL_2, + MUX_edpFsm_state_mkFSMstate$write_1__SEL_1, + MUX_edpFsm_state_mkFSMstate$write_1__SEL_2, + MUX_edpFsm_state_mkFSMstate$write_1__SEL_3, + MUX_edpFsm_state_mkFSMstate$write_1__SEL_4, + MUX_edpFsm_state_mkFSMstate$write_1__SEL_5, + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6; // remaining internal signals reg [7 : 0] CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10; @@ -330,12 +330,12 @@ module mkEDCPAdapter(CLK, wire [47 : 0] x__h3792, x__h5523, x__h5564, x__h5619, y__h5585, y__h5630; wire [31 : 0] bedw__h2286; wire [15 : 0] x__h5652, x__h5720; - wire [7 : 0] IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d544; + wire [7 : 0] IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d466; wire [3 : 0] x__h2311; wire IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21__ETC___d152, IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23__ETC___d150, - dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d532, - dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d533, + dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454, + dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d455, dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155, dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23_AND_ETC___d196, eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100, @@ -454,14 +454,6 @@ module mkEDCPAdapter(CLK, // rule RL_ecp_ingress assign WILL_FIRE_RL_ecp_ingress = ecpReqF$EMPTY_N && !eDoReq ; - // rule RL_edpFsm_action_l237c14 - assign WILL_FIRE_RL_edpFsm_action_l237c14 = - ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd1 ; - - // rule RL_edpFsm_action_l238c14 - assign WILL_FIRE_RL_edpFsm_action_l238c14 = - ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd2 ; - // rule RL_dcp_to_cp_request assign WILL_FIRE_RL_dcp_to_cp_request = dcpReqF$EMPTY_N && @@ -472,14 +464,6 @@ module mkEDCPAdapter(CLK, assign WILL_FIRE_RL_cp_to_dcp_response = dcpRespF$FULL_N && cpRespF$EMPTY_N ; - // rule RL_edpFsm_action_l239c14 - assign WILL_FIRE_RL_edpFsm_action_l239c14 = - ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd3 ; - - // rule RL_edpFsm_action_l241c16 - assign WILL_FIRE_RL_edpFsm_action_l241c16 = - ecpRespF$FULL_N && isWrtResp && edpFsm_state_mkFSMstate == 4'd4 ; - // rule RL_edpFsm_action_l243c16 assign WILL_FIRE_RL_edpFsm_action_l243c16 = ecpRespF$FULL_N && !isWrtResp && @@ -495,19 +479,6 @@ module mkEDCPAdapter(CLK, (!edpFsm_start_reg_1 || edpFsm_state_fired) && edpFsm_start_reg ; - // rule RL_edpFsm_action_l236c14 - assign WILL_FIRE_RL_edpFsm_action_l236c14 = - ecpRespF$FULL_N && edpFsm_start_wire$whas && - edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 ; - - // rule RL_ecp_egress - assign WILL_FIRE_RL_ecp_egress = - edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 && - (!edpFsm_start_reg_1 || edpFsm_state_fired) && - !edpFsm_start_reg && - eMAddrF$EMPTY_N && - dcpRespF$EMPTY_N ; - // rule RL_edpFsm_idle_l235c3 assign WILL_FIRE_RL_edpFsm_idle_l235c3 = !edpFsm_start_wire$whas && edpFsm_state_mkFSMstate == 4'd5 ; @@ -526,9 +497,26 @@ module mkEDCPAdapter(CLK, dcpReqF$D_OUT[78:77] != 2'd0 && (dcpReqF$D_OUT[78:77] == 2'd1 && dcpReqF$D_OUT[76] || dcpReqF$D_OUT[78:77] != 2'd1 && dcpReqF$D_OUT[44])) ; + assign MUX_edpFsm_start_reg$write_1__SEL_2 = + edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 && + (!edpFsm_start_reg_1 || edpFsm_state_fired) && + !edpFsm_start_reg && + eMAddrF$EMPTY_N && + dcpRespF$EMPTY_N ; assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_1 = WILL_FIRE_RL_edpFsm_idle_l235c3_1 || WILL_FIRE_RL_edpFsm_idle_l235c3 ; + assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 = + ecpRespF$FULL_N && edpFsm_start_wire$whas && + edpFsm_abort_whas__19_AND_edpFsm_abort_wget__2_ETC___d253 ; + assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 = + ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd1 ; + assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 = + ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd2 ; + assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 = + ecpRespF$FULL_N && edpFsm_state_mkFSMstate == 4'd3 ; + assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 = + ecpRespF$FULL_N && isWrtResp && edpFsm_state_mkFSMstate == 4'd4 ; always@(dcpReqF$D_OUT or lastResp) begin case (dcpReqF$D_OUT[78:77]) @@ -647,11 +635,11 @@ module mkEDCPAdapter(CLK, WILL_FIRE_RL_edpFsm_idle_l235c3 || WILL_FIRE_RL_edpFsm_action_l244c16 || WILL_FIRE_RL_edpFsm_action_l243c16 || - WILL_FIRE_RL_edpFsm_action_l241c16 || - WILL_FIRE_RL_edpFsm_action_l239c14 || - WILL_FIRE_RL_edpFsm_action_l238c14 || - WILL_FIRE_RL_edpFsm_action_l237c14 || - WILL_FIRE_RL_edpFsm_action_l236c14 ; + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 ; assign edpFsm_state_overlap_pw$whas = 1'b0 ; // register doInFlight @@ -709,7 +697,8 @@ module mkEDCPAdapter(CLK, // register edpFsm_start_reg assign edpFsm_start_reg$D_IN = !WILL_FIRE_RL_edpFsm_fsm_start ; assign edpFsm_start_reg$EN = - WILL_FIRE_RL_edpFsm_fsm_start || WILL_FIRE_RL_ecp_egress ; + WILL_FIRE_RL_edpFsm_fsm_start || + MUX_edpFsm_start_reg$write_1__SEL_2 ; // register edpFsm_start_reg_1 assign edpFsm_start_reg_1$D_IN = edpFsm_start_wire$whas ; @@ -726,22 +715,27 @@ module mkEDCPAdapter(CLK, // register edpFsm_state_mkFSMstate always@(MUX_edpFsm_state_mkFSMstate$write_1__SEL_1 or - WILL_FIRE_RL_edpFsm_action_l236c14 or - WILL_FIRE_RL_edpFsm_action_l237c14 or - WILL_FIRE_RL_edpFsm_action_l238c14 or - WILL_FIRE_RL_edpFsm_action_l239c14 or - WILL_FIRE_RL_edpFsm_action_l241c16 or + MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 or + MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 or + MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 or + MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 or + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 or WILL_FIRE_RL_edpFsm_action_l243c16 or WILL_FIRE_RL_edpFsm_action_l244c16) begin case (1'b1) // synopsys parallel_case MUX_edpFsm_state_mkFSMstate$write_1__SEL_1: edpFsm_state_mkFSMstate$D_IN = 4'd0; - WILL_FIRE_RL_edpFsm_action_l236c14: edpFsm_state_mkFSMstate$D_IN = 4'd1; - WILL_FIRE_RL_edpFsm_action_l237c14: edpFsm_state_mkFSMstate$D_IN = 4'd2; - WILL_FIRE_RL_edpFsm_action_l238c14: edpFsm_state_mkFSMstate$D_IN = 4'd3; - WILL_FIRE_RL_edpFsm_action_l239c14: edpFsm_state_mkFSMstate$D_IN = 4'd4; - WILL_FIRE_RL_edpFsm_action_l241c16: edpFsm_state_mkFSMstate$D_IN = 4'd5; + MUX_edpFsm_state_mkFSMstate$write_1__SEL_2: + edpFsm_state_mkFSMstate$D_IN = 4'd1; + MUX_edpFsm_state_mkFSMstate$write_1__SEL_3: + edpFsm_state_mkFSMstate$D_IN = 4'd2; + MUX_edpFsm_state_mkFSMstate$write_1__SEL_4: + edpFsm_state_mkFSMstate$D_IN = 4'd3; + MUX_edpFsm_state_mkFSMstate$write_1__SEL_5: + edpFsm_state_mkFSMstate$D_IN = 4'd4; + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6: + edpFsm_state_mkFSMstate$D_IN = 4'd5; WILL_FIRE_RL_edpFsm_action_l243c16: edpFsm_state_mkFSMstate$D_IN = 4'd6; WILL_FIRE_RL_edpFsm_action_l244c16: edpFsm_state_mkFSMstate$D_IN = 4'd7; default: edpFsm_state_mkFSMstate$D_IN = @@ -751,28 +745,30 @@ module mkEDCPAdapter(CLK, assign edpFsm_state_mkFSMstate$EN = WILL_FIRE_RL_edpFsm_idle_l235c3_1 || WILL_FIRE_RL_edpFsm_idle_l235c3 || - WILL_FIRE_RL_edpFsm_action_l236c14 || - WILL_FIRE_RL_edpFsm_action_l237c14 || - WILL_FIRE_RL_edpFsm_action_l238c14 || - WILL_FIRE_RL_edpFsm_action_l239c14 || - WILL_FIRE_RL_edpFsm_action_l241c16 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 || WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16 ; // register eeDat assign eeDat$D_IN = dcpRespF$D_OUT[41:10] ; - assign eeDat$EN = WILL_FIRE_RL_ecp_egress && dcpRespF$D_OUT[44:43] != 2'd1 ; + assign eeDat$EN = + MUX_edpFsm_start_reg$write_1__SEL_2 && + dcpRespF$D_OUT[44:43] != 2'd1 ; // register eeDmh assign eeDmh$D_IN = { dcpRespF$D_OUT[9:2], CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10, 16'h0 } ; - assign eeDmh$EN = WILL_FIRE_RL_ecp_egress ; + assign eeDmh$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ; // register eeMDst assign eeMDst$D_IN = eMAddrF$D_OUT ; - assign eeMDst$EN = WILL_FIRE_RL_ecp_egress ; + assign eeMDst$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ; // register eePli always@(dcpRespF$D_OUT) @@ -783,11 +779,11 @@ module mkEDCPAdapter(CLK, default: eePli$D_IN = 16'd10; endcase end - assign eePli$EN = WILL_FIRE_RL_ecp_egress ; + assign eePli$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ; // register isWrtResp assign isWrtResp$D_IN = dcpRespF$D_OUT[44:43] == 2'd1 ; - assign isWrtResp$EN = WILL_FIRE_RL_ecp_egress ; + assign isWrtResp$EN = MUX_edpFsm_start_reg$write_1__SEL_2 ; // register lastResp assign lastResp$D_IN = MUX_dcpRespF$enq_1__VAL_2 ; @@ -804,11 +800,11 @@ module mkEDCPAdapter(CLK, (dcpReqF$D_OUT[78:77] == 2'd0 && !dcpReqF$D_OUT[40] || dcpReqF$D_OUT[78:77] != 2'd0 && (dcpReqF$D_OUT[78:77] == 2'd1 && - (!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d533 || + (!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d455 || !lastTag[8]) && !dcpReqF$D_OUT[76] || dcpReqF$D_OUT[78:77] != 2'd1 && - (!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d532 || + (!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 || !lastTag[8]) && !dcpReqF$D_OUT[44])) ; @@ -871,7 +867,7 @@ module mkEDCPAdapter(CLK, WILL_FIRE_RL_dcp_to_cp_request && dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155 || WILL_FIRE_RL_cp_to_dcp_response ; - assign dcpRespF$DEQ = WILL_FIRE_RL_ecp_egress ; + assign dcpRespF$DEQ = MUX_edpFsm_start_reg$write_1__SEL_2 ; assign dcpRespF$CLR = 1'b0 ; // submodule eMAddrF @@ -879,7 +875,7 @@ module mkEDCPAdapter(CLK, assign eMAddrF$ENQ = eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100 && eDoReq ; - assign eMAddrF$DEQ = WILL_FIRE_RL_ecp_egress ; + assign eMAddrF$DEQ = MUX_edpFsm_start_reg$write_1__SEL_2 ; assign eMAddrF$CLR = 1'b0 ; // submodule ecpReqF @@ -897,30 +893,30 @@ module mkEDCPAdapter(CLK, assign ecpReqF$CLR = 1'b0 ; // submodule ecpRespF - always@(WILL_FIRE_RL_edpFsm_action_l236c14 or + always@(MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 or MUX_ecpRespF$enq_1__VAL_1 or - WILL_FIRE_RL_edpFsm_action_l237c14 or + MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 or MUX_ecpRespF$enq_1__VAL_2 or - WILL_FIRE_RL_edpFsm_action_l238c14 or + MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 or MUX_ecpRespF$enq_1__VAL_3 or - WILL_FIRE_RL_edpFsm_action_l239c14 or + MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 or MUX_ecpRespF$enq_1__VAL_4 or - WILL_FIRE_RL_edpFsm_action_l241c16 or + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 or MUX_ecpRespF$enq_1__VAL_5 or WILL_FIRE_RL_edpFsm_action_l243c16 or MUX_ecpRespF$enq_1__VAL_6 or WILL_FIRE_RL_edpFsm_action_l244c16 or MUX_ecpRespF$enq_1__VAL_7) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_edpFsm_action_l236c14: + MUX_edpFsm_state_mkFSMstate$write_1__SEL_2: ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_1; - WILL_FIRE_RL_edpFsm_action_l237c14: + MUX_edpFsm_state_mkFSMstate$write_1__SEL_3: ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_2; - WILL_FIRE_RL_edpFsm_action_l238c14: + MUX_edpFsm_state_mkFSMstate$write_1__SEL_4: ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_3; - WILL_FIRE_RL_edpFsm_action_l239c14: + MUX_edpFsm_state_mkFSMstate$write_1__SEL_5: ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_4; - WILL_FIRE_RL_edpFsm_action_l241c16: + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6: ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_5; WILL_FIRE_RL_edpFsm_action_l243c16: ecpRespF$D_IN = MUX_ecpRespF$enq_1__VAL_6; @@ -930,11 +926,11 @@ module mkEDCPAdapter(CLK, endcase end assign ecpRespF$ENQ = - WILL_FIRE_RL_edpFsm_action_l236c14 || - WILL_FIRE_RL_edpFsm_action_l237c14 || - WILL_FIRE_RL_edpFsm_action_l238c14 || - WILL_FIRE_RL_edpFsm_action_l239c14 || - WILL_FIRE_RL_edpFsm_action_l241c16 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 || WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16 ; assign ecpRespF$DEQ = EN_server_response_get ; @@ -945,7 +941,7 @@ module mkEDCPAdapter(CLK, (dcpReqF$D_OUT[78:77] == 2'd0) ? dcpRespF$FULL_N : (dcpReqF$D_OUT[78:77] == 2'd1 || - !dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d532 || + !dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 || !lastTag[8] || dcpReqF$D_OUT[44] || dcpRespF$FULL_N) && @@ -953,34 +949,34 @@ module mkEDCPAdapter(CLK, assign IF_dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23__ETC___d150 = (dcpReqF$D_OUT[78:77] == 2'd1) ? dcpRespF$FULL_N && - (dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d533 && + (dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d455 && lastTag[8] && !dcpReqF$D_OUT[76] || cpReqF$FULL_N) : - dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d532 && + dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 && lastTag[8] && !dcpReqF$D_OUT[44] || cpReqF$FULL_N ; - assign IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d544 = + assign IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d466 = dcpRespF$D_OUT[42] ? 8'h70 : 8'h30 ; assign bedw__h2286 = { x__h5652, ecpReqF$D_OUT[27:20], ecpReqF$D_OUT[37:30] } ; - assign dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d532 = + assign dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 = dcpReqF$D_OUT[39:32] == lastTag[7:0] ; - assign dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d533 = + assign dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d455 = dcpReqF$D_OUT[71:64] == lastTag[7:0] ; assign dcpReqF_first__19_BITS_78_TO_77_20_EQ_0_21_OR__ETC___d155 = dcpReqF$D_OUT[78:77] == 2'd0 || dcpReqF$D_OUT[78:77] == 2'd1 || - dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d532 && + dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 && lastTag[8] && !dcpReqF$D_OUT[44] ; assign dcpReqF_first__19_BITS_78_TO_77_20_EQ_1_23_AND_ETC___d196 = dcpReqF$D_OUT[78:77] == 2'd1 && - (!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d533 || + (!dcpReqF_first__19_BITS_71_TO_64_37_EQ_IF_lastT_ETC___d455 || !lastTag[8] || dcpReqF$D_OUT[76]) || dcpReqF$D_OUT[78:77] != 2'd1 && - (!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d532 || + (!dcpReqF_first__19_BITS_39_TO_32_24_EQ_IF_lastT_ETC___d454 || !lastTag[8] || dcpReqF$D_OUT[44]) ; assign eMAddrF_i_notFull__9_AND_IF_eDMH_0_BITS_13_TO__ETC___d100 = @@ -1086,17 +1082,17 @@ module mkEDCPAdapter(CLK, endcase end always@(dcpRespF$D_OUT or - IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d544) + IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d466) begin case (dcpRespF$D_OUT[44:43]) 2'd0: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 = - IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d544; + IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d466; 2'd1: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 = dcpRespF$D_OUT[10] ? 8'h70 : 8'h30; default: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q10 = - IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d544; + IF_dcpRespF_first__49_BIT_42_56_THEN_0x70_ELSE_ETC___d466; endcase end @@ -1198,28 +1194,28 @@ module mkEDCPAdapter(CLK, begin #0; if (RST_N) - if (WILL_FIRE_RL_edpFsm_action_l237c14 && - (WILL_FIRE_RL_edpFsm_action_l238c14 || - WILL_FIRE_RL_edpFsm_action_l239c14 || - WILL_FIRE_RL_edpFsm_action_l241c16 || + if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 && + (MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 || WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16)) $display("Error: \"bsv/eth/EDCP.bsv\", line 237, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l237c14] and\n [RL_edpFsm_action_l238c14, RL_edpFsm_action_l239c14,\n RL_edpFsm_action_l241c16, RL_edpFsm_action_l243c16,\n RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n"); if (RST_N) - if (WILL_FIRE_RL_edpFsm_action_l238c14 && - (WILL_FIRE_RL_edpFsm_action_l239c14 || - WILL_FIRE_RL_edpFsm_action_l241c16 || + if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 && + (MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 || WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16)) $display("Error: \"bsv/eth/EDCP.bsv\", line 238, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l238c14] and\n [RL_edpFsm_action_l239c14, RL_edpFsm_action_l241c16,\n RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n"); if (RST_N) - if (WILL_FIRE_RL_edpFsm_action_l239c14 && - (WILL_FIRE_RL_edpFsm_action_l241c16 || + if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 && + (MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 || WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16)) $display("Error: \"bsv/eth/EDCP.bsv\", line 239, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l239c14] and\n [RL_edpFsm_action_l241c16, RL_edpFsm_action_l243c16,\n RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n"); if (RST_N) - if (WILL_FIRE_RL_edpFsm_action_l241c16 && + if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 && (WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16)) $display("Error: \"bsv/eth/EDCP.bsv\", line 241, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l241c16] and\n [RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n"); @@ -1228,11 +1224,11 @@ module mkEDCPAdapter(CLK, WILL_FIRE_RL_edpFsm_action_l244c16) $display("Error: \"bsv/eth/EDCP.bsv\", line 243, column 16: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l243c16] and\n [RL_edpFsm_action_l244c16] ) fired in the same clock cycle.\n"); if (RST_N) - if (WILL_FIRE_RL_edpFsm_action_l236c14 && - (WILL_FIRE_RL_edpFsm_action_l237c14 || - WILL_FIRE_RL_edpFsm_action_l238c14 || - WILL_FIRE_RL_edpFsm_action_l239c14 || - WILL_FIRE_RL_edpFsm_action_l241c16 || + if (MUX_edpFsm_state_mkFSMstate$write_1__SEL_2 && + (MUX_edpFsm_state_mkFSMstate$write_1__SEL_3 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_4 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_5 || + MUX_edpFsm_state_mkFSMstate$write_1__SEL_6 || WILL_FIRE_RL_edpFsm_action_l243c16 || WILL_FIRE_RL_edpFsm_action_l244c16)) $display("Error: \"bsv/eth/EDCP.bsv\", line 236, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_edpFsm_action_l236c14] and\n [RL_edpFsm_action_l237c14, RL_edpFsm_action_l238c14,\n RL_edpFsm_action_l239c14, RL_edpFsm_action_l241c16,\n RL_edpFsm_action_l243c16, RL_edpFsm_action_l244c16] ) fired in the same\n clock cycle.\n"); diff --git a/rtl/mkEDDPAdapter.v b/rtl/mkEDDPAdapter.v index 22ca5505..612f7e3a 100644 --- a/rtl/mkEDDPAdapter.v +++ b/rtl/mkEDDPAdapter.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Wed Sep 19 14:36:25 EDT 2012 +// On Mon Sep 24 13:37:54 EDT 2012 // // // Ports: diff --git a/rtl/mkFTop_n210.v b/rtl/mkFTop_n210.v index 73a47420..0eccb35b 100644 --- a/rtl/mkFTop_n210.v +++ b/rtl/mkFTop_n210.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 10:16:50 EDT 2012 +// On Mon Sep 24 13:40:37 EDT 2012 // // // Ports: @@ -1726,9 +1726,9 @@ module mkFTop_n210(sys0_clkp, CASE_emuxclient0_request_get_BITS_9_TO_8_3_0__ETC__q4, emux$client0_request_get[7:0] } ; assign edcp$EN_server_request_put = - edcp$RDY_server_request_put && emux$RDY_client0_request_get ; + emux$RDY_client0_request_get && edcp$RDY_server_request_put ; assign edcp$EN_server_response_get = - edcp$RDY_server_response_get && emux$RDY_client0_response_put ; + emux$RDY_client0_response_put && edcp$RDY_server_response_get ; assign edcp$EN_client_request_get = cp$RDY_server_request_put && edcp$RDY_client_request_get ; assign edcp$EN_client_response_put = @@ -1758,9 +1758,9 @@ module mkFTop_n210(sys0_clkp, CASE_emuxclient1_request_get_BITS_9_TO_8_3_0__ETC__q12, emux$client1_request_get[7:0] } ; assign eddp0$EN_server_request_put = - eddp0$RDY_server_request_put && emux$RDY_client1_request_get ; + emux$RDY_client1_request_get && eddp0$RDY_server_request_put ; assign eddp0$EN_server_response_get = - eddp0$RDY_server_response_get && emux$RDY_client1_response_put ; + emux$RDY_client1_response_put && eddp0$RDY_server_response_get ; assign eddp0$EN_client_request_get = edp0$RDY_server_request_put && eddp0$RDY_client_request_get ; assign eddp0$EN_client_response_put = @@ -1792,9 +1792,9 @@ module mkFTop_n210(sys0_clkp, CASE_emuxclient2_request_get_BITS_9_TO_8_3_0__ETC__q20, emux$client2_request_get[7:0] } ; assign eddp1$EN_server_request_put = - eddp1$RDY_server_request_put && emux$RDY_client2_request_get ; + emux$RDY_client2_request_get && eddp1$RDY_server_request_put ; assign eddp1$EN_server_response_get = - eddp1$RDY_server_response_get && emux$RDY_client2_response_put ; + emux$RDY_client2_response_put && eddp1$RDY_server_response_get ; assign eddp1$EN_client_request_get = edp1$RDY_server_request_put && eddp1$RDY_client_request_get ; assign eddp1$EN_client_response_put = @@ -1913,17 +1913,17 @@ module mkFTop_n210(sys0_clkp, assign emux$EN_server_response_get = emux$RDY_server_response_get && gbe0$RDY_client_response_put ; assign emux$EN_client0_request_get = - edcp$RDY_server_request_put && emux$RDY_client0_request_get ; + emux$RDY_client0_request_get && edcp$RDY_server_request_put ; assign emux$EN_client0_response_put = - edcp$RDY_server_response_get && emux$RDY_client0_response_put ; + emux$RDY_client0_response_put && edcp$RDY_server_response_get ; assign emux$EN_client1_request_get = - eddp0$RDY_server_request_put && emux$RDY_client1_request_get ; + emux$RDY_client1_request_get && eddp0$RDY_server_request_put ; assign emux$EN_client1_response_put = - eddp0$RDY_server_response_get && emux$RDY_client1_response_put ; + emux$RDY_client1_response_put && eddp0$RDY_server_response_get ; assign emux$EN_client2_request_get = - eddp1$RDY_server_request_put && emux$RDY_client2_request_get ; + emux$RDY_client2_request_get && eddp1$RDY_server_request_put ; assign emux$EN_client2_response_put = - eddp1$RDY_server_response_get && emux$RDY_client2_response_put ; + emux$RDY_client2_response_put && eddp1$RDY_server_response_get ; // submodule gbe0 assign gbe0$client_response_put = diff --git a/rtl/mkGMAC.v b/rtl/mkGMAC.v index 51ac1ea1..e08af7ac 100644 --- a/rtl/mkGMAC.v +++ b/rtl/mkGMAC.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:44:14 EDT 2012 +// On Mon Sep 24 13:37:57 EDT 2012 // // // Ports: @@ -23,9 +23,9 @@ // RDY_phyInterrupt O 1 const // CLK_gmii_tx_tx_clk O 1 clock // CLK_GATE_gmii_tx_tx_clk O 1 const -// CLK_rxclkBnd O 1 clock +// CLK_rxclkBnd O 1 // CLK_GATE_rxclkBnd O 1 const -// CLK_rxClk I 1 clock +// CLK_rxClk I 1 // CLK_txClk I 1 clock // CLK I 1 clock // RST_N I 1 reset @@ -356,21 +356,12 @@ module mkGMAC(CLK_rxClk, // ports of submodule crs_cc wire crs_cc$sD_IN, crs_cc$sEN; - // ports of submodule gmii_rx_clk - wire gmii_rx_clk$O; - - // ports of submodule gmii_rxc_dly - wire gmii_rxc_dly$DATAOUT; - // ports of submodule intr_cc wire intr_cc$dD_OUT, intr_cc$sD_IN, intr_cc$sEN; // ports of submodule phyReset wire phyReset$OUT_RST_N; - // ports of submodule rxClk_BUFR - wire rxClk_BUFR$O; - // ports of submodule rxRS_crc wire [31 : 0] rxRS_crc$complete; wire [7 : 0] rxRS_crc$add_data; @@ -397,85 +388,97 @@ module mkGMAC(CLK_rxClk, // ports of submodule txRS_iobTxClk wire txRS_iobTxClk$Q; + // ports of submodule txRS_iobTxClk_cdi + wire txRS_iobTxClk_cdi$CLK_OUT; + // ports of submodule txRS_iobTxClk_reset wire txRS_iobTxClk_reset$RESET_OUT; // ports of submodule txRS_iobTxData wire txRS_iobTxData$CE, + txRS_iobTxData$D0, txRS_iobTxData$D1, - txRS_iobTxData$D2, txRS_iobTxData$Q, txRS_iobTxData$S; // ports of submodule txRS_iobTxData_1 wire txRS_iobTxData_1$CE, + txRS_iobTxData_1$D0, txRS_iobTxData_1$D1, - txRS_iobTxData_1$D2, txRS_iobTxData_1$Q, txRS_iobTxData_1$S; // ports of submodule txRS_iobTxData_2 wire txRS_iobTxData_2$CE, + txRS_iobTxData_2$D0, txRS_iobTxData_2$D1, - txRS_iobTxData_2$D2, txRS_iobTxData_2$Q, txRS_iobTxData_2$S; // ports of submodule txRS_iobTxData_3 wire txRS_iobTxData_3$CE, + txRS_iobTxData_3$D0, txRS_iobTxData_3$D1, - txRS_iobTxData_3$D2, txRS_iobTxData_3$Q, txRS_iobTxData_3$S; // ports of submodule txRS_iobTxData_4 wire txRS_iobTxData_4$CE, + txRS_iobTxData_4$D0, txRS_iobTxData_4$D1, - txRS_iobTxData_4$D2, txRS_iobTxData_4$Q, txRS_iobTxData_4$S; // ports of submodule txRS_iobTxData_5 wire txRS_iobTxData_5$CE, + txRS_iobTxData_5$D0, txRS_iobTxData_5$D1, - txRS_iobTxData_5$D2, txRS_iobTxData_5$Q, txRS_iobTxData_5$S; // ports of submodule txRS_iobTxData_6 wire txRS_iobTxData_6$CE, + txRS_iobTxData_6$D0, txRS_iobTxData_6$D1, - txRS_iobTxData_6$D2, txRS_iobTxData_6$Q, txRS_iobTxData_6$S; // ports of submodule txRS_iobTxData_7 wire txRS_iobTxData_7$CE, + txRS_iobTxData_7$D0, txRS_iobTxData_7$D1, - txRS_iobTxData_7$D2, txRS_iobTxData_7$Q, txRS_iobTxData_7$S; + // ports of submodule txRS_iobTxData_cdi + wire txRS_iobTxData_cdi$CLK_OUT; + // ports of submodule txRS_iobTxData_reset wire txRS_iobTxData_reset$RESET_OUT; // ports of submodule txRS_iobTxEna wire txRS_iobTxEna$CE, + txRS_iobTxEna$D0, txRS_iobTxEna$D1, - txRS_iobTxEna$D2, txRS_iobTxEna$Q, txRS_iobTxEna$S; + // ports of submodule txRS_iobTxEna_cdi + wire txRS_iobTxEna_cdi$CLK_OUT; + // ports of submodule txRS_iobTxEna_reset wire txRS_iobTxEna_reset$RESET_OUT; // ports of submodule txRS_iobTxErr wire txRS_iobTxErr$CE, + txRS_iobTxErr$D0, txRS_iobTxErr$D1, - txRS_iobTxErr$D2, txRS_iobTxErr$Q, txRS_iobTxErr$S; + // ports of submodule txRS_iobTxErr_cdi + wire txRS_iobTxErr_cdi$CLK_OUT; + // ports of submodule txRS_iobTxErr_reset wire txRS_iobTxErr_reset$RESET_OUT; @@ -525,19 +528,19 @@ module mkGMAC(CLK_rxClk, MUX_txRS_ifgCnt_value$write_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h12376, v__h6530; + reg [63 : 0] v__h12184, v__h6338; reg [1 : 0] CASE_rxRS_rxFdD_OUT_BITS_9_TO_8_3_0_rxRS_rxF_ETC__q1, CASE_tx_put_BITS_9_TO_8_3_0_tx_put_BITS_9_TO_8_ETC__q2; - wire txRS_lenCnt_value_45_ULT_59___d294, - txRS_preambleCnt_value_19_ULT_7___d295; + wire txRS_lenCnt_value_45_ULT_59___d298, + txRS_preambleCnt_value_19_ULT_7___d296; // oscillator and gates for output clock CLK_gmii_tx_tx_clk assign CLK_gmii_tx_tx_clk = txRS_iobTxClk$Q ; assign CLK_GATE_gmii_tx_tx_clk = 1'b1 ; // oscillator and gates for output clock CLK_rxclkBnd - assign CLK_rxclkBnd = rxClk_BUFR$O ; - assign CLK_GATE_rxclkBnd = 1'b1 ; + assign CLK_rxclkBnd = CLK_rxClk ; + assign CLK_GATE_rxclkBnd = 1'd1 ; // value method gmii_tx_txd assign gmii_tx_txd = @@ -602,24 +605,6 @@ module mkGMAC(CLK_rxClk, .sEN(crs_cc$sEN), .dD_OUT()); - // submodule gmii_rx_clk - BUFIO gmii_rx_clk(.I(gmii_rxc_dly$DATAOUT), .O(gmii_rx_clk$O)); - - // submodule gmii_rxc_dly - IODELAY #(.IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(32'd0), - .DELAY_SRC("I"), - .SIGNAL_PATTERN("CLOCK"), - .HIGH_PERFORMANCE_MODE("TRUE")) gmii_rxc_dly(.IDATAIN(CLK_rxClk), - .ODATAIN(32'd0), - .DATAIN(32'd0), - .C(32'd0), - .T(32'd0), - .CE(32'd0), - .INC(32'd0), - .RST(32'd0), - .DATAOUT(gmii_rxc_dly$DATAOUT)); - // submodule intr_cc SyncBit #(.init(1'd0)) intr_cc(.sCLK(CLK), .dCLK(CLK), @@ -633,14 +618,8 @@ module mkGMAC(CLK_rxClk, .IN_RST_N(RST_N), .OUT_RST_N(phyReset$OUT_RST_N)); - // submodule rxClk_BUFR - BUFR #(.BUFR_DIVIDE("BYPASS")) rxClk_BUFR(.I(gmii_rxc_dly$DATAOUT), - .CE(1'd1), - .CLR(1'd0), - .O(rxClk_BUFR$O)); - // submodule rxRS_crc - mkCRC32 rxRS_crc(.CLK(rxClk_BUFR$O), + mkCRC32 rxRS_crc(.CLK(CLK_rxClk), .RST_N(rxRS_rxRst$OUT_RST_N), .add_data(rxRS_crc$add_data), .EN_add(rxRS_crc$EN_add), @@ -654,7 +633,7 @@ module mkGMAC(CLK_rxClk, .RDY_complete()); // submodule rxRS_ovfBit - SyncBit #(.init(1'd0)) rxRS_ovfBit(.sCLK(rxClk_BUFR$O), + SyncBit #(.init(1'd0)) rxRS_ovfBit(.sCLK(CLK_rxClk), .dCLK(CLK), .sRST_N(rxRS_rxRst$OUT_RST_N), .sD_IN(rxRS_ovfBit$sD_IN), @@ -664,7 +643,7 @@ module mkGMAC(CLK_rxClk, // submodule rxRS_rxF SyncFIFO #(.dataWidth(32'd10), .depth(32'd8), - .indxWidth(32'd3)) rxRS_rxF(.sCLK(rxClk_BUFR$O), + .indxWidth(32'd3)) rxRS_rxF(.sCLK(CLK_rxClk), .dCLK(CLK), .sRST_N(rxRS_rxRst$OUT_RST_N), .sD_IN(rxRS_rxF$sD_IN), @@ -676,14 +655,14 @@ module mkGMAC(CLK_rxClk, // submodule rxRS_rxOperateS SyncBit #(.init(1'd0)) rxRS_rxOperateS(.sCLK(CLK), - .dCLK(rxClk_BUFR$O), + .dCLK(CLK_rxClk), .sRST_N(RST_N), .sD_IN(rxRS_rxOperateS$sD_IN), .sEN(rxRS_rxOperateS$sEN), .dD_OUT(rxRS_rxOperateS$dD_OUT)); // submodule rxRS_rxRst - SyncResetA #(.RSTDELAY(32'd1)) rxRS_rxRst(.CLK(rxClk_BUFR$O), + SyncResetA #(.RSTDELAY(32'd1)) rxRS_rxRst(.CLK(CLK_rxClk), .IN_RST_N(RST_N), .OUT_RST_N(rxRS_rxRst$OUT_RST_N)); @@ -703,137 +682,168 @@ module mkGMAC(CLK_rxClk, // submodule txRS_iobTxClk // iobTxClk output is 180 degress out-of-phase for 4 nS SU + 4 nS Hold - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxClk(.C(CLK_txClk), - .R(txRS_iobTxClk_reset$RESET_OUT), - .D1(1'd0), - .D2(1'd1), - .CE(1'd1), - .S(1'd0), - .Q(txRS_iobTxClk$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'd0), + .SRTYPE("SYNC")) txRS_iobTxClk(.R(txRS_iobTxClk_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxClk_cdi$CLK_OUT), + .D0(1'd0), + .D1(1'd1), + .CE(1'd1), + .S(1'd0), + .Q(txRS_iobTxClk$Q)); + + // submodule txRS_iobTxClk_cdi + ClockInverter txRS_iobTxClk_cdi(.CLK_IN(CLK_txClk), + .PREEDGE(), + .CLK_OUT(txRS_iobTxClk_cdi$CLK_OUT)); // submodule txRS_iobTxClk_reset ResetInverter txRS_iobTxClk_reset(.RESET_IN(txRS_txRst$OUT_RST_N), .RESET_OUT(txRS_iobTxClk_reset$RESET_OUT)); // submodule txRS_iobTxData - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxData(.C(CLK_txClk), - .R(txRS_iobTxData_reset$RESET_OUT), - .CE(txRS_iobTxData$CE), - .D1(txRS_iobTxData$D1), - .D2(txRS_iobTxData$D2), - .S(txRS_iobTxData$S), - .Q(txRS_iobTxData$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC")) txRS_iobTxData(.R(txRS_iobTxData_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxData_cdi$CLK_OUT), + .CE(txRS_iobTxData$CE), + .D0(txRS_iobTxData$D0), + .D1(txRS_iobTxData$D1), + .S(txRS_iobTxData$S), + .Q(txRS_iobTxData$Q)); // submodule txRS_iobTxData_1 - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxData_1(.C(CLK_txClk), - .R(txRS_iobTxData_reset$RESET_OUT), - .CE(txRS_iobTxData_1$CE), - .D1(txRS_iobTxData_1$D1), - .D2(txRS_iobTxData_1$D2), - .S(txRS_iobTxData_1$S), - .Q(txRS_iobTxData_1$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC")) txRS_iobTxData_1(.R(txRS_iobTxData_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxData_cdi$CLK_OUT), + .CE(txRS_iobTxData_1$CE), + .D0(txRS_iobTxData_1$D0), + .D1(txRS_iobTxData_1$D1), + .S(txRS_iobTxData_1$S), + .Q(txRS_iobTxData_1$Q)); // submodule txRS_iobTxData_2 - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxData_2(.C(CLK_txClk), - .R(txRS_iobTxData_reset$RESET_OUT), - .CE(txRS_iobTxData_2$CE), - .D1(txRS_iobTxData_2$D1), - .D2(txRS_iobTxData_2$D2), - .S(txRS_iobTxData_2$S), - .Q(txRS_iobTxData_2$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC")) txRS_iobTxData_2(.R(txRS_iobTxData_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxData_cdi$CLK_OUT), + .CE(txRS_iobTxData_2$CE), + .D0(txRS_iobTxData_2$D0), + .D1(txRS_iobTxData_2$D1), + .S(txRS_iobTxData_2$S), + .Q(txRS_iobTxData_2$Q)); // submodule txRS_iobTxData_3 - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxData_3(.C(CLK_txClk), - .R(txRS_iobTxData_reset$RESET_OUT), - .CE(txRS_iobTxData_3$CE), - .D1(txRS_iobTxData_3$D1), - .D2(txRS_iobTxData_3$D2), - .S(txRS_iobTxData_3$S), - .Q(txRS_iobTxData_3$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC")) txRS_iobTxData_3(.R(txRS_iobTxData_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxData_cdi$CLK_OUT), + .CE(txRS_iobTxData_3$CE), + .D0(txRS_iobTxData_3$D0), + .D1(txRS_iobTxData_3$D1), + .S(txRS_iobTxData_3$S), + .Q(txRS_iobTxData_3$Q)); // submodule txRS_iobTxData_4 - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxData_4(.C(CLK_txClk), - .R(txRS_iobTxData_reset$RESET_OUT), - .CE(txRS_iobTxData_4$CE), - .D1(txRS_iobTxData_4$D1), - .D2(txRS_iobTxData_4$D2), - .S(txRS_iobTxData_4$S), - .Q(txRS_iobTxData_4$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC")) txRS_iobTxData_4(.R(txRS_iobTxData_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxData_cdi$CLK_OUT), + .CE(txRS_iobTxData_4$CE), + .D0(txRS_iobTxData_4$D0), + .D1(txRS_iobTxData_4$D1), + .S(txRS_iobTxData_4$S), + .Q(txRS_iobTxData_4$Q)); // submodule txRS_iobTxData_5 - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxData_5(.C(CLK_txClk), - .R(txRS_iobTxData_reset$RESET_OUT), - .CE(txRS_iobTxData_5$CE), - .D1(txRS_iobTxData_5$D1), - .D2(txRS_iobTxData_5$D2), - .S(txRS_iobTxData_5$S), - .Q(txRS_iobTxData_5$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC")) txRS_iobTxData_5(.R(txRS_iobTxData_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxData_cdi$CLK_OUT), + .CE(txRS_iobTxData_5$CE), + .D0(txRS_iobTxData_5$D0), + .D1(txRS_iobTxData_5$D1), + .S(txRS_iobTxData_5$S), + .Q(txRS_iobTxData_5$Q)); // submodule txRS_iobTxData_6 - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxData_6(.C(CLK_txClk), - .R(txRS_iobTxData_reset$RESET_OUT), - .CE(txRS_iobTxData_6$CE), - .D1(txRS_iobTxData_6$D1), - .D2(txRS_iobTxData_6$D2), - .S(txRS_iobTxData_6$S), - .Q(txRS_iobTxData_6$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC")) txRS_iobTxData_6(.R(txRS_iobTxData_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxData_cdi$CLK_OUT), + .CE(txRS_iobTxData_6$CE), + .D0(txRS_iobTxData_6$D0), + .D1(txRS_iobTxData_6$D1), + .S(txRS_iobTxData_6$S), + .Q(txRS_iobTxData_6$Q)); // submodule txRS_iobTxData_7 - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxData_7(.C(CLK_txClk), - .R(txRS_iobTxData_reset$RESET_OUT), - .CE(txRS_iobTxData_7$CE), - .D1(txRS_iobTxData_7$D1), - .D2(txRS_iobTxData_7$D2), - .S(txRS_iobTxData_7$S), - .Q(txRS_iobTxData_7$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC")) txRS_iobTxData_7(.R(txRS_iobTxData_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxData_cdi$CLK_OUT), + .CE(txRS_iobTxData_7$CE), + .D0(txRS_iobTxData_7$D0), + .D1(txRS_iobTxData_7$D1), + .S(txRS_iobTxData_7$S), + .Q(txRS_iobTxData_7$Q)); + + // submodule txRS_iobTxData_cdi + ClockInverter txRS_iobTxData_cdi(.CLK_IN(CLK_txClk), + .PREEDGE(), + .CLK_OUT(txRS_iobTxData_cdi$CLK_OUT)); // submodule txRS_iobTxData_reset ResetInverter txRS_iobTxData_reset(.RESET_IN(txRS_txRst$OUT_RST_N), .RESET_OUT(txRS_iobTxData_reset$RESET_OUT)); // submodule txRS_iobTxEna - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxEna(.C(CLK_txClk), - .R(txRS_iobTxEna_reset$RESET_OUT), - .CE(txRS_iobTxEna$CE), - .D1(txRS_iobTxEna$D1), - .D2(txRS_iobTxEna$D2), - .S(txRS_iobTxEna$S), - .Q(txRS_iobTxEna$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC")) txRS_iobTxEna(.R(txRS_iobTxEna_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxEna_cdi$CLK_OUT), + .CE(txRS_iobTxEna$CE), + .D0(txRS_iobTxEna$D0), + .D1(txRS_iobTxEna$D1), + .S(txRS_iobTxEna$S), + .Q(txRS_iobTxEna$Q)); + + // submodule txRS_iobTxEna_cdi + ClockInverter txRS_iobTxEna_cdi(.CLK_IN(CLK_txClk), + .PREEDGE(), + .CLK_OUT(txRS_iobTxEna_cdi$CLK_OUT)); // submodule txRS_iobTxEna_reset ResetInverter txRS_iobTxEna_reset(.RESET_IN(txRS_txRst$OUT_RST_N), .RESET_OUT(txRS_iobTxEna_reset$RESET_OUT)); // submodule txRS_iobTxErr - ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'd0), - .SRTYPE("SYNC")) txRS_iobTxErr(.C(CLK_txClk), - .R(txRS_iobTxErr_reset$RESET_OUT), - .CE(txRS_iobTxErr$CE), - .D1(txRS_iobTxErr$D1), - .D2(txRS_iobTxErr$D2), - .S(txRS_iobTxErr$S), - .Q(txRS_iobTxErr$Q)); + ODDR2 #(.DDR_ALIGNMENT("NONE"), + .INIT(1'b0), + .SRTYPE("SYNC")) txRS_iobTxErr(.R(txRS_iobTxErr_reset$RESET_OUT), + .C0(CLK_txClk), + .C1(txRS_iobTxErr_cdi$CLK_OUT), + .CE(txRS_iobTxErr$CE), + .D0(txRS_iobTxErr$D0), + .D1(txRS_iobTxErr$D1), + .S(txRS_iobTxErr$S), + .Q(txRS_iobTxErr$Q)); + + // submodule txRS_iobTxErr_cdi + ClockInverter txRS_iobTxErr_cdi(.CLK_IN(CLK_txClk), + .PREEDGE(), + .CLK_OUT(txRS_iobTxErr_cdi$CLK_OUT)); // submodule txRS_iobTxErr_reset ResetInverter txRS_iobTxErr_reset(.RESET_IN(txRS_txRst$OUT_RST_N), @@ -907,7 +917,7 @@ module mkGMAC(CLK_rxClk, // rule RL_txRS_egress_SOF assign CAN_FIRE_RL_txRS_egress_SOF = txRS_txF$dEMPTY_N && - (txRS_preambleCnt_value_19_ULT_7___d295 || + (txRS_preambleCnt_value_19_ULT_7___d296 || txRS_preambleCnt_value == 5'd7 || txRS_txF$dEMPTY_N) && txRS_txOperateS$dD_OUT && @@ -928,7 +938,7 @@ module mkGMAC(CLK_rxClk, // rule RL_txRS_egress_EOF assign CAN_FIRE_RL_txRS_egress_EOF = txRS_txF$dEMPTY_N && - (txRS_lenCnt_value_45_ULT_59___d294 || txRS_txF$dEMPTY_N) && + (txRS_lenCnt_value_45_ULT_59___d298 || txRS_txF$dEMPTY_N) && txRS_txOperateS$dD_OUT && txRS_txActive && txRS_txF$dD_OUT[9:8] == 2'd1 ; @@ -944,13 +954,13 @@ module mkGMAC(CLK_rxClk, WILL_FIRE_RL_rxRS_ingress_noadvance && rxRS_rxActive ; assign MUX_txRS_crc$add_1__SEL_1 = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d295 && + !txRS_preambleCnt_value_19_ULT_7___d296 && txRS_preambleCnt_value != 5'd7 ; assign MUX_txRS_crcDbgCnt_value$write_1__SEL_1 = WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd4 ; assign MUX_txRS_emitFCS$write_1__SEL_1 = WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d294 ; + !txRS_lenCnt_value_45_ULT_59___d298 ; assign MUX_txRS_ifgCnt_value$write_1__SEL_1 = WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd1 ; assign MUX_rxRS_crcDbgCnt_value$write_1__VAL_1 = @@ -1004,7 +1014,7 @@ module mkGMAC(CLK_rxClk, endcase end assign MUX_txRS_txData_1$wset_1__VAL_4 = - txRS_preambleCnt_value_19_ULT_7___d295 ? + txRS_preambleCnt_value_19_ULT_7___d296 ? 8'd85 : ((txRS_preambleCnt_value == 5'd7) ? 8'd213 : @@ -1061,7 +1071,7 @@ module mkGMAC(CLK_rxClk, txRS_txOperateS$dD_OUT && txRS_ifgCnt_value != 5'h0 ; assign txRS_lenCnt_incAction$whas = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d295 && + !txRS_preambleCnt_value_19_ULT_7___d296 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_Body || WILL_FIRE_RL_txRS_egress_EOF || @@ -1069,7 +1079,7 @@ module mkGMAC(CLK_rxClk, assign txRS_lenCnt_decAction$whas = 1'b0 ; assign txRS_crcDbgCnt_incAction$whas = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d295 && + !txRS_preambleCnt_value_19_ULT_7___d296 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_Body || WILL_FIRE_RL_txRS_egress_EOF ; @@ -1166,7 +1176,7 @@ module mkGMAC(CLK_rxClk, txRS_crcDbgCnt_incAction$whas && !WILL_FIRE_RL_txRS_egress_FCS ; // register txRS_doPad - assign txRS_doPad$D_IN = txRS_lenCnt_value_45_ULT_59___d294 ; + assign txRS_doPad$D_IN = txRS_lenCnt_value_45_ULT_59___d298 ; assign txRS_doPad$EN = WILL_FIRE_RL_txRS_egress_EOF ; // register txRS_emitFCS @@ -1176,7 +1186,7 @@ module mkGMAC(CLK_rxClk, MUX_txRS_emitFCS$write_1__VAL_2 ; assign txRS_emitFCS$EN = WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d294 || + !txRS_lenCnt_value_45_ULT_59___d298 || WILL_FIRE_RL_txRS_egress_FCS ; // register txRS_ifgCnt_value @@ -1192,7 +1202,7 @@ module mkGMAC(CLK_rxClk, assign txRS_isSOF$D_IN = !MUX_txRS_crc$add_1__SEL_1 ; assign txRS_isSOF$EN = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d295 && + !txRS_preambleCnt_value_19_ULT_7___d296 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd1 ; @@ -1218,7 +1228,7 @@ module mkGMAC(CLK_rxClk, assign txRS_txActive$D_IN = !MUX_txRS_emitFCS$write_1__SEL_1 ; assign txRS_txActive$EN = WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d294 || + !txRS_lenCnt_value_45_ULT_59___d298 || WILL_FIRE_RL_txRS_egress_SOF ; // register txRS_txDV @@ -1292,7 +1302,7 @@ module mkGMAC(CLK_rxClk, MUX_txRS_crc$add_1__VAL_2 ; assign txRS_crc$EN_add = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d295 && + !txRS_preambleCnt_value_19_ULT_7___d296 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_EOF || WILL_FIRE_RL_txRS_egress_Body ; @@ -1301,62 +1311,62 @@ module mkGMAC(CLK_rxClk, // submodule txRS_iobTxData assign txRS_iobTxData$CE = 1'd1 ; + assign txRS_iobTxData$D0 = txRS_txData[0] ; assign txRS_iobTxData$D1 = txRS_txData[0] ; - assign txRS_iobTxData$D2 = txRS_txData[0] ; assign txRS_iobTxData$S = 1'd0 ; // submodule txRS_iobTxData_1 assign txRS_iobTxData_1$CE = 1'd1 ; + assign txRS_iobTxData_1$D0 = txRS_txData[1] ; assign txRS_iobTxData_1$D1 = txRS_txData[1] ; - assign txRS_iobTxData_1$D2 = txRS_txData[1] ; assign txRS_iobTxData_1$S = 1'd0 ; // submodule txRS_iobTxData_2 assign txRS_iobTxData_2$CE = 1'd1 ; + assign txRS_iobTxData_2$D0 = txRS_txData[2] ; assign txRS_iobTxData_2$D1 = txRS_txData[2] ; - assign txRS_iobTxData_2$D2 = txRS_txData[2] ; assign txRS_iobTxData_2$S = 1'd0 ; // submodule txRS_iobTxData_3 assign txRS_iobTxData_3$CE = 1'd1 ; + assign txRS_iobTxData_3$D0 = txRS_txData[3] ; assign txRS_iobTxData_3$D1 = txRS_txData[3] ; - assign txRS_iobTxData_3$D2 = txRS_txData[3] ; assign txRS_iobTxData_3$S = 1'd0 ; // submodule txRS_iobTxData_4 assign txRS_iobTxData_4$CE = 1'd1 ; + assign txRS_iobTxData_4$D0 = txRS_txData[4] ; assign txRS_iobTxData_4$D1 = txRS_txData[4] ; - assign txRS_iobTxData_4$D2 = txRS_txData[4] ; assign txRS_iobTxData_4$S = 1'd0 ; // submodule txRS_iobTxData_5 assign txRS_iobTxData_5$CE = 1'd1 ; + assign txRS_iobTxData_5$D0 = txRS_txData[5] ; assign txRS_iobTxData_5$D1 = txRS_txData[5] ; - assign txRS_iobTxData_5$D2 = txRS_txData[5] ; assign txRS_iobTxData_5$S = 1'd0 ; // submodule txRS_iobTxData_6 assign txRS_iobTxData_6$CE = 1'd1 ; + assign txRS_iobTxData_6$D0 = txRS_txData[6] ; assign txRS_iobTxData_6$D1 = txRS_txData[6] ; - assign txRS_iobTxData_6$D2 = txRS_txData[6] ; assign txRS_iobTxData_6$S = 1'd0 ; // submodule txRS_iobTxData_7 assign txRS_iobTxData_7$CE = 1'd1 ; + assign txRS_iobTxData_7$D0 = txRS_txData[7] ; assign txRS_iobTxData_7$D1 = txRS_txData[7] ; - assign txRS_iobTxData_7$D2 = txRS_txData[7] ; assign txRS_iobTxData_7$S = 1'd0 ; // submodule txRS_iobTxEna assign txRS_iobTxEna$CE = 1'd1 ; + assign txRS_iobTxEna$D0 = txRS_txDV ; assign txRS_iobTxEna$D1 = txRS_txDV ; - assign txRS_iobTxEna$D2 = txRS_txDV ; assign txRS_iobTxEna$S = 1'd0 ; // submodule txRS_iobTxErr assign txRS_iobTxErr$CE = 1'd1 ; + assign txRS_iobTxErr$D0 = txRS_txER ; assign txRS_iobTxErr$D1 = txRS_txER ; - assign txRS_iobTxErr$D2 = txRS_txER ; assign txRS_iobTxErr$S = 1'd0 ; // submodule txRS_txF @@ -1366,10 +1376,10 @@ module mkGMAC(CLK_rxClk, assign txRS_txF$sENQ = EN_tx_put ; assign txRS_txF$dDEQ = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d295 && + !txRS_preambleCnt_value_19_ULT_7___d296 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d294 || + !txRS_lenCnt_value_45_ULT_59___d298 || WILL_FIRE_RL_txRS_egress_Body ; // submodule txRS_txOperateS @@ -1384,8 +1394,8 @@ module mkGMAC(CLK_rxClk, assign txRS_unfBit$sEN = txRS_txOperateS$dD_OUT ; // remaining internal signals - assign txRS_lenCnt_value_45_ULT_59___d294 = txRS_lenCnt_value < 12'd59 ; - assign txRS_preambleCnt_value_19_ULT_7___d295 = + assign txRS_lenCnt_value_45_ULT_59___d298 = txRS_lenCnt_value < 12'd59 ; + assign txRS_preambleCnt_value_19_ULT_7___d296 = txRS_preambleCnt_value < 5'd7 ; always@(rxRS_rxF$dD_OUT) begin @@ -1426,6 +1436,51 @@ module mkGMAC(CLK_rxClk, end end + always@(posedge CLK_rxClk) + begin + if (!rxRS_rxRst$OUT_RST_N) + begin + rxRS_crcDbgCnt_value <= `BSV_ASSIGNMENT_DELAY 12'd0; + rxRS_crcEnd <= `BSV_ASSIGNMENT_DELAY 1'd0; + rxRS_fullD <= `BSV_ASSIGNMENT_DELAY 1'd0; + rxRS_isSOF <= `BSV_ASSIGNMENT_DELAY 1'd1; + rxRS_preambleCnt_value <= `BSV_ASSIGNMENT_DELAY 4'd0; + rxRS_rxAPipe <= `BSV_ASSIGNMENT_DELAY 6'd0; + rxRS_rxActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + rxRS_rxDV <= `BSV_ASSIGNMENT_DELAY 1'd0; + rxRS_rxDVD <= `BSV_ASSIGNMENT_DELAY 1'd0; + rxRS_rxDVD2 <= `BSV_ASSIGNMENT_DELAY 1'd0; + rxRS_rxER <= `BSV_ASSIGNMENT_DELAY 1'd0; + end + else + begin + if (rxRS_crcDbgCnt_value$EN) + rxRS_crcDbgCnt_value <= `BSV_ASSIGNMENT_DELAY + rxRS_crcDbgCnt_value$D_IN; + if (rxRS_crcEnd$EN) + rxRS_crcEnd <= `BSV_ASSIGNMENT_DELAY rxRS_crcEnd$D_IN; + if (rxRS_fullD$EN) + rxRS_fullD <= `BSV_ASSIGNMENT_DELAY rxRS_fullD$D_IN; + if (rxRS_isSOF$EN) + rxRS_isSOF <= `BSV_ASSIGNMENT_DELAY rxRS_isSOF$D_IN; + if (rxRS_preambleCnt_value$EN) + rxRS_preambleCnt_value <= `BSV_ASSIGNMENT_DELAY + rxRS_preambleCnt_value$D_IN; + if (rxRS_rxAPipe$EN) + rxRS_rxAPipe <= `BSV_ASSIGNMENT_DELAY rxRS_rxAPipe$D_IN; + if (rxRS_rxActive$EN) + rxRS_rxActive <= `BSV_ASSIGNMENT_DELAY rxRS_rxActive$D_IN; + if (rxRS_rxDV$EN) rxRS_rxDV <= `BSV_ASSIGNMENT_DELAY rxRS_rxDV$D_IN; + if (rxRS_rxDVD$EN) + rxRS_rxDVD <= `BSV_ASSIGNMENT_DELAY rxRS_rxDVD$D_IN; + if (rxRS_rxDVD2$EN) + rxRS_rxDVD2 <= `BSV_ASSIGNMENT_DELAY rxRS_rxDVD2$D_IN; + if (rxRS_rxER$EN) rxRS_rxER <= `BSV_ASSIGNMENT_DELAY rxRS_rxER$D_IN; + end + if (rxRS_rxData$EN) rxRS_rxData <= `BSV_ASSIGNMENT_DELAY rxRS_rxData$D_IN; + if (rxRS_rxPipe$EN) rxRS_rxPipe <= `BSV_ASSIGNMENT_DELAY rxRS_rxPipe$D_IN; + end + always@(posedge CLK_txClk) begin if (!txRS_txRst$OUT_RST_N) @@ -1474,51 +1529,6 @@ module mkGMAC(CLK_rxClk, end end - always@(posedge rxClk_BUFR$O) - begin - if (!rxRS_rxRst$OUT_RST_N) - begin - rxRS_crcDbgCnt_value <= `BSV_ASSIGNMENT_DELAY 12'd0; - rxRS_crcEnd <= `BSV_ASSIGNMENT_DELAY 1'd0; - rxRS_fullD <= `BSV_ASSIGNMENT_DELAY 1'd0; - rxRS_isSOF <= `BSV_ASSIGNMENT_DELAY 1'd1; - rxRS_preambleCnt_value <= `BSV_ASSIGNMENT_DELAY 4'd0; - rxRS_rxAPipe <= `BSV_ASSIGNMENT_DELAY 6'd0; - rxRS_rxActive <= `BSV_ASSIGNMENT_DELAY 1'd0; - rxRS_rxDV <= `BSV_ASSIGNMENT_DELAY 1'd0; - rxRS_rxDVD <= `BSV_ASSIGNMENT_DELAY 1'd0; - rxRS_rxDVD2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - rxRS_rxER <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (rxRS_crcDbgCnt_value$EN) - rxRS_crcDbgCnt_value <= `BSV_ASSIGNMENT_DELAY - rxRS_crcDbgCnt_value$D_IN; - if (rxRS_crcEnd$EN) - rxRS_crcEnd <= `BSV_ASSIGNMENT_DELAY rxRS_crcEnd$D_IN; - if (rxRS_fullD$EN) - rxRS_fullD <= `BSV_ASSIGNMENT_DELAY rxRS_fullD$D_IN; - if (rxRS_isSOF$EN) - rxRS_isSOF <= `BSV_ASSIGNMENT_DELAY rxRS_isSOF$D_IN; - if (rxRS_preambleCnt_value$EN) - rxRS_preambleCnt_value <= `BSV_ASSIGNMENT_DELAY - rxRS_preambleCnt_value$D_IN; - if (rxRS_rxAPipe$EN) - rxRS_rxAPipe <= `BSV_ASSIGNMENT_DELAY rxRS_rxAPipe$D_IN; - if (rxRS_rxActive$EN) - rxRS_rxActive <= `BSV_ASSIGNMENT_DELAY rxRS_rxActive$D_IN; - if (rxRS_rxDV$EN) rxRS_rxDV <= `BSV_ASSIGNMENT_DELAY rxRS_rxDV$D_IN; - if (rxRS_rxDVD$EN) - rxRS_rxDVD <= `BSV_ASSIGNMENT_DELAY rxRS_rxDVD$D_IN; - if (rxRS_rxDVD2$EN) - rxRS_rxDVD2 <= `BSV_ASSIGNMENT_DELAY rxRS_rxDVD2$D_IN; - if (rxRS_rxER$EN) rxRS_rxER <= `BSV_ASSIGNMENT_DELAY rxRS_rxER$D_IN; - end - if (rxRS_rxData$EN) rxRS_rxData <= `BSV_ASSIGNMENT_DELAY rxRS_rxData$D_IN; - if (rxRS_rxPipe$EN) rxRS_rxPipe <= `BSV_ASSIGNMENT_DELAY rxRS_rxPipe$D_IN; - end - // synopsys translate_off `ifdef BSV_NO_INITIAL_BLOCKS `else // not BSV_NO_INITIAL_BLOCKS @@ -1559,6 +1569,25 @@ module mkGMAC(CLK_rxClk, // handling of system tasks + // synopsys translate_off + always@(negedge CLK_rxClk) + begin + #0; + if (rxRS_rxRst$OUT_RST_N) + if (WILL_FIRE_RL_rxRS_ingress_noadvance) + begin + v__h6338 = $time; + #0; + end + if (rxRS_rxRst$OUT_RST_N) + if (WILL_FIRE_RL_rxRS_ingress_noadvance) + $display("[%0d]: %m: RX FCS:%08x from %d elements", + v__h6338, + rxRS_crc$complete, + $unsigned(rxRS_crcDbgCnt_value)); + end + // synopsys translate_on + // synopsys translate_off always@(negedge CLK_txClk) begin @@ -1566,13 +1595,13 @@ module mkGMAC(CLK_rxClk, if (txRS_txRst$OUT_RST_N) if (WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd4) begin - v__h12376 = $time; + v__h12184 = $time; #0; end if (txRS_txRst$OUT_RST_N) if (WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd4) $display("[%0d]: %m: TX FCS:%08x from %d elements", - v__h12376, + v__h12184, { txRS_crc$result[7:0], txRS_crc$result[15:8], txRS_crc$result[23:16], @@ -1580,25 +1609,5 @@ module mkGMAC(CLK_rxClk, $unsigned(txRS_crcDbgCnt_value)); end // synopsys translate_on - - // synopsys translate_off - always@(negedge rxClk_BUFR$O or - negedge gmii_rx_clk$O or negedge gmii_rxc_dly$DATAOUT) - begin - #0; - if (rxRS_rxRst$OUT_RST_N) - if (WILL_FIRE_RL_rxRS_ingress_noadvance) - begin - v__h6530 = $time; - #0; - end - if (rxRS_rxRst$OUT_RST_N) - if (WILL_FIRE_RL_rxRS_ingress_noadvance) - $display("[%0d]: %m: RX FCS:%08x from %d elements", - v__h6530, - rxRS_crc$complete, - $unsigned(rxRS_crcDbgCnt_value)); - end - // synopsys translate_on endmodule // mkGMAC diff --git a/rtl/mkGbeQABS.v b/rtl/mkGbeQABS.v index cf786cfd..1b10db22 100644 --- a/rtl/mkGbeQABS.v +++ b/rtl/mkGbeQABS.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Wed Sep 19 14:36:35 EDT 2012 +// On Mon Sep 24 13:38:39 EDT 2012 // // // Ports: diff --git a/rtl/mkGbeWrk.v b/rtl/mkGbeWrk.v index b4f22c82..67bd9192 100644 --- a/rtl/mkGbeWrk.v +++ b/rtl/mkGbeWrk.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Wed Sep 19 14:36:33 EDT 2012 +// On Mon Sep 24 13:38:14 EDT 2012 // // // Ports: @@ -241,9 +241,9 @@ module mkGbeWrk(wciS0_Clk, WILL_FIRE_RL_wci_wslv_respF_incCtr; // inputs to muxes for submodule ports - reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1; - wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2, - MUX_wci_wslv_respF_q_1$write_1__VAL_2, + reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2; + wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1, + MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, @@ -251,8 +251,8 @@ module mkGbeWrk(wciS0_Clk, wire MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__VAL_2, - MUX_wci_wslv_respF_q_0$write_1__SEL_1, - MUX_wci_wslv_respF_q_1$write_1__SEL_1; + MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_2; // remaining internal signals reg [63 : 0] v__h3618, v__h3792, v__h3936; @@ -381,10 +381,10 @@ module mkGbeWrk(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; - assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_c_r == 2'd0 ; - assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_c_r == 2'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 = @@ -393,6 +393,10 @@ module mkGbeWrk(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = + (wci_wslv_respF_c_r == 2'd1) ? + MUX_wci_wslv_respF_q_0$write_1__VAL_2 : + wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 or WILL_FIRE_RL_wci_cfrd or @@ -400,24 +404,20 @@ module mkGbeWrk(wciS0_Clk, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wci_wslv_ctl_op_complete: - MUX_wci_wslv_respF_q_0$write_1__VAL_1 = + MUX_wci_wslv_respF_q_0$write_1__VAL_2 = MUX_wci_wslv_respF_x_wire$wset_1__VAL_1; WILL_FIRE_RL_wci_cfrd: - MUX_wci_wslv_respF_q_0$write_1__VAL_1 = + MUX_wci_wslv_respF_q_0$write_1__VAL_2 = MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; WILL_FIRE_RL_wci_cfwr: - MUX_wci_wslv_respF_q_0$write_1__VAL_1 = 34'h1C0DE4201; - default: MUX_wci_wslv_respF_q_0$write_1__VAL_1 = + MUX_wci_wslv_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_wslv_respF_q_0$write_1__VAL_2 = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_wslv_respF_q_0$write_1__VAL_2 = - (wci_wslv_respF_c_r == 2'd1) ? - MUX_wci_wslv_respF_q_0$write_1__VAL_1 : - wci_wslv_respF_q_1 ; - assign MUX_wci_wslv_respF_q_1$write_1__VAL_2 = + assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = (wci_wslv_respF_c_r == 2'd2) ? - MUX_wci_wslv_respF_q_0$write_1__VAL_1 : + MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; @@ -431,7 +431,7 @@ module mkGbeWrk(wciS0_Clk, wciS0_MAddr, wciS0_MData } ; assign wci_wslv_wciReq$whas = 1'd1 ; - assign wci_wslv_respF_x_wire$wget = MUX_wci_wslv_respF_q_0$write_1__VAL_1 ; + assign wci_wslv_respF_x_wire$wget = MUX_wci_wslv_respF_q_0$write_1__VAL_2 ; assign wci_wslv_respF_x_wire$whas = WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ; @@ -560,16 +560,16 @@ module mkGbeWrk(wciS0_Clk, WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_0 - always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_wslv_respF_both or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_wslv_respF_both or + MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - MUX_wci_wslv_respF_q_0$write_1__SEL_1: - wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; WILL_FIRE_RL_wci_wslv_respF_both: + wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; + MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; WILL_FIRE_RL_wci_wslv_respF_decCtr: wci_wslv_respF_q_0$D_IN = wci_wslv_respF_q_1; @@ -578,23 +578,23 @@ module mkGbeWrk(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = + WILL_FIRE_RL_wci_wslv_respF_both || WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_c_r == 2'd0 || - WILL_FIRE_RL_wci_wslv_respF_both || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or - MUX_wci_wslv_respF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_wslv_respF_both or - MUX_wci_wslv_respF_q_1$write_1__VAL_2 or + always@(WILL_FIRE_RL_wci_wslv_respF_both or + MUX_wci_wslv_respF_q_1$write_1__VAL_1 or + MUX_wci_wslv_respF_q_1$write_1__SEL_2 or + MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_wslv_respF_q_1$write_1__SEL_1: - wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; WILL_FIRE_RL_wci_wslv_respF_both: - wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_2; + wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; + MUX_wci_wslv_respF_q_1$write_1__SEL_2: + wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; WILL_FIRE_RL_wci_wslv_respF_decCtr: wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA; default: wci_wslv_respF_q_1$D_IN = @@ -602,9 +602,9 @@ module mkGbeWrk(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = + WILL_FIRE_RL_wci_wslv_respF_both || WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_c_r == 2'd1 || - WILL_FIRE_RL_wci_wslv_respF_both || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg diff --git a/rtl/mkIQADCWorker.v b/rtl/mkIQADCWorker.v index b8bafb4b..138a4fb9 100644 --- a/rtl/mkIQADCWorker.v +++ b/rtl/mkIQADCWorker.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Wed Sep 19 10:18:44 EDT 2012 +// On Mon Sep 24 13:38:48 EDT 2012 // // // Ports: @@ -1123,7 +1123,7 @@ module mkIQADCWorker(CLK_sys0_clk, y__h15134, y__h8736; wire [11 : 0] x_burstLength__h61311; - wire [10 : 0] adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255, + wire [10 : 0] adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240, x__h17225, x__h19509, x__h22936, @@ -1139,38 +1139,38 @@ module mkIQADCWorker(CLK_sys0_clk, adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d379, adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d390, adcCore_colGate_sampF_RDY_first__93_AND_NOT_ad_ETC___d750, - adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1303, + adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1304, adcCore_iseqFsm_abort_whas__69_AND_adcCore_ise_ETC___d941, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1248, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1250, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1251, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1252, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1253, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1254, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1260, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1267, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1234, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1235, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1236, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1237, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1238, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1239, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1261, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263, adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1344, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1241, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1242, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1243, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1244, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1245, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1246, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1247, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1265, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1266, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1304, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1231, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1232, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1233, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1250, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1258, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1259, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1305, adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1343, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1236, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1237, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1238, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1239, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1240, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1261, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1226, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1227, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1228, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1229, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1249, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1251, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1268, adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1218, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219, @@ -1180,14 +1180,14 @@ module mkIQADCWorker(CLK_sys0_clk, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1230, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1231, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1234, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1264, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1242, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1243, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1244, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1247, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1255, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1267, fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1342, wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d1097, z__h18156, @@ -1796,7 +1796,7 @@ module mkIQADCWorker(CLK_sys0_clk, x1_data__h14312 } ; assign MUX_adcCore_colGate_sampF$enq_1__VAL_3 = { 2'd0, - adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1303, + adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1304, 4'd15, d_data__h14708 } ; assign MUX_adcCore_colGate_syncMesg$write_1__VAL_1 = @@ -1804,7 +1804,7 @@ module mkIQADCWorker(CLK_sys0_clk, assign MUX_adcCore_colGate_timeMesg$write_1__VAL_1 = adcCore_colGate_timeMesg - 3'd1 ; assign MUX_adcCore_colGate_uprollCnt$write_1__VAL_2 = - adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1303 ? + adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1304 ? 16'd0 : adcCore_colGate_uprollCnt + 16'd1 ; assign MUX_adcCore_iseqFsm_jj_delay_count$write_1__VAL_1 = @@ -2560,23 +2560,23 @@ module mkIQADCWorker(CLK_sys0_clk, // register fcAdc_countNow assign fcAdc_countNow$D_IN = { fcAdc_grayCounter_rdCounter[17], - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1255, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1218, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1234, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1243, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1247, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1244, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1267, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1242, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248, + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224, fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1264, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1230, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1231, - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1231 ^ + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225 ^ fcAdc_grayCounter_rdCounter[0] } ; assign fcAdc_countNow$EN = fcAdc_pulseAction ; @@ -2991,16 +2991,16 @@ module mkIQADCWorker(CLK_sys0_clk, // submodule adcCore_sampF_memory assign adcCore_sampF_memory$ADDRA = - { adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1236, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1237, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1238, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1261, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1239, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1240, - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1240 ^ + { adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1227, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1226, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1228, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1268, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1249, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1251, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1229, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230, + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230 ^ adcCore_sampF_rWrPtr_rsCounter[0] } ; assign adcCore_sampF_memory$ADDRB = adcCore_sampF_pwDequeue$whas ? x__h22936[9:0] : x2__h22905 ; @@ -3186,124 +3186,124 @@ module mkIQADCWorker(CLK_sys0_clk, assign adcCore_colGate_sampF_RDY_first__93_AND_NOT_ad_ETC___d750 = adcCore_colGate_sampF$EMPTY_N && adcCore_sampF_rWrPtr_rsCounter != - { adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[10], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[10] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[9], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[9] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[8], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[8] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[7], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[7] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[6], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[6] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[5], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[5] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[4], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[4] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[3], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[3] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[2], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[2] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[1], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[1] ^ - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255[0] } ; - assign adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1303 = + { adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[10], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[10] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[9], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[9] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[8], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[8] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[7], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[7] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[6], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[6] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[5], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[5] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[4], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[4] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[3], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[3] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[2], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[2] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[1], + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[1] ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240[0] } ; + assign adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1304 = adcCore_colGate_uprollCnt == adcCore_maxBurstLengthR$dD_OUT - 16'd1 ; assign adcCore_iseqFsm_abort_whas__69_AND_adcCore_ise_ETC___d941 = (adcCore_iseqFsm_state_mkFSMstate == 4'd0 || adcCore_iseqFsm_state_mkFSMstate == 4'd10) && (!adcCore_iseqFsm_start_reg_1 || adcCore_iseqFsm_state_fired) ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1255 = + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1240 = x_dReadBin__h21322 + 11'd512 ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1248 = + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1234 = adcCore_sampF_rRdPtr_rdCounter[10] ^ adcCore_sampF_rRdPtr_rdCounter[9] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1248 ^ - adcCore_sampF_rRdPtr_rdCounter[8] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1250 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1251 ^ - adcCore_sampF_rRdPtr_rdCounter[6] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1251 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249 ^ - adcCore_sampF_rRdPtr_rdCounter[7] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1252 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1250 ^ + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1235 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263 ^ adcCore_sampF_rRdPtr_rdCounter[5] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1253 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1252 ^ + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1236 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1235 ^ adcCore_sampF_rRdPtr_rdCounter[4] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1254 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1253 ^ + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1237 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1236 ^ adcCore_sampF_rRdPtr_rdCounter[3] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1260 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1267 ^ - adcCore_sampF_rRdPtr_rdCounter[1] ; - assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1267 = - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1254 ^ + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1238 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1237 ^ adcCore_sampF_rRdPtr_rdCounter[2] ; + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1239 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1238 ^ + adcCore_sampF_rRdPtr_rdCounter[1] ; + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1261 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1234 ^ + adcCore_sampF_rRdPtr_rdCounter[8] ; + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1261 ^ + adcCore_sampF_rRdPtr_rdCounter[7] ; + assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263 = + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262 ^ + adcCore_sampF_rRdPtr_rdCounter[6] ; assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1344 = z__h20496 ^ adcCore_sampF_rRdPtr_rsCounter[10] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1241 = + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1231 = adcCore_sampF_rRdPtr_rsCounter[10] ^ adcCore_sampF_rRdPtr_rsCounter[9] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1242 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1241 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1232 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1231 ^ adcCore_sampF_rRdPtr_rsCounter[8] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1243 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1245 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1233 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260 ^ + adcCore_sampF_rRdPtr_rsCounter[1] ; + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1250 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254 ^ adcCore_sampF_rRdPtr_rsCounter[6] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1244 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1243 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1250 ^ adcCore_sampF_rRdPtr_rsCounter[5] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1245 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1242 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1232 ^ adcCore_sampF_rRdPtr_rsCounter[7] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1246 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1247 ^ - adcCore_sampF_rRdPtr_rsCounter[1] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1247 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1265 ^ - adcCore_sampF_rRdPtr_rsCounter[2] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1265 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1266 ^ - adcCore_sampF_rRdPtr_rsCounter[3] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1266 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1244 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1258 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253 ^ adcCore_sampF_rRdPtr_rsCounter[4] ; - assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1304 = - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1246 ^ + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1259 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1258 ^ + adcCore_sampF_rRdPtr_rsCounter[3] ; + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1259 ^ + adcCore_sampF_rRdPtr_rsCounter[2] ; + assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1305 = + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1233 ^ adcCore_sampF_rRdPtr_rsCounter[0] ; assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1343 = z__h18212 ^ adcCore_sampF_rWrPtr_rsCounter[10] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232 = - adcCore_sampF_rWrPtr_rsCounter[10] ^ - adcCore_sampF_rWrPtr_rsCounter[9] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232 ^ - adcCore_sampF_rWrPtr_rsCounter[8] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233 ^ + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1226 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1227 ^ adcCore_sampF_rWrPtr_rsCounter[7] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1236 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235 ^ + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1227 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256 ^ + adcCore_sampF_rWrPtr_rsCounter[8] ; + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1228 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1226 ^ adcCore_sampF_rWrPtr_rsCounter[6] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1237 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1236 ^ - adcCore_sampF_rWrPtr_rsCounter[5] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1238 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1237 ^ - adcCore_sampF_rWrPtr_rsCounter[4] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1239 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1261 ^ + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1229 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1251 ^ adcCore_sampF_rWrPtr_rsCounter[2] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1240 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1239 ^ + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1229 ^ adcCore_sampF_rWrPtr_rsCounter[1] ; - assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1261 = - adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1238 ^ + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1249 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1268 ^ + adcCore_sampF_rWrPtr_rsCounter[4] ; + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1251 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1249 ^ adcCore_sampF_rWrPtr_rsCounter[3] ; + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256 = + adcCore_sampF_rWrPtr_rsCounter[10] ^ + adcCore_sampF_rWrPtr_rsCounter[9] ; + assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1268 = + adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1228 ^ + adcCore_sampF_rWrPtr_rsCounter[5] ; assign adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919 = adcCore_spiI_reqF_head_wrapped == adcCore_spiI_reqF_tail_wrapped && @@ -3324,53 +3324,53 @@ module mkIQADCWorker(CLK_sys0_clk, assign d_data__h14708 = adcCore_averageD$dD_OUT ? avgDataBW__h14621 : adcCore_samp ; assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1218 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220 ^ + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1255 ^ fcAdc_grayCounter_rdCounter[15] ; assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219 = fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1218 ^ fcAdc_grayCounter_rdCounter[14] ; assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220 = - fcAdc_grayCounter_rdCounter[17] ^ - fcAdc_grayCounter_rdCounter[16] ; + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1247 ^ + fcAdc_grayCounter_rdCounter[11] ; assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1234 ^ - fcAdc_grayCounter_rdCounter[12] ; + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266 ^ + fcAdc_grayCounter_rdCounter[8] ; assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221 ^ - fcAdc_grayCounter_rdCounter[11] ; + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224 ^ + fcAdc_grayCounter_rdCounter[3] ; assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223 = fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222 ^ - fcAdc_grayCounter_rdCounter[10] ; + fcAdc_grayCounter_rdCounter[2] ; assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223 ^ - fcAdc_grayCounter_rdCounter[9] ; + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248 ^ + fcAdc_grayCounter_rdCounter[4] ; assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224 ^ - fcAdc_grayCounter_rdCounter[8] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225 ^ - fcAdc_grayCounter_rdCounter[7] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226 ^ - fcAdc_grayCounter_rdCounter[6] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227 ^ - fcAdc_grayCounter_rdCounter[5] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1230 ^ - fcAdc_grayCounter_rdCounter[2] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1230 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1264 ^ - fcAdc_grayCounter_rdCounter[3] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1231 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229 ^ + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223 ^ fcAdc_grayCounter_rdCounter[1] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1234 = + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1242 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1267 ^ + fcAdc_grayCounter_rdCounter[6] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1243 = fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219 ^ fcAdc_grayCounter_rdCounter[13] ; - assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1264 = - fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228 ^ - fcAdc_grayCounter_rdCounter[4] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1244 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220 ^ + fcAdc_grayCounter_rdCounter[10] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1247 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1243 ^ + fcAdc_grayCounter_rdCounter[12] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1248 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1242 ^ + fcAdc_grayCounter_rdCounter[5] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1255 = + fcAdc_grayCounter_rdCounter[17] ^ + fcAdc_grayCounter_rdCounter[16] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1244 ^ + fcAdc_grayCounter_rdCounter[9] ; + assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1267 = + fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221 ^ + fcAdc_grayCounter_rdCounter[7] ; assign fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1342 = z__h7456 ^ fcAdc_grayCounter_rsCounter[17] ; assign rdat__h62664 = @@ -3387,16 +3387,16 @@ module mkIQADCWorker(CLK_sys0_clk, wci_wslv_reqF$D_OUT[43:42] != 2'b01 || adcCore_reqF$FULL_N) ; assign wti_nowReq_BITS_63_TO_0__q1 = wti_nowReq[63:0] ; assign x2__h22905 = - { adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1241, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1242, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1245, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1243, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1244, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1266, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1265, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1247, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1246, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1304 } ; + { adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1231, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1232, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1250, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1258, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1259, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1233, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1305 } ; assign x__h14971 = x__h14981 + y__h15132 ; assign x__h14981 = adcCore_colGate_avgEven + y__h15134 ; assign x__h15047 = y__h15134 + y__h15132 ; @@ -3418,29 +3418,29 @@ module mkIQADCWorker(CLK_sys0_clk, adcCore_sampF_memory$DOB[36] ? 12'd1 : 12'd4095 ; assign x_dReadBin__h21322 = { adcCore_sampF_rRdPtr_rdCounter[10], - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1248, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1251, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1250, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1252, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1253, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1254, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1267, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1260, - adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1260 ^ + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1234, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1261, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1235, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1236, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1237, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1238, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1239, + adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1239 ^ adcCore_sampF_rRdPtr_rdCounter[0] } ; assign x_sReadBin__h21319 = { adcCore_sampF_rRdPtr_rsCounter[10], - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1241, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1242, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1245, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1243, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1244, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1266, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1265, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1247, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1246, - adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1304 } ; + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1231, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1232, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1254, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1250, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1253, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1258, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1259, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1233, + adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1305 } ; assign y__h15132 = { 2'd0, adcCore_samp[15:0] } ; assign y__h15134 = { 2'd0, adcCore_samp[31:16] } ; assign y__h18112 = ~x__h17225 ; diff --git a/rtl/mkLedN210.v b/rtl/mkLedN210.v index d94406ff..736392af 100644 --- a/rtl/mkLedN210.v +++ b/rtl/mkLedN210.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Wed Sep 19 10:17:44 EDT 2012 +// On Mon Sep 24 13:37:41 EDT 2012 // // // Ports: diff --git a/rtl/mkOCCP.v b/rtl/mkOCCP.v index 95997f13..612e2466 100644 --- a/rtl/mkOCCP.v +++ b/rtl/mkOCCP.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:46:26 EDT 2012 +// On Mon Sep 24 13:39:57 EDT 2012 // // // Ports: @@ -4581,7 +4581,7 @@ module mkOCCP(pciDevice, IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4969, IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4978, IF_cpReq_363_BITS_37_TO_36_858_EQ_2_859_THEN_c_ETC___d4988, - IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5437, + IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5440, NOT_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_649_ETC___d2712, NOT_cpReq_363_BITS_64_TO_62_364_EQ_0_852_857_A_ETC___d5044, NOT_cpReq_363_BITS_64_TO_62_364_EQ_3_863_856_A_ETC___d3947, @@ -4681,23 +4681,23 @@ module mkOCCP(pciDevice, cpReq_363_BIT_36_910_AND_NOT_wci_busy_9_496_45_ETC___d3474, timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d61, timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d70, - timeServ_refFromRise_3_ULE_199800000___d5431, - timeServ_refFromRise_3_ULT_200200000___d5850, - wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861, - wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862, - wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863, - wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864, - wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865, - wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852, - wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851, - wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853, - wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854, - wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855, - wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856, - wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857, - wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858, - wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859, - wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860, + timeServ_refFromRise_3_ULE_199800000___d5430, + timeServ_refFromRise_3_ULT_200200000___d5853, + wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864, + wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865, + wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866, + wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867, + wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868, + wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855, + wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854, + wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856, + wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857, + wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858, + wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859, + wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860, + wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861, + wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862, + wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863, wci_wReset_n_10_616_AND_NOT_wci_busy_10_636_51_ETC___d3515, wci_wReset_n_11_756_AND_NOT_wci_busy_11_776_57_ETC___d3577, wci_wReset_n_12_896_AND_NOT_wci_busy_12_916_63_ETC___d3639, @@ -8218,7 +8218,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy assign WILL_FIRE_RL_wci_wrkBusy = ((wci_wciResponse$wget[33:32] == 2'd0) ? - wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 || + wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 || wci_respF$FULL_N : wci_respF$FULL_N) && wci_busy ; @@ -8242,7 +8242,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_1 assign WILL_FIRE_RL_wci_wrkBusy_1 = ((wci_wciResponse_1$wget[33:32] == 2'd0) ? - wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 || + wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 || wci_respF_1$FULL_N : wci_respF_1$FULL_N) && wci_busy_1 ; @@ -8266,7 +8266,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_2 assign WILL_FIRE_RL_wci_wrkBusy_2 = ((wci_wciResponse_2$wget[33:32] == 2'd0) ? - wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 || + wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 || wci_respF_2$FULL_N : wci_respF_2$FULL_N) && wci_busy_2 ; @@ -8290,7 +8290,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_3 assign WILL_FIRE_RL_wci_wrkBusy_3 = ((wci_wciResponse_3$wget[33:32] == 2'd0) ? - wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 || + wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 || wci_respF_3$FULL_N : wci_respF_3$FULL_N) && wci_busy_3 ; @@ -8314,7 +8314,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_4 assign WILL_FIRE_RL_wci_wrkBusy_4 = ((wci_wciResponse_4$wget[33:32] == 2'd0) ? - wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 || + wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 || wci_respF_4$FULL_N : wci_respF_4$FULL_N) && wci_busy_4 ; @@ -8338,7 +8338,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_5 assign WILL_FIRE_RL_wci_wrkBusy_5 = ((wci_wciResponse_5$wget[33:32] == 2'd0) ? - wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 || + wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 || wci_respF_5$FULL_N : wci_respF_5$FULL_N) && wci_busy_5 ; @@ -8362,7 +8362,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_6 assign WILL_FIRE_RL_wci_wrkBusy_6 = ((wci_wciResponse_6$wget[33:32] == 2'd0) ? - wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 || + wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 || wci_respF_6$FULL_N : wci_respF_6$FULL_N) && wci_busy_6 ; @@ -8386,7 +8386,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_7 assign WILL_FIRE_RL_wci_wrkBusy_7 = ((wci_wciResponse_7$wget[33:32] == 2'd0) ? - wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 || + wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 || wci_respF_7$FULL_N : wci_respF_7$FULL_N) && wci_busy_7 ; @@ -8410,7 +8410,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_8 assign WILL_FIRE_RL_wci_wrkBusy_8 = ((wci_wciResponse_8$wget[33:32] == 2'd0) ? - wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 || + wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 || wci_respF_8$FULL_N : wci_respF_8$FULL_N) && wci_busy_8 ; @@ -8434,7 +8434,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_9 assign WILL_FIRE_RL_wci_wrkBusy_9 = ((wci_wciResponse_9$wget[33:32] == 2'd0) ? - wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 || + wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 || wci_respF_9$FULL_N : wci_respF_9$FULL_N) && wci_busy_9 ; @@ -8458,7 +8458,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_10 assign WILL_FIRE_RL_wci_wrkBusy_10 = ((wci_wciResponse_10$wget[33:32] == 2'd0) ? - wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 || + wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 || wci_respF_10$FULL_N : wci_respF_10$FULL_N) && wci_busy_10 ; @@ -8482,7 +8482,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_11 assign WILL_FIRE_RL_wci_wrkBusy_11 = ((wci_wciResponse_11$wget[33:32] == 2'd0) ? - wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 || + wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 || wci_respF_11$FULL_N : wci_respF_11$FULL_N) && wci_busy_11 ; @@ -8506,7 +8506,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_12 assign WILL_FIRE_RL_wci_wrkBusy_12 = ((wci_wciResponse_12$wget[33:32] == 2'd0) ? - wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 || + wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 || wci_respF_12$FULL_N : wci_respF_12$FULL_N) && wci_busy_12 ; @@ -8530,7 +8530,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_13 assign WILL_FIRE_RL_wci_wrkBusy_13 = ((wci_wciResponse_13$wget[33:32] == 2'd0) ? - wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 || + wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 || wci_respF_13$FULL_N : wci_respF_13$FULL_N) && wci_busy_13 ; @@ -8554,7 +8554,7 @@ module mkOCCP(pciDevice, // rule RL_wci_wrkBusy_14 assign WILL_FIRE_RL_wci_wrkBusy_14 = ((wci_wciResponse_14$wget[33:32] == 2'd0) ? - wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 || + wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 || wci_respF_14$FULL_N : wci_respF_14$FULL_N) && wci_busy_14 ; @@ -8578,7 +8578,7 @@ module mkOCCP(pciDevice, // inputs to muxes for submodule ports assign MUX_wci_busy$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 || + (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 || wci_wciResponse$wget[33:32] != 2'd0) ; assign MUX_wci_busy$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T || @@ -8586,7 +8586,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T ; assign MUX_wci_busy_1$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 || + (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 || wci_wciResponse_1$wget[33:32] != 2'd0) ; assign MUX_wci_busy_1$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T || @@ -8594,7 +8594,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T ; assign MUX_wci_busy_10$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 || + (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 || wci_wciResponse_10$wget[33:32] != 2'd0) ; assign MUX_wci_busy_10$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8602,7 +8602,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_11$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 || + (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 || wci_wciResponse_11$wget[33:32] != 2'd0) ; assign MUX_wci_busy_11$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8610,7 +8610,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_12$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 || + (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 || wci_wciResponse_12$wget[33:32] != 2'd0) ; assign MUX_wci_busy_12$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8618,7 +8618,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_13$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 || + (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 || wci_wciResponse_13$wget[33:32] != 2'd0) ; assign MUX_wci_busy_13$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8626,7 +8626,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_14$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 || + (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 || wci_wciResponse_14$wget[33:32] != 2'd0) ; assign MUX_wci_busy_14$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8634,7 +8634,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_2$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 || + (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 || wci_wciResponse_2$wget[33:32] != 2'd0) ; assign MUX_wci_busy_2$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T || @@ -8642,7 +8642,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T ; assign MUX_wci_busy_3$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 || + (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 || wci_wciResponse_3$wget[33:32] != 2'd0) ; assign MUX_wci_busy_3$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T || @@ -8650,7 +8650,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T ; assign MUX_wci_busy_4$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 || + (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 || wci_wciResponse_4$wget[33:32] != 2'd0) ; assign MUX_wci_busy_4$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8658,7 +8658,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T ; assign MUX_wci_busy_5$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 || + (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 || wci_wciResponse_5$wget[33:32] != 2'd0) ; assign MUX_wci_busy_5$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8666,7 +8666,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_6$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 || + (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 || wci_wciResponse_6$wget[33:32] != 2'd0) ; assign MUX_wci_busy_6$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8674,7 +8674,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_7$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 || + (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 || wci_wciResponse_7$wget[33:32] != 2'd0) ; assign MUX_wci_busy_7$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8682,7 +8682,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_8$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 || + (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 || wci_wciResponse_8$wget[33:32] != 2'd0) ; assign MUX_wci_busy_8$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -8690,7 +8690,7 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T ; assign MUX_wci_busy_9$write_1__SEL_1 = WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 || + (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 || wci_wciResponse_9$wget[33:32] != 2'd0) ; assign MUX_wci_busy_9$write_1__SEL_2 = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || @@ -10519,91 +10519,91 @@ module mkOCCP(pciDevice, assign MUX_wci_respF_9$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_9 } ; assign MUX_wci_respTimr$write_1__VAL_2 = (wci_wciResponse$wget[33:32] == 2'd0) ? - (wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 ? + (wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 ? x__h11494 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_1$write_1__VAL_2 = (wci_wciResponse_1$wget[33:32] == 2'd0) ? - (wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 ? + (wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 ? x__h15799 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_10$write_1__VAL_2 = (wci_wciResponse_10$wget[33:32] == 2'd0) ? - (wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 ? + (wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 ? x__h54517 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_11$write_1__VAL_2 = (wci_wciResponse_11$wget[33:32] == 2'd0) ? - (wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 ? + (wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 ? x__h58819 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_12$write_1__VAL_2 = (wci_wciResponse_12$wget[33:32] == 2'd0) ? - (wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 ? + (wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 ? x__h63121 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_13$write_1__VAL_2 = (wci_wciResponse_13$wget[33:32] == 2'd0) ? - (wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 ? + (wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 ? x__h67423 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_14$write_1__VAL_2 = (wci_wciResponse_14$wget[33:32] == 2'd0) ? - (wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 ? + (wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 ? x__h71725 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_2$write_1__VAL_2 = (wci_wciResponse_2$wget[33:32] == 2'd0) ? - (wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 ? + (wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 ? x__h20101 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_3$write_1__VAL_2 = (wci_wciResponse_3$wget[33:32] == 2'd0) ? - (wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 ? + (wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 ? x__h24403 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_4$write_1__VAL_2 = (wci_wciResponse_4$wget[33:32] == 2'd0) ? - (wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 ? + (wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 ? x__h28705 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_5$write_1__VAL_2 = (wci_wciResponse_5$wget[33:32] == 2'd0) ? - (wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 ? + (wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 ? x__h33007 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_6$write_1__VAL_2 = (wci_wciResponse_6$wget[33:32] == 2'd0) ? - (wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 ? + (wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 ? x__h37309 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_7$write_1__VAL_2 = (wci_wciResponse_7$wget[33:32] == 2'd0) ? - (wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 ? + (wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 ? x__h41611 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_8$write_1__VAL_2 = (wci_wciResponse_8$wget[33:32] == 2'd0) ? - (wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 ? + (wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 ? x__h45913 : 32'd0) : 32'd0 ; assign MUX_wci_respTimr_9$write_1__VAL_2 = (wci_wciResponse_9$wget[33:32] == 2'd0) ? - (wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 ? + (wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 ? x__h50215 : 32'd0) : 32'd0 ; @@ -12024,8 +12024,8 @@ module mkOCCP(pciDevice, timeServ_fracSeconds - timeServ_lastSecond ; assign timeServ_delSecond$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5431 && - timeServ_refFromRise_3_ULT_200200000___d5850 ; + !timeServ_refFromRise_3_ULE_199800000___d5430 && + timeServ_refFromRise_3_ULT_200200000___d5853 ; // register timeServ_fracInc assign timeServ_fracInc$D_IN = timeServ_fracInc + x__h4160 ; @@ -12054,8 +12054,8 @@ module mkOCCP(pciDevice, assign timeServ_lastSecond$D_IN = timeServ_fracSeconds ; assign timeServ_lastSecond$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5431 && - timeServ_refFromRise_3_ULT_200200000___d5850 ; + !timeServ_refFromRise_3_ULE_199800000___d5430 && + timeServ_refFromRise_3_ULT_200200000___d5853 ; // register timeServ_now assign timeServ_now$D_IN = @@ -12108,8 +12108,8 @@ module mkOCCP(pciDevice, // register timeServ_ppsOK assign timeServ_ppsOK$D_IN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5431 && - timeServ_refFromRise_3_ULT_200200000___d5850 || + !timeServ_refFromRise_3_ULE_199800000___d5430 && + timeServ_refFromRise_3_ULT_200200000___d5853 || timeServ_ppsOK && !timeServ_ppsLost ; assign timeServ_ppsOK$EN = 1'd1 ; @@ -12121,16 +12121,16 @@ module mkOCCP(pciDevice, assign timeServ_refFreeSamp$D_IN = timeServ_refFreeCount ; assign timeServ_refFreeSamp$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5431 && - timeServ_refFromRise_3_ULT_200200000___d5850 ; + !timeServ_refFromRise_3_ULE_199800000___d5430 && + timeServ_refFromRise_3_ULT_200200000___d5853 ; // register timeServ_refFreeSpan assign timeServ_refFreeSpan$D_IN = timeServ_refFreeCount - timeServ_refFreeSamp ; assign timeServ_refFreeSpan$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5431 && - timeServ_refFromRise_3_ULT_200200000___d5850 ; + !timeServ_refFromRise_3_ULE_199800000___d5430 && + timeServ_refFromRise_3_ULT_200200000___d5853 ; // register timeServ_refFromRise assign timeServ_refFromRise$D_IN = @@ -12141,7 +12141,7 @@ module mkOCCP(pciDevice, // register timeServ_refPerCount assign timeServ_refPerCount$D_IN = - IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5437 ? + IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5440 ? 28'd0 : timeServ_refPerCount + 28'd1 ; assign timeServ_refPerCount$EN = 1'd1 ; @@ -12153,7 +12153,7 @@ module mkOCCP(pciDevice, x__h4453 ; assign timeServ_refSecCount$EN = timeServ_setRefF$dEMPTY_N || - IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5437 ; + IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5440 ; // register timeServ_rplTimeControl assign timeServ_rplTimeControl$D_IN = cpReq[32:28] ; @@ -12182,7 +12182,7 @@ module mkOCCP(pciDevice, assign wci_busy$D_IN = !MUX_wci_busy$write_1__SEL_1 ; assign wci_busy$EN = WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 || + (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 || wci_wciResponse$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || @@ -12192,7 +12192,7 @@ module mkOCCP(pciDevice, assign wci_busy_1$D_IN = !MUX_wci_busy_1$write_1__SEL_1 ; assign wci_busy_1$EN = WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 || + (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 || wci_wciResponse_1$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || @@ -12202,7 +12202,7 @@ module mkOCCP(pciDevice, assign wci_busy_10$D_IN = !MUX_wci_busy_10$write_1__SEL_1 ; assign wci_busy_10$EN = WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 || + (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 || wci_wciResponse_10$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12212,7 +12212,7 @@ module mkOCCP(pciDevice, assign wci_busy_11$D_IN = !MUX_wci_busy_11$write_1__SEL_1 ; assign wci_busy_11$EN = WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 || + (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 || wci_wciResponse_11$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12222,7 +12222,7 @@ module mkOCCP(pciDevice, assign wci_busy_12$D_IN = !MUX_wci_busy_12$write_1__SEL_1 ; assign wci_busy_12$EN = WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 || + (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 || wci_wciResponse_12$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12232,7 +12232,7 @@ module mkOCCP(pciDevice, assign wci_busy_13$D_IN = !MUX_wci_busy_13$write_1__SEL_1 ; assign wci_busy_13$EN = WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 || + (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 || wci_wciResponse_13$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12242,7 +12242,7 @@ module mkOCCP(pciDevice, assign wci_busy_14$D_IN = !MUX_wci_busy_14$write_1__SEL_1 ; assign wci_busy_14$EN = WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 || + (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 || wci_wciResponse_14$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12252,7 +12252,7 @@ module mkOCCP(pciDevice, assign wci_busy_2$D_IN = !MUX_wci_busy_2$write_1__SEL_1 ; assign wci_busy_2$EN = WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 || + (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 || wci_wciResponse_2$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || @@ -12262,7 +12262,7 @@ module mkOCCP(pciDevice, assign wci_busy_3$D_IN = !MUX_wci_busy_3$write_1__SEL_1 ; assign wci_busy_3$EN = WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 || + (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 || wci_wciResponse_3$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || @@ -12272,7 +12272,7 @@ module mkOCCP(pciDevice, assign wci_busy_4$D_IN = !MUX_wci_busy_4$write_1__SEL_1 ; assign wci_busy_4$EN = WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 || + (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 || wci_wciResponse_4$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || @@ -12282,7 +12282,7 @@ module mkOCCP(pciDevice, assign wci_busy_5$D_IN = !MUX_wci_busy_5$write_1__SEL_1 ; assign wci_busy_5$EN = WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 || + (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 || wci_wciResponse_5$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12292,7 +12292,7 @@ module mkOCCP(pciDevice, assign wci_busy_6$D_IN = !MUX_wci_busy_6$write_1__SEL_1 ; assign wci_busy_6$EN = WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 || + (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 || wci_wciResponse_6$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12302,7 +12302,7 @@ module mkOCCP(pciDevice, assign wci_busy_7$D_IN = !MUX_wci_busy_7$write_1__SEL_1 ; assign wci_busy_7$EN = WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 || + (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 || wci_wciResponse_7$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12312,7 +12312,7 @@ module mkOCCP(pciDevice, assign wci_busy_8$D_IN = !MUX_wci_busy_8$write_1__SEL_1 ; assign wci_busy_8$EN = WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 || + (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 || wci_wciResponse_8$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -12322,7 +12322,7 @@ module mkOCCP(pciDevice, assign wci_busy_9$D_IN = !MUX_wci_busy_9$write_1__SEL_1 ; assign wci_busy_9$EN = WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 || + (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 || wci_wciResponse_9$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || @@ -14214,7 +14214,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct$D_IN = wci_reqF_c_r ; assign wci_respTimrAct$EN = WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 || + (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 || wci_wciResponse$wget[33:32] != 2'd0) || wci_reqF_c_r ; @@ -14222,7 +14222,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_1$D_IN = wci_reqF_1_c_r ; assign wci_respTimrAct_1$EN = WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 || + (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 || wci_wciResponse_1$wget[33:32] != 2'd0) || wci_reqF_1_c_r ; @@ -14230,7 +14230,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_10$D_IN = wci_reqF_10_c_r ; assign wci_respTimrAct_10$EN = WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 || + (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 || wci_wciResponse_10$wget[33:32] != 2'd0) || wci_reqF_10_c_r ; @@ -14238,7 +14238,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_11$D_IN = wci_reqF_11_c_r ; assign wci_respTimrAct_11$EN = WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 || + (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 || wci_wciResponse_11$wget[33:32] != 2'd0) || wci_reqF_11_c_r ; @@ -14246,7 +14246,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_12$D_IN = wci_reqF_12_c_r ; assign wci_respTimrAct_12$EN = WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 || + (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 || wci_wciResponse_12$wget[33:32] != 2'd0) || wci_reqF_12_c_r ; @@ -14254,7 +14254,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_13$D_IN = wci_reqF_13_c_r ; assign wci_respTimrAct_13$EN = WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 || + (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 || wci_wciResponse_13$wget[33:32] != 2'd0) || wci_reqF_13_c_r ; @@ -14262,7 +14262,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_14$D_IN = wci_reqF_14_c_r ; assign wci_respTimrAct_14$EN = WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 || + (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 || wci_wciResponse_14$wget[33:32] != 2'd0) || wci_reqF_14_c_r ; @@ -14270,7 +14270,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_2$D_IN = wci_reqF_2_c_r ; assign wci_respTimrAct_2$EN = WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 || + (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 || wci_wciResponse_2$wget[33:32] != 2'd0) || wci_reqF_2_c_r ; @@ -14278,7 +14278,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_3$D_IN = wci_reqF_3_c_r ; assign wci_respTimrAct_3$EN = WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 || + (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 || wci_wciResponse_3$wget[33:32] != 2'd0) || wci_reqF_3_c_r ; @@ -14286,7 +14286,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_4$D_IN = wci_reqF_4_c_r ; assign wci_respTimrAct_4$EN = WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 || + (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 || wci_wciResponse_4$wget[33:32] != 2'd0) || wci_reqF_4_c_r ; @@ -14294,7 +14294,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_5$D_IN = wci_reqF_5_c_r ; assign wci_respTimrAct_5$EN = WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 || + (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 || wci_wciResponse_5$wget[33:32] != 2'd0) || wci_reqF_5_c_r ; @@ -14302,7 +14302,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_6$D_IN = wci_reqF_6_c_r ; assign wci_respTimrAct_6$EN = WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 || + (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 || wci_wciResponse_6$wget[33:32] != 2'd0) || wci_reqF_6_c_r ; @@ -14310,7 +14310,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_7$D_IN = wci_reqF_7_c_r ; assign wci_respTimrAct_7$EN = WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 || + (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 || wci_wciResponse_7$wget[33:32] != 2'd0) || wci_reqF_7_c_r ; @@ -14318,7 +14318,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_8$D_IN = wci_reqF_8_c_r ; assign wci_respTimrAct_8$EN = WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 || + (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 || wci_wciResponse_8$wget[33:32] != 2'd0) || wci_reqF_8_c_r ; @@ -14326,7 +14326,7 @@ module mkOCCP(pciDevice, assign wci_respTimrAct_9$D_IN = wci_reqF_9_c_r ; assign wci_respTimrAct_9$EN = WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 || + (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 || wci_wciResponse_9$wget[33:32] != 2'd0) || wci_reqF_9_c_r ; @@ -15431,7 +15431,7 @@ module mkOCCP(pciDevice, // submodule cpReqF assign cpReqF$D_IN = server_request_put ; assign cpReqF$ENQ = EN_server_request_put ; - assign cpReqF$DEQ = WILL_FIRE_RL_reqRcv ; + assign cpReqF$DEQ = cpReqF$EMPTY_N && cpReq[64:62] == 3'd0 ; assign cpReqF$CLR = 1'b0 ; // submodule cpRespF @@ -15589,7 +15589,7 @@ module mkOCCP(pciDevice, end assign wci_respF$ENQ = WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 || + (!wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 || wci_wciResponse$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T || @@ -15643,7 +15643,7 @@ module mkOCCP(pciDevice, end assign wci_respF_1$ENQ = WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 || + (!wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 || wci_wciResponse_1$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T || @@ -15698,7 +15698,7 @@ module mkOCCP(pciDevice, end assign wci_respF_10$ENQ = WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 || + (!wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 || wci_wciResponse_10$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -15753,7 +15753,7 @@ module mkOCCP(pciDevice, end assign wci_respF_11$ENQ = WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 || + (!wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 || wci_wciResponse_11$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -15808,7 +15808,7 @@ module mkOCCP(pciDevice, end assign wci_respF_12$ENQ = WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 || + (!wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 || wci_wciResponse_12$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -15863,7 +15863,7 @@ module mkOCCP(pciDevice, end assign wci_respF_13$ENQ = WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 || + (!wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 || wci_wciResponse_13$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -15918,7 +15918,7 @@ module mkOCCP(pciDevice, end assign wci_respF_14$ENQ = WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 || + (!wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 || wci_wciResponse_14$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -15973,7 +15973,7 @@ module mkOCCP(pciDevice, end assign wci_respF_2$ENQ = WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 || + (!wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 || wci_wciResponse_2$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T || @@ -16028,7 +16028,7 @@ module mkOCCP(pciDevice, end assign wci_respF_3$ENQ = WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 || + (!wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 || wci_wciResponse_3$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16083,7 +16083,7 @@ module mkOCCP(pciDevice, end assign wci_respF_4$ENQ = WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 || + (!wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 || wci_wciResponse_4$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16138,7 +16138,7 @@ module mkOCCP(pciDevice, end assign wci_respF_5$ENQ = WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 || + (!wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 || wci_wciResponse_5$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16193,7 +16193,7 @@ module mkOCCP(pciDevice, end assign wci_respF_6$ENQ = WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 || + (!wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 || wci_wciResponse_6$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16248,7 +16248,7 @@ module mkOCCP(pciDevice, end assign wci_respF_7$ENQ = WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 || + (!wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 || wci_wciResponse_7$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16303,7 +16303,7 @@ module mkOCCP(pciDevice, end assign wci_respF_8$ENQ = WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 || + (!wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 || wci_wciResponse_8$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16358,7 +16358,7 @@ module mkOCCP(pciDevice, end assign wci_respF_9$ENQ = WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 || + (!wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 || wci_wciResponse_9$wget[33:32] != 2'd0) || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || @@ -16653,7 +16653,7 @@ module mkOCCP(pciDevice, !wci_busy_14 && wci_respF_14$FULL_N && !dispatched ; - assign IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5437 = + assign IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d5440 = timeServ_ppsOK ? timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD : timeServ_delSec != timeServ_fracSeconds[49:48] ; @@ -17234,18 +17234,18 @@ module mkOCCP(pciDevice, (rom_serverAdapter_outData_deqCalled$whas ? 3'd7 : 3'd0) ; assign timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d61 = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - (timeServ_refFromRise_3_ULE_199800000___d5431 || - !timeServ_refFromRise_3_ULT_200200000___d5850) || + (timeServ_refFromRise_3_ULE_199800000___d5430 || + !timeServ_refFromRise_3_ULT_200200000___d5853) || timeServ_refFromRise > 28'd200200000 ; assign timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d70 = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d5431 && - timeServ_refFromRise_3_ULT_200200000___d5850 && + !timeServ_refFromRise_3_ULE_199800000___d5430 && + timeServ_refFromRise_3_ULT_200200000___d5853 && timeServ_ppsOK && !timeServ_disableServo$dD_OUT ; - assign timeServ_refFromRise_3_ULE_199800000___d5431 = + assign timeServ_refFromRise_3_ULE_199800000___d5430 = timeServ_refFromRise <= 28'd199800000 ; - assign timeServ_refFromRise_3_ULT_200200000___d5850 = + assign timeServ_refFromRise_3_ULT_200200000___d5853 = timeServ_refFromRise < 28'd200200000 ; assign toCount__h11335 = 32'd1 << wci_wTimeout ; assign toCount__h15643 = 32'd1 << wci_wTimeout_1 ; @@ -17277,35 +17277,35 @@ module mkOCCP(pciDevice, assign wciAddr__h76749 = { wci_pageWindow_12, cpReq[23:4] } ; assign wciAddr__h76815 = { wci_pageWindow_13, cpReq[23:4] } ; assign wciAddr__h76881 = { wci_pageWindow_14, cpReq[23:4] } ; - assign wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 = + assign wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 = wci_respTimr_10 < toCount__h54361 ; - assign wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 = + assign wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 = wci_respTimr_11 < toCount__h58663 ; - assign wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 = + assign wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 = wci_respTimr_12 < toCount__h62965 ; - assign wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 = + assign wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 = wci_respTimr_13 < toCount__h67267 ; - assign wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 = + assign wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 = wci_respTimr_14 < toCount__h71569 ; - assign wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 = + assign wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 = wci_respTimr_1 < toCount__h15643 ; - assign wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 = + assign wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 = wci_respTimr < toCount__h11335 ; - assign wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 = + assign wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 = wci_respTimr_2 < toCount__h19945 ; - assign wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 = + assign wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 = wci_respTimr_3 < toCount__h24247 ; - assign wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 = + assign wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 = wci_respTimr_4 < toCount__h28549 ; - assign wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 = + assign wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 = wci_respTimr_5 < toCount__h32851 ; - assign wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 = + assign wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 = wci_respTimr_6 < toCount__h37153 ; - assign wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 = + assign wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 = wci_respTimr_7 < toCount__h41455 ; - assign wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 = + assign wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 = wci_respTimr_8 < toCount__h45757 ; - assign wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 = + assign wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 = wci_respTimr_9 < toCount__h50059 ; assign wci_wReset_n_10_616_AND_NOT_wci_busy_10_636_51_ETC___d3515 = wci_wReset_n_10 && !wci_busy_10 && !wci_reqF_10_c_r && @@ -17344,77 +17344,77 @@ module mkOCCP(pciDevice, wci_wReset_n_9 && !wci_busy_9 && !wci_reqF_9_c_r && !dispatched ; assign wci_wciResponse_10_wget__623_BITS_33_TO_32_624_ETC___d1652 = wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && (wci_reqPend_10 == 2'd1 || wci_reqPend_10 == 2'd2 || wci_reqPend_10 == 2'd3) ; assign wci_wciResponse_11_wget__763_BITS_33_TO_32_764_ETC___d1792 = wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && (wci_reqPend_11 == 2'd1 || wci_reqPend_11 == 2'd2 || wci_reqPend_11 == 2'd3) ; assign wci_wciResponse_12_wget__903_BITS_33_TO_32_904_ETC___d1932 = wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && (wci_reqPend_12 == 2'd1 || wci_reqPend_12 == 2'd2 || wci_reqPend_12 == 2'd3) ; assign wci_wciResponse_13_wget__043_BITS_33_TO_32_044_ETC___d2072 = wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && (wci_reqPend_13 == 2'd1 || wci_reqPend_13 == 2'd2 || wci_reqPend_13 == 2'd3) ; assign wci_wciResponse_14_wget__183_BITS_33_TO_32_184_ETC___d2212 = wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && (wci_reqPend_14 == 2'd1 || wci_reqPend_14 == 2'd2 || wci_reqPend_14 == 2'd3) ; assign wci_wciResponse_1_wget__63_BITS_33_TO_32_64_EQ_ETC___d392 = wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && (wci_reqPend_1 == 2'd1 || wci_reqPend_1 == 2'd2 || wci_reqPend_1 == 2'd3) ; assign wci_wciResponse_2_wget__03_BITS_33_TO_32_04_EQ_ETC___d532 = wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && (wci_reqPend_2 == 2'd1 || wci_reqPend_2 == 2'd2 || wci_reqPend_2 == 2'd3) ; assign wci_wciResponse_3_wget__43_BITS_33_TO_32_44_EQ_ETC___d672 = wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && (wci_reqPend_3 == 2'd1 || wci_reqPend_3 == 2'd2 || wci_reqPend_3 == 2'd3) ; assign wci_wciResponse_4_wget__83_BITS_33_TO_32_84_EQ_ETC___d812 = wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && (wci_reqPend_4 == 2'd1 || wci_reqPend_4 == 2'd2 || wci_reqPend_4 == 2'd3) ; assign wci_wciResponse_5_wget__23_BITS_33_TO_32_24_EQ_ETC___d952 = wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && (wci_reqPend_5 == 2'd1 || wci_reqPend_5 == 2'd2 || wci_reqPend_5 == 2'd3) ; assign wci_wciResponse_6_wget__063_BITS_33_TO_32_064__ETC___d1092 = wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && (wci_reqPend_6 == 2'd1 || wci_reqPend_6 == 2'd2 || wci_reqPend_6 == 2'd3) ; assign wci_wciResponse_7_wget__203_BITS_33_TO_32_204__ETC___d1232 = wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && (wci_reqPend_7 == 2'd1 || wci_reqPend_7 == 2'd2 || wci_reqPend_7 == 2'd3) ; assign wci_wciResponse_8_wget__343_BITS_33_TO_32_344__ETC___d1372 = wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && (wci_reqPend_8 == 2'd1 || wci_reqPend_8 == 2'd2 || wci_reqPend_8 == 2'd3) ; assign wci_wciResponse_9_wget__483_BITS_33_TO_32_484__ETC___d1512 = wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && (wci_reqPend_9 == 2'd1 || wci_reqPend_9 == 2'd2 || wci_reqPend_9 == 2'd3) ; assign wci_wciResponse_wget__23_BITS_33_TO_32_24_EQ_0_ETC___d252 = wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && (wci_reqPend == 2'd1 || wci_reqPend == 2'd2 || wci_reqPend == 2'd3) ; assign wn___1__h75213 = cpReq[27:24] - 4'd1 ; @@ -23796,7 +23796,7 @@ module mkOCCP(pciDevice, cpReq[3:0]); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && wci_reqPend == 2'd1) begin v__h11627 = $time; @@ -23804,12 +23804,12 @@ module mkOCCP(pciDevice, end if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && wci_reqPend == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h11627); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && wci_reqPend == 2'd2) begin v__h11717 = $time; @@ -23817,12 +23817,12 @@ module mkOCCP(pciDevice, end if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && wci_reqPend == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h11717); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && wci_reqPend == 2'd3) begin v__h11806 = $time; @@ -23830,7 +23830,7 @@ module mkOCCP(pciDevice, end if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5851 && + !wci_respTimr_28_ULT_1_SL_wci_wTimeout_29_30___d5854 && wci_reqPend == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h11806); if (RST_N) @@ -23902,7 +23902,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && wci_reqPend_1 == 2'd1) begin v__h15929 = $time; @@ -23911,13 +23911,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && wci_reqPend_1 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h15929); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && wci_reqPend_1 == 2'd2) begin v__h16019 = $time; @@ -23926,13 +23926,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && wci_reqPend_1 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h16019); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && wci_reqPend_1 == 2'd3) begin v__h16108 = $time; @@ -23941,7 +23941,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5852 && + !wci_respTimr_1_68_ULT_1_SL_wci_wTimeout_1_69_70___d5855 && wci_reqPend_1 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h16108); if (RST_N) @@ -24025,7 +24025,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && wci_reqPend_2 == 2'd1) begin v__h20231 = $time; @@ -24034,13 +24034,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && wci_reqPend_2 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h20231); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && wci_reqPend_2 == 2'd2) begin v__h20321 = $time; @@ -24049,13 +24049,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && wci_reqPend_2 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h20321); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && wci_reqPend_2 == 2'd3) begin v__h20410 = $time; @@ -24064,7 +24064,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5853 && + !wci_respTimr_2_08_ULT_1_SL_wci_wTimeout_2_09_10___d5856 && wci_reqPend_2 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h20410); if (RST_N) @@ -24148,7 +24148,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && wci_reqPend_3 == 2'd1) begin v__h24533 = $time; @@ -24157,13 +24157,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && wci_reqPend_3 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h24533); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && wci_reqPend_3 == 2'd2) begin v__h24623 = $time; @@ -24172,13 +24172,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && wci_reqPend_3 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h24623); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && wci_reqPend_3 == 2'd3) begin v__h24712 = $time; @@ -24187,7 +24187,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5854 && + !wci_respTimr_3_48_ULT_1_SL_wci_wTimeout_3_49_50___d5857 && wci_reqPend_3 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h24712); if (RST_N) @@ -24271,7 +24271,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && wci_reqPend_4 == 2'd1) begin v__h28835 = $time; @@ -24280,13 +24280,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && wci_reqPend_4 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h28835); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && wci_reqPend_4 == 2'd2) begin v__h28925 = $time; @@ -24295,13 +24295,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && wci_reqPend_4 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h28925); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && wci_reqPend_4 == 2'd3) begin v__h29014 = $time; @@ -24310,7 +24310,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5855 && + !wci_respTimr_4_88_ULT_1_SL_wci_wTimeout_4_89_90___d5858 && wci_reqPend_4 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h29014); if (RST_N) @@ -24394,7 +24394,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && wci_reqPend_5 == 2'd1) begin v__h33137 = $time; @@ -24403,13 +24403,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && wci_reqPend_5 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h33137); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && wci_reqPend_5 == 2'd2) begin v__h33227 = $time; @@ -24418,13 +24418,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && wci_reqPend_5 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h33227); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && wci_reqPend_5 == 2'd3) begin v__h33316 = $time; @@ -24433,7 +24433,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5856 && + !wci_respTimr_5_28_ULT_1_SL_wci_wTimeout_5_29_30___d5859 && wci_reqPend_5 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h33316); if (RST_N) @@ -24517,7 +24517,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && wci_reqPend_6 == 2'd1) begin v__h37439 = $time; @@ -24526,13 +24526,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && wci_reqPend_6 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h37439); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && wci_reqPend_6 == 2'd2) begin v__h37529 = $time; @@ -24541,13 +24541,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && wci_reqPend_6 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h37529); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && wci_reqPend_6 == 2'd3) begin v__h37618 = $time; @@ -24556,7 +24556,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5857 && + !wci_respTimr_6_068_ULT_1_SL_wci_wTimeout_6_069_ETC___d5860 && wci_reqPend_6 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h37618); if (RST_N) @@ -24640,7 +24640,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && wci_reqPend_7 == 2'd1) begin v__h41741 = $time; @@ -24649,13 +24649,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && wci_reqPend_7 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h41741); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && wci_reqPend_7 == 2'd2) begin v__h41831 = $time; @@ -24664,13 +24664,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && wci_reqPend_7 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h41831); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && wci_reqPend_7 == 2'd3) begin v__h41920 = $time; @@ -24679,7 +24679,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5858 && + !wci_respTimr_7_208_ULT_1_SL_wci_wTimeout_7_209_ETC___d5861 && wci_reqPend_7 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h41920); if (RST_N) @@ -24763,7 +24763,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && wci_reqPend_8 == 2'd1) begin v__h46043 = $time; @@ -24772,13 +24772,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && wci_reqPend_8 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h46043); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && wci_reqPend_8 == 2'd2) begin v__h46133 = $time; @@ -24787,13 +24787,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && wci_reqPend_8 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h46133); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && wci_reqPend_8 == 2'd3) begin v__h46222 = $time; @@ -24802,7 +24802,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5859 && + !wci_respTimr_8_348_ULT_1_SL_wci_wTimeout_8_349_ETC___d5862 && wci_reqPend_8 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h46222); if (RST_N) @@ -24886,7 +24886,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && wci_reqPend_9 == 2'd1) begin v__h50345 = $time; @@ -24895,13 +24895,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && wci_reqPend_9 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h50345); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && wci_reqPend_9 == 2'd2) begin v__h50435 = $time; @@ -24910,13 +24910,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && wci_reqPend_9 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h50435); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && wci_reqPend_9 == 2'd3) begin v__h50524 = $time; @@ -24925,7 +24925,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5860 && + !wci_respTimr_9_488_ULT_1_SL_wci_wTimeout_9_489_ETC___d5863 && wci_reqPend_9 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h50524); if (RST_N) @@ -25009,7 +25009,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && wci_reqPend_10 == 2'd1) begin v__h54647 = $time; @@ -25018,13 +25018,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && wci_reqPend_10 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h54647); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && wci_reqPend_10 == 2'd2) begin v__h54737 = $time; @@ -25033,13 +25033,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && wci_reqPend_10 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h54737); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && wci_reqPend_10 == 2'd3) begin v__h54826 = $time; @@ -25048,7 +25048,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_10 && wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5861 && + !wci_respTimr_10_628_ULT_1_SL_wci_wTimeout_10_6_ETC___d5864 && wci_reqPend_10 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h54826); if (RST_N) @@ -25132,7 +25132,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && wci_reqPend_11 == 2'd1) begin v__h58949 = $time; @@ -25141,13 +25141,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && wci_reqPend_11 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h58949); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && wci_reqPend_11 == 2'd2) begin v__h59039 = $time; @@ -25156,13 +25156,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && wci_reqPend_11 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h59039); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && wci_reqPend_11 == 2'd3) begin v__h59128 = $time; @@ -25171,7 +25171,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_11 && wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5862 && + !wci_respTimr_11_768_ULT_1_SL_wci_wTimeout_11_7_ETC___d5865 && wci_reqPend_11 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h59128); if (RST_N) @@ -25255,7 +25255,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && wci_reqPend_12 == 2'd1) begin v__h63251 = $time; @@ -25264,13 +25264,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && wci_reqPend_12 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h63251); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && wci_reqPend_12 == 2'd2) begin v__h63341 = $time; @@ -25279,13 +25279,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && wci_reqPend_12 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h63341); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && wci_reqPend_12 == 2'd3) begin v__h63430 = $time; @@ -25294,7 +25294,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_12 && wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5863 && + !wci_respTimr_12_908_ULT_1_SL_wci_wTimeout_12_9_ETC___d5866 && wci_reqPend_12 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h63430); if (RST_N) @@ -25378,7 +25378,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && wci_reqPend_13 == 2'd1) begin v__h67553 = $time; @@ -25387,13 +25387,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && wci_reqPend_13 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h67553); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && wci_reqPend_13 == 2'd2) begin v__h67643 = $time; @@ -25402,13 +25402,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && wci_reqPend_13 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h67643); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && wci_reqPend_13 == 2'd3) begin v__h67732 = $time; @@ -25417,7 +25417,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_13 && wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5864 && + !wci_respTimr_13_048_ULT_1_SL_wci_wTimeout_13_0_ETC___d5867 && wci_reqPend_13 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h67732); if (RST_N) @@ -25501,7 +25501,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && wci_reqPend_14 == 2'd1) begin v__h71855 = $time; @@ -25510,13 +25510,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && wci_reqPend_14 == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h71855); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && wci_reqPend_14 == 2'd2) begin v__h71945 = $time; @@ -25525,13 +25525,13 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && wci_reqPend_14 == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h71945); if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && wci_reqPend_14 == 2'd3) begin v__h72034 = $time; @@ -25540,7 +25540,7 @@ module mkOCCP(pciDevice, if (RST_N) if (WILL_FIRE_RL_wci_wrkBusy_14 && wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5865 && + !wci_respTimr_14_188_ULT_1_SL_wci_wTimeout_14_1_ETC___d5868 && wci_reqPend_14 == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h72034); if (RST_N) diff --git a/rtl/mkOCEDP4B.v b/rtl/mkOCEDP4B.v index 4b0a7e2d..952f3928 100644 --- a/rtl/mkOCEDP4B.v +++ b/rtl/mkOCEDP4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 10:16:43 EDT 2012 +// On Mon Sep 24 13:40:30 EDT 2012 // // // Ports: @@ -1862,7 +1862,7 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_wmi_wmi_respF_incCtr; // inputs to muxes for submodule ports - reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1; + reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2; reg [10 : 0] MUX_bram_memory$a_put_2__VAL_3, MUX_bram_memory$a_put_2__VAL_4, MUX_bram_memory_1$a_put_2__VAL_3, @@ -1888,13 +1888,13 @@ module mkOCEDP4B(pciDevice, MUX_edp_outBF_wDataIn$wset_1__VAL_7, MUX_edp_outBF_wDataIn$wset_1__VAL_8, MUX_edp_outBF_wDataIn$wset_1__VAL_9; - wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2, - MUX_wci_respF_q_1$write_1__VAL_2, + wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1, + MUX_wci_respF_q_1$write_1__VAL_1, MUX_wci_respF_x_wire$wset_1__VAL_1, MUX_wci_respF_x_wire$wset_1__VAL_2, MUX_wmi_wmi_respF_q_0$write_1__VAL_1, MUX_wmi_wmi_respF_q_0$write_1__VAL_2, - MUX_wmi_wmi_respF_q_1$write_1__VAL_2; + MUX_wmi_wmi_respF_q_1$write_1__VAL_1; wire [31 : 0] MUX_bml_fabFlowAddr$write_1__VAL_1, MUX_bml_fabFlowAddr$write_1__VAL_3, MUX_bml_fabMesgAddr$write_1__VAL_1, @@ -1968,8 +1968,8 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory_1$b_put_1__SEL_1, MUX_bram_memory_1$b_put_1__SEL_2, MUX_bram_memory_2$a_put_1__SEL_1, - MUX_bram_memory_2$a_put_1__SEL_2, MUX_bram_memory_2$a_put_1__SEL_3, + MUX_bram_memory_2$a_put_2__SEL_2, MUX_bram_memory_2$b_put_1__SEL_1, MUX_bram_memory_2$b_put_1__SEL_2, MUX_bram_memory_3$a_put_1__SEL_1, @@ -1988,8 +1988,8 @@ module mkOCEDP4B(pciDevice, MUX_wci_illegalEdge$write_1__SEL_1, MUX_wci_illegalEdge$write_1__SEL_2, MUX_wci_illegalEdge$write_1__VAL_2, - MUX_wci_respF_q_0$write_1__SEL_1, - MUX_wci_respF_q_1$write_1__SEL_1, + MUX_wci_respF_q_0$write_1__SEL_2, + MUX_wci_respF_q_1$write_1__SEL_2, MUX_wmi_bufDwell$write_1__SEL_1, MUX_wmi_bytesRemainResp$write_1__SEL_1, MUX_wmi_doneWithMesg$write_1__PSEL_1, @@ -1998,8 +1998,8 @@ module mkOCEDP4B(pciDevice, MUX_wmi_wmi_dhF_levelsValid$write_1__SEL_2, MUX_wmi_wmi_mFlagF_levelsValid$write_1__SEL_2, MUX_wmi_wmi_reqF_levelsValid$write_1__SEL_2, - MUX_wmi_wmi_respF_q_0$write_1__SEL_1, - MUX_wmi_wmi_respF_q_1$write_1__SEL_1, + MUX_wmi_wmi_respF_q_0$write_1__SEL_2, + MUX_wmi_wmi_respF_q_1$write_1__SEL_2, MUX_wmi_wrActive$write_1__SEL_1, MUX_wmi_wrFinalize$write_1__SEL_1; @@ -2021,11 +2021,11 @@ module mkOCEDP4B(pciDevice, v__h92126, v__h94025, v__h94787; - reg [31 : 0] IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2707, - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2708, - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2709, - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2710, - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d3165, + reg [31 : 0] IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841, + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842, + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843, + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844, + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724, _theResult____h118030, rdata__h110466; reg [3 : 0] CASE_edp_lastRuleFired_10_1_edp_lastRuleFired__ETC__q5; @@ -2067,22 +2067,22 @@ module mkOCEDP4B(pciDevice, CASE_edp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q7, CASE_edp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q19, CASE_wmi_p4B_NOT_wmi_p4B_EQ_3_OR_bram_serverAd_ETC__q20, - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3229, + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809, IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839, - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3230, + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803, IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849, - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3231, + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812, IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859, - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3232, + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810, IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869, IF_bml_dpControl_wget__213_BITS_1_TO_0_219_EQ__ETC___d2290, IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1076, - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3189, + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777, IF_wmi_p4B_096_EQ_1_099_THEN_bram_serverAdapte_ETC___d2105; wire [127 : 0] IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1201, IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1206, rdata__h40976; - wire [31 : 0] bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2851, + wire [31 : 0] bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2973, mesgMeta_opcode__h108747, nowLS__h82713, nowMS__h81770, @@ -2156,10 +2156,10 @@ module mkOCEDP4B(pciDevice, x__h35667, y__h35666, y__h35668; - wire [9 : 0] IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3200, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3225, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3226, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3227, + wire [9 : 0] IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2731, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2732, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2733, y__h24458, y__h33109, y__h36607, @@ -2183,7 +2183,7 @@ module mkOCEDP4B(pciDevice, ab__h5926, ab__h7456, ab__h8853, - edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d3151, + edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2699, idx__h26173, idx__h28404, idx__h29708, @@ -2198,16 +2198,16 @@ module mkOCEDP4B(pciDevice, NOT_bml_lclBufDone_237_304_AND_IF_bml_dpContro_ETC___d2317, NOT_edp_outBF_rRdPtr_83_PLUS_1024_283_EQ_edp_o_ETC___d1285, NOT_wmi_wrActive_011_012_OR_NOT_wmi_rdActive_0_ETC___d2021, - bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3067, - bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3068, - bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d3235, - bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3087, - bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3088, - bram_serverAdapterA_1_cnt_44_SLT_3___d2853, - bram_serverAdapterA_2_cnt_62_SLT_3___d2854, + bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3163, + bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164, + bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2822, + bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3183, + bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3184, + bram_serverAdapterA_1_cnt_44_SLT_3___d2975, + bram_serverAdapterA_2_cnt_62_SLT_3___d2976, bram_serverAdapterA_2_outDataCore_notEmpty__38_ETC___d1157, - bram_serverAdapterA_3_cnt_80_SLT_3___d2855, - bram_serverAdapterA_cnt_6_SLT_3___d2852, + bram_serverAdapterA_3_cnt_80_SLT_3___d2977, + bram_serverAdapterA_cnt_6_SLT_3___d2974, bram_serverAdapterA_outDataCore_notEmpty_OR_br_ETC___d1159, bram_serverAdapterB_1_cnt_03_SLT_3___d1961, bram_serverAdapterB_1_outData_outData_whas__98_ETC___d1989, @@ -2224,9 +2224,9 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mReqF_first__82_BIT_63_83_OR_IF_ed_ETC___d798, edp_tlpBRAM_rdRespDwRemain_188_ULE_4___d1190, edp_tlpBRAM_readRemainDWLen_010_ULE_4___d1011, - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148, - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149, - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150, + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698, + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695, + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696, hasPush_AND_edp_dpControl_wget__431_BITS_7_TO__ETC___d1451, hasPush_AND_edp_dpControl_wget__431_BITS_7_TO__ETC___d1485, hasPush_AND_edp_dpControl_wget__431_BITS_7_TO__ETC___d1503, @@ -2797,7 +2797,7 @@ module mkOCEDP4B(pciDevice, assign WILL_FIRE_RL_edp_tlpBRAM_writeData = edp_tlpBRAM_mReqF$EMPTY_N && (IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839 || - bram_serverAdapterA_cnt_6_SLT_3___d2852) && + bram_serverAdapterA_cnt_6_SLT_3___d2974) && IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d872 && edp_tlpBRAM_mReqF$D_OUT[129:128] == 2'd1 ; @@ -2811,10 +2811,10 @@ module mkOCEDP4B(pciDevice, // rule RL_edp_tlpBRAM_read_NextReq assign WILL_FIRE_RL_edp_tlpBRAM_read_NextReq = - bram_serverAdapterA_cnt_6_SLT_3___d2852 && - bram_serverAdapterA_1_cnt_44_SLT_3___d2853 && - bram_serverAdapterA_2_cnt_62_SLT_3___d2854 && - bram_serverAdapterA_3_cnt_80_SLT_3___d2855 && + bram_serverAdapterA_cnt_6_SLT_3___d2974 && + bram_serverAdapterA_1_cnt_44_SLT_3___d2975 && + bram_serverAdapterA_2_cnt_62_SLT_3___d2976 && + bram_serverAdapterA_3_cnt_80_SLT_3___d2977 && edp_tlpBRAM_mReqF$EMPTY_N && edp_tlpBRAM_readStarted && edp_tlpBRAM_mReqF$D_OUT[129:128] != 2'd0 && @@ -2957,7 +2957,7 @@ module mkOCEDP4B(pciDevice, // rule RL_edp_mhFsm_action_l169c11 assign WILL_FIRE_RL_edp_mhFsm_action_l169c11 = NOT_edp_outBF_rRdPtr_83_PLUS_1024_283_EQ_edp_o_ETC___d1285 && - edp_mhFsm_start_reg_1_1$whas && + edp_mhFsm_start_wire$whas && (edp_mhFsm_state_mkFSMstate == 4'd0 || edp_mhFsm_state_mkFSMstate == 4'd6) && !WILL_FIRE_RL_edp_fhFsm_action_l161c11 && @@ -2968,7 +2968,7 @@ module mkOCEDP4B(pciDevice, // rule RL_edp_mhFsm_idle_l168c3 assign WILL_FIRE_RL_edp_mhFsm_idle_l168c3 = - !edp_mhFsm_start_reg_1_1$whas && + !edp_mhFsm_start_wire$whas && edp_mhFsm_state_mkFSMstate == 4'd6 ; // rule RL_wmi_reqMetadata @@ -2990,7 +2990,7 @@ module mkOCEDP4B(pciDevice, // rule RL_wmi_doWriteReq assign CAN_FIRE_RL_wmi_doWriteReq = wmi_wmi_operateD && wmi_wmi_peerIsReady && wmi_wmi_dhF$EMPTY_N && - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3189 && + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 && wmi_wrActive ; assign WILL_FIRE_RL_wmi_doWriteReq = CAN_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ; @@ -3013,7 +3013,7 @@ module mkOCEDP4B(pciDevice, // rule RL_wmi_doReadReq assign WILL_FIRE_RL_wmi_doReadReq = - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3189 && + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 && wmi_rdActive && !WILL_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ; @@ -3122,8 +3122,8 @@ module mkOCEDP4B(pciDevice, // rule RL_wci_respF_incCtr assign WILL_FIRE_RL_wci_respF_incCtr = ((wci_respF_c_r == 2'd0) ? - wci_respF_x_wire$whas : - wci_respF_c_r != 2'd1 || wci_respF_x_wire$whas) && + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) && wci_respF_enqueueing$whas && !(wci_respF_c_r != 2'd0) ; @@ -3134,8 +3134,8 @@ module mkOCEDP4B(pciDevice, // rule RL_wci_respF_both assign WILL_FIRE_RL_wci_respF_both = ((wci_respF_c_r == 2'd1) ? - wci_respF_x_wire$whas : - wci_respF_c_r != 2'd2 || wci_respF_x_wire$whas) && + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) && wci_respF_c_r != 2'd0 && wci_respF_enqueueing$whas ; @@ -3169,7 +3169,7 @@ module mkOCEDP4B(pciDevice, bml_lclBufStart) ; assign MUX_bml_lclBufsCF$write_1__SEL_1 = wci_cState == 3'd2 && - (bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d3235 || + (bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2822 || NOT_bml_lclBufDone_237_304_AND_IF_bml_dpContro_ETC___d2317) ; assign MUX_bml_lclCredit$write_1__SEL_1 = WILL_FIRE_RL_bml_lcredit && @@ -3185,7 +3185,7 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd0 ; assign MUX_bram_memory$a_put_1__SEL_3 = WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3229 ; + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 ; assign MUX_bram_memory$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd0 ; assign MUX_bram_memory$b_put_1__SEL_2 = @@ -3200,7 +3200,7 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd1 ; assign MUX_bram_memory_1$a_put_1__SEL_3 = WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3230 ; + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 ; assign MUX_bram_memory_1$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd1 ; assign MUX_bram_memory_1$b_put_1__SEL_2 = @@ -3209,13 +3209,13 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_edp_tlpBRAM_writeReq && !edp_tlpBRAM_mReqF$D_OUT[63] && edp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd2 ; - assign MUX_bram_memory_2$a_put_1__SEL_2 = + assign MUX_bram_memory_2$a_put_1__SEL_3 = + WILL_FIRE_RL_edp_tlpBRAM_writeData && + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 ; + assign MUX_bram_memory_2$a_put_2__SEL_2 = WILL_FIRE_RL_edp_tlpBRAM_read_FirstReq && !edp_tlpBRAM_mReqF$D_OUT[60] && edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd2 ; - assign MUX_bram_memory_2$a_put_1__SEL_3 = - WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3231 ; assign MUX_bram_memory_2$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd2 ; assign MUX_bram_memory_2$b_put_1__SEL_2 = @@ -3230,7 +3230,7 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd3 ; assign MUX_bram_memory_3$a_put_1__SEL_3 = WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3232 ; + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 ; assign MUX_bram_memory_3$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd3 ; assign MUX_bram_memory_3$b_put_1__SEL_2 = @@ -3278,9 +3278,9 @@ module mkOCEDP4B(pciDevice, wci_reqF$D_OUT[36:34] == 3'd5 || wci_reqF$D_OUT[36:34] == 3'd6 || wci_reqF$D_OUT[36:34] == 3'd7) ; - assign MUX_wci_respF_q_0$write_1__SEL_1 = + assign MUX_wci_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ; - assign MUX_wci_respF_q_1$write_1__SEL_1 = + assign MUX_wci_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ; assign MUX_wmi_bufDwell$write_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd4 && @@ -3307,9 +3307,9 @@ module mkOCEDP4B(pciDevice, assign MUX_wmi_wmi_reqF_levelsValid$write_1__SEL_2 = wmi_wmi_reqF$FULL_N && wmi_wmi_operateD && wmi_wmi_peerIsReady && wmi_wmi_wmiReq$wget[31:29] != 3'd0 ; - assign MUX_wmi_wmi_respF_q_0$write_1__SEL_1 = + assign MUX_wmi_wmi_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wmi_wmi_respF_incCtr && wmi_wmi_respF_c_r == 2'd0 ; - assign MUX_wmi_wmi_respF_q_1$write_1__SEL_1 = + assign MUX_wmi_wmi_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wmi_wmi_respF_incCtr && wmi_wmi_respF_c_r == 2'd1 ; assign MUX_wmi_wrActive$write_1__SEL_1 = WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd4 ; @@ -3317,11 +3317,11 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd4 && wmi_doneWithMesg ; assign MUX_bml_crdBuf_value$write_1__VAL_3 = - bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3067 ? + bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3163 ? 16'd0 : bml_crdBuf_value + 16'd1 ; assign MUX_bml_fabBuf_value$write_1__VAL_3 = - bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3068 ? + bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164 ? 16'd0 : bml_fabBuf_value + 16'd1 ; assign MUX_bml_fabBufsAvail$write_1__VAL_1 = @@ -3329,23 +3329,23 @@ module mkOCEDP4B(pciDevice, assign MUX_bml_fabBufsAvail$write_1__VAL_2 = (dpControl[3:2] == 2'd1) ? x__h114823 : 16'd0 ; assign MUX_bml_fabFlowAddr$write_1__VAL_1 = - bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3068 ? + bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164 ? bml_fabFlowBase : - bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2851 ; + bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2973 ; assign MUX_bml_fabFlowAddr$write_1__VAL_3 = - bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3067 ? + bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3163 ? bml_fabFlowBase : - bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2851 ; + bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2973 ; assign MUX_bml_fabMesgAddr$write_1__VAL_1 = - bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3068 ? + bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164 ? bml_fabMesgBase : bml_fabMesgAddr + bml_fabMesgSize ; assign MUX_bml_fabMetaAddr$write_1__VAL_1 = - bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3068 ? + bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164 ? bml_fabMetaBase : bml_fabMetaAddr + bml_fabMetaSize ; assign MUX_bml_lclBuf_value$write_1__VAL_3 = - bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3087 ? + bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3183 ? 16'd0 : bml_lclBuf_value + 16'd1 ; assign MUX_bml_lclBufsAR$write_1__VAL_1 = @@ -3356,7 +3356,7 @@ module mkOCEDP4B(pciDevice, assign MUX_bml_lclBufsAR$write_1__VAL_2 = (dpControl[3:2] == 2'd1) ? bml_lclNumBufs : 16'd0 ; assign MUX_bml_lclBufsCF$write_1__VAL_1 = - bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d3235 ? + bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2822 ? x__h116059 : x__h116096 ; assign MUX_bml_lclBufsCF$write_1__VAL_2 = @@ -3364,23 +3364,23 @@ module mkOCEDP4B(pciDevice, assign MUX_bml_lclCredit$write_1__VAL_1 = (bml_lclBufDone && !bml_remStart) ? x__h116212 : x__h116217 ; assign MUX_bml_lclMesgAddr$write_1__VAL_2 = - bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3087 ? + bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3183 ? bml_mesgBase : bml_lclMesgAddr + bml_mesgSize ; assign MUX_bml_lclMetaAddr$write_1__VAL_2 = - bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3087 ? + bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3183 ? bml_metaBase : bml_lclMetaAddr + bml_metaSize ; assign MUX_bml_remBuf_value$write_1__VAL_3 = - bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3088 ? + bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3184 ? 16'd0 : bml_remBuf_value + 16'd1 ; assign MUX_bml_remMesgAddr$write_1__VAL_2 = - bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3088 ? + bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3184 ? bml_mesgBase : bml_remMesgAddr + bml_mesgSize ; assign MUX_bml_remMetaAddr$write_1__VAL_2 = - bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3088 ? + bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3184 ? bml_metaBase : bml_remMetaAddr + bml_metaSize ; always@(idx__h26173 or @@ -3427,10 +3427,10 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_mReqF$D_OUT[23:16], edp_tlpBRAM_mReqF$D_OUT[31:24] } ; assign MUX_bram_memory$a_put_3__VAL_3 = - { IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2707[7:0], - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2707[15:8], - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2707[23:16], - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2707[31:24] } ; + { IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841[7:0], + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841[15:8], + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841[23:16], + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841[31:24] } ; assign MUX_bram_memory$b_put_2__VAL_1 = wmi_lclMesgAddr[14:4] + { 1'd0, wmi_addr[13:4] } ; always@(idx__h28404 or @@ -3473,10 +3473,10 @@ module mkOCEDP4B(pciDevice, endcase end assign MUX_bram_memory_1$a_put_3__VAL_3 = - { IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2708[7:0], - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2708[15:8], - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2708[23:16], - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2708[31:24] } ; + { IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842[7:0], + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842[15:8], + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842[23:16], + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842[31:24] } ; always@(idx__h29708 or edp_tlpBRAM_writeDWAddr_PLUS_3__q11 or edp_tlpBRAM_writeDWAddr or @@ -3517,10 +3517,10 @@ module mkOCEDP4B(pciDevice, endcase end assign MUX_bram_memory_2$a_put_3__VAL_3 = - { IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2709[7:0], - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2709[15:8], - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2709[23:16], - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2709[31:24] } ; + { IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843[7:0], + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843[15:8], + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843[23:16], + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843[31:24] } ; always@(idx__h31012 or edp_tlpBRAM_writeDWAddr_PLUS_3__q11 or edp_tlpBRAM_writeDWAddr or @@ -3561,10 +3561,10 @@ module mkOCEDP4B(pciDevice, endcase end assign MUX_bram_memory_3$a_put_3__VAL_3 = - { IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2710[7:0], - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2710[15:8], - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2710[23:16], - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2710[31:24] } ; + { IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844[7:0], + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844[15:8], + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844[23:16], + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844[31:24] } ; assign MUX_edp_doorSeqDwell$write_1__VAL_1 = edp_doorSeqDwell - 4'd1 ; assign MUX_edp_fabMesgAccu$write_1__VAL_2 = edp_fabMesgAccu + y__h86228 ; assign MUX_edp_fabMeta$write_1__VAL_2 = @@ -3717,6 +3717,10 @@ module mkOCEDP4B(pciDevice, wci_reqF$D_OUT[36:34] != 3'd6 ; assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ; assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ; + assign MUX_wci_respF_q_0$write_1__VAL_1 = + (wci_respF_c_r == 2'd1) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + wci_respF_q_1 ; always@(WILL_FIRE_RL_wci_ctl_op_complete or MUX_wci_respF_x_wire$wset_1__VAL_1 or WILL_FIRE_RL_wci_cfrd or @@ -3724,23 +3728,19 @@ module mkOCEDP4B(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wci_ctl_op_complete: - MUX_wci_respF_q_0$write_1__VAL_1 = + MUX_wci_respF_q_0$write_1__VAL_2 = MUX_wci_respF_x_wire$wset_1__VAL_1; WILL_FIRE_RL_wci_cfrd: - MUX_wci_respF_q_0$write_1__VAL_1 = + MUX_wci_respF_q_0$write_1__VAL_2 = MUX_wci_respF_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_1 = 34'h1C0DE4201; - default: MUX_wci_respF_q_0$write_1__VAL_1 = + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_respF_q_0$write_1__VAL_2 = - (wci_respF_c_r == 2'd1) ? - MUX_wci_respF_q_0$write_1__VAL_1 : - wci_respF_q_1 ; - assign MUX_wci_respF_q_1$write_1__VAL_2 = + assign MUX_wci_respF_q_1$write_1__VAL_1 = (wci_respF_c_r == 2'd2) ? - MUX_wci_respF_q_0$write_1__VAL_1 : + MUX_wci_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_respF_x_wire$wset_1__VAL_1 = wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; @@ -3763,14 +3763,14 @@ module mkOCEDP4B(pciDevice, assign MUX_wmi_p4B$write_1__VAL_2 = wmi_p4B + 2'd1 ; assign MUX_wmi_wmi_respF_c_r$write_1__VAL_1 = wmi_wmi_respF_c_r + 2'd1 ; assign MUX_wmi_wmi_respF_c_r$write_1__VAL_2 = wmi_wmi_respF_c_r - 2'd1 ; - assign MUX_wmi_wmi_respF_q_0$write_1__VAL_1 = { 2'd1, rdata__h110466 } ; - assign MUX_wmi_wmi_respF_q_0$write_1__VAL_2 = + assign MUX_wmi_wmi_respF_q_0$write_1__VAL_1 = (wmi_wmi_respF_c_r == 2'd1) ? - MUX_wmi_wmi_respF_q_0$write_1__VAL_1 : + MUX_wmi_wmi_respF_q_0$write_1__VAL_2 : wmi_wmi_respF_q_1 ; - assign MUX_wmi_wmi_respF_q_1$write_1__VAL_2 = + assign MUX_wmi_wmi_respF_q_0$write_1__VAL_2 = { 2'd1, rdata__h110466 } ; + assign MUX_wmi_wmi_respF_q_1$write_1__VAL_1 = (wmi_wmi_respF_c_r == 2'd2) ? - MUX_wmi_wmi_respF_q_0$write_1__VAL_1 : + MUX_wmi_wmi_respF_q_0$write_1__VAL_2 : 34'd0 ; // inlined wires @@ -3929,7 +3929,7 @@ module mkOCEDP4B(pciDevice, assign bram_serverAdapterA_2_cnt_1$wget = 3'd1 ; assign bram_serverAdapterA_2_cnt_1$whas = (MUX_bram_memory_2$a_put_1__SEL_1 || - MUX_bram_memory_2$a_put_1__SEL_2 || + MUX_bram_memory_2$a_put_2__SEL_2 || MUX_bram_memory_2$a_put_1__SEL_3 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) && (!ab__h7456[1] || ab__h7456[0]) ; @@ -3941,7 +3941,7 @@ module mkOCEDP4B(pciDevice, assign bram_serverAdapterA_2_writeWithResp$wget = ab__h7456 ; assign bram_serverAdapterA_2_writeWithResp$whas = MUX_bram_memory_2$a_put_1__SEL_1 || - MUX_bram_memory_2$a_put_1__SEL_2 || + MUX_bram_memory_2$a_put_2__SEL_2 || MUX_bram_memory_2$a_put_1__SEL_3 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_serverAdapterA_2_s1_1$wget = @@ -4057,10 +4057,8 @@ module mkOCEDP4B(pciDevice, wciS0_MAddr, wciS0_MData } ; assign wci_wciReq$whas = 1'd1 ; - assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_1 ; - assign wci_respF_x_wire$whas = - WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || - WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ; + assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ; assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ; assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ; assign wci_sFlagReg_1$wget = 1'b0 ; @@ -4197,11 +4195,11 @@ module mkOCEDP4B(pciDevice, assign edp_fhFsm_state_fired_1$wget = 1'd1 ; assign edp_fhFsm_state_fired_1$whas = edp_fhFsm_state_set_pw$whas ; assign edp_mhFsm_start_wire$wget = 1'd1 ; - assign edp_mhFsm_start_wire$whas = edp_mhFsm_start_reg_1_1$whas ; - assign edp_mhFsm_start_reg_1_1$wget = 1'd1 ; - assign edp_mhFsm_start_reg_1_1$whas = + assign edp_mhFsm_start_wire$whas = WILL_FIRE_RL_edp_mhFsm_fsm_start || edp_mhFsm_start_reg_1 && !edp_mhFsm_state_fired ; + assign edp_mhFsm_start_reg_1_1$wget = 1'd1 ; + assign edp_mhFsm_start_reg_1_1$whas = edp_mhFsm_start_wire$whas ; assign edp_mhFsm_abort$wget = 1'b0 ; assign edp_mhFsm_abort$whas = 1'b0 ; assign edp_mhFsm_state_fired_1$wget = 1'd1 ; @@ -4222,7 +4220,7 @@ module mkOCEDP4B(pciDevice, wmiS0_MData, wmiS0_MDataByteEn } ; assign wmi_wmi_wmiDh$whas = 1'd1 ; - assign wmi_wmi_respF_x_wire$wget = MUX_wmi_wmi_respF_q_0$write_1__VAL_1 ; + assign wmi_wmi_respF_x_wire$wget = MUX_wmi_wmi_respF_q_0$write_1__VAL_2 ; assign wmi_wmi_respF_x_wire$whas = WILL_FIRE_RL_wmi_doReadResp ; assign wmi_wmi_operateD_1$wget = 1'd1 ; assign wmi_wmi_operateD_1$whas = wci_cState == 3'd2 ; @@ -4325,12 +4323,12 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_wmi_respMetadata ; assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ; assign wci_reqF_r_deq$whas = - WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || - WILL_FIRE_RL_wci_ctl_op_start ; + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; assign wci_reqF_r_clr$whas = 1'b0 ; assign wci_respF_enqueueing$whas = - WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || - WILL_FIRE_RL_wci_ctl_op_complete ; + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ; assign wci_sThreadBusy_pw$whas = 1'b0 ; assign wci_wci_cfwr_pw$whas = @@ -4594,7 +4592,7 @@ module mkOCEDP4B(pciDevice, MUX_bml_lclBufsCF$write_1__VAL_2 ; assign bml_lclBufsCF$EN = wci_cState == 3'd2 && - (bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d3235 || + (bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2822 || NOT_bml_lclBufDone_237_304_AND_IF_bml_dpContro_ETC___d2317) || WILL_FIRE_RL_bml_initAccumulators ; @@ -5155,7 +5153,7 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_edp_send_metaMH ; // register edp_mhFsm_start_reg_1 - assign edp_mhFsm_start_reg_1$D_IN = edp_mhFsm_start_reg_1_1$whas ; + assign edp_mhFsm_start_reg_1$D_IN = edp_mhFsm_start_wire$whas ; assign edp_mhFsm_start_reg_1$EN = 1'd1 ; // register edp_mhFsm_state_can_overlap @@ -5216,10 +5214,10 @@ module mkOCEDP4B(pciDevice, assign edp_outBF_rCache$D_IN = { 1'd1, edp_outBF_rWrPtr, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3200, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3225, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3226, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3227 } ; + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2732, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2733, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2731 } ; assign edp_outBF_rCache$EN = edp_outBF_pwEnqueue$whas ; // register edp_outBF_rRdPtr @@ -5531,44 +5529,44 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ; // register wci_respF_q_0 - always@(MUX_wci_respF_q_0$write_1__SEL_1 or + always@(WILL_FIRE_RL_wci_respF_both or MUX_wci_respF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0$write_1__SEL_2 or MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) begin case (1'b1) // synopsys parallel_case - MUX_wci_respF_q_0$write_1__SEL_1: - wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; + MUX_wci_respF_q_0$write_1__SEL_2: wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1; default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end assign wci_respF_q_0$EN = - WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || WILL_FIRE_RL_wci_respF_decCtr ; // register wci_respF_q_1 - always@(MUX_wci_respF_q_1$write_1__SEL_1 or - MUX_wci_respF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_respF_both or - MUX_wci_respF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1$write_1__VAL_1 or + MUX_wci_respF_q_1$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_respF_q_1$write_1__SEL_1: - wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; WILL_FIRE_RL_wci_respF_both: - wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_2; + wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1; + MUX_wci_respF_q_1$write_1__SEL_2: + wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA; default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end assign wci_respF_q_1$EN = - WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || WILL_FIRE_RL_wci_respF_decCtr ; // register wci_sFlagReg @@ -5798,16 +5796,16 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_wmi_wmi_respF_decCtr ; // register wmi_wmi_respF_q_0 - always@(MUX_wmi_wmi_respF_q_0$write_1__SEL_1 or + always@(WILL_FIRE_RL_wmi_wmi_respF_both or MUX_wmi_wmi_respF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wmi_wmi_respF_both or + MUX_wmi_wmi_respF_q_0$write_1__SEL_2 or MUX_wmi_wmi_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_wmi_respF_decCtr or wmi_wmi_respF_q_1) begin case (1'b1) // synopsys parallel_case - MUX_wmi_wmi_respF_q_0$write_1__SEL_1: - wmi_wmi_respF_q_0$D_IN = MUX_wmi_wmi_respF_q_0$write_1__VAL_1; WILL_FIRE_RL_wmi_wmi_respF_both: + wmi_wmi_respF_q_0$D_IN = MUX_wmi_wmi_respF_q_0$write_1__VAL_1; + MUX_wmi_wmi_respF_q_0$write_1__SEL_2: wmi_wmi_respF_q_0$D_IN = MUX_wmi_wmi_respF_q_0$write_1__VAL_2; WILL_FIRE_RL_wmi_wmi_respF_decCtr: wmi_wmi_respF_q_0$D_IN = wmi_wmi_respF_q_1; @@ -5816,30 +5814,30 @@ module mkOCEDP4B(pciDevice, endcase end assign wmi_wmi_respF_q_0$EN = - WILL_FIRE_RL_wmi_wmi_respF_incCtr && wmi_wmi_respF_c_r == 2'd0 || WILL_FIRE_RL_wmi_wmi_respF_both || + WILL_FIRE_RL_wmi_wmi_respF_incCtr && wmi_wmi_respF_c_r == 2'd0 || WILL_FIRE_RL_wmi_wmi_respF_decCtr ; // register wmi_wmi_respF_q_1 - always@(MUX_wmi_wmi_respF_q_1$write_1__SEL_1 or - MUX_wmi_wmi_respF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wmi_wmi_respF_both or - MUX_wmi_wmi_respF_q_1$write_1__VAL_2 or + always@(WILL_FIRE_RL_wmi_wmi_respF_both or + MUX_wmi_wmi_respF_q_1$write_1__VAL_1 or + MUX_wmi_wmi_respF_q_1$write_1__SEL_2 or + MUX_wmi_wmi_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_wmi_respF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wmi_wmi_respF_q_1$write_1__SEL_1: - wmi_wmi_respF_q_1$D_IN = MUX_wmi_wmi_respF_q_0$write_1__VAL_1; WILL_FIRE_RL_wmi_wmi_respF_both: - wmi_wmi_respF_q_1$D_IN = MUX_wmi_wmi_respF_q_1$write_1__VAL_2; + wmi_wmi_respF_q_1$D_IN = MUX_wmi_wmi_respF_q_1$write_1__VAL_1; + MUX_wmi_wmi_respF_q_1$write_1__SEL_2: + wmi_wmi_respF_q_1$D_IN = MUX_wmi_wmi_respF_q_0$write_1__VAL_2; WILL_FIRE_RL_wmi_wmi_respF_decCtr: wmi_wmi_respF_q_1$D_IN = 34'd0; default: wmi_wmi_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end assign wmi_wmi_respF_q_1$EN = - WILL_FIRE_RL_wmi_wmi_respF_incCtr && wmi_wmi_respF_c_r == 2'd1 || WILL_FIRE_RL_wmi_wmi_respF_both || + WILL_FIRE_RL_wmi_wmi_respF_incCtr && wmi_wmi_respF_c_r == 2'd1 || WILL_FIRE_RL_wmi_wmi_respF_decCtr ; // register wmi_wmi_sFlagReg @@ -5969,7 +5967,7 @@ module mkOCEDP4B(pciDevice, !edp_tlpBRAM_mReqF$D_OUT[60] && edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd0 || WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3229 || + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_memory$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd0 || @@ -6062,7 +6060,7 @@ module mkOCEDP4B(pciDevice, !edp_tlpBRAM_mReqF$D_OUT[60] && edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd1 || WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3230 || + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_memory_1$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd1 || @@ -6073,7 +6071,7 @@ module mkOCEDP4B(pciDevice, // submodule bram_memory_2 always@(MUX_bram_memory_2$a_put_1__SEL_1 or edp_tlpBRAM_mReqF$D_OUT or - MUX_bram_memory_2$a_put_1__SEL_2 or + MUX_bram_memory_2$a_put_2__SEL_2 or MUX_bram_memory_2$a_put_1__SEL_3 or MUX_bram_memory_2$a_put_2__VAL_3 or WILL_FIRE_RL_edp_tlpBRAM_read_NextReq or @@ -6082,7 +6080,7 @@ module mkOCEDP4B(pciDevice, case (1'b1) // synopsys parallel_case MUX_bram_memory_2$a_put_1__SEL_1: bram_memory_2$ADDRA = edp_tlpBRAM_mReqF$D_OUT[62:52]; - MUX_bram_memory_2$a_put_1__SEL_2: + MUX_bram_memory_2$a_put_2__SEL_2: bram_memory_2$ADDRA = edp_tlpBRAM_mReqF$D_OUT[41:31]; MUX_bram_memory_2$a_put_1__SEL_3: bram_memory_2$ADDRA = MUX_bram_memory_2$a_put_2__VAL_3; @@ -6111,7 +6109,7 @@ module mkOCEDP4B(pciDevice, MUX_bram_memory$a_put_3__VAL_1 or MUX_bram_memory_2$a_put_1__SEL_3 or MUX_bram_memory_2$a_put_3__VAL_3 or - MUX_bram_memory_2$a_put_1__SEL_2 or + MUX_bram_memory_2$a_put_2__SEL_2 or WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) begin case (1'b1) // synopsys parallel_case @@ -6119,7 +6117,7 @@ module mkOCEDP4B(pciDevice, bram_memory_2$DIA = MUX_bram_memory$a_put_3__VAL_1; MUX_bram_memory_2$a_put_1__SEL_3: bram_memory_2$DIA = MUX_bram_memory_2$a_put_3__VAL_3; - MUX_bram_memory_2$a_put_1__SEL_2 || + MUX_bram_memory_2$a_put_2__SEL_2 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq: bram_memory_2$DIA = 32'd0; default: bram_memory_2$DIA = 32'hAAAAAAAA /* unspecified value */ ; @@ -6142,7 +6140,7 @@ module mkOCEDP4B(pciDevice, endcase end assign bram_memory_2$WEA = - !MUX_bram_memory_2$a_put_1__SEL_2 && + !MUX_bram_memory_2$a_put_2__SEL_2 && !WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_memory_2$WEB = !MUX_bram_memory_2$b_put_1__SEL_1 && @@ -6155,7 +6153,7 @@ module mkOCEDP4B(pciDevice, !edp_tlpBRAM_mReqF$D_OUT[60] && edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd2 || WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3231 || + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_memory_2$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd2 || @@ -6248,7 +6246,7 @@ module mkOCEDP4B(pciDevice, !edp_tlpBRAM_mReqF$D_OUT[60] && edp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd3 || WILL_FIRE_RL_edp_tlpBRAM_writeData && - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3232 || + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq ; assign bram_memory_3$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd3 || @@ -6405,10 +6403,10 @@ module mkOCEDP4B(pciDevice, x__h20653[10:0] : edp_outBF_rRdPtr[10:0] ; assign edp_outBF_memory$DIA = - { IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3200, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3225, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3226, - IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3227 } ; + { IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2732, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2733, + IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2731 } ; assign edp_outBF_memory$DIB = 40'hAAAAAAAAAA /* unspecified value */ ; assign edp_outBF_memory$WEA = edp_outBF_pwEnqueue$whas ; assign edp_outBF_memory$WEB = 1'd0 ; @@ -6543,21 +6541,12 @@ module mkOCEDP4B(pciDevice, // remaining internal signals assign IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d872 = (IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849 || - bram_serverAdapterA_1_cnt_44_SLT_3___d2853) && + bram_serverAdapterA_1_cnt_44_SLT_3___d2975) && (IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859 || - bram_serverAdapterA_2_cnt_62_SLT_3___d2854) && + bram_serverAdapterA_2_cnt_62_SLT_3___d2976) && (IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2855) ; - assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3200 = - (!edp_outBF_wDataIn$whas || - edp_outBF_wDataIn$wget[39:38] == 2'd0) ? - { 2'd0, - edp_outBF_wDataIn$whas ? - edp_outBF_wDataIn$wget[37:30] : - 8'd0 } : - { CASE_edp_outBF_wDataInwget_BITS_39_TO_38_3_1__ETC__q29, - edp_outBF_wDataIn$wget[37:30] } ; - assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3225 = + bram_serverAdapterA_3_cnt_80_SLT_3___d2977) ; + assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2730 = (!edp_outBF_wDataIn$whas || edp_outBF_wDataIn$wget[29:28] == 2'd0) ? { 2'd0, @@ -6566,16 +6555,7 @@ module mkOCEDP4B(pciDevice, 8'd0 } : { CASE_edp_outBF_wDataInwget_BITS_29_TO_28_3_1__ETC__q30, edp_outBF_wDataIn$wget[27:20] } ; - assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3226 = - (!edp_outBF_wDataIn$whas || - edp_outBF_wDataIn$wget[19:18] == 2'd0) ? - { 2'd0, - edp_outBF_wDataIn$whas ? - edp_outBF_wDataIn$wget[17:10] : - 8'd0 } : - { CASE_edp_outBF_wDataInwget_BITS_19_TO_18_3_1__ETC__q31, - edp_outBF_wDataIn$wget[17:10] } ; - assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d3227 = + assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2731 = (!edp_outBF_wDataIn$whas || edp_outBF_wDataIn$wget[9:8] == 2'd0) ? { 2'd0, @@ -6584,11 +6564,29 @@ module mkOCEDP4B(pciDevice, 8'd0 } : { CASE_edp_outBF_wDataInwget_BITS_9_TO_8_3_1_ed_ETC__q32, edp_outBF_wDataIn$wget[7:0] } ; + assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2732 = + (!edp_outBF_wDataIn$whas || + edp_outBF_wDataIn$wget[39:38] == 2'd0) ? + { 2'd0, + edp_outBF_wDataIn$whas ? + edp_outBF_wDataIn$wget[37:30] : + 8'd0 } : + { CASE_edp_outBF_wDataInwget_BITS_39_TO_38_3_1__ETC__q29, + edp_outBF_wDataIn$wget[37:30] } ; + assign IF_NOT_edp_outBF_wDataIn_whas__20_21_OR_edp_ou_ETC___d2733 = + (!edp_outBF_wDataIn$whas || + edp_outBF_wDataIn$wget[19:18] == 2'd0) ? + { 2'd0, + edp_outBF_wDataIn$whas ? + edp_outBF_wDataIn$wget[17:10] : + 8'd0 } : + { CASE_edp_outBF_wDataInwget_BITS_19_TO_18_3_1__ETC__q31, + edp_outBF_wDataIn$wget[17:10] } ; assign IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1085 = IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1076 && CASE_edp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q19 ; assign IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1201 = - edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d3151[0] ? + edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2699[0] ? { bram_serverAdapterA_3_outData_outData$wget[7:0], bram_serverAdapterA_3_outData_outData$wget[15:8], bram_serverAdapterA_3_outData_outData$wget[23:16], @@ -6622,7 +6620,7 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterA_1_outData_outData$wget[23:16], bram_serverAdapterA_1_outData_outData$wget[31:24] } ; assign IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1206 = - edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d3151[0] ? + edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2699[0] ? { bram_serverAdapterA_1_outData_outData$wget[7:0], bram_serverAdapterA_1_outData_outData$wget[15:8], bram_serverAdapterA_1_outData_outData$wget[23:16], @@ -6701,7 +6699,7 @@ module mkOCEDP4B(pciDevice, 2'd0 : 2'd2 ; assign ab__h7456 = - (MUX_bram_memory_2$a_put_1__SEL_2 || + (MUX_bram_memory_2$a_put_2__SEL_2 || WILL_FIRE_RL_edp_tlpBRAM_read_NextReq) ? 2'd0 : 2'd2 ; @@ -6710,30 +6708,30 @@ module mkOCEDP4B(pciDevice, WILL_FIRE_RL_wmi_reqMetadata) ? 2'd0 : 2'd2 ; - assign bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3067 = + assign bml_crdBuf_value_195_EQ_bml_crdBuf_modulus_bw__ETC___d3163 = bml_crdBuf_value == bml_crdBuf_modulus ; - assign bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3068 = + assign bml_fabBuf_value_180_EQ_bml_fabBuf_modulus_bw__ETC___d3164 = bml_fabBuf_value == bml_fabBuf_modulus ; - assign bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2851 = + assign bml_fabFlowAddr_252_PLUS_bml_fabFlowSize_253___d2973 = bml_fabFlowAddr + bml_fabFlowSize ; - assign bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d3235 = + assign bml_lclBufDone_237_AND_IF_bml_dpControl_wget___ETC___d2822 = bml_lclBufDone && CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q9 ; - assign bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3087 = + assign bml_lclBuf_value_150_EQ_bml_lclBuf_modulus_bw__ETC___d3183 = bml_lclBuf_value == bml_lclBuf_modulus ; - assign bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3088 = + assign bml_remBuf_value_165_EQ_bml_remBuf_modulus_bw__ETC___d3184 = bml_remBuf_value == bml_remBuf_modulus ; assign bram_serverAdapterA_1_cnt_44_PLUS_IF_bram_serv_ETC___d150 = bram_serverAdapterA_1_cnt + (bram_serverAdapterA_1_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_1_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_1_cnt_44_SLT_3___d2853 = + assign bram_serverAdapterA_1_cnt_44_SLT_3___d2975 = (bram_serverAdapterA_1_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_2_cnt_62_PLUS_IF_bram_serv_ETC___d268 = bram_serverAdapterA_2_cnt + (bram_serverAdapterA_2_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_2_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_2_cnt_62_SLT_3___d2854 = + assign bram_serverAdapterA_2_cnt_62_SLT_3___d2976 = (bram_serverAdapterA_2_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_2_outDataCore_notEmpty__38_ETC___d1157 = (bram_serverAdapterA_2_outDataCore$EMPTY_N || @@ -6749,13 +6747,13 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterA_3_cnt + (bram_serverAdapterA_3_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_3_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_3_cnt_80_SLT_3___d2855 = + assign bram_serverAdapterA_3_cnt_80_SLT_3___d2977 = (bram_serverAdapterA_3_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32 = bram_serverAdapterA_cnt + (bram_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_cnt_6_SLT_3___d2852 = + assign bram_serverAdapterA_cnt_6_SLT_3___d2974 = (bram_serverAdapterA_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_outDataCore_notEmpty_OR_br_ETC___d1159 = (bram_serverAdapterA_outDataCore$EMPTY_N || @@ -6833,7 +6831,7 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_readNxtDWAddr + 13'd3 ; assign edp_tlpBRAM_readRemainDWLen_010_ULE_4___d1011 = edp_tlpBRAM_readRemainDWLen <= 10'd4 ; - assign edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d3151 = + assign edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2699 = edp_tlpBRAM_readReq$D_OUT[30:29] + (edp_tlpBRAM_readReq$D_OUT[60] ? 2'd0 : 2'd1) ; assign edp_tlpBRAM_writeDWAddr_PLUS_1__q12 = @@ -6842,11 +6840,11 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_writeDWAddr + 13'd2 ; assign edp_tlpBRAM_writeDWAddr_PLUS_3__q11 = edp_tlpBRAM_writeDWAddr + 13'd3 ; - assign edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148 = + assign edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 = edp_tlpBRAM_writeRemainDWLen <= 10'd1 ; - assign edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149 = + assign edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695 = edp_tlpBRAM_writeRemainDWLen <= 10'd2 ; - assign edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150 = + assign edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 = edp_tlpBRAM_writeRemainDWLen <= 10'd3 ; assign hasPush_AND_edp_dpControl_wget__431_BITS_7_TO__ETC___d1451 = hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 && @@ -6960,16 +6958,16 @@ module mkOCEDP4B(pciDevice, assign rdat__h119220 = hasDebugLogic ? edp_dbgBytesTxDeq : 32'd0 ; assign rdat__h119231 = hasDebugLogic ? edpDebug : 32'd0 ; assign rdata__h40976 = - edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d3151[1] ? + edp_tlpBRAM_readReq_first__061_BITS_30_TO_29_0_ETC___d2699[1] ? IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1201 : IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d1206 ; assign rreq_tag__h86003 = (y__h85835 == edp_mesgLengthRemainPush) ? 8'h01 : 8'h0 ; assign rresp_data__h35592 = - { IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d3165[7:0], - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d3165[15:8], - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d3165[23:16], - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d3165[31:24] } ; + { IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724[7:0], + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724[15:8], + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724[23:16], + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724[31:24] } ; assign spanToNextPage__h85809 = 13'd4096 - { 1'd0, edp_srcMesgAccu[11:0] } ; assign thisRequestLength__h85810 = (x__h85845[12:0] <= spanToNextPage__h85809) ? @@ -7085,15 +7083,6 @@ module mkOCEDP4B(pciDevice, endcase end always@(edp_tlpBRAM_readReq$D_OUT) - begin - case (edp_tlpBRAM_readReq$D_OUT[18:15]) - 4'b1100: x__h35674 = 2'b10; - 4'b1110: x__h35674 = 2'b01; - 4'b1111: x__h35674 = 2'b0; - default: x__h35674 = 2'b11; - endcase - end - always@(edp_tlpBRAM_readReq$D_OUT) begin case (edp_tlpBRAM_readReq$D_OUT[14:11]) 4'b1100: x__h35697 = 2'b10; @@ -7102,6 +7091,15 @@ module mkOCEDP4B(pciDevice, default: x__h35697 = 2'b11; endcase end + always@(edp_tlpBRAM_readReq$D_OUT) + begin + case (edp_tlpBRAM_readReq$D_OUT[18:15]) + 4'b1100: x__h35674 = 2'b10; + 4'b1110: x__h35674 = 2'b01; + 4'b1111: x__h35674 = 2'b0; + default: x__h35674 = 2'b11; + endcase + end always@(edp_lastRuleFired) begin case (edp_lastRuleFired) @@ -7242,10 +7240,10 @@ module mkOCEDP4B(pciDevice, endcase end always@(idx__h26173 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) begin case (idx__h26173) 2'd0: @@ -7253,20 +7251,20 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148; + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; 2'd2: IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149; + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; 2'd3: IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d839 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150; + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; endcase end always@(idx__h28404 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) begin case (idx__h28404) 2'd0: @@ -7274,20 +7272,20 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148; + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; 2'd2: IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149; + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; 2'd3: IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d849 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150; + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; endcase end always@(idx__h29708 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) begin case (idx__h29708) 2'd0: @@ -7295,20 +7293,20 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148; + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; 2'd2: IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149; + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; 2'd3: IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d859 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150; + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; endcase end always@(idx__h31012 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) begin case (idx__h31012) 2'd0: @@ -7316,57 +7314,57 @@ module mkOCEDP4B(pciDevice, edp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148; + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; 2'd2: IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149; + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; 2'd3: IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d869 = - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150; + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; endcase end always@(edp_tlpBRAM_mReqF$D_OUT or - bram_serverAdapterA_3_cnt_80_SLT_3___d2855 or - bram_serverAdapterA_cnt_6_SLT_3___d2852 or - bram_serverAdapterA_1_cnt_44_SLT_3___d2853 or - bram_serverAdapterA_2_cnt_62_SLT_3___d2854) + bram_serverAdapterA_3_cnt_80_SLT_3___d2977 or + bram_serverAdapterA_cnt_6_SLT_3___d2974 or + bram_serverAdapterA_1_cnt_44_SLT_3___d2975 or + bram_serverAdapterA_2_cnt_62_SLT_3___d2976) begin case (edp_tlpBRAM_mReqF$D_OUT[51:50]) 2'd0: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q7 = - bram_serverAdapterA_cnt_6_SLT_3___d2852; + bram_serverAdapterA_cnt_6_SLT_3___d2974; 2'd1: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q7 = - bram_serverAdapterA_1_cnt_44_SLT_3___d2853; + bram_serverAdapterA_1_cnt_44_SLT_3___d2975; 2'd2: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q7 = - bram_serverAdapterA_2_cnt_62_SLT_3___d2854; + bram_serverAdapterA_2_cnt_62_SLT_3___d2976; 2'd3: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q7 = edp_tlpBRAM_mReqF$D_OUT[51:50] != 2'd3 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2855; + bram_serverAdapterA_3_cnt_80_SLT_3___d2977; endcase end always@(edp_tlpBRAM_mReqF$D_OUT or - bram_serverAdapterA_3_cnt_80_SLT_3___d2855 or - bram_serverAdapterA_cnt_6_SLT_3___d2852 or - bram_serverAdapterA_1_cnt_44_SLT_3___d2853 or - bram_serverAdapterA_2_cnt_62_SLT_3___d2854) + bram_serverAdapterA_3_cnt_80_SLT_3___d2977 or + bram_serverAdapterA_cnt_6_SLT_3___d2974 or + bram_serverAdapterA_1_cnt_44_SLT_3___d2975 or + bram_serverAdapterA_2_cnt_62_SLT_3___d2976) begin case (edp_tlpBRAM_mReqF$D_OUT[30:29]) 2'd0: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q8 = - bram_serverAdapterA_cnt_6_SLT_3___d2852; + bram_serverAdapterA_cnt_6_SLT_3___d2974; 2'd1: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q8 = - bram_serverAdapterA_1_cnt_44_SLT_3___d2853; + bram_serverAdapterA_1_cnt_44_SLT_3___d2975; 2'd2: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q8 = - bram_serverAdapterA_2_cnt_62_SLT_3___d2854; + bram_serverAdapterA_2_cnt_62_SLT_3___d2976; 2'd3: CASE_edp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q8 = edp_tlpBRAM_mReqF$D_OUT[30:29] != 2'd3 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2855; + bram_serverAdapterA_3_cnt_80_SLT_3___d2977; endcase end always@(wmi_addr or @@ -7377,16 +7375,16 @@ module mkOCEDP4B(pciDevice, begin case (wmi_addr[3:2]) 2'd0: - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3189 = + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 = bram_serverAdapterB_cnt_5_SLT_3___d1960; 2'd1: - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3189 = + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 = bram_serverAdapterB_1_cnt_03_SLT_3___d1961; 2'd2: - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3189 = + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 = bram_serverAdapterB_2_cnt_21_SLT_3___d1962; 2'd3: - IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d3189 = + IF_wmi_addr_039_BITS_3_TO_2_040_EQ_0_041_THEN__ETC___d2777 = wmi_addr[3:2] != 2'd3 || bram_serverAdapterB_3_cnt_39_SLT_3___d1963; endcase @@ -7405,103 +7403,103 @@ module mkOCEDP4B(pciDevice, endcase end always@(idx__h26173 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) begin case (idx__h26173) 2'd0: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3229 = + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 = edp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3229 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148; + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; 2'd2: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3229 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149; + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; 2'd3: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3229 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150; + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2809 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; endcase end always@(idx__h28404 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) begin case (idx__h28404) 2'd0: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3230 = + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 = edp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3230 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148; + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; 2'd2: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3230 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149; + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; 2'd3: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3230 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150; + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2803 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; endcase end always@(idx__h29708 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) begin case (idx__h29708) 2'd0: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3231 = + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = edp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3231 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148; + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; 2'd2: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3231 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149; + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; 2'd3: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3231 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150; + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2812 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; endcase end always@(idx__h31012 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696 or edp_tlpBRAM_writeRemainDWLen or - edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148 or - edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149) + edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698 or + edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695) begin case (idx__h31012) 2'd0: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3232 = + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 = edp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3232 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d3148; + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_1___d2698; 2'd2: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3232 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d3149; + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_2___d2695; 2'd3: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d3232 = - !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d3150; + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2810 = + !edp_tlpBRAM_writeRemainDWLen_26_ULE_3___d2696; endcase end always@(idx__h26173 or edp_tlpBRAM_mReqF$D_OUT) begin case (idx__h26173) 2'd0: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2707 = + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841 = edp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2707 = + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841 = edp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2707 = + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841 = edp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2707 = + IF_0_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2841 = edp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end @@ -7509,16 +7507,16 @@ module mkOCEDP4B(pciDevice, begin case (idx__h28404) 2'd0: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2708 = + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842 = edp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2708 = + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842 = edp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2708 = + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842 = edp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2708 = + IF_1_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2842 = edp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end @@ -7526,16 +7524,16 @@ module mkOCEDP4B(pciDevice, begin case (idx__h29708) 2'd0: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2709 = + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843 = edp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2709 = + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843 = edp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2709 = + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843 = edp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2709 = + IF_2_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2843 = edp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end @@ -7543,16 +7541,16 @@ module mkOCEDP4B(pciDevice, begin case (idx__h31012) 2'd0: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2710 = + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844 = edp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2710 = + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844 = edp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2710 = + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844 = edp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2710 = + IF_3_MINUS_edp_tlpBRAM_writeDWAddr_22_BITS_1_T_ETC___d2844 = edp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end @@ -7569,27 +7567,6 @@ module mkOCEDP4B(pciDevice, !bml_fabDone; endcase end - always@(edp_tlpBRAM_readReq$D_OUT or - bram_serverAdapterA_3_outData_outData$wget or - bram_serverAdapterA_outData_outData$wget or - bram_serverAdapterA_1_outData_outData$wget or - bram_serverAdapterA_2_outData_outData$wget) - begin - case (edp_tlpBRAM_readReq$D_OUT[30:29]) - 2'd0: - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d3165 = - bram_serverAdapterA_outData_outData$wget; - 2'd1: - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d3165 = - bram_serverAdapterA_1_outData_outData$wget; - 2'd2: - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d3165 = - bram_serverAdapterA_2_outData_outData$wget; - 2'd3: - IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d3165 = - bram_serverAdapterA_3_outData_outData$wget; - endcase - end always@(edp_tlpBRAM_readReq$D_OUT or bram_serverAdapterA_3_outDataCore$EMPTY_N or bram_serverAdapterA_3_outData_enqData$whas or @@ -7620,6 +7597,27 @@ module mkOCEDP4B(pciDevice, bram_serverAdapterA_3_outData_enqData$whas; endcase end + always@(edp_tlpBRAM_readReq$D_OUT or + bram_serverAdapterA_3_outData_outData$wget or + bram_serverAdapterA_outData_outData$wget or + bram_serverAdapterA_1_outData_outData$wget or + bram_serverAdapterA_2_outData_outData$wget) + begin + case (edp_tlpBRAM_readReq$D_OUT[30:29]) + 2'd0: + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724 = + bram_serverAdapterA_outData_outData$wget; + 2'd1: + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724 = + bram_serverAdapterA_1_outData_outData$wget; + 2'd2: + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724 = + bram_serverAdapterA_2_outData_outData$wget; + 2'd3: + IF_edp_tlpBRAM_readReq_first__061_BITS_30_TO_2_ETC___d2724 = + bram_serverAdapterA_3_outData_outData$wget; + endcase + end always@(edp_tlpBRAM_readReq$D_OUT or bram_serverAdapterA_3_outData_outData$whas or bram_serverAdapterA_outData_outData$whas or diff --git a/rtl/mkPWrk_n210.v b/rtl/mkPWrk_n210.v index 8c338236..a3a2c010 100644 --- a/rtl/mkPWrk_n210.v +++ b/rtl/mkPWrk_n210.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Wed Sep 19 10:18:16 EDT 2012 +// On Mon Sep 24 13:38:16 EDT 2012 // // // Ports: @@ -493,7 +493,7 @@ module mkPWrk_n210(RST_N_sys0_rst, s4__h1408, s5__h1407, s6__h1406; - wire _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d394, + wire _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397, wci_wslv_reqF_i_notEmpty__69_AND_IF_wci_wslv_r_ETC___d350, wci_wslv_reqF_i_notEmpty__69_AND_wci_wslv_reqF_ETC___d329; @@ -971,49 +971,49 @@ module mkPWrk_n210(RST_N_sys0_rst, assign i2cC_vrReadData$D_IN = i2cC_tSDA$O ; assign i2cC_vrReadData$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d394 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; // register i2cC_vrReadData_1 assign i2cC_vrReadData_1$D_IN = i2cC_vrReadData ; assign i2cC_vrReadData_1$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d394 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; // register i2cC_vrReadData_2 assign i2cC_vrReadData_2$D_IN = i2cC_vrReadData_1 ; assign i2cC_vrReadData_2$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d394 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; // register i2cC_vrReadData_3 assign i2cC_vrReadData_3$D_IN = i2cC_vrReadData_2 ; assign i2cC_vrReadData_3$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d394 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; // register i2cC_vrReadData_4 assign i2cC_vrReadData_4$D_IN = i2cC_vrReadData_3 ; assign i2cC_vrReadData_4$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d394 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; // register i2cC_vrReadData_5 assign i2cC_vrReadData_5$D_IN = i2cC_vrReadData_4 ; assign i2cC_vrReadData_5$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d394 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; // register i2cC_vrReadData_6 assign i2cC_vrReadData_6$D_IN = i2cC_vrReadData_5 ; assign i2cC_vrReadData_6$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d394 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; // register i2cC_vrReadData_7 assign i2cC_vrReadData_7$D_IN = i2cC_vrReadData_6 ; assign i2cC_vrReadData_7$EN = WILL_FIRE_RL_i2cC_running_read && - _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d394 ; + _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 ; // register macV assign macV$D_IN = { macV[39:0], i2cC_fResponse$D_OUT } ; @@ -1238,7 +1238,7 @@ module mkPWrk_n210(RST_N_sys0_rst, assign _154742503901866210315206599__q3 = 87'h7FFFFFF1FFFFFE3FFFFFC7 ; assign _166153498389916941667817601160445959__q4 = 117'h1FFFFFFC7FFFFF8FFFFFFE00000007 ; - assign _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d394 = + assign _306783360_BIT_i2cC_rPlayIndex_value__8_BITS_6__ETC___d397 = _306783360__q2[i2cC_rPlayIndex$Q_OUT[6:0]] ; assign _306783360__q2 = 117'd306783360 ; assign a0__h1421 = {3{i2cC_rAddress[0]}} ; diff --git a/rtl/mkPktFork.v b/rtl/mkPktFork.v index 7fb55863..aed5fa37 100644 --- a/rtl/mkPktFork.v +++ b/rtl/mkPktFork.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:32 EDT 2012 +// On Mon Sep 24 13:39:04 EDT 2012 // // // Ports: @@ -95,7 +95,7 @@ module mkPktFork(pfk, wire MUX_f0Active$write_1__SEL_1, MUX_f1Active$write_1__SEL_1; // remaining internal signals - reg IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58; + reg IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62; wire [6 : 0] y__h611, y__h836; wire IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33, IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42, @@ -117,34 +117,34 @@ module mkPktFork(pfk, arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi(.CLK(CLK), .RST_N(RST_N), .D_IN(fi$D_IN), - .ENQ(fi$ENQ), - .DEQ(fi$DEQ), .CLR(fi$CLR), + .DEQ(fi$DEQ), + .ENQ(fi$ENQ), .D_OUT(fi$D_OUT), - .FULL_N(fi$FULL_N), - .EMPTY_N(fi$EMPTY_N)); + .EMPTY_N(fi$EMPTY_N), + .FULL_N(fi$FULL_N)); // submodule fo0 arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fo0(.CLK(CLK), .RST_N(RST_N), .D_IN(fo0$D_IN), - .ENQ(fo0$ENQ), - .DEQ(fo0$DEQ), .CLR(fo0$CLR), + .DEQ(fo0$DEQ), + .ENQ(fo0$ENQ), .D_OUT(fo0$D_OUT), - .FULL_N(fo0$FULL_N), - .EMPTY_N(fo0$EMPTY_N)); + .EMPTY_N(fo0$EMPTY_N), + .FULL_N(fo0$FULL_N)); // submodule fo1 arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fo1(.CLK(CLK), .RST_N(RST_N), .D_IN(fo1$D_IN), - .ENQ(fo1$ENQ), - .DEQ(fo1$DEQ), .CLR(fo1$CLR), + .DEQ(fo1$DEQ), + .ENQ(fo1$ENQ), .D_OUT(fo1$D_OUT), - .FULL_N(fo1$FULL_N), - .EMPTY_N(fo1$EMPTY_N)); + .EMPTY_N(fo1$EMPTY_N), + .FULL_N(fo1$FULL_N)); // rule RL_fo0_advance assign WILL_FIRE_RL_fo0_advance = fo0$FULL_N && fi$EMPTY_N && f0Active ; @@ -164,17 +164,17 @@ module mkPktFork(pfk, // inputs to muxes for submodule ports assign MUX_f0Active$write_1__SEL_1 = WILL_FIRE_RL_select && - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 ; + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 ; assign MUX_f1Active$write_1__SEL_1 = WILL_FIRE_RL_select && - !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 ; + !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 ; // register f0Active assign f0Active$D_IN = MUX_f0Active$write_1__SEL_1 ? !fi$D_OUT[151] : !fi$D_OUT[151] ; assign f0Active$EN = WILL_FIRE_RL_select && - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 || + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 || WILL_FIRE_RL_fo0_advance ; // register f1Active @@ -182,34 +182,34 @@ module mkPktFork(pfk, MUX_f1Active$write_1__SEL_1 ? !fi$D_OUT[151] : !fi$D_OUT[151] ; assign f1Active$EN = WILL_FIRE_RL_select && - !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 || + !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 || WILL_FIRE_RL_fo1_advance ; // submodule fi assign fi$D_IN = iport_put ; - assign fi$ENQ = EN_iport_put ; + assign fi$CLR = 1'b0 ; assign fi$DEQ = WILL_FIRE_RL_select || WILL_FIRE_RL_fo1_advance || WILL_FIRE_RL_fo0_advance ; - assign fi$CLR = 1'b0 ; + assign fi$ENQ = EN_iport_put ; // submodule fo0 assign fo0$D_IN = fi$D_OUT ; + assign fo0$CLR = 1'b0 ; + assign fo0$DEQ = EN_oport0_get ; assign fo0$ENQ = WILL_FIRE_RL_select && - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 || + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 || WILL_FIRE_RL_fo0_advance ; - assign fo0$DEQ = EN_oport0_get ; - assign fo0$CLR = 1'b0 ; // submodule fo1 assign fo1$D_IN = fi$D_OUT ; + assign fo1$CLR = 1'b0 ; + assign fo1$DEQ = EN_oport1_get ; assign fo1$ENQ = WILL_FIRE_RL_select && - !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 || + !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 || WILL_FIRE_RL_fo1_advance ; - assign fo1$DEQ = EN_oport1_get ; - assign fo1$CLR = 1'b0 ; // remaining internal signals assign IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33 = @@ -222,7 +222,7 @@ module mkPktFork(pfk, pfk[11:8] == fi$D_OUT[60:57] ; assign fi_RDY_first_AND_IF_IF_pfk_BITS_13_TO_12_5_EQ__ETC___d47 = fi$EMPTY_N && - (IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 ? + (IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 ? fo0$FULL_N : fo1$FULL_N) ; assign fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d67 = @@ -238,17 +238,17 @@ module mkPktFork(pfk, begin case (pfk[13:12]) 2'd0: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 = + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 = fi$D_OUT[150:144] == y__h611; 2'd1: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 = + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 = fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d67 && fi$D_OUT[124:120] == 5'b01010; 2'd2: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 = + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 = IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33; 2'd3: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d58 = + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d62 = IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42; endcase end diff --git a/rtl/mkPktMerge.v b/rtl/mkPktMerge.v index 25bce469..199f27e9 100644 --- a/rtl/mkPktMerge.v +++ b/rtl/mkPktMerge.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:32 EDT 2012 +// On Mon Sep 24 13:39:04 EDT 2012 // // // Ports: @@ -118,34 +118,34 @@ module mkPktMerge(CLK, arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi0(.CLK(CLK), .RST_N(RST_N), .D_IN(fi0$D_IN), - .ENQ(fi0$ENQ), - .DEQ(fi0$DEQ), .CLR(fi0$CLR), + .DEQ(fi0$DEQ), + .ENQ(fi0$ENQ), .D_OUT(fi0$D_OUT), - .FULL_N(fi0$FULL_N), - .EMPTY_N(fi0$EMPTY_N)); + .EMPTY_N(fi0$EMPTY_N), + .FULL_N(fi0$FULL_N)); // submodule fi1 arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi1(.CLK(CLK), .RST_N(RST_N), .D_IN(fi1$D_IN), - .ENQ(fi1$ENQ), - .DEQ(fi1$DEQ), .CLR(fi1$CLR), + .DEQ(fi1$DEQ), + .ENQ(fi1$ENQ), .D_OUT(fi1$D_OUT), - .FULL_N(fi1$FULL_N), - .EMPTY_N(fi1$EMPTY_N)); + .EMPTY_N(fi1$EMPTY_N), + .FULL_N(fi1$FULL_N)); // submodule fo arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fo(.CLK(CLK), .RST_N(RST_N), .D_IN(fo$D_IN), - .ENQ(fo$ENQ), - .DEQ(fo$DEQ), .CLR(fo$CLR), + .DEQ(fo$DEQ), + .ENQ(fo$ENQ), .D_OUT(fo$D_OUT), - .FULL_N(fo$FULL_N), - .EMPTY_N(fo$EMPTY_N)); + .EMPTY_N(fo$EMPTY_N), + .FULL_N(fo$FULL_N)); // rule RL_arbitrate assign WILL_FIRE_RL_arbitrate = @@ -209,19 +209,19 @@ module mkPktMerge(CLK, // submodule fi0 assign fi0$D_IN = iport0_put ; - assign fi0$ENQ = EN_iport0_put ; + assign fi0$CLR = 1'b0 ; assign fi0$DEQ = WILL_FIRE_RL_arbitrate && fi0HasPrio || WILL_FIRE_RL_fi0_advance ; - assign fi0$CLR = 1'b0 ; + assign fi0$ENQ = EN_iport0_put ; // submodule fi1 assign fi1$D_IN = iport1_put ; - assign fi1$ENQ = EN_iport1_put ; + assign fi1$CLR = 1'b0 ; assign fi1$DEQ = WILL_FIRE_RL_arbitrate && !fi0HasPrio || WILL_FIRE_RL_fi1_advance ; - assign fi1$CLR = 1'b0 ; + assign fi1$ENQ = EN_iport1_put ; // submodule fo always@(WILL_FIRE_RL_arbitrate or @@ -237,11 +237,11 @@ module mkPktMerge(CLK, 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end + assign fo$CLR = 1'b0 ; + assign fo$DEQ = EN_oport_get ; assign fo$ENQ = WILL_FIRE_RL_arbitrate || WILL_FIRE_RL_fi0_advance || WILL_FIRE_RL_fi1_advance ; - assign fo$DEQ = EN_oport_get ; - assign fo$CLR = 1'b0 ; // remaining internal signals assign fo_RDY_enq_AND_IF_fi0HasPrio_2_THEN_fi0_RDY_de_ETC___d24 = diff --git a/rtl/mkQABSMF.v b/rtl/mkQABSMF.v index c5530789..71595a7a 100644 --- a/rtl/mkQABSMF.v +++ b/rtl/mkQABSMF.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:44:10 EDT 2012 +// On Mon Sep 24 13:37:52 EDT 2012 // // // Ports: @@ -209,10 +209,10 @@ module mkQABSMF(et0, MUX_merge_fi1Active$write_1__VAL_2; // remaining internal signals - reg [7 : 0] IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d692, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d691, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d690, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d693; + reg [7 : 0] IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727, + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726, + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725, + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728; reg [1 : 0] CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q51, CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q50, CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q49, @@ -269,9 +269,9 @@ module mkQABSMF(et0, CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q19, CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q20, CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q21; - wire [39 : 0] IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d694; + wire [39 : 0] IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d729; wire [19 : 0] IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d136; - wire [15 : 0] seen__h10682; + wire [15 : 0] seen__h10467; wire [9 : 0] IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d395, IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d396, IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d397, @@ -288,19 +288,19 @@ module mkQABSMF(et0, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d134, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d145, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d155; - wire [7 : 0] IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d686, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d687, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d688, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689; - wire [2 : 0] frk_ptr_08_PLUS_1___d749; + wire [7 : 0] IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d721, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d722, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d723, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d724; + wire [2 : 0] frk_ptr_08_PLUS_1___d783; wire [1 : 0] IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d122, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d132, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d153; - wire IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d865, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d866, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d867, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d875, + wire IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d898, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d899, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d900, NOT_frk_stageSent_16_17_OR_frk_srcF_i_notEmpty_ETC___d323, merge_fo_i_notFull_AND_IF_merge_fi0HasPrio_06__ETC___d108; @@ -465,18 +465,18 @@ module mkQABSMF(et0, assign MUX_merge_fi1Active$write_1__SEL_1 = WILL_FIRE_RL_merge_arbitrate && !merge_fi0HasPrio ; assign MUX_frk_ptr$write_1__VAL_1 = - frk_stageSent ? 3'd0 : frk_ptr_08_PLUS_1___d749 ; + frk_stageSent ? 3'd0 : frk_ptr_08_PLUS_1___d783 ; assign MUX_frk_ptr$write_1__VAL_2 = (frk_srcF$D_OUT[9:8] != 2'd0 || frk_srcF$D_OUT[19:18] != 2'd0 || frk_srcF$D_OUT[29:28] != 2'd0 || frk_srcF$D_OUT[39:38] != 2'd0) ? 3'd0 : - frk_ptr_08_PLUS_1___d749 ; + frk_ptr_08_PLUS_1___d783 ; assign MUX_merge_fi0Active$write_1__VAL_1 = - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d867 && - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d866 && - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d865 && - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d875 ; + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d900 && + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d899 && + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d898 && + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689 ; assign MUX_merge_fi0Active$write_1__VAL_2 = merge_fi0$D_OUT[9:8] == 2'd0 && merge_fi0$D_OUT[19:18] == 2'd0 && merge_fi0$D_OUT[29:28] == 2'd0 && @@ -505,13 +505,13 @@ module mkQABSMF(et0, merge_fi1$D_OUT[7:0] } ; assign MUX_merge_fo$enq_1__VAL_3 = { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d136, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d866 ? + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d899 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d688 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d723 } : IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d145, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d867 ? + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d900 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d724 } : IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d155 } ; // register frk_decided @@ -524,7 +524,7 @@ module mkQABSMF(et0, WILL_FIRE_RL_frk_decide ; // register frk_match0 - assign frk_match0$D_IN = et0 == seen__h10682 ; + assign frk_match0$D_IN = et0 == seen__h10467 ; assign frk_match0$EN = WILL_FIRE_RL_frk_decide ; // register frk_ptr @@ -551,7 +551,7 @@ module mkQABSMF(et0, // register frk_sr assign frk_sr$D_IN = - { IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d694, + { IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d729, CASE_frk_sr_BITS_119_TO_118_3_0_frk_sr_BITS_11_ETC__q37, frk_sr[117:110], CASE_frk_sr_BITS_109_TO_108_3_0_frk_sr_BITS_10_ETC__q38, @@ -621,7 +621,7 @@ module mkQABSMF(et0, // submodule frk_d0F assign frk_d0F$D_IN = frk_stageSent ? - IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d694 : + IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d729 : { IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d350, IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d373, IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d397, @@ -712,61 +712,61 @@ module mkQABSMF(et0, { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q19 ? 2'd2 : 2'd3, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d692 } ; + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 } ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d396 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q20 ? { 2'd1, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d692 } : + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 } : IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d395 ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d397 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q21 ? { 2'd0, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d692 } : + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 } : IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_1_ETC___d396 ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d371 = { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q13 ? 2'd2 : 2'd3, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d691 } ; + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 } ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d372 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q14 ? { 2'd1, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d691 } : + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 } : IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d371 ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d373 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q15 ? { 2'd0, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d691 } : + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 } : IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_2_ETC___d372 ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d348 = { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q16 ? 2'd2 : 2'd3, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d690 } ; + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 } ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d349 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q17 ? { 2'd1, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d690 } : + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 } : IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d348 ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d350 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q18 ? { 2'd0, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d690 } : + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 } : IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_3_ETC___d349 ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d418 = { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q22 ? 2'd2 : 2'd3, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d693 } ; + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 } ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d419 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q23 ? { 2'd1, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d693 } : + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 } : IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d418 ; assign IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d420 = CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q24 ? { 2'd0, - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d693 } : + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 } : IF_IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_9_ETC___d419 ; assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d122 = (merge_fi0HasPrio ? @@ -779,9 +779,9 @@ module mkQABSMF(et0, merge_fi0$D_OUT[39:38] == 2'd1 : merge_fi1$D_OUT[39:38] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d686 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d721 } : { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d122, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d686 } ; + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d721 } ; assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d132 = (merge_fi0HasPrio ? merge_fi0$D_OUT[29:28] == 2'd2 : @@ -793,17 +793,17 @@ module mkQABSMF(et0, merge_fi0$D_OUT[29:28] == 2'd1 : merge_fi1$D_OUT[29:28] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d687 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d722 } : { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d132, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d687 } ; + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d722 } ; assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d136 = - { IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d875 ? + { IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d686 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d721 } : IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d124, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d865 ? + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d898 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d687 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d722 } : IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d134 } ; assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143 = (merge_fi0HasPrio ? @@ -816,9 +816,9 @@ module mkQABSMF(et0, merge_fi0$D_OUT[19:18] == 2'd1 : merge_fi1$D_OUT[19:18] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d688 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d723 } : { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d688 } ; + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d723 } ; assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d153 = (merge_fi0HasPrio ? merge_fi0$D_OUT[9:8] == 2'd2 : @@ -830,10 +830,10 @@ module mkQABSMF(et0, merge_fi0$D_OUT[9:8] == 2'd1 : merge_fi1$D_OUT[9:8] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d724 } : { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d153, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689 } ; - assign IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d694 = + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d724 } ; + assign IF_frk_srcF_first__68_BITS_39_TO_38_69_EQ_0_70_ETC___d729 = { CASE_frk_srcFD_OUT_BITS_39_TO_38_3_0_frk_srcF_ETC__q25, frk_srcF$D_OUT[37:30], CASE_frk_srcFD_OUT_BITS_29_TO_28_3_0_frk_srcF_ETC__q26, @@ -842,44 +842,44 @@ module mkQABSMF(et0, frk_srcF$D_OUT[17:10], CASE_frk_srcFD_OUT_BITS_9_TO_8_3_0_frk_srcFD_ETC__q28, frk_srcF$D_OUT[7:0] } ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d686 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689 = + merge_fi0HasPrio ? + merge_fi0$D_OUT[39:38] == 2'd0 : + merge_fi1$D_OUT[39:38] == 2'd0 ; + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d721 = merge_fi0HasPrio ? merge_fi0$D_OUT[37:30] : merge_fi1$D_OUT[37:30] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d687 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d722 = merge_fi0HasPrio ? merge_fi0$D_OUT[27:20] : merge_fi1$D_OUT[27:20] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d688 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d723 = merge_fi0HasPrio ? merge_fi0$D_OUT[17:10] : merge_fi1$D_OUT[17:10] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d689 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d724 = merge_fi0HasPrio ? merge_fi0$D_OUT[7:0] : merge_fi1$D_OUT[7:0] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d865 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d898 = merge_fi0HasPrio ? merge_fi0$D_OUT[29:28] == 2'd0 : merge_fi1$D_OUT[29:28] == 2'd0 ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d866 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d899 = merge_fi0HasPrio ? merge_fi0$D_OUT[19:18] == 2'd0 : merge_fi1$D_OUT[19:18] == 2'd0 ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d867 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d900 = merge_fi0HasPrio ? merge_fi0$D_OUT[9:8] == 2'd0 : merge_fi1$D_OUT[9:8] == 2'd0 ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d875 = - merge_fi0HasPrio ? - merge_fi0$D_OUT[39:38] == 2'd0 : - merge_fi1$D_OUT[39:38] == 2'd0 ; assign NOT_frk_stageSent_16_17_OR_frk_srcF_i_notEmpty_ETC___d323 = (!frk_stageSent || frk_srcF$EMPTY_N) && (frk_match0 ? frk_d0F$FULL_N : frk_d1F$FULL_N) ; - assign frk_ptr_08_PLUS_1___d749 = frk_ptr + 3'd1 ; + assign frk_ptr_08_PLUS_1___d783 = frk_ptr + 3'd1 ; assign merge_fo_i_notFull_AND_IF_merge_fi0HasPrio_06__ETC___d108 = merge_fo$FULL_N && (merge_fi0HasPrio ? merge_fi0$EMPTY_N : merge_fi1$EMPTY_N) ; - assign seen__h10682 = { frk_srcF$D_OUT[7:0], frk_srcF$D_OUT[17:10] } ; + assign seen__h10467 = { frk_srcF$D_OUT[7:0], frk_srcF$D_OUT[17:10] } ; always@(frk_d1F$D_OUT) begin case (frk_d1F$D_OUT[39:38]) @@ -992,12 +992,12 @@ module mkQABSMF(et0, begin case (frk_ptr) 3'd0: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d691 = + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 = frk_sr[27:20]; 3'd1: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d691 = + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 = frk_sr[67:60]; - default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d691 = + default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_27_T_ETC___d726 = frk_sr[107:100]; endcase end @@ -1044,12 +1044,12 @@ module mkQABSMF(et0, begin case (frk_ptr) 3'd0: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d690 = + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 = frk_sr[37:30]; 3'd1: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d690 = + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 = frk_sr[77:70]; - default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d690 = + default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_37_T_ETC___d725 = frk_sr[117:110]; endcase end @@ -1096,12 +1096,12 @@ module mkQABSMF(et0, begin case (frk_ptr) 3'd0: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d692 = + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 = frk_sr[17:10]; 3'd1: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d692 = + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 = frk_sr[57:50]; - default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d692 = + default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_17_T_ETC___d727 = frk_sr[97:90]; endcase end @@ -1148,12 +1148,12 @@ module mkQABSMF(et0, begin case (frk_ptr) 3'd0: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d693 = + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 = frk_sr[7:0]; 3'd1: - IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d693 = + IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 = frk_sr[47:40]; - default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d693 = + default: IF_frk_ptr_08_EQ_0_26_THEN_frk_sr_12_BITS_7_TO_ETC___d728 = frk_sr[87:80]; endcase end diff --git a/rtl/mkQABSMF3.v b/rtl/mkQABSMF3.v index a56a1089..4d97b440 100644 --- a/rtl/mkQABSMF3.v +++ b/rtl/mkQABSMF3.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:44:12 EDT 2012 +// On Mon Sep 24 13:37:51 EDT 2012 // // // Ports: @@ -356,14 +356,14 @@ module mkQABSMF3(et0, MUX_merge1_fi1Active$write_1__VAL_2; // remaining internal signals - reg [7 : 0] IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1324, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1325, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1326, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1327, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1328, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1329, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1330, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1331; + reg [7 : 0] IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301, + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302, + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303, + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304, + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305, + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306, + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307, + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308; reg [1 : 0] CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q91, CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q90, CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q89, @@ -376,10 +376,10 @@ module mkQABSMF3(et0, CASE_client2_response_put_BITS_29_TO_28_3_0_cl_ETC__q102, CASE_client2_response_put_BITS_39_TO_38_3_0_cl_ETC__q101, CASE_client2_response_put_BITS_9_TO_8_3_0_clie_ETC__q104, - CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q7, - CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q6, - CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q5, - CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q8, + CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q11, + CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q10, + CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q9, + CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q12, CASE_fork0_d1FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q87, CASE_fork0_d1FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q86, CASE_fork0_d1FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q85, @@ -396,14 +396,14 @@ module mkQABSMF3(et0, CASE_fork0_srcFD_OUT_BITS_29_TO_28_3_0_fork0__ETC__q42, CASE_fork0_srcFD_OUT_BITS_39_TO_38_3_0_fork0__ETC__q41, CASE_fork0_srcFD_OUT_BITS_9_TO_8_3_0_fork0_sr_ETC__q44, - CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3, - CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2, - CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1, - CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q4, - CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q15, - CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q14, - CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q13, - CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q16, + CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q7, + CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q6, + CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q5, + CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q8, + CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3, + CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2, + CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1, + CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q4, CASE_fork1_sr_BITS_109_TO_108_3_0_fork1_sr_BIT_ETC__q78, CASE_fork1_sr_BITS_119_TO_118_3_0_fork1_sr_BIT_ETC__q77, CASE_fork1_sr_BITS_49_TO_48_3_0_fork1_sr_BITS__ETC__q84, @@ -424,10 +424,10 @@ module mkQABSMF3(et0, CASE_merge0_fi1D_OUT_BITS_29_TO_28_3_0_merge0_ETC__q54, CASE_merge0_fi1D_OUT_BITS_39_TO_38_3_0_merge0_ETC__q53, CASE_merge0_fi1D_OUT_BITS_9_TO_8_3_0_merge0_f_ETC__q56, - CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q11, - CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q10, - CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q9, - CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q12, + CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q15, + CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q14, + CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q13, + CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q16, CASE_merge1_fi0D_OUT_BITS_19_TO_18_3_0_merge1_ETC__q59, CASE_merge1_fi0D_OUT_BITS_29_TO_28_3_0_merge1_ETC__q58, CASE_merge1_fi0D_OUT_BITS_39_TO_38_3_0_merge1_ETC__q57, @@ -468,11 +468,11 @@ module mkQABSMF3(et0, CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q38, CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q39, CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q40; - wire [39 : 0] IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1332, - IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1333; + wire [39 : 0] IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1309, + IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1310; wire [19 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d136, IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d296; - wire [15 : 0] seen__h15791, seen__h26359; + wire [15 : 0] seen__h16118, seen__h26918; wire [9 : 0] IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d508, IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d509, IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d510, @@ -505,15 +505,15 @@ module mkQABSMF3(et0, IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d294, IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d305, IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d315; - wire [7 : 0] IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1316, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1317, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1318, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1319, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1320, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1321, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1322, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1323; - wire [2 : 0] fork0_ptr_68_PLUS_1___d1429, fork1_ptr_35_PLUS_1___d1430; + wire [7 : 0] IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1293, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1294, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1295, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1296, + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1297, + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1298, + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1299, + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1300; + wire [2 : 0] fork0_ptr_68_PLUS_1___d1411, fork1_ptr_35_PLUS_1___d1412; wire [1 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d122, IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d132, IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143, @@ -522,14 +522,14 @@ module mkQABSMF3(et0, IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d292, IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d303, IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d313; - wire IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1300, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1313, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1642, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1643, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1305, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1645, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1646, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1647, + wire IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1626, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1627, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1628, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648, + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1630, + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1631, + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1632, + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1649, NOT_fork0_stageSent_76_77_OR_fork0_srcF_i_notE_ETC___d483, NOT_fork1_stageSent_43_44_OR_fork1_srcF_i_notE_ETC___d750, merge0_fo_i_notFull_AND_IF_merge0_fi0HasPrio_0_ETC___d108, @@ -540,25 +540,25 @@ module mkQABSMF3(et0, // actionvalue method server_response_get assign server_response_get = - { CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q9, + { CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q13, merge0_fo$D_OUT[37:30], - CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q10, + CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q14, merge0_fo$D_OUT[27:20], - CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q11, + CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q15, merge0_fo$D_OUT[17:10], - CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q12, + CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q16, merge0_fo$D_OUT[7:0] } ; assign RDY_server_response_get = merge0_fo$EMPTY_N ; // actionvalue method client0_request_get assign client0_request_get = - { CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q5, + { CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q9, fork0_d0F$D_OUT[37:30], - CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q6, + CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q10, fork0_d0F$D_OUT[27:20], - CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q7, + CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q11, fork0_d0F$D_OUT[17:10], - CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q8, + CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q12, fork0_d0F$D_OUT[7:0] } ; assign RDY_client0_request_get = fork0_d0F$EMPTY_N ; @@ -567,13 +567,13 @@ module mkQABSMF3(et0, // actionvalue method client1_request_get assign client1_request_get = - { CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1, + { CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q5, fork1_d0F$D_OUT[37:30], - CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2, + CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q6, fork1_d0F$D_OUT[27:20], - CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3, + CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q7, fork1_d0F$D_OUT[17:10], - CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q4, + CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q8, fork1_d0F$D_OUT[7:0] } ; assign RDY_client1_request_get = fork1_d0F$EMPTY_N ; @@ -582,13 +582,13 @@ module mkQABSMF3(et0, // actionvalue method client2_request_get assign client2_request_get = - { CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q13, + { CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1, fork1_d1F$D_OUT[37:30], - CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q14, + CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2, fork1_d1F$D_OUT[27:20], - CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q15, + CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3, fork1_d1F$D_OUT[17:10], - CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q16, + CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q4, fork1_d1F$D_OUT[7:0] } ; assign RDY_client2_request_get = fork1_d1F$EMPTY_N ; @@ -829,28 +829,28 @@ module mkQABSMF3(et0, assign MUX_merge1_fi1Active$write_1__SEL_1 = WILL_FIRE_RL_merge1_arbitrate && !merge1_fi0HasPrio ; assign MUX_fork0_ptr$write_1__VAL_1 = - fork0_stageSent ? 3'd0 : fork0_ptr_68_PLUS_1___d1429 ; + fork0_stageSent ? 3'd0 : fork0_ptr_68_PLUS_1___d1411 ; assign MUX_fork0_ptr$write_1__VAL_2 = (fork0_srcF$D_OUT[9:8] != 2'd0 || fork0_srcF$D_OUT[19:18] != 2'd0 || fork0_srcF$D_OUT[29:28] != 2'd0 || fork0_srcF$D_OUT[39:38] != 2'd0) ? 3'd0 : - fork0_ptr_68_PLUS_1___d1429 ; + fork0_ptr_68_PLUS_1___d1411 ; assign MUX_fork1_ptr$write_1__VAL_1 = - fork1_stageSent ? 3'd0 : fork1_ptr_35_PLUS_1___d1430 ; + fork1_stageSent ? 3'd0 : fork1_ptr_35_PLUS_1___d1412 ; assign MUX_fork1_ptr$write_1__VAL_2 = (fork1_srcF$D_OUT[9:8] != 2'd0 || fork1_srcF$D_OUT[19:18] != 2'd0 || fork1_srcF$D_OUT[29:28] != 2'd0 || fork1_srcF$D_OUT[39:38] != 2'd0) ? 3'd0 : - fork1_ptr_35_PLUS_1___d1430 ; + fork1_ptr_35_PLUS_1___d1412 ; assign MUX_merge0_fi0Active$write_1__VAL_1 = - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1643 && - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1642 && - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1300 && - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1313 ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1628 && + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1627 && + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1626 && + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648 ; assign MUX_merge0_fi0Active$write_1__VAL_2 = merge0_fi0$D_OUT[9:8] == 2'd0 && merge0_fi0$D_OUT[19:18] == 2'd0 && @@ -881,19 +881,19 @@ module mkQABSMF3(et0, merge0_fi1$D_OUT[7:0] } ; assign MUX_merge0_fo$enq_1__VAL_3 = { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d136, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1642 ? + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1627 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1318 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1295 } : IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1643 ? + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1628 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1319 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1296 } : IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d155 } ; assign MUX_merge1_fi0Active$write_1__VAL_1 = - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1647 && - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1646 && - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1645 && - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1305 ; + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1632 && + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1631 && + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1630 && + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1649 ; assign MUX_merge1_fi0Active$write_1__VAL_2 = merge1_fi0$D_OUT[9:8] == 2'd0 && merge1_fi0$D_OUT[19:18] == 2'd0 && @@ -924,13 +924,13 @@ module mkQABSMF3(et0, merge1_fi1$D_OUT[7:0] } ; assign MUX_merge1_fo$enq_1__VAL_3 = { IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d296, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1646 ? + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1631 ? { 2'd0, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1322 } : + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1299 } : IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d305, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1647 ? + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1632 ? { 2'd0, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1323 } : + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1300 } : IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d315 } ; // register fork0_decided @@ -944,7 +944,7 @@ module mkQABSMF3(et0, WILL_FIRE_RL_fork0_decide ; // register fork0_match0 - assign fork0_match0$D_IN = et0 == seen__h15791 ; + assign fork0_match0$D_IN = et0 == seen__h16118 ; assign fork0_match0$EN = WILL_FIRE_RL_fork0_decide ; // register fork0_ptr @@ -973,7 +973,7 @@ module mkQABSMF3(et0, // register fork0_sr assign fork0_sr$D_IN = - { IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1332, + { IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1309, CASE_fork0_sr_BITS_119_TO_118_3_0_fork0_sr_BIT_ETC__q65, fork0_sr[117:110], CASE_fork0_sr_BITS_109_TO_108_3_0_fork0_sr_BIT_ETC__q66, @@ -1018,7 +1018,7 @@ module mkQABSMF3(et0, WILL_FIRE_RL_fork1_decide ; // register fork1_match0 - assign fork1_match0$D_IN = did == seen__h26359 ; + assign fork1_match0$D_IN = did == seen__h26918 ; assign fork1_match0$EN = WILL_FIRE_RL_fork1_decide ; // register fork1_ptr @@ -1047,7 +1047,7 @@ module mkQABSMF3(et0, // register fork1_sr assign fork1_sr$D_IN = - { IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1333, + { IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1310, CASE_fork1_sr_BITS_119_TO_118_3_0_fork1_sr_BIT_ETC__q77, fork1_sr[117:110], CASE_fork1_sr_BITS_109_TO_108_3_0_fork1_sr_BIT_ETC__q78, @@ -1156,7 +1156,7 @@ module mkQABSMF3(et0, // submodule fork0_d0F assign fork0_d0F$D_IN = fork0_stageSent ? - IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1332 : + IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1309 : { IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d510, IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d533, IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d557, @@ -1190,7 +1190,7 @@ module mkQABSMF3(et0, // submodule fork1_d0F assign fork1_d0F$D_IN = fork1_stageSent ? - IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1333 : + IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1310 : { IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d777, IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d800, IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d824, @@ -1338,121 +1338,121 @@ module mkQABSMF3(et0, { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q17 ? 2'd2 : 2'd3, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1324 } ; + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 } ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d509 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q18 ? { 2'd1, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1324 } : + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 } : IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d508 ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d510 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q19 ? { 2'd0, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1324 } : + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 } : IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d509 ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d531 = { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q20 ? 2'd2 : 2'd3, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1325 } ; + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 } ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d532 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q21 ? { 2'd1, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1325 } : + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 } : IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d531 ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d533 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q22 ? { 2'd0, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1325 } : + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 } : IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d532 ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d555 = { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q23 ? 2'd2 : 2'd3, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1326 } ; + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 } ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d556 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q24 ? { 2'd1, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1326 } : + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 } : IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d555 ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d557 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q25 ? { 2'd0, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1326 } : + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 } : IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d556 ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d578 = { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q26 ? 2'd2 : 2'd3, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1327 } ; + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 } ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d579 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q27 ? { 2'd1, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1327 } : + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 } : IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d578 ; assign IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d580 = CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q28 ? { 2'd0, - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1327 } : + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 } : IF_IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BI_ETC___d579 ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d775 = { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q29 ? 2'd2 : 2'd3, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1328 } ; + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 } ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d776 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q30 ? { 2'd1, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1328 } : + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 } : IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d775 ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d777 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q31 ? { 2'd0, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1328 } : + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 } : IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d776 ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d798 = { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q32 ? 2'd2 : 2'd3, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1329 } ; + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 } ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d799 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q33 ? { 2'd1, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1329 } : + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 } : IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d798 ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d800 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q34 ? { 2'd0, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1329 } : + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 } : IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d799 ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d822 = { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q35 ? 2'd2 : 2'd3, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1330 } ; + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 } ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d823 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q36 ? { 2'd1, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1330 } : + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 } : IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d822 ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d824 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q37 ? { 2'd0, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1330 } : + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 } : IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d823 ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d845 = { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q38 ? 2'd2 : 2'd3, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1331 } ; + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 } ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d846 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q39 ? { 2'd1, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1331 } : + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 } : IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d845 ; assign IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d847 = CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q40 ? { 2'd0, - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1331 } : + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 } : IF_IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BI_ETC___d846 ; assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d122 = (merge0_fi0HasPrio ? @@ -1465,9 +1465,9 @@ module mkQABSMF3(et0, merge0_fi0$D_OUT[39:38] == 2'd1 : merge0_fi1$D_OUT[39:38] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1316 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1293 } : { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d122, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1316 } ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1293 } ; assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d132 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[29:28] == 2'd2 : @@ -1479,17 +1479,17 @@ module mkQABSMF3(et0, merge0_fi0$D_OUT[29:28] == 2'd1 : merge0_fi1$D_OUT[29:28] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1317 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1294 } : { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d132, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1317 } ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1294 } ; assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d136 = - { IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1313 ? + { IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1316 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1293 } : IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d124, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1300 ? + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1626 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1317 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1294 } : IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d134 } ; assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143 = (merge0_fi0HasPrio ? @@ -1502,9 +1502,9 @@ module mkQABSMF3(et0, merge0_fi0$D_OUT[19:18] == 2'd1 : merge0_fi1$D_OUT[19:18] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1318 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1295 } : { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1318 } ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1295 } ; assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d153 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[9:8] == 2'd2 : @@ -1516,9 +1516,9 @@ module mkQABSMF3(et0, merge0_fi0$D_OUT[9:8] == 2'd1 : merge0_fi1$D_OUT[9:8] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1319 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1296 } : { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d153, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1319 } ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1296 } ; assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d282 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[39:38] == 2'd2 : @@ -1530,9 +1530,9 @@ module mkQABSMF3(et0, merge1_fi0$D_OUT[39:38] == 2'd1 : merge1_fi1$D_OUT[39:38] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1320 } : + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1297 } : { IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d282, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1320 } ; + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1297 } ; assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d292 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[29:28] == 2'd2 : @@ -1544,17 +1544,17 @@ module mkQABSMF3(et0, merge1_fi0$D_OUT[29:28] == 2'd1 : merge1_fi1$D_OUT[29:28] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1321 } : + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1298 } : { IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d292, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1321 } ; + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1298 } ; assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d296 = - { IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1305 ? + { IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1649 ? { 2'd0, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1320 } : + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1297 } : IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d284, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1645 ? + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1630 ? { 2'd0, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1321 } : + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1298 } : IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d294 } ; assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d303 = (merge1_fi0HasPrio ? @@ -1567,9 +1567,9 @@ module mkQABSMF3(et0, merge1_fi0$D_OUT[19:18] == 2'd1 : merge1_fi1$D_OUT[19:18] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1322 } : + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1299 } : { IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d303, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1322 } ; + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1299 } ; assign IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d313 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[9:8] == 2'd2 : @@ -1581,10 +1581,10 @@ module mkQABSMF3(et0, merge1_fi0$D_OUT[9:8] == 2'd1 : merge1_fi1$D_OUT[9:8] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1323 } : + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1300 } : { IF_IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_fir_ETC___d313, - IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1323 } ; - assign IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1332 = + IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1300 } ; + assign IF_fork0_srcF_first__28_BITS_39_TO_38_29_EQ_0__ETC___d1309 = { CASE_fork0_srcFD_OUT_BITS_39_TO_38_3_0_fork0__ETC__q41, fork0_srcF$D_OUT[37:30], CASE_fork0_srcFD_OUT_BITS_29_TO_28_3_0_fork0__ETC__q42, @@ -1593,7 +1593,7 @@ module mkQABSMF3(et0, fork0_srcF$D_OUT[17:10], CASE_fork0_srcFD_OUT_BITS_9_TO_8_3_0_fork0_sr_ETC__q44, fork0_srcF$D_OUT[7:0] } ; - assign IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1333 = + assign IF_fork1_srcF_first__95_BITS_39_TO_38_96_EQ_0__ETC___d1310 = { CASE_fork1_srcFD_OUT_BITS_39_TO_38_3_0_fork1__ETC__q45, fork1_srcF$D_OUT[37:30], CASE_fork1_srcFD_OUT_BITS_29_TO_28_3_0_fork1__ETC__q46, @@ -1602,240 +1602,240 @@ module mkQABSMF3(et0, fork1_srcF$D_OUT[17:10], CASE_fork1_srcFD_OUT_BITS_9_TO_8_3_0_fork1_sr_ETC__q48, fork1_srcF$D_OUT[7:0] } ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1300 = - merge0_fi0HasPrio ? - merge0_fi0$D_OUT[29:28] == 2'd0 : - merge0_fi1$D_OUT[29:28] == 2'd0 ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1313 = - merge0_fi0HasPrio ? - merge0_fi0$D_OUT[39:38] == 2'd0 : - merge0_fi1$D_OUT[39:38] == 2'd0 ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1316 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1293 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[37:30] : merge0_fi1$D_OUT[37:30] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1317 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1294 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[27:20] : merge0_fi1$D_OUT[27:20] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1318 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1295 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[17:10] : merge0_fi1$D_OUT[17:10] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1319 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1296 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[7:0] : merge0_fi1$D_OUT[7:0] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1642 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1626 = + merge0_fi0HasPrio ? + merge0_fi0$D_OUT[29:28] == 2'd0 : + merge0_fi1$D_OUT[29:28] == 2'd0 ; + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1627 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[19:18] == 2'd0 : merge0_fi1$D_OUT[19:18] == 2'd0 ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1643 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1628 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[9:8] == 2'd0 : merge0_fi1$D_OUT[9:8] == 2'd0 ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1305 = - merge1_fi0HasPrio ? - merge1_fi0$D_OUT[39:38] == 2'd0 : - merge1_fi1$D_OUT[39:38] == 2'd0 ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1320 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1648 = + merge0_fi0HasPrio ? + merge0_fi0$D_OUT[39:38] == 2'd0 : + merge0_fi1$D_OUT[39:38] == 2'd0 ; + assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1297 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[37:30] : merge1_fi1$D_OUT[37:30] ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1321 = + assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1298 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[27:20] : merge1_fi1$D_OUT[27:20] ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1322 = + assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1299 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[17:10] : merge1_fi1$D_OUT[17:10] ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1323 = + assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1300 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[7:0] : merge1_fi1$D_OUT[7:0] ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1645 = + assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1630 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[29:28] == 2'd0 : merge1_fi1$D_OUT[29:28] == 2'd0 ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1646 = + assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1631 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[19:18] == 2'd0 : merge1_fi1$D_OUT[19:18] == 2'd0 ; - assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1647 = + assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1632 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[9:8] == 2'd0 : merge1_fi1$D_OUT[9:8] == 2'd0 ; + assign IF_merge1_fi0HasPrio_66_THEN_merge1_fi0_first__ETC___d1649 = + merge1_fi0HasPrio ? + merge1_fi0$D_OUT[39:38] == 2'd0 : + merge1_fi1$D_OUT[39:38] == 2'd0 ; assign NOT_fork0_stageSent_76_77_OR_fork0_srcF_i_notE_ETC___d483 = (!fork0_stageSent || fork0_srcF$EMPTY_N) && (fork0_match0 ? fork0_d0F$FULL_N : fork0_d1F$FULL_N) ; assign NOT_fork1_stageSent_43_44_OR_fork1_srcF_i_notE_ETC___d750 = (!fork1_stageSent || fork1_srcF$EMPTY_N) && (fork1_match0 ? fork1_d0F$FULL_N : fork1_d1F$FULL_N) ; - assign fork0_ptr_68_PLUS_1___d1429 = fork0_ptr + 3'd1 ; - assign fork1_ptr_35_PLUS_1___d1430 = fork1_ptr + 3'd1 ; + assign fork0_ptr_68_PLUS_1___d1411 = fork0_ptr + 3'd1 ; + assign fork1_ptr_35_PLUS_1___d1412 = fork1_ptr + 3'd1 ; assign merge0_fo_i_notFull_AND_IF_merge0_fi0HasPrio_0_ETC___d108 = merge0_fo$FULL_N && (merge0_fi0HasPrio ? merge0_fi0$EMPTY_N : merge0_fi1$EMPTY_N) ; assign merge1_fo_i_notFull__62_AND_IF_merge1_fi0HasPr_ETC___d268 = merge1_fo$FULL_N && (merge1_fi0HasPrio ? merge1_fi0$EMPTY_N : merge1_fi1$EMPTY_N) ; - assign seen__h15791 = { fork0_srcF$D_OUT[7:0], fork0_srcF$D_OUT[17:10] } ; - assign seen__h26359 = { fork1_srcF$D_OUT[27:20], fork1_srcF$D_OUT[37:30] } ; + assign seen__h16118 = { fork0_srcF$D_OUT[7:0], fork0_srcF$D_OUT[17:10] } ; + assign seen__h26918 = { fork1_srcF$D_OUT[27:20], fork1_srcF$D_OUT[37:30] } ; + always@(fork1_d1F$D_OUT) + begin + case (fork1_d1F$D_OUT[39:38]) + 2'd0, 2'd1, 2'd2: + CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1 = + fork1_d1F$D_OUT[39:38]; + 2'd3: CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1 = 2'd3; + endcase + end + always@(fork1_d1F$D_OUT) + begin + case (fork1_d1F$D_OUT[29:28]) + 2'd0, 2'd1, 2'd2: + CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2 = + fork1_d1F$D_OUT[29:28]; + 2'd3: CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2 = 2'd3; + endcase + end + always@(fork1_d1F$D_OUT) + begin + case (fork1_d1F$D_OUT[19:18]) + 2'd0, 2'd1, 2'd2: + CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3 = + fork1_d1F$D_OUT[19:18]; + 2'd3: CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3 = 2'd3; + endcase + end + always@(fork1_d1F$D_OUT) + begin + case (fork1_d1F$D_OUT[9:8]) + 2'd0, 2'd1, 2'd2: + CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q4 = + fork1_d1F$D_OUT[9:8]; + 2'd3: CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q4 = 2'd3; + endcase + end always@(fork1_d0F$D_OUT) begin case (fork1_d0F$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1 = + CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q5 = fork1_d0F$D_OUT[39:38]; - 2'd3: CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1 = 2'd3; + 2'd3: CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q5 = 2'd3; endcase end always@(fork1_d0F$D_OUT) begin case (fork1_d0F$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2 = + CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q6 = fork1_d0F$D_OUT[29:28]; - 2'd3: CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2 = 2'd3; + 2'd3: CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q6 = 2'd3; endcase end always@(fork1_d0F$D_OUT) begin case (fork1_d0F$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3 = + CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q7 = fork1_d0F$D_OUT[19:18]; - 2'd3: CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3 = 2'd3; + 2'd3: CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q7 = 2'd3; endcase end always@(fork1_d0F$D_OUT) begin case (fork1_d0F$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q4 = + CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q8 = fork1_d0F$D_OUT[9:8]; - 2'd3: CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q4 = 2'd3; + 2'd3: CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q8 = 2'd3; endcase end always@(fork0_d0F$D_OUT) begin case (fork0_d0F$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q5 = + CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q9 = fork0_d0F$D_OUT[39:38]; - 2'd3: CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q5 = 2'd3; + 2'd3: CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q9 = 2'd3; endcase end always@(fork0_d0F$D_OUT) begin case (fork0_d0F$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q6 = + CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q10 = fork0_d0F$D_OUT[29:28]; - 2'd3: CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q6 = 2'd3; + 2'd3: CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q10 = 2'd3; endcase end always@(fork0_d0F$D_OUT) begin case (fork0_d0F$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q7 = + CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q11 = fork0_d0F$D_OUT[19:18]; - 2'd3: CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q7 = 2'd3; + 2'd3: CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q11 = 2'd3; endcase end always@(fork0_d0F$D_OUT) begin case (fork0_d0F$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q8 = + CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q12 = fork0_d0F$D_OUT[9:8]; - 2'd3: CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q8 = 2'd3; + 2'd3: CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q12 = 2'd3; endcase end always@(merge0_fo$D_OUT) begin case (merge0_fo$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q9 = + CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q13 = merge0_fo$D_OUT[39:38]; - 2'd3: CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q9 = 2'd3; + 2'd3: CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q13 = 2'd3; endcase end always@(merge0_fo$D_OUT) begin case (merge0_fo$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q10 = + CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q14 = merge0_fo$D_OUT[29:28]; - 2'd3: CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q10 = 2'd3; + 2'd3: CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q14 = 2'd3; endcase end always@(merge0_fo$D_OUT) begin case (merge0_fo$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q11 = + CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q15 = merge0_fo$D_OUT[19:18]; - 2'd3: CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q11 = 2'd3; + 2'd3: CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q15 = 2'd3; endcase end always@(merge0_fo$D_OUT) begin case (merge0_fo$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q12 = + CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q16 = merge0_fo$D_OUT[9:8]; - 2'd3: CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q12 = 2'd3; - endcase - end - always@(fork1_d1F$D_OUT) - begin - case (fork1_d1F$D_OUT[39:38]) - 2'd0, 2'd1, 2'd2: - CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q13 = - fork1_d1F$D_OUT[39:38]; - 2'd3: CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q13 = 2'd3; - endcase - end - always@(fork1_d1F$D_OUT) - begin - case (fork1_d1F$D_OUT[29:28]) - 2'd0, 2'd1, 2'd2: - CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q14 = - fork1_d1F$D_OUT[29:28]; - 2'd3: CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q14 = 2'd3; - endcase - end - always@(fork1_d1F$D_OUT) - begin - case (fork1_d1F$D_OUT[19:18]) - 2'd0, 2'd1, 2'd2: - CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q15 = - fork1_d1F$D_OUT[19:18]; - 2'd3: CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q15 = 2'd3; - endcase - end - always@(fork1_d1F$D_OUT) - begin - case (fork1_d1F$D_OUT[9:8]) - 2'd0, 2'd1, 2'd2: - CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q16 = - fork1_d1F$D_OUT[9:8]; - 2'd3: CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q16 = 2'd3; + 2'd3: CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q16 = 2'd3; endcase end always@(fork0_ptr or fork0_sr) begin case (fork0_ptr) 3'd0: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1324 = + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 = fork0_sr[37:30]; 3'd1: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1324 = + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 = fork0_sr[77:70]; - default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1324 = + default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1301 = fork0_sr[117:110]; endcase end @@ -1882,12 +1882,12 @@ module mkQABSMF3(et0, begin case (fork0_ptr) 3'd0: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1325 = + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 = fork0_sr[27:20]; 3'd1: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1325 = + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 = fork0_sr[67:60]; - default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1325 = + default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1302 = fork0_sr[107:100]; endcase end @@ -1934,12 +1934,12 @@ module mkQABSMF3(et0, begin case (fork0_ptr) 3'd0: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1326 = + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 = fork0_sr[17:10]; 3'd1: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1326 = + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 = fork0_sr[57:50]; - default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1326 = + default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1303 = fork0_sr[97:90]; endcase end @@ -1986,12 +1986,12 @@ module mkQABSMF3(et0, begin case (fork0_ptr) 3'd0: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1327 = + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 = fork0_sr[7:0]; 3'd1: - IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1327 = + IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 = fork0_sr[47:40]; - default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1327 = + default: IF_fork0_ptr_68_EQ_0_86_THEN_fork0_sr_72_BITS__ETC___d1304 = fork0_sr[87:80]; endcase end @@ -2038,12 +2038,12 @@ module mkQABSMF3(et0, begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1328 = + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 = fork1_sr[37:30]; 3'd1: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1328 = + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 = fork1_sr[77:70]; - default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1328 = + default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1305 = fork1_sr[117:110]; endcase end @@ -2090,12 +2090,12 @@ module mkQABSMF3(et0, begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1329 = + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 = fork1_sr[27:20]; 3'd1: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1329 = + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 = fork1_sr[67:60]; - default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1329 = + default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1306 = fork1_sr[107:100]; endcase end @@ -2142,12 +2142,12 @@ module mkQABSMF3(et0, begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1330 = + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 = fork1_sr[17:10]; 3'd1: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1330 = + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 = fork1_sr[57:50]; - default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1330 = + default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1307 = fork1_sr[97:90]; endcase end @@ -2194,12 +2194,12 @@ module mkQABSMF3(et0, begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1331 = + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 = fork1_sr[7:0]; 3'd1: - IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1331 = + IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 = fork1_sr[47:40]; - default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1331 = + default: IF_fork1_ptr_35_EQ_0_53_THEN_fork1_sr_39_BITS__ETC___d1308 = fork1_sr[87:80]; endcase end diff --git a/rtl/mkQBGMAC.v b/rtl/mkQBGMAC.v index 71a8492b..1e7e6cda 100644 --- a/rtl/mkQBGMAC.v +++ b/rtl/mkQBGMAC.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Wed Sep 19 14:36:28 EDT 2012 +// On Mon Sep 24 13:37:58 EDT 2012 // // // Ports: diff --git a/rtl/mkSMAdapter16B.v b/rtl/mkSMAdapter16B.v index ea9d7c88..203d6bf8 100644 --- a/rtl/mkSMAdapter16B.v +++ b/rtl/mkSMAdapter16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:07 EDT 2012 +// On Mon Sep 24 13:38:28 EDT 2012 // // // Ports: @@ -913,7 +913,9 @@ module mkSMAdapter16B(wciS0_Clk, WILL_FIRE_RL_wmi_reqF_decCtr, WILL_FIRE_RL_wmi_reqF_deq, WILL_FIRE_RL_wmi_reqF_incCtr, + WILL_FIRE_RL_wmrd_mesgBegin, WILL_FIRE_RL_wmrd_mesgBodyRequest, + WILL_FIRE_RL_wmrd_mesgBodyResponse, WILL_FIRE_RL_wmrd_mesgResptoWsi, WILL_FIRE_RL_wmwt_doAbort, WILL_FIRE_RL_wmwt_mesgBegin, @@ -930,21 +932,21 @@ module mkSMAdapter16B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2; wire [168 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, - MUX_wsiM_reqFifo_q_1$write_1__VAL_2, + MUX_wsiM_reqFifo_q_1$write_1__VAL_1, MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3; wire [145 : 0] MUX_wmi_dhF_q_0$write_1__VAL_1, MUX_wmi_dhF_q_0$write_1__VAL_2, - MUX_wmi_dhF_q_1$write_1__VAL_2; + MUX_wmi_dhF_q_1$write_1__VAL_1; wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; - wire [31 : 0] MUX_mesgCount$write_1__VAL_2, + wire [31 : 0] MUX_mesgCount$write_1__VAL_1, MUX_thisMesg$write_1__VAL_1, MUX_thisMesg$write_1__VAL_2, MUX_wmi_mFlagF_q_0$write_1__VAL_1, MUX_wmi_mFlagF_q_1$write_1__VAL_1, - MUX_wmi_mFlagF_x_wire$wset_1__VAL_1, + MUX_wmi_mFlagF_x_wire$wset_1__VAL_2, MUX_wmi_reqF_q_0$write_1__VAL_1, MUX_wmi_reqF_q_0$write_1__VAL_2, MUX_wmi_reqF_q_1$write_1__VAL_1, @@ -953,6 +955,7 @@ module mkSMAdapter16B(wciS0_Clk, wire [15 : 0] MUX_unrollCnt$write_1__VAL_1, MUX_unrollCnt$write_1__VAL_2; wire [13 : 0] MUX_fabWordsRemain$write_1__VAL_1, MUX_fabWordsRemain$write_1__VAL_2, + MUX_mesgLengthSoFar$write_1__VAL_1, MUX_mesgReqAddr$write_1__VAL_2; wire [11 : 0] MUX_fabRespCredit_value$write_1__VAL_2; wire [8 : 0] MUX_opcode$write_1__VAL_3; @@ -969,102 +972,101 @@ module mkSMAdapter16B(wciS0_Clk, wire MUX_endOfMessage$write_1__SEL_1, MUX_mesgCount$write_1__SEL_1, MUX_mesgReqOK$write_1__SEL_3, - MUX_unrollCnt$write_1__SEL_1, - MUX_unrollCnt$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, MUX_wci_wslv_respF_q_1$write_1__SEL_2, - MUX_wmi_dhF_q_0$write_1__SEL_1, - MUX_wmi_dhF_q_1$write_1__SEL_1, + MUX_wmi_dhF_q_0$write_1__SEL_2, + MUX_wmi_dhF_q_1$write_1__SEL_2, MUX_wmi_mFlagF_q_0$write_1__SEL_2, MUX_wmi_mFlagF_q_1$write_1__SEL_2, + MUX_wmi_mFlagF_x_wire$wset_1__SEL_1, MUX_wmi_reqF_q_0$write_1__SEL_2, MUX_wmi_reqF_q_1$write_1__SEL_2, - MUX_wsiM_reqFifo_q_0$write_1__SEL_1, - MUX_wsiM_reqFifo_q_1$write_1__SEL_1, + MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals reg [63 : 0] v__h18191, - v__h22600, - v__h22659, - v__h24493, - v__h24676, - v__h24872, - v__h25530, + v__h21903, + v__h21962, + v__h23796, + v__h23979, + v__h24175, + v__h24833, v__h3651, v__h3825, v__h3969; - reg [31 : 0] g_data__h25042; - wire [163 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d923; - wire [31 : 0] rdat__h25085, - rdat__h25091, - rdat__h25097, - rdat__h25110, - rdat__h25133, - rdat__h25233, - rdat__h25247, - rdat__h25255, - rdat__h25261, - rdat__h25275, - rdat__h25283, - rdat__h25289, - rdat__h25295, - rdat__h25301, - rdat__h25307, - rdat__h25317, + reg [31 : 0] g_data__h24345; + wire [163 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d919; + wire [31 : 0] rdat__h24388, + rdat__h24394, + rdat__h24400, + rdat__h24413, + rdat__h24436, + rdat__h24536, + rdat__h24550, + rdat__h24558, + rdat__h24564, + rdat__h24578, + rdat__h24586, + rdat__h24592, + rdat__h24598, + rdat__h24604, + rdat__h24610, + rdat__h24620, value__h6580, x__h18791; wire [23 : 0] b__h17902, - mesgMetaF_length__h23181, + mesgMetaF_length__h22484, residue__h17765, x__h18022; wire [15 : 0] sendData_byteEn__h18734, wsiBurstLength__h18650, - x__h25137, - x_length__h24073; - wire [13 : 0] b__h18275, mlB__h23014, mlInc__h23013; + x__h24440, + x_length__h23376; + wire [13 : 0] b__h18275, mlB__h22317, mlInc__h22316; wire [11 : 0] b__h15090, sendData_burstLength__h18732, x__h16444; - wire [7 : 0] mesgMetaF_opcode__h23180; - wire [4 : 0] x__h23220, - x__h23232, - x__h23244, - x__h23256, - x__h23268, - x__h23280, - x__h23292, - x__h23304, - x__h23316, - x__h23328, - x__h23340, - x__h23352, - x__h23364, - x__h23376, - x__h23388, - y__h23221, - y__h23233, - y__h23245, - y__h23257, - y__h23269, - y__h23281, - y__h23293, - y__h23305, - y__h23317, - y__h23329, - y__h23341, - y__h23353, - y__h23365, - y__h23377, - y__h23389; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d915; + wire [7 : 0] mesgMetaF_opcode__h22483; + wire [4 : 0] x__h22523, + x__h22535, + x__h22547, + x__h22559, + x__h22571, + x__h22583, + x__h22595, + x__h22607, + x__h22619, + x__h22631, + x__h22643, + x__h22655, + x__h22667, + x__h22679, + x__h22691, + y__h22524, + y__h22536, + y__h22548, + y__h22560, + y__h22572, + y__h22584, + y__h22596, + y__h22608, + y__h22620, + y__h22632, + y__h22644, + y__h22656, + y__h22668, + y__h22680, + y__h22692; + wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d916; wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542, wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670, x__h18446, - x__h25311; + x__h24614; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1237,6 +1239,15 @@ module mkSMAdapter16B(wciS0_Clk, !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wmrd_mesgBegin + assign WILL_FIRE_RL_wmrd_mesgBegin = + wci_wslv_cState == 3'd2 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + !wmi_sThreadBusy_d && + !wmi_sDataThreadBusy_d && + unrollCnt == 16'd0 ; + // rule RL_wsipass_doMessagePush assign WILL_FIRE_RL_wsipass_doMessagePush = wsiS_reqFifo$EMPTY_N && @@ -1244,6 +1255,14 @@ module mkSMAdapter16B(wciS0_Clk, wci_wslv_cState == 3'd2 && smaCtrl[3:0] == 4'h0 ; + // rule RL_wmrd_mesgBodyResponse + assign WILL_FIRE_RL_wmrd_mesgBodyResponse = + wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && + wci_wslv_cState == 3'd2 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + unrollCnt != 16'd0 ; + // rule RL_wmwt_mesgBegin assign CAN_FIRE_RL_wmwt_mesgBegin = wsiS_reqFifo$EMPTY_N && mesgTokenF$FULL_N && @@ -1448,23 +1467,10 @@ module mkSMAdapter16B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[165] ; assign MUX_mesgCount$write_1__SEL_1 = - MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ; + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ; assign MUX_mesgReqOK$write_1__SEL_3 = CAN_FIRE_RL_wmrd_mesgBodyPreRequest && !WILL_FIRE_RL_wmrd_mesgBodyRequest ; - assign MUX_unrollCnt$write_1__SEL_1 = - wci_wslv_cState == 3'd2 && - (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || - smaCtrl[3:0] == 4'h9) && - !wmi_sThreadBusy_d && - !wmi_sDataThreadBusy_d && - unrollCnt == 16'd0 ; - assign MUX_unrollCnt$write_1__SEL_2 = - wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && - wci_wslv_cState == 3'd2 && - (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || - smaCtrl[3:0] == 4'h9) && - unrollCnt != 16'd0 ; assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || @@ -1484,27 +1490,29 @@ module mkSMAdapter16B(wciS0_Clk, assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_c_r == 2'd1 ; - assign MUX_wmi_dhF_q_0$write_1__SEL_1 = + assign MUX_wmi_dhF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 ; - assign MUX_wmi_dhF_q_1$write_1__SEL_1 = + assign MUX_wmi_dhF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 ; assign MUX_wmi_mFlagF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ; assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ; + assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 ; assign MUX_wmi_reqF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ; assign MUX_wmi_reqF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 ; - assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; - assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; + assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 ; - assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = CAN_FIRE_RL_wmwt_messagePush && !WILL_FIRE_RL_wmwt_messageFinalize ; @@ -1515,12 +1523,14 @@ module mkSMAdapter16B(wciS0_Clk, assign MUX_fabWordsRemain$write_1__VAL_1 = (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17902[13:0] ; assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; - assign MUX_mesgCount$write_1__VAL_2 = mesgCount + 32'd1 ; + assign MUX_mesgCount$write_1__VAL_1 = mesgCount + 32'd1 ; + assign MUX_mesgLengthSoFar$write_1__VAL_1 = + mesgLengthSoFar + mlInc__h22316 ; assign MUX_mesgReqAddr$write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[9:0], 4'd0 } ; assign MUX_opcode$write_1__VAL_3 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ; assign MUX_thisMesg$write_1__VAL_1 = - { mesgCount[7:0], mesgMetaF_opcode__h23180, x_length__h24073 } ; + { mesgCount[7:0], mesgMetaF_opcode__h22483, x_length__h23376 } ; assign MUX_thisMesg$write_1__VAL_2 = { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; assign MUX_unrollCnt$write_1__VAL_1 = @@ -1560,25 +1570,25 @@ module mkSMAdapter16B(wciS0_Clk, 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h25042 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24345 } ; assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r + 2'd1 ; assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ; assign MUX_wmi_dhF_q_0$write_1__VAL_1 = - { 1'd1, wsiS_reqFifo$D_OUT[165], wsiS_reqFifo$D_OUT[151:8] } ; - assign MUX_wmi_dhF_q_0$write_1__VAL_2 = (wmi_dhF_c_r == 2'd1) ? - MUX_wmi_dhF_q_0$write_1__VAL_1 : + MUX_wmi_dhF_q_0$write_1__VAL_2 : wmi_dhF_q_1 ; - assign MUX_wmi_dhF_q_1$write_1__VAL_2 = - (wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_0$write_1__VAL_1 : 146'd0 ; + assign MUX_wmi_dhF_q_0$write_1__VAL_2 = + { 1'd1, wsiS_reqFifo$D_OUT[165], wsiS_reqFifo$D_OUT[151:8] } ; + assign MUX_wmi_dhF_q_1$write_1__VAL_1 = + (wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_0$write_1__VAL_2 : 146'd0 ; assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ; assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ; assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 = (wmi_mFlagF_c_r == 2'd1) ? value__h6580 : wmi_mFlagF_q_1 ; assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 = (wmi_mFlagF_c_r == 2'd2) ? value__h6580 : 32'd0 ; - assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_1 = - { mesgMetaF_opcode__h23180, mesgMetaF_length__h23181 } ; + assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 = + { mesgMetaF_opcode__h22483, mesgMetaF_length__h22484 } ; assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r + 2'd1 ; assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r - 2'd1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_1 = @@ -1600,17 +1610,17 @@ module mkSMAdapter16B(wciS0_Clk, assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = (MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 || MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2) ? wsiS_reqFifo$D_OUT : MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; - assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = - (wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 = + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = (wsiM_reqFifo_c_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : + MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 = (respF_rCache[181] && respF_rCache[180:169] == respF_rRdPtr) ? @@ -1653,7 +1663,7 @@ module mkSMAdapter16B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_mFlagF_x_wire$wget = value__h6580 ; assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ; - assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_1 ; + assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_2 ; assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_wmiResponse$wget = { wmiM0_SResp, wmiM0_SData } ; assign wmi_wmiResponse$whas = 1'd1 ; @@ -1665,7 +1675,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_operateD_1$whas = wci_wslv_cState == 3'd2 ; assign wmi_peerIsReady_1$wget = 1'd1 ; assign wmi_peerIsReady_1$whas = wmiM0_SReset_n ; - assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ; + assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ; assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; assign wsiM_operateD_1$wget = 1'd1 ; assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ; @@ -1743,9 +1753,9 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_reqF_dequeueing$whas = WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'd0 ; assign wmi_mFlagF_enqueueing$whas = + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && - wsiS_reqFifo$D_OUT[165] || - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 ; + wsiS_reqFifo$D_OUT[165] ; assign wmi_mFlagF_dequeueing$whas = WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_q_0[27] && wmi_mFlagF_c_r != 2'd0 ; @@ -1755,9 +1765,9 @@ module mkSMAdapter16B(wciS0_Clk, wmi_operateD && wmi_peerIsReady && !wmi_sDataThreadBusy_d && wmi_dhF_c_r != 2'd0 ; assign wsiM_reqFifo_enqueueing$whas = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 || - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; @@ -1770,7 +1780,8 @@ module mkSMAdapter16B(wciS0_Clk, assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ; assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; - assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ; + assign respF_pwEnqueue$whas = + WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; assign wsi_Es_mDataInfo_w$whas = 1'd1 ; @@ -1816,11 +1827,11 @@ module mkSMAdapter16B(wciS0_Clk, // register fabWordsRemain assign fabWordsRemain$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? MUX_fabWordsRemain$write_1__VAL_1 : MUX_fabWordsRemain$write_1__VAL_2 ; assign fabWordsRemain$EN = - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wmrd_mesgBodyRequest ; // register firstMsgReq @@ -1830,38 +1841,38 @@ module mkSMAdapter16B(wciS0_Clk, // register lastMesg assign lastMesg$D_IN = (MUX_endOfMessage$write_1__SEL_1 || - MUX_unrollCnt$write_1__SEL_1) ? + WILL_FIRE_RL_wmrd_mesgBegin) ? thisMesg : 32'hFEFEFFFE ; assign lastMesg$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[165] || - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wci_ctrl_IsO ; // register mesgCount always@(MUX_mesgCount$write_1__SEL_1 or - MUX_mesgCount$write_1__VAL_2 or + MUX_mesgCount$write_1__VAL_1 or WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_mesgCount$write_1__SEL_1: - mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2; + mesgCount$D_IN = MUX_mesgCount$write_1__VAL_1; WILL_FIRE_RL_wmwt_messageFinalize: - mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2; + mesgCount$D_IN = MUX_mesgCount$write_1__VAL_1; WILL_FIRE_RL_wci_ctrl_IsO: mesgCount$D_IN = 32'd0; default: mesgCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign mesgCount$EN = - MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 || + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 || WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wci_ctrl_IsO ; // register mesgLengthSoFar assign mesgLengthSoFar$D_IN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ? - mlB__h23014 : + MUX_mesgLengthSoFar$write_1__VAL_1 : 14'd0 ; assign mesgLengthSoFar$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || @@ -1873,21 +1884,22 @@ module mkSMAdapter16B(wciS0_Clk, // register mesgReqAddr assign mesgReqAddr$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? 14'd0 : MUX_mesgReqAddr$write_1__VAL_2 ; assign mesgReqAddr$EN = WILL_FIRE_RL_wmrd_mesgBodyRequest || - MUX_unrollCnt$write_1__SEL_1 ; + WILL_FIRE_RL_wmrd_mesgBegin ; // register mesgReqOK assign mesgReqOK$D_IN = - MUX_unrollCnt$write_1__SEL_2 || MUX_unrollCnt$write_1__SEL_1 ; + WILL_FIRE_RL_wmrd_mesgBodyResponse || + WILL_FIRE_RL_wmrd_mesgBegin ; assign mesgReqOK$EN = CAN_FIRE_RL_wmrd_mesgBodyPreRequest && !WILL_FIRE_RL_wmrd_mesgBodyRequest || - MUX_unrollCnt$write_1__SEL_1 || - MUX_unrollCnt$write_1__SEL_2 ; + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; // register opcode assign opcode$D_IN = @@ -1917,10 +1929,10 @@ module mkSMAdapter16B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d915, + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d916, respF_pwEnqueue$whas && respF_wDataIn$wget[165], respF_pwEnqueue$whas && respF_wDataIn$wget[164], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d923 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d919 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr @@ -1939,13 +1951,13 @@ module mkSMAdapter16B(wciS0_Clk, // register thisMesg always@(MUX_endOfMessage$write_1__SEL_1 or MUX_thisMesg$write_1__VAL_1 or - MUX_unrollCnt$write_1__SEL_1 or + WILL_FIRE_RL_wmrd_mesgBegin or MUX_thisMesg$write_1__VAL_2 or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_endOfMessage$write_1__SEL_1: thisMesg$D_IN = MUX_thisMesg$write_1__VAL_1; - MUX_unrollCnt$write_1__SEL_1: + WILL_FIRE_RL_wmrd_mesgBegin: thisMesg$D_IN = MUX_thisMesg$write_1__VAL_2; WILL_FIRE_RL_wci_ctrl_IsO: thisMesg$D_IN = 32'hFEFEFFFE; default: thisMesg$D_IN = 32'hAAAAAAAA /* unspecified value */ ; @@ -1954,16 +1966,17 @@ module mkSMAdapter16B(wciS0_Clk, assign thisMesg$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[165] || - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wci_ctrl_IsO ; // register unrollCnt assign unrollCnt$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? MUX_unrollCnt$write_1__VAL_1 : MUX_unrollCnt$write_1__VAL_2 ; assign unrollCnt$EN = - MUX_unrollCnt$write_1__SEL_1 || MUX_unrollCnt$write_1__SEL_2 ; + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; // register valExpect assign valExpect$D_IN = valExpect + 128'd1 ; @@ -2110,16 +2123,16 @@ module mkSMAdapter16B(wciS0_Clk, WILL_FIRE_RL_wmi_dhF_incCtr || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_0 - always@(MUX_wmi_dhF_q_0$write_1__SEL_1 or + always@(WILL_FIRE_RL_wmi_dhF_both or MUX_wmi_dhF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wmi_dhF_both or + MUX_wmi_dhF_q_0$write_1__SEL_2 or MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1) begin case (1'b1) // synopsys parallel_case - MUX_wmi_dhF_q_0$write_1__SEL_1: - wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; WILL_FIRE_RL_wmi_dhF_both: + wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; + MUX_wmi_dhF_q_0$write_1__SEL_2: wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_0$D_IN = wmi_dhF_q_1; default: wmi_dhF_q_0$D_IN = @@ -2127,29 +2140,29 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wmi_dhF_q_0$EN = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 || WILL_FIRE_RL_wmi_dhF_both || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 - always@(MUX_wmi_dhF_q_1$write_1__SEL_1 or - MUX_wmi_dhF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wmi_dhF_both or - MUX_wmi_dhF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + always@(WILL_FIRE_RL_wmi_dhF_both or + MUX_wmi_dhF_q_1$write_1__VAL_1 or + MUX_wmi_dhF_q_1$write_1__SEL_2 or + MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wmi_dhF_q_1$write_1__SEL_1: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; WILL_FIRE_RL_wmi_dhF_both: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_2; + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_1; + MUX_wmi_dhF_q_1$write_1__SEL_2: + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1$D_IN = 146'd0; default: wmi_dhF_q_1$D_IN = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_1$EN = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 || WILL_FIRE_RL_wmi_dhF_both || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_errorSticky @@ -2350,16 +2363,16 @@ module mkSMAdapter16B(wciS0_Clk, WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_0 - always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or + always@(WILL_FIRE_RL_wsiM_reqFifo_both or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - MUX_wsiM_reqFifo_q_0$write_1__SEL_1: - wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; + MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1; @@ -2368,22 +2381,22 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or - MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wsiM_reqFifo_q_1$write_1__SEL_1: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; WILL_FIRE_RL_wsiM_reqFifo_both: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2; + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__SEL_2: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1$D_IN = 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; @@ -2392,8 +2405,8 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -2522,10 +2535,10 @@ module mkSMAdapter16B(wciS0_Clk, x__h16444[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d915, + { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d916, respF_pwEnqueue$whas && respF_wDataIn$wget[165], respF_pwEnqueue$whas && respF_wDataIn$wget[164], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d923 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d919 } ; assign respF_memory$DIB = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; @@ -2544,7 +2557,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_respF$ENQ = wmi_respF$FULL_N && wmi_operateD && wmi_peerIsReady && wmi_wmiResponse$wget[129:128] != 2'd0 ; - assign wmi_respF$DEQ = MUX_unrollCnt$write_1__SEL_2 ; + assign wmi_respF$DEQ = WILL_FIRE_RL_wmrd_mesgBodyResponse ; assign wmi_respF$CLR = 1'b0 ; // submodule wsiS_reqFifo @@ -2554,9 +2567,9 @@ module mkSMAdapter16B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d915 = + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d916 = respF_pwEnqueue$whas ? respF_wDataIn$wget[168:166] : 3'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d923 = + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d919 = respF_pwEnqueue$whas ? respF_wDataIn$wget[163:0] : 164'd0 ; assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && @@ -2564,33 +2577,33 @@ module mkSMAdapter16B(wciS0_Clk, assign b__h15090 = -fabWordsCurReq[11:0] ; assign b__h17902 = x__h18022 + residue__h17765 ; assign b__h18275 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; - assign mesgMetaF_length__h23181 = + assign mesgMetaF_length__h22484 = (wsiS_reqFifo$D_OUT[165] && wsiS_reqFifo$D_OUT[23:8] == 16'd0 && mesgLengthSoFar == 14'd0) ? 24'd0 : - { 10'd0, mlB__h23014 } ; - assign mesgMetaF_opcode__h23180 = opcode[8] ? opcode[7:0] : 8'd0 ; - assign mlB__h23014 = mesgLengthSoFar + mlInc__h23013 ; - assign mlInc__h23013 = + { 10'd0, mlB__h22317 } ; + assign mesgMetaF_opcode__h22483 = opcode[8] ? opcode[7:0] : 8'd0 ; + assign mlB__h22317 = MUX_mesgLengthSoFar$write_1__VAL_1 ; + assign mlInc__h22316 = wsiS_reqFifo$D_OUT[165] ? - { 9'd0, x__h23220 + y__h23221 } : + { 9'd0, x__h22523 + y__h22524 } : 14'd16 ; - assign rdat__h25085 = hasDebugLogic ? mesgCount : 32'd0 ; - assign rdat__h25091 = hasDebugLogic ? abortCount : 32'd0 ; - assign rdat__h25097 = hasDebugLogic ? thisMesg : 32'd0 ; - assign rdat__h25110 = hasDebugLogic ? lastMesg : 32'd0 ; - assign rdat__h25133 = hasDebugLogic ? { 16'd0, x__h25137 } : 32'd0 ; - assign rdat__h25233 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h25247 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h25255 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h25261 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h25275 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h25283 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h25289 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; - assign rdat__h25295 = hasDebugLogic ? wmwtPushCount : 32'd0 ; - assign rdat__h25301 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; - assign rdat__h25307 = hasDebugLogic ? { 31'd0, x__h25311 } : 32'd0 ; - assign rdat__h25317 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; + assign rdat__h24388 = hasDebugLogic ? mesgCount : 32'd0 ; + assign rdat__h24394 = hasDebugLogic ? abortCount : 32'd0 ; + assign rdat__h24400 = hasDebugLogic ? thisMesg : 32'd0 ; + assign rdat__h24413 = hasDebugLogic ? lastMesg : 32'd0 ; + assign rdat__h24436 = hasDebugLogic ? { 16'd0, x__h24440 } : 32'd0 ; + assign rdat__h24536 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h24550 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h24558 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h24564 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h24578 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h24586 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h24592 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; + assign rdat__h24598 = hasDebugLogic ? wmwtPushCount : 32'd0 ; + assign rdat__h24604 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; + assign rdat__h24610 = hasDebugLogic ? { 31'd0, x__h24614 } : 32'd0 ; + assign rdat__h24620 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; assign residue__h17765 = ({ 2'd0, wmi_sFlagReg[3:0] } == 6'd0) ? 24'd0 : 24'd1 ; assign sendData_burstLength__h18732 = @@ -2602,9 +2615,9 @@ module mkSMAdapter16B(wciS0_Clk, thisMesg[15:0] : ((unrollCnt == 16'd1) ? x__h18791[15:0] : 16'd65535) ; assign value__h6580 = - MUX_endOfMessage$write_1__SEL_1 ? - MUX_wmi_mFlagF_x_wire$wset_1__VAL_1 : - 32'hAAAAAAAA /* unspecified value */ ; + MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 ? + 32'hAAAAAAAA /* unspecified value */ : + MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 ; assign wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 = wmi_respF$EMPTY_N && (smaCtrl[4] || respF_rRdPtr + 12'd1024 != respF_rWrPtr) ; @@ -2724,74 +2737,74 @@ module mkSMAdapter16B(wciS0_Clk, 6'd31) ? 32'h7FFFFFFF : 32'hFFFFFFFF))))))))))))))))))))))))))))))) ; - assign x__h23220 = x__h23232 + y__h23233 ; - assign x__h23232 = x__h23244 + y__h23245 ; - assign x__h23244 = x__h23256 + y__h23257 ; - assign x__h23256 = x__h23268 + y__h23269 ; - assign x__h23268 = x__h23280 + y__h23281 ; - assign x__h23280 = x__h23292 + y__h23293 ; - assign x__h23292 = x__h23304 + y__h23305 ; - assign x__h23304 = x__h23316 + y__h23317 ; - assign x__h23316 = x__h23328 + y__h23329 ; - assign x__h23328 = x__h23340 + y__h23341 ; - assign x__h23340 = x__h23352 + y__h23353 ; - assign x__h23352 = x__h23364 + y__h23365 ; - assign x__h23364 = x__h23376 + y__h23377 ; - assign x__h23376 = x__h23388 + y__h23389 ; - assign x__h23388 = { 4'd0, wsiS_reqFifo$D_OUT[23] } ; - assign x__h25137 = { wsiS_statusR, wsiM_statusR } ; - assign x__h25311 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; - assign x_length__h24073 = { 2'd0, mlB__h23014 } ; - assign y__h23221 = { 4'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h23233 = { 4'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h23245 = { 4'd0, wsiS_reqFifo$D_OUT[10] } ; - assign y__h23257 = { 4'd0, wsiS_reqFifo$D_OUT[11] } ; - assign y__h23269 = { 4'd0, wsiS_reqFifo$D_OUT[12] } ; - assign y__h23281 = { 4'd0, wsiS_reqFifo$D_OUT[13] } ; - assign y__h23293 = { 4'd0, wsiS_reqFifo$D_OUT[14] } ; - assign y__h23305 = { 4'd0, wsiS_reqFifo$D_OUT[15] } ; - assign y__h23317 = { 4'd0, wsiS_reqFifo$D_OUT[16] } ; - assign y__h23329 = { 4'd0, wsiS_reqFifo$D_OUT[17] } ; - assign y__h23341 = { 4'd0, wsiS_reqFifo$D_OUT[18] } ; - assign y__h23353 = { 4'd0, wsiS_reqFifo$D_OUT[19] } ; - assign y__h23365 = { 4'd0, wsiS_reqFifo$D_OUT[20] } ; - assign y__h23377 = { 4'd0, wsiS_reqFifo$D_OUT[21] } ; - assign y__h23389 = { 4'd0, wsiS_reqFifo$D_OUT[22] } ; + assign x__h22523 = x__h22535 + y__h22536 ; + assign x__h22535 = x__h22547 + y__h22548 ; + assign x__h22547 = x__h22559 + y__h22560 ; + assign x__h22559 = x__h22571 + y__h22572 ; + assign x__h22571 = x__h22583 + y__h22584 ; + assign x__h22583 = x__h22595 + y__h22596 ; + assign x__h22595 = x__h22607 + y__h22608 ; + assign x__h22607 = x__h22619 + y__h22620 ; + assign x__h22619 = x__h22631 + y__h22632 ; + assign x__h22631 = x__h22643 + y__h22644 ; + assign x__h22643 = x__h22655 + y__h22656 ; + assign x__h22655 = x__h22667 + y__h22668 ; + assign x__h22667 = x__h22679 + y__h22680 ; + assign x__h22679 = x__h22691 + y__h22692 ; + assign x__h22691 = { 4'd0, wsiS_reqFifo$D_OUT[23] } ; + assign x__h24440 = { wsiS_statusR, wsiM_statusR } ; + assign x__h24614 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; + assign x_length__h23376 = { 2'd0, mlB__h22317 } ; + assign y__h22524 = { 4'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h22536 = { 4'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h22548 = { 4'd0, wsiS_reqFifo$D_OUT[10] } ; + assign y__h22560 = { 4'd0, wsiS_reqFifo$D_OUT[11] } ; + assign y__h22572 = { 4'd0, wsiS_reqFifo$D_OUT[12] } ; + assign y__h22584 = { 4'd0, wsiS_reqFifo$D_OUT[13] } ; + assign y__h22596 = { 4'd0, wsiS_reqFifo$D_OUT[14] } ; + assign y__h22608 = { 4'd0, wsiS_reqFifo$D_OUT[15] } ; + assign y__h22620 = { 4'd0, wsiS_reqFifo$D_OUT[16] } ; + assign y__h22632 = { 4'd0, wsiS_reqFifo$D_OUT[17] } ; + assign y__h22644 = { 4'd0, wsiS_reqFifo$D_OUT[18] } ; + assign y__h22656 = { 4'd0, wsiS_reqFifo$D_OUT[19] } ; + assign y__h22668 = { 4'd0, wsiS_reqFifo$D_OUT[20] } ; + assign y__h22680 = { 4'd0, wsiS_reqFifo$D_OUT[21] } ; + assign y__h22692 = { 4'd0, wsiS_reqFifo$D_OUT[22] } ; always@(wci_wslv_reqF$D_OUT or smaCtrl or - rdat__h25085 or - rdat__h25091 or - rdat__h25097 or - rdat__h25110 or - rdat__h25133 or - rdat__h25233 or - rdat__h25247 or - rdat__h25255 or - rdat__h25261 or - rdat__h25275 or - rdat__h25283 or - rdat__h25289 or - rdat__h25295 or rdat__h25301 or rdat__h25307 or rdat__h25317) + rdat__h24388 or + rdat__h24394 or + rdat__h24400 or + rdat__h24413 or + rdat__h24436 or + rdat__h24536 or + rdat__h24550 or + rdat__h24558 or + rdat__h24564 or + rdat__h24578 or + rdat__h24586 or + rdat__h24592 or + rdat__h24598 or rdat__h24604 or rdat__h24610 or rdat__h24620) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h25042 = smaCtrl; - 8'h04: g_data__h25042 = rdat__h25085; - 8'h08: g_data__h25042 = rdat__h25091; - 8'h10: g_data__h25042 = rdat__h25097; - 8'h14: g_data__h25042 = rdat__h25110; - 8'h18: g_data__h25042 = rdat__h25133; - 8'h20: g_data__h25042 = rdat__h25233; - 8'h24: g_data__h25042 = rdat__h25247; - 8'h28: g_data__h25042 = rdat__h25255; - 8'h2C: g_data__h25042 = rdat__h25261; - 8'h30: g_data__h25042 = rdat__h25275; - 8'h34: g_data__h25042 = rdat__h25283; - 8'h38: g_data__h25042 = rdat__h25289; - 8'h3C: g_data__h25042 = rdat__h25295; - 8'h40: g_data__h25042 = rdat__h25301; - 8'h44: g_data__h25042 = rdat__h25307; - 8'h48: g_data__h25042 = rdat__h25317; - default: g_data__h25042 = 32'd0; + 8'h0: g_data__h24345 = smaCtrl; + 8'h04: g_data__h24345 = rdat__h24388; + 8'h08: g_data__h24345 = rdat__h24394; + 8'h10: g_data__h24345 = rdat__h24400; + 8'h14: g_data__h24345 = rdat__h24413; + 8'h18: g_data__h24345 = rdat__h24436; + 8'h20: g_data__h24345 = rdat__h24536; + 8'h24: g_data__h24345 = rdat__h24550; + 8'h28: g_data__h24345 = rdat__h24558; + 8'h2C: g_data__h24345 = rdat__h24564; + 8'h30: g_data__h24345 = rdat__h24578; + 8'h34: g_data__h24345 = rdat__h24586; + 8'h38: g_data__h24345 = rdat__h24592; + 8'h3C: g_data__h24345 = rdat__h24598; + 8'h40: g_data__h24345 = rdat__h24604; + 8'h44: g_data__h24345 = rdat__h24610; + 8'h48: g_data__h24345 = rdat__h24620; + default: g_data__h24345 = 32'd0; endcase end @@ -3177,13 +3190,13 @@ module mkSMAdapter16B(wciS0_Clk, begin #0; if (wciS0_MReset_n) - if (MUX_unrollCnt$write_1__SEL_1) + if (WILL_FIRE_RL_wmrd_mesgBegin) begin v__h18191 = $time; #0; end if (wciS0_MReset_n) - if (MUX_unrollCnt$write_1__SEL_1) + if (WILL_FIRE_RL_wmrd_mesgBegin) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", v__h18191, mesgCount, @@ -3192,46 +3205,46 @@ module mkSMAdapter16B(wciS0_Clk, if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[164]) begin - v__h22600 = $time; + v__h21903 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[164]) $display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x", - v__h22600, + v__h21903, mesgCount, wsiS_reqFifo$D_OUT[163:152], wsiS_reqFifo$D_OUT[7:0]); if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[164]) begin - v__h22659 = $time; + v__h21962 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[164]) $display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x", - v__h22659, + v__h21962, mesgCount); if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_doAbort) begin - v__h24493 = $time; + v__h23796 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_doAbort) - $display("[%0d]: %m: wmwt_doAbort", v__h24493); + $display("[%0d]: %m: wmwt_doAbort", v__h23796); if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_messageFinalize) begin - v__h24676 = $time; + v__h23979 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_messageFinalize) $display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x", - v__h24676, + v__h23979, mesgCount, thisMesg[15:0]); if (wciS0_MReset_n) @@ -3249,26 +3262,26 @@ module mkSMAdapter16B(wciS0_Clk, if (wciS0_MReset_n) if (WILL_FIRE_RL_wci_cfwr) begin - v__h24872 = $time; + v__h24175 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h24872, + v__h24175, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h25530 = $time; + v__h24833 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x", - v__h25530, + v__h24833, smaCtrl); if (wciS0_MReset_n) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) diff --git a/rtl/mkSMAdapter32B.v b/rtl/mkSMAdapter32B.v index e922c704..2b328181 100644 --- a/rtl/mkSMAdapter32B.v +++ b/rtl/mkSMAdapter32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:14 EDT 2012 +// On Mon Sep 24 13:38:30 EDT 2012 // // // Ports: @@ -912,7 +912,9 @@ module mkSMAdapter32B(wciS0_Clk, WILL_FIRE_RL_wmi_reqF_decCtr, WILL_FIRE_RL_wmi_reqF_deq, WILL_FIRE_RL_wmi_reqF_incCtr, + WILL_FIRE_RL_wmrd_mesgBegin, WILL_FIRE_RL_wmrd_mesgBodyRequest, + WILL_FIRE_RL_wmrd_mesgBodyResponse, WILL_FIRE_RL_wmrd_mesgResptoWsi, WILL_FIRE_RL_wmwt_doAbort, WILL_FIRE_RL_wmwt_mesgBegin, @@ -969,8 +971,6 @@ module mkSMAdapter32B(wciS0_Clk, wire MUX_endOfMessage$write_1__SEL_1, MUX_mesgCount$write_1__SEL_1, MUX_mesgReqOK$write_1__SEL_3, - MUX_unrollCnt$write_1__SEL_1, - MUX_unrollCnt$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, @@ -1000,7 +1000,7 @@ module mkSMAdapter32B(wciS0_Clk, v__h3825, v__h3969; reg [31 : 0] g_data__h25001; - wire [307 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966; + wire [307 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d963; wire [31 : 0] rdat__h25044, rdat__h25050, rdat__h25056, @@ -1089,7 +1089,7 @@ module mkSMAdapter32B(wciS0_Clk, y__h22860, y__h22872, y__h22884; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965; + wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964; wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542, wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669, @@ -1267,6 +1267,15 @@ module mkSMAdapter32B(wciS0_Clk, !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wmrd_mesgBegin + assign WILL_FIRE_RL_wmrd_mesgBegin = + wci_wslv_cState == 3'd2 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + !wmi_sThreadBusy_d && + !wmi_sDataThreadBusy_d && + unrollCnt == 16'd0 ; + // rule RL_wsipass_doMessagePush assign WILL_FIRE_RL_wsipass_doMessagePush = wsiS_reqFifo$EMPTY_N && @@ -1274,6 +1283,14 @@ module mkSMAdapter32B(wciS0_Clk, wci_wslv_cState == 3'd2 && smaCtrl[3:0] == 4'h0 ; + // rule RL_wmrd_mesgBodyResponse + assign WILL_FIRE_RL_wmrd_mesgBodyResponse = + wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && + wci_wslv_cState == 3'd2 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + unrollCnt != 16'd0 ; + // rule RL_wmwt_mesgBegin assign CAN_FIRE_RL_wmwt_mesgBegin = wsiS_reqFifo$EMPTY_N && mesgTokenF$FULL_N && @@ -1478,23 +1495,10 @@ module mkSMAdapter32B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[309] ; assign MUX_mesgCount$write_1__SEL_1 = - MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ; + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ; assign MUX_mesgReqOK$write_1__SEL_3 = CAN_FIRE_RL_wmrd_mesgBodyPreRequest && !WILL_FIRE_RL_wmrd_mesgBodyRequest ; - assign MUX_unrollCnt$write_1__SEL_1 = - wci_wslv_cState == 3'd2 && - (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || - smaCtrl[3:0] == 4'h9) && - !wmi_sThreadBusy_d && - !wmi_sDataThreadBusy_d && - unrollCnt == 16'd0 ; - assign MUX_unrollCnt$write_1__SEL_2 = - wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && - wci_wslv_cState == 3'd2 && - (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || - smaCtrl[3:0] == 4'h9) && - unrollCnt != 16'd0 ; assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || @@ -1533,10 +1537,10 @@ module mkSMAdapter32B(wciS0_Clk, assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; - assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 ; + assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = CAN_FIRE_RL_wmwt_messagePush && !WILL_FIRE_RL_wmwt_messageFinalize ; @@ -1789,9 +1793,9 @@ module mkSMAdapter32B(wciS0_Clk, wmi_operateD && wmi_peerIsReady && !wmi_sDataThreadBusy_d && wmi_dhF_c_r != 2'd0 ; assign wsiM_reqFifo_enqueueing$whas = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 || + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; @@ -1804,7 +1808,8 @@ module mkSMAdapter32B(wciS0_Clk, assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ; assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; - assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ; + assign respF_pwEnqueue$whas = + WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; assign wsi_Es_mDataInfo_w$whas = 1'd1 ; @@ -1850,11 +1855,11 @@ module mkSMAdapter32B(wciS0_Clk, // register fabWordsRemain assign fabWordsRemain$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? MUX_fabWordsRemain$write_1__VAL_1 : MUX_fabWordsRemain$write_1__VAL_2 ; assign fabWordsRemain$EN = - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wmrd_mesgBodyRequest ; // register firstMsgReq @@ -1864,13 +1869,13 @@ module mkSMAdapter32B(wciS0_Clk, // register lastMesg assign lastMesg$D_IN = (MUX_endOfMessage$write_1__SEL_1 || - MUX_unrollCnt$write_1__SEL_1) ? + WILL_FIRE_RL_wmrd_mesgBegin) ? thisMesg : 32'hFEFEFFFE ; assign lastMesg$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[309] || - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wci_ctrl_IsO ; // register mesgCount @@ -1888,7 +1893,7 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign mesgCount$EN = - MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 || + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 || WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wci_ctrl_IsO ; @@ -1907,21 +1912,22 @@ module mkSMAdapter32B(wciS0_Clk, // register mesgReqAddr assign mesgReqAddr$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? 14'd0 : MUX_mesgReqAddr$write_1__VAL_2 ; assign mesgReqAddr$EN = WILL_FIRE_RL_wmrd_mesgBodyRequest || - MUX_unrollCnt$write_1__SEL_1 ; + WILL_FIRE_RL_wmrd_mesgBegin ; // register mesgReqOK assign mesgReqOK$D_IN = - MUX_unrollCnt$write_1__SEL_2 || MUX_unrollCnt$write_1__SEL_1 ; + WILL_FIRE_RL_wmrd_mesgBodyResponse || + WILL_FIRE_RL_wmrd_mesgBegin ; assign mesgReqOK$EN = CAN_FIRE_RL_wmrd_mesgBodyPreRequest && !WILL_FIRE_RL_wmrd_mesgBodyRequest || - MUX_unrollCnt$write_1__SEL_1 || - MUX_unrollCnt$write_1__SEL_2 ; + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; // register opcode assign opcode$D_IN = @@ -1951,10 +1957,10 @@ module mkSMAdapter32B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965, + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964, respF_pwEnqueue$whas && respF_wDataIn$wget[309], respF_pwEnqueue$whas && respF_wDataIn$wget[308], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d963 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr @@ -1973,13 +1979,13 @@ module mkSMAdapter32B(wciS0_Clk, // register thisMesg always@(MUX_endOfMessage$write_1__SEL_1 or MUX_thisMesg$write_1__VAL_1 or - MUX_unrollCnt$write_1__SEL_1 or + WILL_FIRE_RL_wmrd_mesgBegin or MUX_thisMesg$write_1__VAL_2 or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_endOfMessage$write_1__SEL_1: thisMesg$D_IN = MUX_thisMesg$write_1__VAL_1; - MUX_unrollCnt$write_1__SEL_1: + WILL_FIRE_RL_wmrd_mesgBegin: thisMesg$D_IN = MUX_thisMesg$write_1__VAL_2; WILL_FIRE_RL_wci_ctrl_IsO: thisMesg$D_IN = 32'hFEFEFFFE; default: thisMesg$D_IN = 32'hAAAAAAAA /* unspecified value */ ; @@ -1988,16 +1994,17 @@ module mkSMAdapter32B(wciS0_Clk, assign thisMesg$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[309] || - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wci_ctrl_IsO ; // register unrollCnt assign unrollCnt$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? MUX_unrollCnt$write_1__VAL_1 : MUX_unrollCnt$write_1__VAL_2 ; assign unrollCnt$EN = - MUX_unrollCnt$write_1__SEL_1 || MUX_unrollCnt$write_1__SEL_2 ; + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; // register valExpect assign valExpect$D_IN = valExpect + 256'd1 ; @@ -2556,10 +2563,10 @@ module mkSMAdapter32B(wciS0_Clk, x__h16444[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965, + { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964, respF_pwEnqueue$whas && respF_wDataIn$wget[309], respF_pwEnqueue$whas && respF_wDataIn$wget[308], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d963 } ; assign respF_memory$DIB = 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; @@ -2578,7 +2585,7 @@ module mkSMAdapter32B(wciS0_Clk, assign wmi_respF$ENQ = wmi_respF$FULL_N && wmi_operateD && wmi_peerIsReady && wmi_wmiResponse$wget[257:256] != 2'd0 ; - assign wmi_respF$DEQ = MUX_unrollCnt$write_1__SEL_2 ; + assign wmi_respF$DEQ = WILL_FIRE_RL_wmrd_mesgBodyResponse ; assign wmi_respF$CLR = 1'b0 ; // submodule wsiS_reqFifo @@ -2588,10 +2595,10 @@ module mkSMAdapter32B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d965 = - respF_pwEnqueue$whas ? respF_wDataIn$wget[312:310] : 3'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966 = + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d963 = respF_pwEnqueue$whas ? respF_wDataIn$wget[307:0] : 308'd0 ; + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d964 = + respF_pwEnqueue$whas ? respF_wDataIn$wget[312:310] : 3'd0 ; assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && (!x__h18446 || wmi_mFlagF_c_r != 2'd2) ; @@ -3253,13 +3260,13 @@ module mkSMAdapter32B(wciS0_Clk, begin #0; if (wciS0_MReset_n) - if (MUX_unrollCnt$write_1__SEL_1) + if (WILL_FIRE_RL_wmrd_mesgBegin) begin v__h18191 = $time; #0; end if (wciS0_MReset_n) - if (MUX_unrollCnt$write_1__SEL_1) + if (WILL_FIRE_RL_wmrd_mesgBegin) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", v__h18191, mesgCount, diff --git a/rtl/mkSMAdapter4B.v b/rtl/mkSMAdapter4B.v index d8a641be..b1745576 100644 --- a/rtl/mkSMAdapter4B.v +++ b/rtl/mkSMAdapter4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:09 EDT 2012 +// On Mon Sep 24 13:38:23 EDT 2012 // // // Ports: @@ -911,7 +911,9 @@ module mkSMAdapter4B(wciS0_Clk, WILL_FIRE_RL_wmi_reqF_decCtr, WILL_FIRE_RL_wmi_reqF_deq, WILL_FIRE_RL_wmi_reqF_incCtr, + WILL_FIRE_RL_wmrd_mesgBegin, WILL_FIRE_RL_wmrd_mesgBodyRequest, + WILL_FIRE_RL_wmrd_mesgBodyResponse, WILL_FIRE_RL_wmrd_mesgResptoWsi, WILL_FIRE_RL_wmwt_doAbort, WILL_FIRE_RL_wmwt_mesgBegin, @@ -928,20 +930,20 @@ module mkSMAdapter4B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2; wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, - MUX_wsiM_reqFifo_q_1$write_1__VAL_1, + MUX_wsiM_reqFifo_q_1$write_1__VAL_2, MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3; wire [37 : 0] MUX_wmi_dhF_q_0$write_1__VAL_1, MUX_wmi_dhF_q_0$write_1__VAL_2, - MUX_wmi_dhF_q_1$write_1__VAL_1; + MUX_wmi_dhF_q_1$write_1__VAL_2; wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; - wire [31 : 0] MUX_mesgCount$write_1__VAL_1, + wire [31 : 0] MUX_mesgCount$write_1__VAL_2, MUX_thisMesg$write_1__VAL_1, MUX_thisMesg$write_1__VAL_2, - MUX_wmi_mFlagF_q_0$write_1__VAL_1, - MUX_wmi_mFlagF_q_1$write_1__VAL_1, + MUX_wmi_mFlagF_q_0$write_1__VAL_2, + MUX_wmi_mFlagF_q_1$write_1__VAL_2, MUX_wmi_mFlagF_x_wire$wset_1__VAL_2, MUX_wmi_reqF_q_0$write_1__VAL_1, MUX_wmi_reqF_q_0$write_1__VAL_2, @@ -951,7 +953,6 @@ module mkSMAdapter4B(wciS0_Clk, wire [15 : 0] MUX_unrollCnt$write_1__VAL_1, MUX_unrollCnt$write_1__VAL_2; wire [13 : 0] MUX_fabWordsRemain$write_1__VAL_1, MUX_fabWordsRemain$write_1__VAL_2, - MUX_mesgLengthSoFar$write_1__VAL_1, MUX_mesgReqAddr$write_1__VAL_2; wire [11 : 0] MUX_fabRespCredit_value$write_1__VAL_2; wire [8 : 0] MUX_opcode$write_1__VAL_3; @@ -968,77 +969,75 @@ module mkSMAdapter4B(wciS0_Clk, wire MUX_endOfMessage$write_1__SEL_1, MUX_mesgCount$write_1__SEL_1, MUX_mesgReqOK$write_1__SEL_3, - MUX_unrollCnt$write_1__SEL_1, - MUX_unrollCnt$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, MUX_wci_wslv_respF_q_1$write_1__SEL_2, - MUX_wmi_dhF_q_0$write_1__SEL_2, - MUX_wmi_dhF_q_1$write_1__SEL_2, - MUX_wmi_mFlagF_q_0$write_1__SEL_2, - MUX_wmi_mFlagF_q_1$write_1__SEL_2, + MUX_wmi_dhF_q_0$write_1__SEL_1, + MUX_wmi_dhF_q_1$write_1__SEL_1, + MUX_wmi_mFlagF_q_0$write_1__SEL_1, + MUX_wmi_mFlagF_q_1$write_1__SEL_1, MUX_wmi_mFlagF_x_wire$wset_1__SEL_1, MUX_wmi_reqF_q_0$write_1__SEL_2, MUX_wmi_reqF_q_1$write_1__SEL_2, - MUX_wsiM_reqFifo_q_0$write_1__SEL_2, - MUX_wsiM_reqFifo_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals reg [63 : 0] v__h18191, - v__h21903, - v__h21962, - v__h23304, - v__h23487, - v__h23683, - v__h24341, + v__h22600, + v__h22659, + v__h24001, + v__h24184, + v__h24380, + v__h25038, v__h3651, v__h3825, v__h3969; - reg [31 : 0] g_data__h23853; - wire [55 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889; - wire [31 : 0] rdat__h23896, - rdat__h23902, - rdat__h23908, - rdat__h23921, - rdat__h23944, - rdat__h24044, - rdat__h24058, - rdat__h24066, - rdat__h24072, - rdat__h24086, - rdat__h24094, - rdat__h24100, - rdat__h24106, - rdat__h24112, - rdat__h24118, - rdat__h24128, + reg [31 : 0] g_data__h24550; + wire [55 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881; + wire [31 : 0] rdat__h24593, + rdat__h24599, + rdat__h24605, + rdat__h24618, + rdat__h24641, + rdat__h24741, + rdat__h24755, + rdat__h24763, + rdat__h24769, + rdat__h24783, + rdat__h24791, + rdat__h24797, + rdat__h24803, + rdat__h24809, + rdat__h24815, + rdat__h24825, value__h6580, x__h18791; wire [23 : 0] b__h17902, - mesgMetaF_length__h22484, + mesgMetaF_length__h23181, residue__h17765, x__h18022; - wire [15 : 0] wsiBurstLength__h18650, x__h23948, x_length__h22884; - wire [13 : 0] b__h18275, mlB__h22317, mlInc__h22316; + wire [15 : 0] wsiBurstLength__h18650, x__h24645, x_length__h23581; + wire [13 : 0] b__h18275, mlB__h23014, mlInc__h23013; wire [11 : 0] b__h15090, sendData_burstLength__h18732, x__h16444; - wire [7 : 0] mesgMetaF_opcode__h22483; + wire [7 : 0] mesgMetaF_opcode__h23180; wire [3 : 0] sendData_byteEn__h18734; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d879, - x__h22523, - x__h22535, - x__h22547, - y__h22524, - y__h22536, - y__h22548; + wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889, + x__h23220, + x__h23232, + x__h23244, + y__h23221, + y__h23233, + y__h23245; wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541, wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669, x__h18446, - x__h24122; + x__h24819; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1210,6 +1209,15 @@ module mkSMAdapter4B(wciS0_Clk, !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wmrd_mesgBegin + assign WILL_FIRE_RL_wmrd_mesgBegin = + wci_wslv_cState == 3'd2 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + !wmi_sThreadBusy_d && + !wmi_sDataThreadBusy_d && + unrollCnt == 16'd0 ; + // rule RL_wsipass_doMessagePush assign WILL_FIRE_RL_wsipass_doMessagePush = wsiS_reqFifo$EMPTY_N && @@ -1217,6 +1225,14 @@ module mkSMAdapter4B(wciS0_Clk, wci_wslv_cState == 3'd2 && smaCtrl[3:0] == 4'h0 ; + // rule RL_wmrd_mesgBodyResponse + assign WILL_FIRE_RL_wmrd_mesgBodyResponse = + wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541 && + wci_wslv_cState == 3'd2 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + unrollCnt != 16'd0 ; + // rule RL_wmwt_mesgBegin assign CAN_FIRE_RL_wmwt_mesgBegin = wsiS_reqFifo$EMPTY_N && mesgTokenF$FULL_N && @@ -1421,23 +1437,10 @@ module mkSMAdapter4B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[57] ; assign MUX_mesgCount$write_1__SEL_1 = - MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ; + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ; assign MUX_mesgReqOK$write_1__SEL_3 = CAN_FIRE_RL_wmrd_mesgBodyPreRequest && !WILL_FIRE_RL_wmrd_mesgBodyRequest ; - assign MUX_unrollCnt$write_1__SEL_1 = - wci_wslv_cState == 3'd2 && - (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || - smaCtrl[3:0] == 4'h9) && - !wmi_sThreadBusy_d && - !wmi_sDataThreadBusy_d && - unrollCnt == 16'd0 ; - assign MUX_unrollCnt$write_1__SEL_2 = - wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541 && - wci_wslv_cState == 3'd2 && - (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || - smaCtrl[3:0] == 4'h9) && - unrollCnt != 16'd0 ; assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || @@ -1457,13 +1460,13 @@ module mkSMAdapter4B(wciS0_Clk, assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && wci_wslv_respF_c_r == 2'd1 ; - assign MUX_wmi_dhF_q_0$write_1__SEL_2 = + assign MUX_wmi_dhF_q_0$write_1__SEL_1 = WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 ; - assign MUX_wmi_dhF_q_1$write_1__SEL_2 = + assign MUX_wmi_dhF_q_1$write_1__SEL_1 = WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 ; - assign MUX_wmi_mFlagF_q_0$write_1__SEL_2 = + assign MUX_wmi_mFlagF_q_0$write_1__SEL_1 = WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ; - assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 = + assign MUX_wmi_mFlagF_q_1$write_1__SEL_1 = WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ; assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 = WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18446 ; @@ -1471,15 +1474,15 @@ module mkSMAdapter4B(wciS0_Clk, WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ; assign MUX_wmi_reqF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 ; - assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; - assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; - assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 ; + assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = CAN_FIRE_RL_wmwt_messagePush && !WILL_FIRE_RL_wmwt_messageFinalize ; @@ -1490,14 +1493,12 @@ module mkSMAdapter4B(wciS0_Clk, assign MUX_fabWordsRemain$write_1__VAL_1 = (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17902[13:0] ; assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; - assign MUX_mesgCount$write_1__VAL_1 = mesgCount + 32'd1 ; - assign MUX_mesgLengthSoFar$write_1__VAL_1 = - mesgLengthSoFar + mlInc__h22316 ; + assign MUX_mesgCount$write_1__VAL_2 = mesgCount + 32'd1 ; assign MUX_mesgReqAddr$write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[11:0], 2'd0 } ; assign MUX_opcode$write_1__VAL_3 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ; assign MUX_thisMesg$write_1__VAL_1 = - { mesgCount[7:0], mesgMetaF_opcode__h22483, x_length__h22884 } ; + { mesgCount[7:0], mesgMetaF_opcode__h23180, x_length__h23581 } ; assign MUX_thisMesg$write_1__VAL_2 = { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; assign MUX_unrollCnt$write_1__VAL_1 = @@ -1537,25 +1538,25 @@ module mkSMAdapter4B(wciS0_Clk, 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h23853 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24550 } ; assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r + 2'd1 ; assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ; assign MUX_wmi_dhF_q_0$write_1__VAL_1 = + { 1'd1, wsiS_reqFifo$D_OUT[57], wsiS_reqFifo$D_OUT[43:8] } ; + assign MUX_wmi_dhF_q_0$write_1__VAL_2 = (wmi_dhF_c_r == 2'd1) ? - MUX_wmi_dhF_q_0$write_1__VAL_2 : + MUX_wmi_dhF_q_0$write_1__VAL_1 : wmi_dhF_q_1 ; - assign MUX_wmi_dhF_q_0$write_1__VAL_2 = - { 1'd1, wsiS_reqFifo$D_OUT[57], wsiS_reqFifo$D_OUT[43:8] } ; - assign MUX_wmi_dhF_q_1$write_1__VAL_1 = - (wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_0$write_1__VAL_2 : 38'd0 ; + assign MUX_wmi_dhF_q_1$write_1__VAL_2 = + (wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_0$write_1__VAL_1 : 38'd0 ; assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ; assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ; - assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 = + assign MUX_wmi_mFlagF_q_0$write_1__VAL_2 = (wmi_mFlagF_c_r == 2'd1) ? value__h6580 : wmi_mFlagF_q_1 ; - assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 = + assign MUX_wmi_mFlagF_q_1$write_1__VAL_2 = (wmi_mFlagF_c_r == 2'd2) ? value__h6580 : 32'd0 ; assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 = - { mesgMetaF_opcode__h22483, mesgMetaF_length__h22484 } ; + { mesgMetaF_opcode__h23180, mesgMetaF_length__h23181 } ; assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r + 2'd1 ; assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r - 2'd1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_1 = @@ -1577,17 +1578,17 @@ module mkSMAdapter4B(wciS0_Clk, assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = (MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 || MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2) ? wsiS_reqFifo$D_OUT : MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; - assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = + (wsiM_reqFifo_c_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 = (wsiM_reqFifo_c_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : 61'h00000AAAAAAAAA00 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 = (respF_rCache[73] && respF_rCache[72:61] == respF_rRdPtr) ? @@ -1630,7 +1631,7 @@ module mkSMAdapter4B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_mFlagF_x_wire$wget = value__h6580 ; assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ; - assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_2 ; + assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_1 ; assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_wmiResponse$wget = { wmiM0_SResp, wmiM0_SData } ; assign wmi_wmiResponse$whas = 1'd1 ; @@ -1642,7 +1643,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wmi_operateD_1$whas = wci_wslv_cState == 3'd2 ; assign wmi_peerIsReady_1$wget = 1'd1 ; assign wmi_peerIsReady_1$whas = wmiM0_SReset_n ; - assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ; + assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ; assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; assign wsiM_operateD_1$wget = 1'd1 ; assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ; @@ -1732,9 +1733,9 @@ module mkSMAdapter4B(wciS0_Clk, wmi_operateD && wmi_peerIsReady && !wmi_sDataThreadBusy_d && wmi_dhF_c_r != 2'd0 ; assign wsiM_reqFifo_enqueueing$whas = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 || + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; @@ -1747,7 +1748,8 @@ module mkSMAdapter4B(wciS0_Clk, assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ; assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; - assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ; + assign respF_pwEnqueue$whas = + WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; assign wsi_Es_mDataInfo_w$whas = 1'd1 ; @@ -1793,11 +1795,11 @@ module mkSMAdapter4B(wciS0_Clk, // register fabWordsRemain assign fabWordsRemain$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? MUX_fabWordsRemain$write_1__VAL_1 : MUX_fabWordsRemain$write_1__VAL_2 ; assign fabWordsRemain$EN = - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wmrd_mesgBodyRequest ; // register firstMsgReq @@ -1807,38 +1809,38 @@ module mkSMAdapter4B(wciS0_Clk, // register lastMesg assign lastMesg$D_IN = (MUX_endOfMessage$write_1__SEL_1 || - MUX_unrollCnt$write_1__SEL_1) ? + WILL_FIRE_RL_wmrd_mesgBegin) ? thisMesg : 32'hFEFEFFFE ; assign lastMesg$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[57] || - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wci_ctrl_IsO ; // register mesgCount always@(MUX_mesgCount$write_1__SEL_1 or - MUX_mesgCount$write_1__VAL_1 or + MUX_mesgCount$write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_mesgCount$write_1__SEL_1: - mesgCount$D_IN = MUX_mesgCount$write_1__VAL_1; + mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2; WILL_FIRE_RL_wmwt_messageFinalize: - mesgCount$D_IN = MUX_mesgCount$write_1__VAL_1; + mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2; WILL_FIRE_RL_wci_ctrl_IsO: mesgCount$D_IN = 32'd0; default: mesgCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign mesgCount$EN = - MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 || + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 || WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wci_ctrl_IsO ; // register mesgLengthSoFar assign mesgLengthSoFar$D_IN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ? - MUX_mesgLengthSoFar$write_1__VAL_1 : + mlB__h23014 : 14'd0 ; assign mesgLengthSoFar$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || @@ -1850,21 +1852,22 @@ module mkSMAdapter4B(wciS0_Clk, // register mesgReqAddr assign mesgReqAddr$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? 14'd0 : MUX_mesgReqAddr$write_1__VAL_2 ; assign mesgReqAddr$EN = WILL_FIRE_RL_wmrd_mesgBodyRequest || - MUX_unrollCnt$write_1__SEL_1 ; + WILL_FIRE_RL_wmrd_mesgBegin ; // register mesgReqOK assign mesgReqOK$D_IN = - MUX_unrollCnt$write_1__SEL_2 || MUX_unrollCnt$write_1__SEL_1 ; + WILL_FIRE_RL_wmrd_mesgBodyResponse || + WILL_FIRE_RL_wmrd_mesgBegin ; assign mesgReqOK$EN = CAN_FIRE_RL_wmrd_mesgBodyPreRequest && !WILL_FIRE_RL_wmrd_mesgBodyRequest || - MUX_unrollCnt$write_1__SEL_1 || - MUX_unrollCnt$write_1__SEL_2 ; + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; // register opcode assign opcode$D_IN = @@ -1894,10 +1897,10 @@ module mkSMAdapter4B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d879, + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889, respF_pwEnqueue$whas && respF_wDataIn$wget[57], respF_pwEnqueue$whas && respF_wDataIn$wget[56], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr @@ -1916,13 +1919,13 @@ module mkSMAdapter4B(wciS0_Clk, // register thisMesg always@(MUX_endOfMessage$write_1__SEL_1 or MUX_thisMesg$write_1__VAL_1 or - MUX_unrollCnt$write_1__SEL_1 or + WILL_FIRE_RL_wmrd_mesgBegin or MUX_thisMesg$write_1__VAL_2 or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_endOfMessage$write_1__SEL_1: thisMesg$D_IN = MUX_thisMesg$write_1__VAL_1; - MUX_unrollCnt$write_1__SEL_1: + WILL_FIRE_RL_wmrd_mesgBegin: thisMesg$D_IN = MUX_thisMesg$write_1__VAL_2; WILL_FIRE_RL_wci_ctrl_IsO: thisMesg$D_IN = 32'hFEFEFFFE; default: thisMesg$D_IN = 32'hAAAAAAAA /* unspecified value */ ; @@ -1931,16 +1934,17 @@ module mkSMAdapter4B(wciS0_Clk, assign thisMesg$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[57] || - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wci_ctrl_IsO ; // register unrollCnt assign unrollCnt$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? MUX_unrollCnt$write_1__VAL_1 : MUX_unrollCnt$write_1__VAL_2 ; assign unrollCnt$EN = - MUX_unrollCnt$write_1__SEL_1 || MUX_unrollCnt$write_1__SEL_2 ; + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; // register valExpect assign valExpect$D_IN = valExpect + 32'd1 ; @@ -2087,44 +2091,44 @@ module mkSMAdapter4B(wciS0_Clk, WILL_FIRE_RL_wmi_dhF_incCtr || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_0 - always@(WILL_FIRE_RL_wmi_dhF_both or + always@(MUX_wmi_dhF_q_0$write_1__SEL_1 or MUX_wmi_dhF_q_0$write_1__VAL_1 or - MUX_wmi_dhF_q_0$write_1__SEL_2 or + WILL_FIRE_RL_wmi_dhF_both or MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_dhF_both: + MUX_wmi_dhF_q_0$write_1__SEL_1: wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; - MUX_wmi_dhF_q_0$write_1__SEL_2: + WILL_FIRE_RL_wmi_dhF_both: wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_0$D_IN = wmi_dhF_q_1; default: wmi_dhF_q_0$D_IN = 38'h2AAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_0$EN = - WILL_FIRE_RL_wmi_dhF_both || WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_dhF_both || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 - always@(WILL_FIRE_RL_wmi_dhF_both or - MUX_wmi_dhF_q_1$write_1__VAL_1 or - MUX_wmi_dhF_q_1$write_1__SEL_2 or - MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + always@(MUX_wmi_dhF_q_1$write_1__SEL_1 or + MUX_wmi_dhF_q_0$write_1__VAL_1 or + WILL_FIRE_RL_wmi_dhF_both or + MUX_wmi_dhF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case + MUX_wmi_dhF_q_1$write_1__SEL_1: + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; WILL_FIRE_RL_wmi_dhF_both: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_1; - MUX_wmi_dhF_q_1$write_1__SEL_2: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1$D_IN = 38'd0; default: wmi_dhF_q_1$D_IN = 38'h2AAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_1$EN = - WILL_FIRE_RL_wmi_dhF_both || WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_dhF_both || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_errorSticky @@ -2145,41 +2149,42 @@ module mkSMAdapter4B(wciS0_Clk, WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_mFlagF_q_0 - always@(WILL_FIRE_RL_wmi_mFlagF_both or - MUX_wmi_mFlagF_q_0$write_1__VAL_1 or - MUX_wmi_mFlagF_q_0$write_1__SEL_2 or - value__h6580 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + always@(MUX_wmi_mFlagF_q_0$write_1__SEL_1 or + value__h6580 or + WILL_FIRE_RL_wmi_mFlagF_both or + MUX_wmi_mFlagF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) begin case (1'b1) // synopsys parallel_case + MUX_wmi_mFlagF_q_0$write_1__SEL_1: wmi_mFlagF_q_0$D_IN = value__h6580; WILL_FIRE_RL_wmi_mFlagF_both: - wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_1; - MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6580; + wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_2; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1; default: wmi_mFlagF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign wmi_mFlagF_q_0$EN = - WILL_FIRE_RL_wmi_mFlagF_both || WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_mFlagF_both || WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_mFlagF_q_1 - always@(WILL_FIRE_RL_wmi_mFlagF_both or - MUX_wmi_mFlagF_q_1$write_1__VAL_1 or - MUX_wmi_mFlagF_q_1$write_1__SEL_2 or - value__h6580 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + always@(MUX_wmi_mFlagF_q_1$write_1__SEL_1 or + value__h6580 or + WILL_FIRE_RL_wmi_mFlagF_both or + MUX_wmi_mFlagF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmi_mFlagF_decCtr) begin case (1'b1) // synopsys parallel_case + MUX_wmi_mFlagF_q_1$write_1__SEL_1: wmi_mFlagF_q_1$D_IN = value__h6580; WILL_FIRE_RL_wmi_mFlagF_both: - wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_1; - MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6580; + wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_2; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0; default: wmi_mFlagF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign wmi_mFlagF_q_1$EN = - WILL_FIRE_RL_wmi_mFlagF_both || WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_mFlagF_both || WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_operateD @@ -2325,16 +2330,16 @@ module mkSMAdapter4B(wciS0_Clk, WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or - MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or + WILL_FIRE_RL_wsiM_reqFifo_both or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; - MUX_wsiM_reqFifo_q_0$write_1__SEL_2: + WILL_FIRE_RL_wsiM_reqFifo_both: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1; @@ -2343,22 +2348,22 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or - MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or + WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; WILL_FIRE_RL_wsiM_reqFifo_both: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; - MUX_wsiM_reqFifo_q_1$write_1__SEL_2: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00; default: wsiM_reqFifo_q_1$D_IN = @@ -2366,8 +2371,8 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -2496,10 +2501,10 @@ module mkSMAdapter4B(wciS0_Clk, x__h16444[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d879, + { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889, respF_pwEnqueue$whas && respF_wDataIn$wget[57], respF_pwEnqueue$whas && respF_wDataIn$wget[56], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 } ; assign respF_memory$DIB = 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; assign respF_memory$WEB = 1'd0 ; @@ -2517,7 +2522,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wmi_respF$ENQ = wmi_respF$FULL_N && wmi_operateD && wmi_peerIsReady && wmi_wmiResponse$wget[33:32] != 2'd0 ; - assign wmi_respF$DEQ = MUX_unrollCnt$write_1__SEL_2 ; + assign wmi_respF$DEQ = WILL_FIRE_RL_wmrd_mesgBodyResponse ; assign wmi_respF$CLR = 1'b0 ; // submodule wsiS_reqFifo @@ -2527,43 +2532,43 @@ module mkSMAdapter4B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d879 = - respF_pwEnqueue$whas ? respF_wDataIn$wget[60:58] : 3'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889 = + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 = respF_pwEnqueue$whas ? respF_wDataIn$wget[55:0] : 56'd0 ; + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889 = + respF_pwEnqueue$whas ? respF_wDataIn$wget[60:58] : 3'd0 ; assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && (!x__h18446 || wmi_mFlagF_c_r != 2'd2) ; assign b__h15090 = -fabWordsCurReq[11:0] ; assign b__h17902 = x__h18022 + residue__h17765 ; assign b__h18275 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; - assign mesgMetaF_length__h22484 = + assign mesgMetaF_length__h23181 = (wsiS_reqFifo$D_OUT[57] && wsiS_reqFifo$D_OUT[11:8] == 4'd0 && mesgLengthSoFar == 14'd0) ? 24'd0 : - { 10'd0, mlB__h22317 } ; - assign mesgMetaF_opcode__h22483 = opcode[8] ? opcode[7:0] : 8'd0 ; - assign mlB__h22317 = MUX_mesgLengthSoFar$write_1__VAL_1 ; - assign mlInc__h22316 = + { 10'd0, mlB__h23014 } ; + assign mesgMetaF_opcode__h23180 = opcode[8] ? opcode[7:0] : 8'd0 ; + assign mlB__h23014 = mesgLengthSoFar + mlInc__h23013 ; + assign mlInc__h23013 = wsiS_reqFifo$D_OUT[57] ? - { 11'd0, x__h22523 + y__h22524 } : + { 11'd0, x__h23220 + y__h23221 } : 14'd4 ; - assign rdat__h23896 = hasDebugLogic ? mesgCount : 32'd0 ; - assign rdat__h23902 = hasDebugLogic ? abortCount : 32'd0 ; - assign rdat__h23908 = hasDebugLogic ? thisMesg : 32'd0 ; - assign rdat__h23921 = hasDebugLogic ? lastMesg : 32'd0 ; - assign rdat__h23944 = hasDebugLogic ? { 16'd0, x__h23948 } : 32'd0 ; - assign rdat__h24044 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h24058 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h24066 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h24072 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h24086 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h24094 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h24100 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; - assign rdat__h24106 = hasDebugLogic ? wmwtPushCount : 32'd0 ; - assign rdat__h24112 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; - assign rdat__h24118 = hasDebugLogic ? { 31'd0, x__h24122 } : 32'd0 ; - assign rdat__h24128 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; + assign rdat__h24593 = hasDebugLogic ? mesgCount : 32'd0 ; + assign rdat__h24599 = hasDebugLogic ? abortCount : 32'd0 ; + assign rdat__h24605 = hasDebugLogic ? thisMesg : 32'd0 ; + assign rdat__h24618 = hasDebugLogic ? lastMesg : 32'd0 ; + assign rdat__h24641 = hasDebugLogic ? { 16'd0, x__h24645 } : 32'd0 ; + assign rdat__h24741 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h24755 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h24763 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h24769 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h24783 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h24791 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h24797 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; + assign rdat__h24803 = hasDebugLogic ? wmwtPushCount : 32'd0 ; + assign rdat__h24809 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; + assign rdat__h24815 = hasDebugLogic ? { 31'd0, x__h24819 } : 32'd0 ; + assign rdat__h24825 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; assign residue__h17765 = ({ 4'd0, wmi_sFlagReg[1:0] } == 6'd0) ? 24'd0 : 24'd1 ; assign sendData_burstLength__h18732 = @@ -2697,50 +2702,50 @@ module mkSMAdapter4B(wciS0_Clk, 6'd31) ? 32'h7FFFFFFF : 32'hFFFFFFFF))))))))))))))))))))))))))))))) ; - assign x__h22523 = x__h22535 + y__h22536 ; - assign x__h22535 = x__h22547 + y__h22548 ; - assign x__h22547 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; - assign x__h23948 = { wsiS_statusR, wsiM_statusR } ; - assign x__h24122 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; - assign x_length__h22884 = { 2'd0, mlB__h22317 } ; - assign y__h22524 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h22536 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h22548 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; + assign x__h23220 = x__h23232 + y__h23233 ; + assign x__h23232 = x__h23244 + y__h23245 ; + assign x__h23244 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; + assign x__h24645 = { wsiS_statusR, wsiM_statusR } ; + assign x__h24819 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; + assign x_length__h23581 = { 2'd0, mlB__h23014 } ; + assign y__h23221 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h23233 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h23245 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; always@(wci_wslv_reqF$D_OUT or smaCtrl or - rdat__h23896 or - rdat__h23902 or - rdat__h23908 or - rdat__h23921 or - rdat__h23944 or - rdat__h24044 or - rdat__h24058 or - rdat__h24066 or - rdat__h24072 or - rdat__h24086 or - rdat__h24094 or - rdat__h24100 or - rdat__h24106 or rdat__h24112 or rdat__h24118 or rdat__h24128) + rdat__h24593 or + rdat__h24599 or + rdat__h24605 or + rdat__h24618 or + rdat__h24641 or + rdat__h24741 or + rdat__h24755 or + rdat__h24763 or + rdat__h24769 or + rdat__h24783 or + rdat__h24791 or + rdat__h24797 or + rdat__h24803 or rdat__h24809 or rdat__h24815 or rdat__h24825) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h23853 = smaCtrl; - 8'h04: g_data__h23853 = rdat__h23896; - 8'h08: g_data__h23853 = rdat__h23902; - 8'h10: g_data__h23853 = rdat__h23908; - 8'h14: g_data__h23853 = rdat__h23921; - 8'h18: g_data__h23853 = rdat__h23944; - 8'h20: g_data__h23853 = rdat__h24044; - 8'h24: g_data__h23853 = rdat__h24058; - 8'h28: g_data__h23853 = rdat__h24066; - 8'h2C: g_data__h23853 = rdat__h24072; - 8'h30: g_data__h23853 = rdat__h24086; - 8'h34: g_data__h23853 = rdat__h24094; - 8'h38: g_data__h23853 = rdat__h24100; - 8'h3C: g_data__h23853 = rdat__h24106; - 8'h40: g_data__h23853 = rdat__h24112; - 8'h44: g_data__h23853 = rdat__h24118; - 8'h48: g_data__h23853 = rdat__h24128; - default: g_data__h23853 = 32'd0; + 8'h0: g_data__h24550 = smaCtrl; + 8'h04: g_data__h24550 = rdat__h24593; + 8'h08: g_data__h24550 = rdat__h24599; + 8'h10: g_data__h24550 = rdat__h24605; + 8'h14: g_data__h24550 = rdat__h24618; + 8'h18: g_data__h24550 = rdat__h24641; + 8'h20: g_data__h24550 = rdat__h24741; + 8'h24: g_data__h24550 = rdat__h24755; + 8'h28: g_data__h24550 = rdat__h24763; + 8'h2C: g_data__h24550 = rdat__h24769; + 8'h30: g_data__h24550 = rdat__h24783; + 8'h34: g_data__h24550 = rdat__h24791; + 8'h38: g_data__h24550 = rdat__h24797; + 8'h3C: g_data__h24550 = rdat__h24803; + 8'h40: g_data__h24550 = rdat__h24809; + 8'h44: g_data__h24550 = rdat__h24815; + 8'h48: g_data__h24550 = rdat__h24825; + default: g_data__h24550 = 32'd0; endcase end @@ -3123,13 +3128,13 @@ module mkSMAdapter4B(wciS0_Clk, begin #0; if (wciS0_MReset_n) - if (MUX_unrollCnt$write_1__SEL_1) + if (WILL_FIRE_RL_wmrd_mesgBegin) begin v__h18191 = $time; #0; end if (wciS0_MReset_n) - if (MUX_unrollCnt$write_1__SEL_1) + if (WILL_FIRE_RL_wmrd_mesgBegin) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", v__h18191, mesgCount, @@ -3138,46 +3143,46 @@ module mkSMAdapter4B(wciS0_Clk, if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56]) begin - v__h21903 = $time; + v__h22600 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56]) $display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x", - v__h21903, + v__h22600, mesgCount, wsiS_reqFifo$D_OUT[55:44], wsiS_reqFifo$D_OUT[7:0]); if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56]) begin - v__h21962 = $time; + v__h22659 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56]) $display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x", - v__h21962, + v__h22659, mesgCount); if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_doAbort) begin - v__h23304 = $time; + v__h24001 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_doAbort) - $display("[%0d]: %m: wmwt_doAbort", v__h23304); + $display("[%0d]: %m: wmwt_doAbort", v__h24001); if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_messageFinalize) begin - v__h23487 = $time; + v__h24184 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wmwt_messageFinalize) $display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x", - v__h23487, + v__h24184, mesgCount, thisMesg[15:0]); if (wciS0_MReset_n) @@ -3195,26 +3200,26 @@ module mkSMAdapter4B(wciS0_Clk, if (wciS0_MReset_n) if (WILL_FIRE_RL_wci_cfwr) begin - v__h23683 = $time; + v__h24380 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h23683, + v__h24380, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h24341 = $time; + v__h25038 = $time; #0; end if (wciS0_MReset_n) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x", - v__h24341, + v__h25038, smaCtrl); if (wciS0_MReset_n) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) diff --git a/rtl/mkSMAdapter8B.v b/rtl/mkSMAdapter8B.v index d44d1b83..fe3f43e8 100644 --- a/rtl/mkSMAdapter8B.v +++ b/rtl/mkSMAdapter8B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:11 EDT 2012 +// On Mon Sep 24 13:38:25 EDT 2012 // // // Ports: @@ -911,7 +911,9 @@ module mkSMAdapter8B(wciS0_Clk, WILL_FIRE_RL_wmi_reqF_decCtr, WILL_FIRE_RL_wmi_reqF_deq, WILL_FIRE_RL_wmi_reqF_incCtr, + WILL_FIRE_RL_wmrd_mesgBegin, WILL_FIRE_RL_wmrd_mesgBodyRequest, + WILL_FIRE_RL_wmrd_mesgBodyResponse, WILL_FIRE_RL_wmrd_mesgResptoWsi, WILL_FIRE_RL_wmwt_doAbort, WILL_FIRE_RL_wmwt_mesgBegin, @@ -968,8 +970,6 @@ module mkSMAdapter8B(wciS0_Clk, wire MUX_endOfMessage$write_1__SEL_1, MUX_mesgCount$write_1__SEL_1, MUX_mesgReqOK$write_1__SEL_3, - MUX_unrollCnt$write_1__SEL_1, - MUX_unrollCnt$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, @@ -999,7 +999,7 @@ module mkSMAdapter8B(wciS0_Clk, v__h3825, v__h3969; reg [31 : 0] g_data__h24017; - wire [91 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d898; + wire [91 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894; wire [31 : 0] rdat__h24060, rdat__h24066, rdat__h24072, @@ -1217,6 +1217,15 @@ module mkSMAdapter8B(wciS0_Clk, !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + // rule RL_wmrd_mesgBegin + assign WILL_FIRE_RL_wmrd_mesgBegin = + wci_wslv_cState == 3'd2 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + !wmi_sThreadBusy_d && + !wmi_sDataThreadBusy_d && + unrollCnt == 16'd0 ; + // rule RL_wsipass_doMessagePush assign WILL_FIRE_RL_wsipass_doMessagePush = wsiS_reqFifo$EMPTY_N && @@ -1224,6 +1233,14 @@ module mkSMAdapter8B(wciS0_Clk, wci_wslv_cState == 3'd2 && smaCtrl[3:0] == 4'h0 ; + // rule RL_wmrd_mesgBodyResponse + assign WILL_FIRE_RL_wmrd_mesgBodyResponse = + wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && + wci_wslv_cState == 3'd2 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + unrollCnt != 16'd0 ; + // rule RL_wmwt_mesgBegin assign CAN_FIRE_RL_wmwt_mesgBegin = wsiS_reqFifo$EMPTY_N && mesgTokenF$FULL_N && @@ -1428,23 +1445,10 @@ module mkSMAdapter8B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[93] ; assign MUX_mesgCount$write_1__SEL_1 = - MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ; + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ; assign MUX_mesgReqOK$write_1__SEL_3 = CAN_FIRE_RL_wmrd_mesgBodyPreRequest && !WILL_FIRE_RL_wmrd_mesgBodyRequest ; - assign MUX_unrollCnt$write_1__SEL_1 = - wci_wslv_cState == 3'd2 && - (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || - smaCtrl[3:0] == 4'h9) && - !wmi_sThreadBusy_d && - !wmi_sDataThreadBusy_d && - unrollCnt == 16'd0 ; - assign MUX_unrollCnt$write_1__SEL_2 = - wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && - wci_wslv_cState == 3'd2 && - (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || - smaCtrl[3:0] == 4'h9) && - unrollCnt != 16'd0 ; assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || @@ -1483,10 +1487,10 @@ module mkSMAdapter8B(wciS0_Clk, assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; + assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 ; - assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = CAN_FIRE_RL_wmwt_messagePush && !WILL_FIRE_RL_wmwt_messageFinalize ; @@ -1739,9 +1743,9 @@ module mkSMAdapter8B(wciS0_Clk, wmi_operateD && wmi_peerIsReady && !wmi_sDataThreadBusy_d && wmi_dhF_c_r != 2'd0 ; assign wsiM_reqFifo_enqueueing$whas = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 || - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; @@ -1754,7 +1758,8 @@ module mkSMAdapter8B(wciS0_Clk, assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ; assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; - assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ; + assign respF_pwEnqueue$whas = + WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; assign wsi_Es_mDataInfo_w$whas = 1'd1 ; @@ -1800,11 +1805,11 @@ module mkSMAdapter8B(wciS0_Clk, // register fabWordsRemain assign fabWordsRemain$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? MUX_fabWordsRemain$write_1__VAL_1 : MUX_fabWordsRemain$write_1__VAL_2 ; assign fabWordsRemain$EN = - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wmrd_mesgBodyRequest ; // register firstMsgReq @@ -1814,13 +1819,13 @@ module mkSMAdapter8B(wciS0_Clk, // register lastMesg assign lastMesg$D_IN = (MUX_endOfMessage$write_1__SEL_1 || - MUX_unrollCnt$write_1__SEL_1) ? + WILL_FIRE_RL_wmrd_mesgBegin) ? thisMesg : 32'hFEFEFFFE ; assign lastMesg$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[93] || - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wci_ctrl_IsO ; // register mesgCount @@ -1838,7 +1843,7 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign mesgCount$EN = - MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 || + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 || WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wci_ctrl_IsO ; @@ -1857,21 +1862,22 @@ module mkSMAdapter8B(wciS0_Clk, // register mesgReqAddr assign mesgReqAddr$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? 14'd0 : MUX_mesgReqAddr$write_1__VAL_2 ; assign mesgReqAddr$EN = WILL_FIRE_RL_wmrd_mesgBodyRequest || - MUX_unrollCnt$write_1__SEL_1 ; + WILL_FIRE_RL_wmrd_mesgBegin ; // register mesgReqOK assign mesgReqOK$D_IN = - MUX_unrollCnt$write_1__SEL_2 || MUX_unrollCnt$write_1__SEL_1 ; + WILL_FIRE_RL_wmrd_mesgBodyResponse || + WILL_FIRE_RL_wmrd_mesgBegin ; assign mesgReqOK$EN = CAN_FIRE_RL_wmrd_mesgBodyPreRequest && !WILL_FIRE_RL_wmrd_mesgBodyRequest || - MUX_unrollCnt$write_1__SEL_1 || - MUX_unrollCnt$write_1__SEL_2 ; + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; // register opcode assign opcode$D_IN = @@ -1904,7 +1910,7 @@ module mkSMAdapter8B(wciS0_Clk, IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893, respF_pwEnqueue$whas && respF_wDataIn$wget[93], respF_pwEnqueue$whas && respF_wDataIn$wget[92], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d898 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr @@ -1923,13 +1929,13 @@ module mkSMAdapter8B(wciS0_Clk, // register thisMesg always@(MUX_endOfMessage$write_1__SEL_1 or MUX_thisMesg$write_1__VAL_1 or - MUX_unrollCnt$write_1__SEL_1 or + WILL_FIRE_RL_wmrd_mesgBegin or MUX_thisMesg$write_1__VAL_2 or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_endOfMessage$write_1__SEL_1: thisMesg$D_IN = MUX_thisMesg$write_1__VAL_1; - MUX_unrollCnt$write_1__SEL_1: + WILL_FIRE_RL_wmrd_mesgBegin: thisMesg$D_IN = MUX_thisMesg$write_1__VAL_2; WILL_FIRE_RL_wci_ctrl_IsO: thisMesg$D_IN = 32'hFEFEFFFE; default: thisMesg$D_IN = 32'hAAAAAAAA /* unspecified value */ ; @@ -1938,16 +1944,17 @@ module mkSMAdapter8B(wciS0_Clk, assign thisMesg$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[93] || - MUX_unrollCnt$write_1__SEL_1 || + WILL_FIRE_RL_wmrd_mesgBegin || WILL_FIRE_RL_wci_ctrl_IsO ; // register unrollCnt assign unrollCnt$D_IN = - MUX_unrollCnt$write_1__SEL_1 ? + WILL_FIRE_RL_wmrd_mesgBegin ? MUX_unrollCnt$write_1__VAL_1 : MUX_unrollCnt$write_1__VAL_2 ; assign unrollCnt$EN = - MUX_unrollCnt$write_1__SEL_1 || MUX_unrollCnt$write_1__SEL_2 ; + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; // register valExpect assign valExpect$D_IN = valExpect + 64'd1 ; @@ -2508,7 +2515,7 @@ module mkSMAdapter8B(wciS0_Clk, { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893, respF_pwEnqueue$whas && respF_wDataIn$wget[93], respF_pwEnqueue$whas && respF_wDataIn$wget[92], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d898 } ; + IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894 } ; assign respF_memory$DIB = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; @@ -2527,7 +2534,7 @@ module mkSMAdapter8B(wciS0_Clk, assign wmi_respF$ENQ = wmi_respF$FULL_N && wmi_operateD && wmi_peerIsReady && wmi_wmiResponse$wget[65:64] != 2'd0 ; - assign wmi_respF$DEQ = MUX_unrollCnt$write_1__SEL_2 ; + assign wmi_respF$DEQ = WILL_FIRE_RL_wmrd_mesgBodyResponse ; assign wmi_respF$CLR = 1'b0 ; // submodule wsiS_reqFifo @@ -2539,7 +2546,7 @@ module mkSMAdapter8B(wciS0_Clk, // remaining internal signals assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d893 = respF_pwEnqueue$whas ? respF_wDataIn$wget[96:94] : 3'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d898 = + assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894 = respF_pwEnqueue$whas ? respF_wDataIn$wget[91:0] : 92'd0 ; assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && @@ -3144,13 +3151,13 @@ module mkSMAdapter8B(wciS0_Clk, begin #0; if (wciS0_MReset_n) - if (MUX_unrollCnt$write_1__SEL_1) + if (WILL_FIRE_RL_wmrd_mesgBegin) begin v__h18191 = $time; #0; end if (wciS0_MReset_n) - if (MUX_unrollCnt$write_1__SEL_1) + if (WILL_FIRE_RL_wmrd_mesgBegin) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", v__h18191, mesgCount, diff --git a/rtl/mkTLPCM.v b/rtl/mkTLPCM.v index 1e7d3e6b..026384e9 100644 --- a/rtl/mkTLPCM.v +++ b/rtl/mkTLPCM.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:33 EDT 2012 +// On Mon Sep 24 13:39:04 EDT 2012 // // // Ports: diff --git a/rtl/mkTLPClientNode.v b/rtl/mkTLPClientNode.v index 4b2a3b64..82fb434f 100644 --- a/rtl/mkTLPClientNode.v +++ b/rtl/mkTLPClientNode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:33 EDT 2012 +// On Mon Sep 24 13:39:04 EDT 2012 // // // Ports: diff --git a/rtl/mkTLPSM.v b/rtl/mkTLPSM.v index c92bbcb1..6f1b18bc 100644 --- a/rtl/mkTLPSM.v +++ b/rtl/mkTLPSM.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:33 EDT 2012 +// On Mon Sep 24 13:39:04 EDT 2012 // // // Ports: diff --git a/rtl/mkTLPServerNode.v b/rtl/mkTLPServerNode.v index cad9130a..44f9473b 100644 --- a/rtl/mkTLPServerNode.v +++ b/rtl/mkTLPServerNode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:45:33 EDT 2012 +// On Mon Sep 24 13:39:04 EDT 2012 // // // Ports: diff --git a/rtl/mkTimeClient.v b/rtl/mkTimeClient.v index ac392fee..d2fca9fc 100644 --- a/rtl/mkTimeClient.v +++ b/rtl/mkTimeClient.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:44:43 EDT 2012 +// On Mon Sep 24 13:38:37 EDT 2012 // // // Ports: diff --git a/rtl/mkWSICaptureWorker4B.v b/rtl/mkWSICaptureWorker4B.v index 408b4bf0..30553680 100644 --- a/rtl/mkWSICaptureWorker4B.v +++ b/rtl/mkWSICaptureWorker4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:44:54 EDT 2012 +// On Mon Sep 24 13:38:42 EDT 2012 // // // Ports: @@ -830,7 +830,6 @@ module mkWSICaptureWorker4B(wciS0_Clk, wire CAN_FIRE_RL_wci_cfrd, WILL_FIRE_RL_dataBram_serverAdapterB_outData_enqAndDeq, WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways, - WILL_FIRE_RL_metaBram_serverAdapterA_outData_setFirstEnq, WILL_FIRE_RL_metaBram_serverAdapterB_1_outData_enqAndDeq, WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways, WILL_FIRE_RL_metaBram_serverAdapterB_2_outData_enqAndDeq, @@ -866,7 +865,6 @@ module mkWSICaptureWorker4B(wciS0_Clk, MUX_dataCount$write_1__SEL_1, MUX_dataCount$write_1__SEL_2, MUX_metaCount$write_1__SEL_1, - MUX_metaCount$write_1__SEL_2, MUX_splitReadInFlight$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, @@ -886,10 +884,11 @@ module mkWSICaptureWorker4B(wciS0_Clk, v__h3958; reg [31 : 0] IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951, v__h26683; - reg CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1, + reg CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q2, IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918, IF_wci_wslv_reqF_first__5_BITS_35_TO_34_80_EQ__ETC___d993, IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d997; + wire [63 : 0] wtiS_nowReq_BITS_63_TO_0__q1; wire [31 : 0] g_data__h27773, rdat___1__h26780, rdat___1__h26864, @@ -917,8 +916,8 @@ module mkWSICaptureWorker4B(wciS0_Clk, wire IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d927, NOT_controlReg_30_BIT_0_31_32_OR_controlReg_30_ETC___d856, controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878, - dataCount_37_ULT_1024___d1092, - metaCount_34_ULT_1024___d1142, + dataCount_37_ULT_1024___d1204, + metaCount_34_ULT_1024___d1203, splaF_i_notEmpty__96_AND_IF_splaF_first__97_BI_ETC___d929; // value method wciS0_sResp @@ -1258,11 +1257,6 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways = WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h800 ; - // rule RL_metaBram_serverAdapterA_outData_setFirstEnq - assign WILL_FIRE_RL_metaBram_serverAdapterA_outData_setFirstEnq = - !metaBram_serverAdapterA_outDataCore$EMPTY_N && - metaBram_serverAdapterA_outData_enqData$whas ; - // rule RL_metaBram_serverAdapterB_stageReadResponseAlways assign WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways = WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 && @@ -1363,10 +1357,6 @@ module mkWSICaptureWorker4B(wciS0_Clk, controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 ; assign MUX_metaCount$write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ; - assign MUX_metaCount$write_1__SEL_2 = - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && - controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 && - wsiS_reqFifo$D_OUT[57] ; assign MUX_splitReadInFlight$write_1__SEL_1 = WILL_FIRE_RL_wci_cfrd && (wci_wslv_reqF$D_OUT[63:52] == 12'h800 || @@ -1502,7 +1492,11 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign wtiS_operateD_1$whas = 1'b0 ; assign nowW$wget = wtiS_nowReq[63:0] ; assign nowW$whas = 1'd1 ; - assign statusReg_w$wget = rdat___1__h26780 ; + assign statusReg_w$wget = + { 6'd40, + !metaCount_34_ULT_1024___d1203, + !dataCount_37_ULT_1024___d1204, + 24'd2361866 } ; assign statusReg_w$whas = 1'd1 ; assign dataBram_serverAdapterA_outData_enqData$wget = dataBram_memory$DOA ; assign dataBram_serverAdapterA_outData_enqData$whas = @@ -1535,7 +1529,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, dataBram_serverAdapterB_outDataCore$FULL_N) && dataBram_serverAdapterB_s1[1] && dataBram_serverAdapterB_s1[0] ; - assign dataBram_serverAdapterB_outData_outData$wget = y_avValue__h25924 ; + assign dataBram_serverAdapterB_outData_outData$wget = + dataBram_serverAdapterB_outDataCore$EMPTY_N ? + dataBram_serverAdapterB_outDataCore$D_OUT : + dataBram_memory$DOB ; assign dataBram_serverAdapterB_outData_outData$whas = dataBram_serverAdapterB_outDataCore$EMPTY_N || !dataBram_serverAdapterB_outDataCore$EMPTY_N && @@ -1561,12 +1558,13 @@ module mkWSICaptureWorker4B(wciS0_Clk, metaBram_serverAdapterA_s1[1] && metaBram_serverAdapterA_s1[0] ; assign metaBram_serverAdapterA_outData_outData$wget = - WILL_FIRE_RL_metaBram_serverAdapterA_outData_setFirstEnq ? - metaBram_memory$DOA : - metaBram_serverAdapterA_outDataCore$D_OUT ; + metaBram_serverAdapterA_outDataCore$EMPTY_N ? + metaBram_serverAdapterA_outDataCore$D_OUT : + metaBram_memory$DOA ; assign metaBram_serverAdapterA_outData_outData$whas = - WILL_FIRE_RL_metaBram_serverAdapterA_outData_setFirstEnq || - metaBram_serverAdapterA_outDataCore$EMPTY_N ; + metaBram_serverAdapterA_outDataCore$EMPTY_N || + !metaBram_serverAdapterA_outDataCore$EMPTY_N && + metaBram_serverAdapterA_outData_enqData$whas ; assign metaBram_serverAdapterA_cnt_1$wget = 3'd1 ; assign metaBram_serverAdapterA_cnt_1$whas = 1'b0 ; assign metaBram_serverAdapterA_cnt_2$wget = 3'h0 ; @@ -1575,16 +1573,22 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign metaBram_serverAdapterA_cnt_3$whas = 1'b0 ; assign metaBram_serverAdapterA_writeWithResp$wget = 2'd2 ; assign metaBram_serverAdapterA_writeWithResp$whas = - MUX_metaCount$write_1__SEL_2 ; + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 && + wsiS_reqFifo$D_OUT[57] ; assign metaBram_serverAdapterA_s1_1$wget = 2'd2 ; - assign metaBram_serverAdapterA_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_serverAdapterA_s1_1$whas = + metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_serverAdapterB_outData_enqData$wget = metaBram_memory$DOB ; assign metaBram_serverAdapterB_outData_enqData$whas = (!metaBram_serverAdapterB_s1[0] || metaBram_serverAdapterB_outDataCore$FULL_N) && metaBram_serverAdapterB_s1[1] && metaBram_serverAdapterB_s1[0] ; - assign metaBram_serverAdapterB_outData_outData$wget = y_avValue__h25968 ; + assign metaBram_serverAdapterB_outData_outData$wget = + metaBram_serverAdapterB_outDataCore$EMPTY_N ? + metaBram_serverAdapterB_outDataCore$D_OUT : + metaBram_memory$DOB ; assign metaBram_serverAdapterB_outData_outData$whas = metaBram_serverAdapterB_outDataCore$EMPTY_N || !metaBram_serverAdapterB_outDataCore$EMPTY_N && @@ -1626,9 +1630,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign metaBram_serverAdapterA_1_cnt_3$whas = 1'b0 ; assign metaBram_serverAdapterA_1_writeWithResp$wget = 2'd2 ; assign metaBram_serverAdapterA_1_writeWithResp$whas = - MUX_metaCount$write_1__SEL_2 ; + metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_serverAdapterA_1_s1_1$wget = 2'd2 ; - assign metaBram_serverAdapterA_1_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_serverAdapterA_1_s1_1$whas = + metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_serverAdapterB_1_outData_enqData$wget = metaBram_memory_1$DOB ; assign metaBram_serverAdapterB_1_outData_enqData$whas = @@ -1636,7 +1641,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, metaBram_serverAdapterB_1_outDataCore$FULL_N) && metaBram_serverAdapterB_1_s1[1] && metaBram_serverAdapterB_1_s1[0] ; - assign metaBram_serverAdapterB_1_outData_outData$wget = y_avValue__h26008 ; + assign metaBram_serverAdapterB_1_outData_outData$wget = + metaBram_serverAdapterB_1_outDataCore$EMPTY_N ? + metaBram_serverAdapterB_1_outDataCore$D_OUT : + metaBram_memory_1$DOB ; assign metaBram_serverAdapterB_1_outData_outData$whas = metaBram_serverAdapterB_1_outDataCore$EMPTY_N || !metaBram_serverAdapterB_1_outDataCore$EMPTY_N && @@ -1678,9 +1686,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign metaBram_serverAdapterA_2_cnt_3$whas = 1'b0 ; assign metaBram_serverAdapterA_2_writeWithResp$wget = 2'd2 ; assign metaBram_serverAdapterA_2_writeWithResp$whas = - MUX_metaCount$write_1__SEL_2 ; + metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_serverAdapterA_2_s1_1$wget = 2'd2 ; - assign metaBram_serverAdapterA_2_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_serverAdapterA_2_s1_1$whas = + metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_serverAdapterB_2_outData_enqData$wget = metaBram_memory_2$DOB ; assign metaBram_serverAdapterB_2_outData_enqData$whas = @@ -1688,7 +1697,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, metaBram_serverAdapterB_2_outDataCore$FULL_N) && metaBram_serverAdapterB_2_s1[1] && metaBram_serverAdapterB_2_s1[0] ; - assign metaBram_serverAdapterB_2_outData_outData$wget = y_avValue__h26048 ; + assign metaBram_serverAdapterB_2_outData_outData$wget = + metaBram_serverAdapterB_2_outDataCore$EMPTY_N ? + metaBram_serverAdapterB_2_outDataCore$D_OUT : + metaBram_memory_2$DOB ; assign metaBram_serverAdapterB_2_outData_outData$whas = metaBram_serverAdapterB_2_outDataCore$EMPTY_N || !metaBram_serverAdapterB_2_outDataCore$EMPTY_N && @@ -1730,9 +1742,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign metaBram_serverAdapterA_3_cnt_3$whas = 1'b0 ; assign metaBram_serverAdapterA_3_writeWithResp$wget = 2'd2 ; assign metaBram_serverAdapterA_3_writeWithResp$whas = - MUX_metaCount$write_1__SEL_2 ; + metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_serverAdapterA_3_s1_1$wget = 2'd2 ; - assign metaBram_serverAdapterA_3_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_serverAdapterA_3_s1_1$whas = + metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_serverAdapterB_3_outData_enqData$wget = metaBram_memory_3$DOB ; assign metaBram_serverAdapterB_3_outData_enqData$whas = @@ -1740,7 +1753,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, metaBram_serverAdapterB_3_outDataCore$FULL_N) && metaBram_serverAdapterB_3_s1[1] && metaBram_serverAdapterB_3_s1[0] ; - assign metaBram_serverAdapterB_3_outData_outData$wget = y_avValue__h26088 ; + assign metaBram_serverAdapterB_3_outData_outData$wget = + metaBram_serverAdapterB_3_outDataCore$EMPTY_N ? + metaBram_serverAdapterB_3_outDataCore$D_OUT : + metaBram_memory_3$DOB ; assign metaBram_serverAdapterB_3_outData_outData$whas = metaBram_serverAdapterB_3_outDataCore$EMPTY_N || !metaBram_serverAdapterB_3_outDataCore$EMPTY_N && @@ -1894,7 +1910,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, // register metaBram_serverAdapterA_1_s1 assign metaBram_serverAdapterA_1_s1$D_IN = - { MUX_metaCount$write_1__SEL_2, 1'b0 } ; + { metaBram_serverAdapterA_writeWithResp$whas, 1'b0 } ; assign metaBram_serverAdapterA_1_s1$EN = 1'd1 ; // register metaBram_serverAdapterA_2_cnt @@ -1904,7 +1920,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, // register metaBram_serverAdapterA_2_s1 assign metaBram_serverAdapterA_2_s1$D_IN = - { MUX_metaCount$write_1__SEL_2, 1'b0 } ; + { metaBram_serverAdapterA_writeWithResp$whas, 1'b0 } ; assign metaBram_serverAdapterA_2_s1$EN = 1'd1 ; // register metaBram_serverAdapterA_3_cnt @@ -1914,7 +1930,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, // register metaBram_serverAdapterA_3_s1 assign metaBram_serverAdapterA_3_s1$D_IN = - { MUX_metaCount$write_1__SEL_2, 1'b0 } ; + { metaBram_serverAdapterA_writeWithResp$whas, 1'b0 } ; assign metaBram_serverAdapterA_3_s1$EN = 1'd1 ; // register metaBram_serverAdapterA_cnt @@ -1924,7 +1940,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, // register metaBram_serverAdapterA_s1 assign metaBram_serverAdapterA_s1$D_IN = - { MUX_metaCount$write_1__SEL_2, 1'b0 } ; + { metaBram_serverAdapterA_writeWithResp$whas, 1'b0 } ; assign metaBram_serverAdapterA_s1$EN = 1'd1 ; // register metaBram_serverAdapterB_1_cnt @@ -1982,11 +1998,11 @@ module mkWSICaptureWorker4B(wciS0_Clk, // register metaCount always@(MUX_metaCount$write_1__SEL_1 or wci_wslv_reqF$D_OUT or - MUX_metaCount$write_1__SEL_2 or + metaBram_serverAdapterA_writeWithResp$whas or MUX_metaCount$write_1__VAL_2 or MUX_controlReg$write_1__SEL_2) case (1'b1) MUX_metaCount$write_1__SEL_1: metaCount$D_IN = wci_wslv_reqF$D_OUT[31:0]; - MUX_metaCount$write_1__SEL_2: + metaBram_serverAdapterA_writeWithResp$whas: metaCount$D_IN = MUX_metaCount$write_1__VAL_2; MUX_controlReg$write_1__SEL_2: metaCount$D_IN = 32'd0; default: metaCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ; @@ -2270,7 +2286,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign metaBram_memory$DIB = 32'd0 ; assign metaBram_memory$WEA = 1'd1 ; assign metaBram_memory$WEB = 1'd0 ; - assign metaBram_memory$ENA = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_memory$ENA = metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_memory$ENB = WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways ; @@ -2281,29 +2297,29 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign metaBram_memory_1$DIB = 32'd0 ; assign metaBram_memory_1$WEA = 1'd1 ; assign metaBram_memory_1$WEB = 1'd0 ; - assign metaBram_memory_1$ENA = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_memory_1$ENA = metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_memory_1$ENB = WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways ; // submodule metaBram_memory_2 assign metaBram_memory_2$ADDRA = metaCount[9:0] ; assign metaBram_memory_2$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; - assign metaBram_memory_2$DIA = nowW$wget[63:32] ; + assign metaBram_memory_2$DIA = wtiS_nowReq_BITS_63_TO_0__q1[63:32] ; assign metaBram_memory_2$DIB = 32'd0 ; assign metaBram_memory_2$WEA = 1'd1 ; assign metaBram_memory_2$WEB = 1'd0 ; - assign metaBram_memory_2$ENA = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_memory_2$ENA = metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_memory_2$ENB = WILL_FIRE_RL_metaBram_serverAdapterB_2_stageReadResponseAlways ; // submodule metaBram_memory_3 assign metaBram_memory_3$ADDRA = metaCount[9:0] ; assign metaBram_memory_3$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; - assign metaBram_memory_3$DIA = nowW$wget[31:0] ; + assign metaBram_memory_3$DIA = wtiS_nowReq_BITS_63_TO_0__q1[31:0] ; assign metaBram_memory_3$DIB = 32'd0 ; assign metaBram_memory_3$WEA = 1'd1 ; assign metaBram_memory_3$WEB = 1'd0 ; - assign metaBram_memory_3$ENA = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_memory_3$ENA = metaBram_serverAdapterA_writeWithResp$whas ; assign metaBram_memory_3$ENB = WILL_FIRE_RL_metaBram_serverAdapterB_3_stageReadResponseAlways ; @@ -2419,12 +2435,12 @@ module mkWSICaptureWorker4B(wciS0_Clk, // remaining internal signals assign IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d927 = IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 && - CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 ; + CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q2 ; assign NOT_controlReg_30_BIT_0_31_32_OR_controlReg_30_ETC___d856 = !controlReg[0] || controlReg[1] && - (!metaCount_34_ULT_1024___d1142 || - !dataCount_37_ULT_1024___d1092) || + (!metaCount_34_ULT_1024___d1203 || + !dataCount_37_ULT_1024___d1204) || (dataBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 && (!wsiS_reqFifo$D_OUT[57] || (metaBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 && @@ -2434,15 +2450,15 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 = controlReg[0] && (!controlReg[1] || - metaCount_34_ULT_1024___d1142 && - dataCount_37_ULT_1024___d1092) ; + metaCount_34_ULT_1024___d1203 && + dataCount_37_ULT_1024___d1204) ; assign dataBram_serverAdapterB_cnt_21_PLUS_IF_dataBra_ETC___d327 = dataBram_serverAdapterB_cnt + (WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways ? 3'd1 : 3'd0) + (dataBram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign dataCount_37_ULT_1024___d1092 = dataCount < 32'd1024 ; + assign dataCount_37_ULT_1024___d1204 = dataCount < 32'd1024 ; assign g_data__h27773 = (wci_wslv_reqF$D_OUT[63:52] == 12'h0) ? v__h26683 : 32'd0 ; assign metaBram_serverAdapterB_1_cnt_57_PLUS_IF_metaB_ETC___d563 = @@ -2475,17 +2491,13 @@ module mkWSICaptureWorker4B(wciS0_Clk, 3'd1 : 3'd0) + (metaBram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign metaCount_34_ULT_1024___d1142 = metaCount < 32'd1024 ; + assign metaCount_34_ULT_1024___d1203 = metaCount < 32'd1024 ; assign mlB__h23066 = mesgLengthSoFar + mlInc__h23065 ; assign mlInc__h23065 = wsiS_reqFifo$D_OUT[57] ? { 11'd0, x__h23114 + y__h23115 } : 14'd4 ; - assign rdat___1__h26780 = - { 6'd40, - !metaCount_34_ULT_1024___d1142, - !dataCount_37_ULT_1024___d1092, - 24'd2361866 } ; + assign rdat___1__h26780 = statusReg_w$wget ; assign rdat___1__h26864 = hasDebugLogic ? { 24'd0, wsiS_statusR } : 32'd0 ; assign rdat___1__h26919 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; @@ -2506,32 +2518,70 @@ module mkWSICaptureWorker4B(wciS0_Clk, splaF$D_OUT[2] ? y_avValue__h25924 : IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 ; + assign wtiS_nowReq_BITS_63_TO_0__q1 = wtiS_nowReq[63:0] ; assign x__h23114 = x__h23126 + y__h23127 ; assign x__h23126 = x__h23138 + y__h23139 ; assign x__h23138 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; assign y__h23115 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; assign y__h23127 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; assign y__h23139 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; - assign y_avValue__h25924 = - dataBram_serverAdapterB_outDataCore$EMPTY_N ? - dataBram_serverAdapterB_outDataCore$D_OUT : - dataBram_memory$DOB ; - assign y_avValue__h25968 = - metaBram_serverAdapterB_outDataCore$EMPTY_N ? - metaBram_serverAdapterB_outDataCore$D_OUT : - metaBram_memory$DOB ; - assign y_avValue__h26008 = - metaBram_serverAdapterB_1_outDataCore$EMPTY_N ? - metaBram_serverAdapterB_1_outDataCore$D_OUT : - metaBram_memory_1$DOB ; - assign y_avValue__h26048 = - metaBram_serverAdapterB_2_outDataCore$EMPTY_N ? - metaBram_serverAdapterB_2_outDataCore$D_OUT : - metaBram_memory_2$DOB ; - assign y_avValue__h26088 = - metaBram_serverAdapterB_3_outDataCore$EMPTY_N ? - metaBram_serverAdapterB_3_outDataCore$D_OUT : - metaBram_memory_3$DOB ; + assign y_avValue__h25924 = dataBram_serverAdapterB_outData_outData$wget ; + assign y_avValue__h25968 = metaBram_serverAdapterB_outData_outData$wget ; + assign y_avValue__h26008 = metaBram_serverAdapterB_1_outData_outData$wget ; + assign y_avValue__h26048 = metaBram_serverAdapterB_2_outData_outData$wget ; + assign y_avValue__h26088 = metaBram_serverAdapterB_3_outData_outData$wget ; + always@(splaF$D_OUT or + metaBram_serverAdapterB_3_outDataCore$EMPTY_N or + metaBram_serverAdapterB_3_outData_enqData$whas or + metaBram_serverAdapterB_outDataCore$EMPTY_N or + metaBram_serverAdapterB_outData_enqData$whas or + metaBram_serverAdapterB_1_outDataCore$EMPTY_N or + metaBram_serverAdapterB_1_outData_enqData$whas or + metaBram_serverAdapterB_2_outDataCore$EMPTY_N or + metaBram_serverAdapterB_2_outData_enqData$whas) + begin + case (splaF$D_OUT[1:0]) + 2'd0: + IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = + metaBram_serverAdapterB_outDataCore$EMPTY_N || + metaBram_serverAdapterB_outData_enqData$whas; + 2'd1: + IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = + metaBram_serverAdapterB_1_outDataCore$EMPTY_N || + metaBram_serverAdapterB_1_outData_enqData$whas; + 2'd2: + IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = + metaBram_serverAdapterB_2_outDataCore$EMPTY_N || + metaBram_serverAdapterB_2_outData_enqData$whas; + 2'd3: + IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = + splaF$D_OUT[1:0] != 2'd3 || + metaBram_serverAdapterB_3_outDataCore$EMPTY_N || + metaBram_serverAdapterB_3_outData_enqData$whas; + endcase + end + always@(splaF$D_OUT or + metaBram_serverAdapterB_3_outData_outData$whas or + metaBram_serverAdapterB_outData_outData$whas or + metaBram_serverAdapterB_1_outData_outData$whas or + metaBram_serverAdapterB_2_outData_outData$whas) + begin + case (splaF$D_OUT[1:0]) + 2'd0: + CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q2 = + metaBram_serverAdapterB_outData_outData$whas; + 2'd1: + CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q2 = + metaBram_serverAdapterB_1_outData_outData$whas; + 2'd2: + CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q2 = + metaBram_serverAdapterB_2_outData_outData$whas; + 2'd3: + CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q2 = + splaF$D_OUT[1:0] != 2'd3 || + metaBram_serverAdapterB_3_outData_outData$whas; + endcase + end always@(wci_wslv_reqF$D_OUT or metaBram_serverAdapterB_3_cnt or metaBram_serverAdapterB_cnt or @@ -2608,58 +2658,6 @@ module mkWSICaptureWorker4B(wciS0_Clk, default: v__h26683 = 32'd0; endcase end - always@(splaF$D_OUT or - metaBram_serverAdapterB_3_outDataCore$EMPTY_N or - metaBram_serverAdapterB_3_outData_enqData$whas or - metaBram_serverAdapterB_outDataCore$EMPTY_N or - metaBram_serverAdapterB_outData_enqData$whas or - metaBram_serverAdapterB_1_outDataCore$EMPTY_N or - metaBram_serverAdapterB_1_outData_enqData$whas or - metaBram_serverAdapterB_2_outDataCore$EMPTY_N or - metaBram_serverAdapterB_2_outData_enqData$whas) - begin - case (splaF$D_OUT[1:0]) - 2'd0: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = - metaBram_serverAdapterB_outDataCore$EMPTY_N || - metaBram_serverAdapterB_outData_enqData$whas; - 2'd1: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = - metaBram_serverAdapterB_1_outDataCore$EMPTY_N || - metaBram_serverAdapterB_1_outData_enqData$whas; - 2'd2: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = - metaBram_serverAdapterB_2_outDataCore$EMPTY_N || - metaBram_serverAdapterB_2_outData_enqData$whas; - 2'd3: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = - splaF$D_OUT[1:0] != 2'd3 || - metaBram_serverAdapterB_3_outDataCore$EMPTY_N || - metaBram_serverAdapterB_3_outData_enqData$whas; - endcase - end - always@(splaF$D_OUT or - metaBram_serverAdapterB_3_outData_outData$whas or - metaBram_serverAdapterB_outData_outData$whas or - metaBram_serverAdapterB_1_outData_outData$whas or - metaBram_serverAdapterB_2_outData_outData$whas) - begin - case (splaF$D_OUT[1:0]) - 2'd0: - CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 = - metaBram_serverAdapterB_outData_outData$whas; - 2'd1: - CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 = - metaBram_serverAdapterB_1_outData_outData$whas; - 2'd2: - CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 = - metaBram_serverAdapterB_2_outData_outData$whas; - 2'd3: - CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 = - splaF$D_OUT[1:0] != 2'd3 || - metaBram_serverAdapterB_3_outData_outData$whas; - endcase - end // handling of inlined registers diff --git a/rtl/mkWSIPatternWorker4B.v b/rtl/mkWSIPatternWorker4B.v index 57227963..a912ba65 100644 --- a/rtl/mkWSIPatternWorker4B.v +++ b/rtl/mkWSIPatternWorker4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Wed Sep 19 10:18:30 EDT 2012 +// On Mon Sep 24 13:38:35 EDT 2012 // // // Ports: @@ -896,7 +896,6 @@ module mkWSIPatternWorker4B(wciS0_Clk, MUX_metaPtr_modulus$write_1__SEL_1, MUX_splitReadInFlight$write_1__SEL_1, MUX_unrollCnt$write_1__SEL_1, - MUX_unrollCnt$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, @@ -918,7 +917,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, v__h31927; reg CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1, IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1033, - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1202, + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205, IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1132; wire [31 : 0] b__h25071, g_data__h32953, @@ -950,7 +949,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, metaBram_serverAdapterB_cnt_51_PLUS_IF_metaBra_ETC___d457; wire [1 : 0] ab__h11456, ab__h14555, ab__h17482, ab__h20409, ab__h23336; wire IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1042, - dataBram_serverAdapterB_cnt_33_SLT_3___d1305, + dataBram_serverAdapterB_cnt_33_SLT_3___d1314, doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d913, doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d923, metaBram_serverAdapterA_1_outData_outData_whas_ETC___d871, @@ -1306,22 +1305,22 @@ module mkWSIPatternWorker4B(wciS0_Clk, // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = ((wsiM_reqFifo_c_r == 2'd0) ? - MUX_unrollCnt$write_1__SEL_2 : - wsiM_reqFifo_c_r != 2'd1 || MUX_unrollCnt$write_1__SEL_2) && - MUX_unrollCnt$write_1__SEL_2 && + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && + wsiM_reqFifo_enqueueing$whas && !WILL_FIRE_RL_wsiM_reqFifo_deq ; // rule RL_wsiM_reqFifo_decCtr assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = - WILL_FIRE_RL_wsiM_reqFifo_deq && !MUX_unrollCnt$write_1__SEL_2 ; + WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ; // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = ((wsiM_reqFifo_c_r == 2'd1) ? - MUX_unrollCnt$write_1__SEL_2 : - wsiM_reqFifo_c_r != 2'd2 || MUX_unrollCnt$write_1__SEL_2) && + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && WILL_FIRE_RL_wsiM_reqFifo_deq && - MUX_unrollCnt$write_1__SEL_2 ; + wsiM_reqFifo_enqueueing$whas ; // rule RL_dataBram_serverAdapterA_outData_enqAndDeq assign WILL_FIRE_RL_dataBram_serverAdapterA_outData_enqAndDeq = @@ -1346,9 +1345,9 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign CAN_FIRE_RL_wci_cfwr = wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && ((wci_wslv_reqF$D_OUT[63:52] == 12'h800) ? - dataBram_serverAdapterB_cnt_33_SLT_3___d1305 : + dataBram_serverAdapterB_cnt_33_SLT_3___d1314 : wci_wslv_reqF$D_OUT[63:52] != 12'h400 || - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1202) && + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205) && wci_wslv_wci_cfwr_pw$whas ; assign WILL_FIRE_RL_wci_cfwr = CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_wslv_ctl_op_start && @@ -1462,7 +1461,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 && wci_wslv_reqF$D_OUT[39:32] == 8'h08 ; assign MUX_mesgCount$write_1__SEL_2 = - MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 ; + wsiM_reqFifo_enqueueing$whas && unrollCnt == 16'd1 ; assign MUX_mesgRemain$write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 && wci_wslv_reqF$D_OUT[39:32] == 8'h10 ; @@ -1501,10 +1500,6 @@ module mkWSIPatternWorker4B(wciS0_Clk, metaReqInFlightF_i_notEmpty__59_AND_metaBram_s_ETC___d875 && wci_wslv_cState == 3'd2 && mesgRemain != 32'd0 ; - assign MUX_unrollCnt$write_1__SEL_2 = - wsiM_reqFifo_c_r != 2'd2 && - doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d923 && - wci_wslv_cState == 3'd2 ; assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || @@ -1645,7 +1640,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign wci_wci_Es_mData_w$wget = wciS0_MData ; assign wci_wci_Es_mData_w$whas = 1'd1 ; assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ; - assign wsiM_reqFifo_x_wire$whas = MUX_unrollCnt$write_1__SEL_2 ; + assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; assign wsiM_operateD_1$wget = 1'd1 ; assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ; assign wsiM_peerIsReady_1$wget = 1'd1 ; @@ -1958,14 +1953,17 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign wci_wslv_wci_ctrl_pw$whas = wci_wslv_reqF$EMPTY_N && !wci_wslv_reqF$D_OUT[68] && wci_wslv_reqF$D_OUT[71:69] == 3'd2 ; - assign wsiM_reqFifo_enqueueing$whas = MUX_unrollCnt$write_1__SEL_2 ; + assign wsiM_reqFifo_enqueueing$whas = + wsiM_reqFifo_c_r != 2'd2 && + doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d923 && + wci_wslv_cState == 3'd2 ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; assign metaPtr_incAction$whas = WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ; assign metaPtr_decAction$whas = 1'b0 ; assign dataBram_serverAdapterA_outData_deqCalled$whas = - MUX_unrollCnt$write_1__SEL_2 && !doZLM ; + wsiM_reqFifo_enqueueing$whas && !doZLM ; assign dataBram_serverAdapterB_outData_deqCalled$whas = MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && splaF$D_OUT[2] && splaF$D_OUT[1:0] == 2'd0 ; @@ -2043,11 +2041,11 @@ module mkWSIPatternWorker4B(wciS0_Clk, // register dataCount always@(MUX_dataCount$write_1__SEL_1 or wci_wslv_reqF$D_OUT or - MUX_unrollCnt$write_1__SEL_2 or + wsiM_reqFifo_enqueueing$whas or MUX_dataCount$write_1__VAL_2 or MUX_controlReg$write_1__SEL_2) case (1'b1) MUX_dataCount$write_1__SEL_1: dataCount$D_IN = wci_wslv_reqF$D_OUT[31:0]; - MUX_unrollCnt$write_1__SEL_2: + wsiM_reqFifo_enqueueing$whas: dataCount$D_IN = MUX_dataCount$write_1__VAL_2; MUX_controlReg$write_1__SEL_2: dataCount$D_IN = 32'd0; default: dataCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ; @@ -2055,7 +2053,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign dataCount$EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 && wci_wslv_reqF$D_OUT[39:32] == 8'h0C || - MUX_unrollCnt$write_1__SEL_2 || + wsiM_reqFifo_enqueueing$whas || MUX_controlReg$write_1__SEL_2 ; // register dataPtr @@ -2069,7 +2067,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, // register doZLM assign doZLM$D_IN = MUX_unrollCnt$write_1__SEL_1 && v__h24454 == 32'd0 ; assign doZLM$EN = - MUX_unrollCnt$write_1__SEL_2 && doZLM || + wsiM_reqFifo_enqueueing$whas && doZLM || MUX_unrollCnt$write_1__SEL_1 ; // register isFirst @@ -2091,7 +2089,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign mesgCount$EN = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 && wci_wslv_reqF$D_OUT[39:32] == 8'h08 || - MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1 || + wsiM_reqFifo_enqueueing$whas && unrollCnt == 16'd1 || MUX_controlReg$write_1__SEL_2 ; // register mesgLengthSoFar @@ -2266,7 +2264,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, MUX_unrollCnt$write_1__VAL_1 : MUX_unrollCnt$write_1__VAL_2 ; assign unrollCnt$EN = - MUX_unrollCnt$write_1__SEL_1 || MUX_unrollCnt$write_1__SEL_2 ; + MUX_unrollCnt$write_1__SEL_1 || wsiM_reqFifo_enqueueing$whas ; // register wci_wslv_cEdge assign wci_wslv_cEdge$D_IN = wci_wslv_reqF$D_OUT[36:34] ; @@ -2567,7 +2565,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, assign loopReqInFlightF$ENQ = WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ; assign loopReqInFlightF$DEQ = - MUX_unrollCnt$write_1__SEL_2 && + wsiM_reqFifo_enqueueing$whas && (thisLength == 32'd0 || unrollCnt == 16'd1) ; assign loopReqInFlightF$CLR = 1'b0 ; @@ -2796,7 +2794,7 @@ module mkWSIPatternWorker4B(wciS0_Clk, dataBram_serverAdapterB_cnt + (dataBram_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) + (dataBram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign dataBram_serverAdapterB_cnt_33_SLT_3___d1305 = + assign dataBram_serverAdapterB_cnt_33_SLT_3___d1314 = (dataBram_serverAdapterB_cnt ^ 3'h4) < 3'd7 ; assign doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d913 = doZLM || @@ -3078,35 +3076,35 @@ module mkWSIPatternWorker4B(wciS0_Clk, begin case (wci_wslv_reqF$D_OUT[35:34]) 2'd0: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1202 = + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205 = (metaBram_serverAdapterB_cnt ^ 3'h4) < 3'd7; 2'd1: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1202 = + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205 = (metaBram_serverAdapterB_1_cnt ^ 3'h4) < 3'd7; 2'd2: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1202 = + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205 = (metaBram_serverAdapterB_2_cnt ^ 3'h4) < 3'd7; 2'd3: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1202 = + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205 = wci_wslv_reqF$D_OUT[35:34] != 2'd3 || (metaBram_serverAdapterB_3_cnt ^ 3'h4) < 3'd7; endcase end always@(wci_wslv_reqF$D_OUT or splaF$FULL_N or - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1202 or - dataBram_serverAdapterB_cnt_33_SLT_3___d1305) + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205 or + dataBram_serverAdapterB_cnt_33_SLT_3___d1314) begin case (wci_wslv_reqF$D_OUT[63:52]) 12'h0: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1132 = 1'b1; 12'h800: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1132 = - dataBram_serverAdapterB_cnt_33_SLT_3___d1305 && splaF$FULL_N; + dataBram_serverAdapterB_cnt_33_SLT_3___d1314 && splaF$FULL_N; default: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1132 = wci_wslv_reqF$D_OUT[63:52] != 12'h400 || splaF$FULL_N && - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1202; + IF_wci_wslv_reqF_first__5_BITS_35_TO_34_076_EQ_ETC___d1205; endcase end always@(splaF$D_OUT or @@ -3496,13 +3494,13 @@ module mkWSIPatternWorker4B(wciS0_Clk, !dataBram_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n) - if (MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1) + if (wsiM_reqFifo_enqueueing$whas && unrollCnt == 16'd1) begin v__h29373 = $time; #0; end if (wciS0_MReset_n) - if (MUX_unrollCnt$write_1__SEL_2 && unrollCnt == 16'd1) + if (wsiM_reqFifo_enqueueing$whas && unrollCnt == 16'd1) $display("[%0d]: %m: wsi_source: End of WSI Producer Egress: mesgCount:%0x thisOpcode:%0x thisLength:%0x", v__h29373, mesgCount, diff --git a/rtl/mkWciInitiator.v b/rtl/mkWciInitiator.v index 8ad84033..fbfa99c7 100644 --- a/rtl/mkWciInitiator.v +++ b/rtl/mkWciInitiator.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:44:26 EDT 2012 +// On Mon Sep 24 13:38:09 EDT 2012 // // // Ports: @@ -334,7 +334,7 @@ module mkWciInitiator(CLK, _dor1initiator_lastConfigAddr$EN_write, _dor1initiator_lastConfigBE$EN_write, initFsm_abort_whas__45_AND_initFsm_abort_wget__ETC___d231, - initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285; + initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258; // output resets assign RST_N_wciM0 = initiator_mReset$OUT_RST_N ; @@ -443,7 +443,7 @@ module mkWciInitiator(CLK, // rule RL_initiator_wrkBusy assign WILL_FIRE_RL_initiator_wrkBusy = ((initiator_wciResponse$wget[33:32] == 2'd0) ? - initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 || + initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 || initiator_respF$FULL_N : initiator_respF$FULL_N) && initiator_busy ; @@ -479,7 +479,7 @@ module mkWciInitiator(CLK, MUX_initiator_busy$write_1__PSEL_1 && initiator_wReset_n ; assign MUX_initiator_busy$write_1__SEL_2 = WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 || initiator_wciResponse$wget[33:32] != 2'd0) ; assign MUX_initiator_lastControlOp$write_1__SEL_1 = WILL_FIRE_RL_initFsm_action_l1107c14 && initiator_wReset_n ; @@ -539,7 +539,7 @@ module mkWciInitiator(CLK, initiator_wciResponse$wget ; assign MUX_initiator_respTimr$write_1__VAL_2 = (initiator_wciResponse$wget[33:32] == 2'd0) ? - (initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 ? + (initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 ? x__h2590 : 32'd0) : 32'd0 ; @@ -675,7 +675,7 @@ module mkWciInitiator(CLK, assign initiator_busy$EN = _dand1initiator_busy$EN_write || WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 || initiator_wciResponse$wget[33:32] != 2'd0) ; // register initiator_lastConfigAddr @@ -813,7 +813,7 @@ module mkWciInitiator(CLK, assign initiator_reqTO$EN = WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && (initiator_reqPend == 2'd1 || initiator_reqPend == 2'd2 || initiator_reqPend == 2'd3) ; @@ -829,7 +829,7 @@ module mkWciInitiator(CLK, assign initiator_respTimrAct$D_IN = initiator_reqF_c_r ; assign initiator_respTimrAct$EN = WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 || initiator_wciResponse$wget[33:32] != 2'd0) || initiator_reqF_c_r ; @@ -893,7 +893,7 @@ module mkWciInitiator(CLK, assign initiator_respF$ENQ = _dand1initiator_respF$EN_enq || WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 || initiator_wciResponse$wget[33:32] != 2'd0) || WILL_FIRE_RL_initFsm_action_l1105c14 ; assign initiator_respF$DEQ = @@ -946,7 +946,7 @@ module mkWciInitiator(CLK, (initFsm_state_mkFSMstate == 4'd0 || initFsm_state_mkFSMstate == 4'd11) && (!initFsm_start_reg_1 || initFsm_state_fired) ; - assign initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 = + assign initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 = initiator_respTimr < toCount__h2428 ; assign toCount__h2428 = 32'd1 << initiator_wTimeout ; assign x__h25066 = { initiator_pageWindow, 20'h0 } ; @@ -1277,7 +1277,7 @@ module mkWciInitiator(CLK, if (RST_N) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && initiator_reqPend == 2'd1) begin v__h2732 = $time; @@ -1286,13 +1286,13 @@ module mkWciInitiator(CLK, if (RST_N) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && initiator_reqPend == 2'd1) $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h2732); if (RST_N) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && initiator_reqPend == 2'd2) begin v__h2822 = $time; @@ -1301,13 +1301,13 @@ module mkWciInitiator(CLK, if (RST_N) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && initiator_reqPend == 2'd2) $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h2822); if (RST_N) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && initiator_reqPend == 2'd3) begin v__h2911 = $time; @@ -1316,7 +1316,7 @@ module mkWciInitiator(CLK, if (RST_N) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d285 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d258 && initiator_reqPend == 2'd3) $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h2911); if (RST_N) diff --git a/rtl/mkWciTarget.v b/rtl/mkWciTarget.v index d82f82a9..15a62b18 100644 --- a/rtl/mkWciTarget.v +++ b/rtl/mkWciTarget.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17) // -// On Fri Sep 21 13:44:27 EDT 2012 +// On Mon Sep 24 13:38:09 EDT 2012 // // // Ports: